Processing method for acquiring static power consumption of chip

Abstract

The invention relates to the technical field of chip testing, in particular to a processing method for obtaining static power consumption of a chip. The method comprises the following steps: S100, obtaining a test result R of a target chip obtained by using automatic test equipment ATE; s200, acquiring a current coefficient a corresponding to the target chip; s300, obtaining an equivalent temperature Tc corresponding to the target temperature T0; s400, according to aj, obtaining a leakage current I0 of the target chip when the working voltage is Vj, 0 and the environment temperature is Tc; and S500, determining the Vj, 0 * I0 as the static power consumption of the target chip when the target chip works at the Vj, 0 and the temperature of the highest temperature point of the target chip is T0 when the system-level platform is used for testing the target chip. According to the invention, the static power consumption of the target chip under the plateform test can be obtained based on the test result of the target chip under the ATE test.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a method for obtaining the static power consumption of a chip. Background Technology

[0002] While platforms (system-level platforms) can be used to obtain the static power consumption (SDP) of a chip at various voltages and temperatures within a product, the workload of obtaining the SDP for each chip at these voltages and temperatures using platforms is too large. In existing technologies, ATE (Automatic Test Equipment) measures the SDP of a chip at various voltages and temperatures during CP (Chip Completion) and FT (Final Test) stages. However, during ATE testing, no program is running on the chip, and the temperature at various points on the chip is relatively similar. In contrast, during platform testing, the chip is running a program, and the temperature differences between different locations on the chip are significant. Therefore, the SDP obtained using ATE testing and platform testing at the same temperature are different, and the SDP obtained from ATE testing cannot be directly used as the SDP obtained from platform testing. How to obtain the SDP of a chip under platform testing based on the test results under ATE testing is a problem that urgently needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a method for obtaining the static power consumption of a chip, so as to obtain the static power consumption of the chip under platform testing based on the test results of the chip under ATE testing.

[0004] According to the present invention, a method for obtaining the static power consumption of a chip is provided, comprising the following steps:

[0005] S100, Obtain the test result R of the target chip obtained using the automated test equipment ATE, R = (r1, r2, ..., r j ,…,r n ), r j To obtain the target chip using ATE at the j-th preset operating voltage V j,0 The test results at that time, r j =(r j,1 ,r j,2 ), r j,1 The target chip obtained using ATE is at a preset first temperature T in the ambient temperature. 1,0 And at a working voltage of V j,0 The test results at that time, r j,1 Including the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 Leakage current I j,1 rj,2 The target chip obtained using ATE is at a preset second temperature T in an ambient temperature. 2,0 And at a working voltage of V j,0 The test results at that time, r j,2 Including the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 Leakage current I j,2 The value of j ranges from 1 to n, where n is the number of preset voltages.

[0006] S200, obtain the current coefficient a corresponding to the target chip, a = (a1, a2, ..., a2) j ,…,a n ), a j Let a be the current coefficient corresponding to the j-th preset voltage of the target chip. j according to Get, NT 1,0 For the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 The average temperature at each preset location, NT 2,0 For the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 The average temperature at each preset location.

[0007] S300, obtain the equivalent temperature T corresponding to the target temperature T0. c T0 is the temperature at the highest point of the target chip when testing the target chip using a system-level platform.

[0008] S400, according to a j Obtain the target chip at an operating voltage of V j,0 And the ambient temperature is T c The leakage current I0 at that time

[0009] S500, V j,0 ×I0 is determined to make the target chip operate at V when testing the target chip using a system-level platform. j,0 Furthermore, the static power consumption of the target chip is the temperature at its highest point, T0.

[0010] Compared with the prior art, the present invention has at least the following beneficial effects:

[0011] This invention can obtain the static power consumption of a target chip under platform testing based on the test results of the target chip under ATE testing. Specifically, this invention obtains the leakage current of the target chip under ATE testing corresponding to various preset voltages and preset temperatures. Based on the leakage current of the target chip at the same preset voltage corresponding to different preset temperatures, this invention obtains the current coefficient 'a' of the target chip corresponding to each preset voltage. j Based on this current coefficient a j This invention can obtain the leakage current of the target chip at any temperature under a preset voltage, by substituting the equivalent temperature corresponding to the target temperature of the platform test. The present invention obtains the leakage current corresponding to the target temperature of the platform test, and then obtains the static power consumption of the target chip under the platform test with the corresponding preset voltage and target temperature.

[0012] Moreover, the present invention obtains a j At that time, NT was used. 1,0 and NT 2,0 NT 1,0 For the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 The average temperature at each preset location, NT 2,0 For the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 The average temperature at each preset location, compared to directly using T 1,0 and T 2,0 Get a j Furthermore, this invention also considers the impact of different leakage currents on the actual temperature of different chips under the same ambient temperature, thereby improving the accuracy of the static power consumption of the target chip under the final platform test obtained by this invention. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A flowchart of a method for obtaining the static power consumption of a chip, provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] According to this embodiment, as Figure 1 As shown, a method for obtaining the static power consumption of a chip is provided, including the following steps:

[0017] S100, Obtain the test result R of the target chip obtained using the automated test equipment ATE, R = (r1, r2, ..., r j ,…,r n ), r j To obtain the target chip using ATE at the j-th preset operating voltage V j,0 The test results at that time, r j =(r j,1 ,r j,2 ), r j,1 The target chip obtained using ATE is at a preset first temperature T in the ambient temperature. 1,0 And at a working voltage of V j,0 The test results at that time, r j,1 Including the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 Leakage current I j,1 r j,2 The target chip obtained using ATE is at a preset second temperature T in an ambient temperature. 2,0 And at a working voltage of V j,0 The test results at that time, r j,2 Including the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 Leakage current I j,2 The value of j ranges from 1 to n, where n is the number of preset voltages.

[0018] In this embodiment, T 1,0 For a relatively low temperature, T 2,0 As an alternative specific implementation method, T is used at a relatively high temperature. 1,0 At 5℃, T 2,0 The temperature is 75℃.

[0019] Those skilled in the art will understand that any prior art method for obtaining the leakage current of a chip at various voltages and temperatures using ATE falls within the protection scope of this invention.

[0020] S200, obtain the current coefficient a corresponding to the target chip, a = (a1, a2, ..., a2) j ,…,a n ), a j Let a be the current coefficient corresponding to the j-th preset voltage of the target chip. j according to Get, NT 1,0 For the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 The average temperature at each preset location, NT 2,0 For the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 The average temperature at each preset location.

[0021] In this embodiment, NT 1,0 By measuring the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 The temperature at each preset location is obtained. In one specific implementation, the target chip has u preset locations, and these u preset locations are at an ambient temperature of T. 1,0 And at a working voltage of V j,0 The temperatures at those times were Tem 1,1 、Tem 1,2 ...,Tem 1,u So NT 1,0 For Tem 1,1 、Tem 1,2 ...,Tem 1,u The average value; u is the preset number of positions.

[0022] In this embodiment, NT 2,0 By measuring the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 The temperature at each preset location is obtained. In one specific implementation, the target chip has u preset locations, and these u preset locations are at an ambient temperature of T. 2,0 And at a working voltage of V j,0 The temperatures at those times were Tem 2,1 、Tem 2,2 ...,Tem 2,u So NT 2,0 For Tem 2,1 、Tem 2,2 ...,Tem 2,u The average value.

[0023] In this embodiment, I j,1 I j,2 NT 1,0and NT 2,0 All values ​​are known, a j For unknown values, I j,1 I j,2 NT 1,0 and NT 2,0 Substitution You can get a j .

[0024] This embodiment obtains a j At that time, NT was used. 1,0 and NT 2,0 Compared to directly using T 1,0 and T 2,0 Get a j This embodiment also considers the impact of different leakage currents on the actual temperature of different chips under the same ambient temperature, which improves the accuracy of the static power consumption of the target chip under the final platform test obtained in this embodiment.

[0025] S300, obtain the equivalent temperature T corresponding to the target temperature T0. c T0 is the temperature at the highest point of the target chip when testing the target chip using a system-level platform.

[0026] This embodiment aims to obtain the target chip's temperature at its highest point, T0, obtained using system-level platform testing, and its operating voltage, V. j,0 The static power consumption at which the target chip reaches its highest temperature is the target temperature T0, and the operating voltage is V. j,0 The static power consumption at the target chip's highest temperature is the target temperature T0, and the operating voltage is V. j,0 Leakage current and V j,0 The accumulation of.

[0027] During ATE testing, no program is running on the chip, and the temperature at various points on the chip is relatively similar, with little difference from the ambient temperature during ATE testing. However, during platform testing, the chip is running a program, resulting in significant temperature differences between different locations on the chip, including a large difference from the temperature at the hottest point. Therefore, even if the ambient temperature during ATE testing and the temperature at the hottest point on the chip are the same during platform testing, the static power consumption will be different, and the static power consumption obtained from ATE testing cannot be directly used as the static power consumption obtained from platform testing. This embodiment will use the target chip obtained from ATE testing at an ambient temperature of equivalent temperature T. c And the operating voltage is V j,0 The leakage current was determined using platform testing at the target chip's highest temperature, T0, and with an operating voltage of V.j,0 The leakage current at that time. As an optional specific implementation, T c This is an empirical value corresponding to T0. For example, when T0 is 100℃, T... c It is 94℃.

[0028] As a preferred embodiment, T c The acquisition process includes:

[0029] S010, Use the system-level platform to obtain the sample chip at its highest temperature T0 and operating voltage V. j,0 The static power consumption BP at time , BP = (BP1, BP2, ..., BP) k ,…,BP q ), BP k The k-th sample chip obtained using the platform has a maximum temperature of T0 and an operating voltage of V. j,0 The static power consumption at that time, where k ranges from 1 to q, and q is the preset number of sample chips.

[0030] In this embodiment, BP k =V j,0 ×BI k BI k The k-th sample chip obtained using the platform has a maximum temperature of T0 and an operating voltage of V. j,0 Leakage current at that time.

[0031] S020, initialize the temperature variable e to 0.

[0032] S030, use ATE to obtain sample chip data at ambient temperature T0-e×ΔT and operating voltage V. j,0 Static power consumption DP e DP e =(DP e,1 ,DP e,2 ,…,DP e,k ,…,DP e,q ), DP e,k The k-th sample chip obtained using ATE is located at an ambient temperature of T0-e×ΔT and an operating voltage of V. j,0 The static power consumption at that time; ΔT is the preset temperature adjustment step size.

[0033] In this embodiment, DP e,k =V j,0 ×DI e,k DI e,k The k-th sample chip obtained using ATE is located at an ambient temperature of T0-e×ΔT and an operating voltage of V. j,0 Leakage current at that time.

[0034] In this embodiment, ΔT is an empirical value, which can be optionally 0.5℃ or 1℃.

[0035] S040, Obtain the e-th static differential sequence H e H e =(|BP1-DP) e,1 |,|BP2-DP e,2 |,…,|BP k -DP e,k |,…,|BP q -DP e,q |).

[0036] S050, if min(H) e If )>p0, then update e to e+1, and repeat S030-S040 until min(H) e If )≤p0, then T0-e×ΔT is determined as T. c min() is used to take the minimum value, and p0 is the preset static power consumption threshold.

[0037] In this embodiment, min(H) e p0 indicates that each sample chip obtained using ATE is operating at an ambient temperature of T0-e×ΔT and an operating voltage of V. j,0 The static power consumption at that time is compared with that of the corresponding sample chip obtained using the system-level platform at the highest temperature T0 and the operating voltage V. j,0 The differences in static power consumption at any given time are all less than the preset static power consumption threshold, that is, the difference in static power consumption for each sample chip obtained using ATE is less than the preset static power consumption threshold. j,0 The static power consumption at that time is compared with that of the corresponding sample chip obtained using the system-level platform at the highest temperature T0 and the operating voltage V. j,0 The difference in static power consumption is small.

[0038] T obtained based on S010-S050 c This allows for a smaller difference between the acquired I0 and the leakage current of the target chip under the same voltage and temperature during platform testing, thus improving the accuracy of the final static power consumption of the target chip under platform testing. S400, according to a j Obtain the target chip at an operating voltage of V j,0 And the ambient temperature is T c The leakage current I0 at that time

[0039]

[0040] In this embodiment, I j,2 aj T c and NT 2,0 All values ​​are known, I0 is an unknown value. j,2 a j T c and NT 2,0 Substitution I0 can then be obtained.

[0041] S500, V j,0 ×I0 is determined to make the target chip operate at V when testing the target chip using a system-level platform. j,0 Furthermore, the static power consumption of the target chip is the temperature at its highest point, T0.

[0042] This embodiment can obtain the static power consumption of the target chip under platform testing based on the test results of the target chip under ATE testing. Specifically, this embodiment obtains the leakage current of the target chip under ATE testing corresponding to each preset voltage and preset temperature. Based on the leakage current of the target chip at the same preset voltage corresponding to different preset temperatures, this embodiment obtains the current coefficient 'a' of the target chip corresponding to each preset voltage. j Based on this current coefficient a j This embodiment can obtain the leakage current at any temperature under a preset voltage corresponding to the target chip, by substituting the equivalent temperature corresponding to the target temperature of the platform test. In this embodiment, the leakage current corresponding to the target temperature of the platform test is obtained, and then the static power consumption of the target chip under the platform test with respect to the corresponding preset voltage and target temperature is obtained.

[0043] This embodiment obtains a j At that time, NT was used. 1,0 and NT 2,0 NT 1,0 For the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 The average temperature at each preset location, NT 2,0 For the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 The average temperature at each preset location, compared to directly using T 1,0 and T 2,0 Get a j This embodiment also considers the impact of different leakage currents on the actual temperature of different chips under the same ambient temperature, which improves the accuracy of the static power consumption of the target chip under the final platform test obtained in this embodiment.

[0044] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A method for obtaining the static power consumption of a chip, characterized in that, Includes the following steps: S100, Obtain the test result R of the target chip obtained using the automated test equipment ATE, R = (r1, r2, ..., r j ,…,r n ), r j To obtain the target chip using ATE at the j-th preset operating voltage V j,0 The test results at that time, r j =(r j,1 ,r j,2 ), r j,1 The target chip obtained using ATE is at a preset first temperature T in the ambient temperature. 1,0 And at a working voltage of V j,0 The test results at that time, r j,1 Including the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 Leakage current I j,1 r j,2 The target chip obtained using ATE is at a preset second temperature T in an ambient temperature. 2,0 And at a working voltage of V j,0 The test results at that time, r j,2 Including the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 Leakage current I j,2 The value of j ranges from 1 to n, where n is the number of preset voltages; S200, obtain the current coefficient a corresponding to the target chip, a = (a1, a2, ..., a2) j ,…,a n ), a j Let a be the current coefficient corresponding to the j-th preset voltage of the target chip. j according to Get, NT 1,0 For the target chip at an ambient temperature of T 1,0 And at a working voltage of V j,0 The average temperature at each preset location, NT 2,0 For the target chip at an ambient temperature of T 2,0 And at a working voltage of V j,0 The average temperature at each preset location; S300, obtain the equivalent temperature T corresponding to the target temperature T0. c T0 is the temperature at the highest point of the target chip when the target chip is tested using a system-level platform. S400, according to a j Obtain the target chip at an operating voltage of V j,0 And the ambient temperature is T c The leakage current I0 at that time S500, V j,0 ×I0 is determined to make the target chip operate at V when testing the target chip using a system-level platform. j,0 Furthermore, the static power consumption of the target chip is the temperature at its highest point, T0.

2. The method for obtaining the static power consumption of a chip according to claim 1, characterized in that, T c The acquisition process includes: S010, Use the system-level platform to obtain the sample chip at its highest temperature T0 and operating voltage V. j,0 The static power consumption BP at time , BP = (BP1, BP2, ..., BP) k ,…,BP q ), BP k The k-th sample chip obtained using the platform has a maximum temperature of T0 and an operating voltage of V. j,0 The static power consumption at that time, where k ranges from 1 to q, and q is the preset number of sample chips; S020, initialize the temperature variable e to 0; S030, use ATE to obtain sample chip data at ambient temperature T0-e×ΔT and operating voltage V. j,0 Static power consumption DP e DP e =(DP e,1 ,DP e,2 ,…,DP e,k ,…,DP e,q ), DP e,k The k-th sample chip obtained using ATE is located at an ambient temperature of T0-e×ΔT and an operating voltage of V. j,0 The static power consumption at that time; ΔT is the preset temperature adjustment step size; S040, Obtain the e-th static differential sequence H e H e =(|BP1-DP) e,1 |,|BP2-DP e,2 |,…,|BP k -DP e,k |,…,|BP q -DP e,q |); S050, if min(H) e If )>p0, then update e to e+1, and repeat S030-S040 until min(H) e If )≤p0, then T0-e×ΔT is determined as T. c min() is used to take the minimum value, and p0 is the preset static power consumption threshold.

3. The method for obtaining the static power consumption of a chip according to claim 1, characterized in that, T 1,0 At 5℃, T 2,0 The temperature is 75℃.

4. The method for obtaining the static power consumption of a chip according to claim 1, characterized in that, T0＝100℃。 5. The method for obtaining the static power consumption of a chip according to claim 4, characterized in that, T0＝94℃。 6. The method for obtaining the static power consumption of a chip according to claim 2, characterized in that, BP k =V j,0 ×BI k BI k The k-th sample chip obtained using the platform has a maximum temperature of T0 and an operating voltage of V. j,0 Leakage current at that time.

7. The method for obtaining the static power consumption of a chip according to claim 2, characterized in that, DP e,k =V j,0 ×DI e,k DI e,k The k-th sample chip obtained using ATE is located at an ambient temperature of T0-e×ΔT and an operating voltage of V. j,0 Leakage current at that time.

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