Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the steps that at least one reference index is obtained, the at least one reference index comprises a popularity index, and the popularity index reflects the popularity distribution state of data to be backed up; according to the at least one reference index, a backup rule for data to be backed up is adjusted; and executing a backup operation on the data to be backed up in the memory module according to the backup rule. Therefore, the backup and / or restoration efficiency in the storage device can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] Generally, to improve the operational stability of storage devices, the memory controller may back up the data currently stored in the storage device before, after, or before performing a system update. Subsequently, in the event of a system failure, the memory controller can use the backup data to restore the system to its original state (i.e., factory default state). Alternatively, the user can manually trigger or configure the system to perform periodic backups.

[0003] However, common data backup and restore mechanisms often only support backups and restores of full disks or partitions (such as the D drive), lacking operational flexibility. Furthermore, taking periodic system backups as an example, if the time window allocated for backup operations is too short, the backup may fail due to unexpected interruption. Conversely, if the time window allocated for backup operations is too long, system resources are wasted. Summary of the Invention

[0004] This invention proposes a memory management method and a storage device that can improve the above-mentioned problems and thus effectively improve the backup and / or restore efficiency within the storage device.

[0005] Embodiments of the present invention provide a memory management method for a storage device, wherein the storage device includes a memory module, and the memory management method includes: obtaining at least one reference index, wherein the at least one reference index includes a popularity index, the popularity index reflecting the popularity distribution state of the data to be backed up; adjusting backup rules for the data to be backed up according to the at least one reference index; and performing a backup operation on the data to be backed up in the memory module according to the backup rules.

[0006] An embodiment of the present invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a memory management method.

[0007] Based on the above, after obtaining at least one reference indicator, including a popularity metric, the backup rules for the data to be backed up can be dynamically adjusted according to that indicator. Specifically, the popularity metric reflects the popularity distribution of the data to be backed up. Subsequently, according to the backup rules, the backup operation can be automatically executed on the data to be backed up within the storage module. This effectively improves the backup and / or restore efficiency within the storage device. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating the execution of a backup operation according to backup rules, as shown in an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram illustrating the execution of a backup operation according to backup rules, as shown in an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram illustrating the execution of a backup operation according to backup rules, as shown in an embodiment of the present invention;

[0014] Figure 7 This is a schematic diagram illustrating the execution of backup operations and the management of the backup status of entity units through a bit mapping table, according to an embodiment of the present invention.

[0015] Figure 8 This is a schematic diagram illustrating the execution of a restore operation and the management of the backup status of an entity unit through a bit mapping table, according to an embodiment of the present invention.

[0016] Figure 9 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0019] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0020] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0021] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0022] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0023] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0024] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0025] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0026] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0027] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0028] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuitry), which is not limited by the present invention.

[0029] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage units for non-volatile storage of data.

[0030] In one embodiment, an entity unit may include at least one entity programmable unit. For example, an entity programmable unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on an entity programmable unit to write data to that entity programmable unit, multiple memory cells in that entity programmable unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programmable unit, a write voltage may be applied to that entity programmable unit to change the threshold voltage of at least some of the memory cells in that entity programmable unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, an entity programmable unit is also referred to as an entity page. For example, the storage capacity of an entity programmable unit may be 16 kilobytes, and the invention is not limited thereto.

[0031] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0032] In one embodiment, a physical erase unit may include multiple physical programmable units. For example, the multiple physical programmable units in a physical erase unit may be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage may be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0033] In one embodiment, an entity unit may include at least one entity erasure unit. In another embodiment, if an entity unit includes multiple entity erasure units, this entity unit is also referred to as a virtual block. Multiple entity erasure units contained in the same virtual block can operate synchronously.

[0034] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A), 301(A+1)-301(B), and 301(B+1)-301(C) with the data area 31, the idle area 32, and the backup area 33, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. Entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data). Furthermore, entity units 301(B+1)-301(C) in the backup area 33 are used to store backup data (also referred to as backed-up data).

[0035] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0036] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0037] In one embodiment, the memory control circuit 23 can perform a backup operation on at least one physical unit (also referred to as a first physical unit) in the data area 31. During the backup operation on the first physical unit, the memory control circuit 23 can select at least one physical unit from the data area 31 as the first physical unit and select at least one physical unit (also referred to as a second physical unit) from the idle area 32. Then, the memory control circuit 23 can back up the data stored in the first physical unit to the second physical unit. After backing up the data stored in the first physical unit to the second physical unit, the memory control circuit 23 can associate the second physical unit with the backup area 33. Furthermore, units 301(B+1)-301(C) in the backup area 33 can await restoration.

[0038] In one embodiment, the memory control circuit 23 may perform a restore operation on at least one physical unit (e.g., a second physical unit) in the backup area 33. In the restore operation performed on the second physical unit, the memory control circuit 23 may reassociate the second physical unit to the data area 31 to replace at least one physical unit (e.g., a first physical unit) in the data area 31.

[0039] In one embodiment, the memory control circuit 23 may be configured with a plurality of logic units 302(1)-302(D) to map physical units in the data area 31 and / or the backup area 33. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0040] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0041] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0042] In one embodiment, during the backup operation of the first physical unit, the memory control circuit 23 may maintain a mapping relationship (also referred to as a first mapping relationship) between at least one logical unit (also referred to as a first logical unit) and the first physical unit. The memory control circuit 23 may access the first physical unit according to the first mapping relationship to read, update, or delete data belonging to the first logical unit.

[0043] In one embodiment, during the backup operation of the first physical unit, the memory control circuit 23 may also establish a mapping relationship (also referred to as a second mapping relationship) between the first logic unit and the second physical unit. It should be noted that this second mapping relationship will be in an inactive state before the restore operation is performed on the second physical unit. For example, in this inactive state, the second mapping relationship will not be used (i.e., it will be ignored).

[0044] In one embodiment, during the restoration operation of the second entity unit, the memory control circuit 23 can remove the first mapping relationship and enable the second mapping relationship. After enabling the second mapping relationship, the second mapping relationship can switch from an inactive state to an enabled state. In the enabled state, the second mapping relationship can be used to replace the first mapping relationship. Subsequently, the memory control circuit 23 can access the second entity unit according to the second mapping relationship to read, update, or delete data belonging to the first logic unit.

[0045] In one embodiment, the memory control circuit 23 may acquire at least one index (also referred to as a reference index). Based on this reference index, the memory control circuit 23 may adjust backup rules for at least a portion of the data currently stored in the memory module 122 (also referred to as backup data). For example, the backup data may include at least a portion of the data currently stored in the data area 31. For example, this backup rule may be used to influence the selection strategy of the memory control circuit 23 for the backup data and / or the data backup strategy when backing up the backup data. Then, the memory control circuit 23 may perform a backup operation on the backup data in the memory module 122 according to this backup rule.

[0046] In one embodiment, the reference metric may include a popularity metric. This popularity metric reflects the popularity distribution of the data to be backed up. For example, assuming the data to be backed up includes a certain data (also referred to as first data), the popularity distribution reflects the popularity of the first data. Alternatively, assuming the data to be backed up includes first data and another data (also referred to as second data), the popularity distribution reflects the relative popularity between the first data and the second data. For example, this relative popularity relationship may reflect that the first data is more popular than the second data, or the second data is more popular than the first data.

[0047] In one embodiment, the memory control circuit 23 can determine the "popularity" of the target data based on the number or frequency with which data belonging to a specific logic unit (also referred to as target data) has been accessed (e.g., read or updated) over a past period. For example, the popularity of the target data can be positively correlated with the number or frequency of accesses over a past period. A higher number or frequency of accesses over a past period indicates higher popularity of the target data. Conversely, a lower number or frequency of accesses over a past period indicates lower popularity (i.e., less popular). The memory control circuit 23 can then set a popularity index corresponding to the target data based on its popularity.

[0048] In one embodiment, the memory control circuit 23 can obtain an evaluation value (also known as a popularity evaluation value) corresponding to the target data based on the number of times or frequency of access to the target data over a past period. This popularity evaluation value is positively correlated with the popularity of the target data. That is, the larger the popularity evaluation value, the higher the popularity of the target data.

[0049] In one embodiment, the memory control circuit 23 can compare a popularity assessment value corresponding to the target data with a threshold value (also called a popularity threshold) to obtain a comparison result. This comparison result reflects the relative relationship between the popularity assessment value and the popularity threshold value. Then, the memory control circuit 23 can determine whether the target data belongs to hot data or cold data based on this comparison result. Hot data has a higher popularity than cold data. For example, if the comparison result shows that the popularity assessment value is greater than the popularity threshold value, the memory control circuit 23 can determine that the target data belongs to hot data. Conversely, if the comparison result shows that the popularity assessment value is not greater than the popularity threshold value, the memory control circuit 23 can determine that the target data belongs to cold data.

[0050] In one embodiment, the memory control circuit 23 can input the popularity evaluation value corresponding to the target data into a specific algorithm or lookup table to obtain the popularity index corresponding to the target data. For example, after inputting the popularity evaluation value corresponding to the target data into a specific algorithm or lookup table, the memory control circuit 23 can obtain the popularity index corresponding to the target data based on the output of this specific algorithm or lookup table.

[0051] In one embodiment, the memory control circuit 23 can record multiple heat indicators corresponding to multiple data points in a management table (also called a heat distribution table). Each heat indicator can reflect the heat or data type of the corresponding data (e.g., hot data or cold data). Taking target data as an example, the heat indicators corresponding to the target data can reflect the heat of the target data through different tag values.

[0052] In one embodiment, the popularity index may include a single bit. For example, if the popularity index corresponding to the target data is "1", it indicates that the target data is hot data; if the popularity index corresponding to the target data is "0", it indicates that the target data is cold data.

[0053] In one embodiment, the popularity index can also reflect the different levels of popularity of the target data through a combination of multiple bits. For example, if the popularity index corresponding to the target data is "11", it means that the target data is the most popular data; if the popularity index corresponding to the target data is "10", it means that the target data is the second most popular data; if the popularity index corresponding to the target data is "01", it means that the target data is the second least popular data; and if the popularity index corresponding to the target data is "00", it means that the target data is the least popular data. However, the way the popularity index is used can also be adjusted according to practical needs, and this invention does not limit it.

[0054] In one embodiment, the reference metric may further include a load metric. This load metric reflects the load level of the storage device 12. For example, the load level of the storage device 12 may be positively correlated with the current busy level of the storage device 12. That is, the higher the current busy level of the storage device 12, the higher the load level of the storage device 12 is likely to be. Conversely, the lower the current busy level of the storage device 12, the lower the load level of the storage device 12 is likely to be (i.e., more idle).

[0055] In one embodiment, the memory control circuit 23 can monitor the interface status of the storage device 12 and / or the operating status of the memory module 122 to determine the load level of the storage device 12. Then, the memory control circuit 23 can obtain this load index based on the load level of the storage device 12.

[0056] In one embodiment, the interface status of storage device 12 can reflect the total amount of data and / or instructions transferred between host system 11 and storage device 12 over a past period. This total amount can be positively correlated with the load level of storage device 12. That is, if the total amount of data and / or instructions transferred between host system 11 and storage device 12 is high over a past period, it indicates that the load level of storage device 12 is higher (i.e., the storage device 12 is busier). In one embodiment, memory control circuit 23 can obtain the load index based on the interface status of storage device 12.

[0057] In one embodiment, the operating state of the memory module 122 can reflect whether the memory module 122 is currently busy or idle. In another embodiment, the operating state of the memory module 122 can also reflect the total number (e.g., depth) of instructions pending processing in the buffer queue (or instruction queue) of the memory module 122. The higher the total number (or the deeper the depth), the longer the memory module 122 is expected to remain busy. In one embodiment, the memory control circuit 23 can obtain load indicators based on the operating state of the memory module 122.

[0058] In one embodiment, the memory control circuit 23 can input parameters representing the interface state of the storage device 12 and / or the operating state of the memory module 122 into a specific algorithm or lookup table to obtain load indicators. For example, after inputting parameters representing the interface state of the storage device 12 and / or the operating state of the memory module 122 into a specific algorithm or lookup table, the memory control circuit 23 can obtain load indicators based on the output of this specific algorithm or lookup table.

[0059] In one embodiment, the reference metric may further include a free window length metric. This free window length metric reflects the measured or predicted duration (also known as the target duration) of the memory module 122 being idle. For example, the memory control circuit 23 may measure or predict this target duration based on the interface status of the storage device 12 and / or the operating status of the memory module 122. Then, the memory control circuit 23 may obtain the free window length metric based on this target duration.

[0060] In one embodiment, the target duration may be negatively correlated with the load level of the storage device 12. That is, the higher the load level of the storage device 12, the shorter the target duration may be (i.e., the shorter the idle time of the memory module 122 under relatively busy conditions). Conversely, the lower the load level of the storage device 12, the longer the target duration may be (i.e., the longer the idle time of the memory module 122 under relatively idle conditions).

[0061] In one embodiment, the memory control circuit 23 can input parameters representing the interface state of the storage device 12 and / or the operating state of the memory module 122 into a specific algorithm or lookup table to obtain a free window length index. For example, after inputting parameters representing the interface state of the storage device 12 and / or the operating state of the memory module 122 into a specific algorithm or lookup table, the memory control circuit 23 can obtain the free window length index based on the output of this specific algorithm or lookup table.

[0062] In one embodiment, the memory control circuit 23 can adjust the backup rules for the data to be backed up based on at least one of the aforementioned multiple reference indicators. In another embodiment, the aforementioned multiple reference indicators can also be adjusted according to practical needs, and the present invention does not impose any limitations on this.

[0063] In one embodiment, the backup rules for the data to be backed up can affect the backup frequency for a specific piece of data (also referred to as the first target data) within the data to be backed up. In other words, in one embodiment, the memory control circuit 23 can determine (e.g., adjust) the backup frequency for the first target data based on at least one reference indicator.

[0064] In one embodiment, if at least one reference indicator reflects that the first target data is hot data (or the first target data has a relatively high popularity), the memory control circuit 23 can increase the backup frequency for the first target data based on the at least one reference indicator. For example, assuming that the system's preset data backup frequency is once every five days, the memory control circuit 23 can set (e.g., increase) the backup frequency for the first target data (e.g., hot data) to once every three days (also referred to as the first backup frequency).

[0065] On the other hand, if at least one reference indicator reflects that the first target data is cold data (or the first target data has relatively low popularity), the memory control circuit 23 can reduce the backup frequency for the first target data based on at least one reference indicator. For example, assuming the system's preset data backup frequency is once every five days, the memory control circuit 23 can set (e.g., reduce) the backup frequency for the first target data (e.g., cold data) to once every seven days (also referred to as the second backup frequency). The first backup frequency can be higher than the second backup frequency. Furthermore, both the first and second backup frequencies can be adjusted according to practical needs.

[0066] In one embodiment, the backup rules for the data to be backed up can also affect the proportion of different types of data backed up within a time window (also known as a target time window) during the backup operation. In other words, in one embodiment, it is assumed that the data to be backed up simultaneously contains a first type of data (e.g., hot data) and a second type of data (e.g., cold data). The memory control circuit 23 can adjust the proportion of the first type of data and the second type of data backed up within the target time window during the backup operation based on at least one reference index.

[0067] In one embodiment, the memory control circuit 23 can set the backup strategy for the data to be backed up according to at least one reference index, such that whenever K pieces of first-type data are backed up, P pieces of second-type data are backed up accordingly, and the ratio of K to P conforms to a preset ratio. For example, the ratio of K to P can be 2:1, 3:1, 4:1, or 5:1, etc., and the present invention is not limited thereto.

[0068] In one embodiment, the memory control circuit 23 can determine the ratio of K to P based on the heat ratio of a first type of data (e.g., hot data) to a second type of data (e.g., cold data) in the data to be backed up. For example, assume that the first type of data and the second type of data in the data to be backed up correspond to a first heat evaluation value H(1) and a second heat evaluation value H(2), respectively. The memory control circuit 23 can determine the ratio of K to P (i.e., K / P) based on the ratio of the first heat evaluation value H(1) to the second heat evaluation value H(2) (i.e., the heat ratio, H(1) / H(2)). For example, the memory control circuit 23 can set the ratio of K to P to be the same as the ratio of the first heat evaluation value H(1) to the second heat evaluation value H(2).

[0069] In one embodiment, the backup rules for the data to be backed up can also affect the window length of the target time window used to perform the backup operation. In other words, in one embodiment, the memory control circuit 23 can adjust the window length of the target time window used to perform the backup operation based on at least one reference index.

[0070] In one embodiment, if at least one reference metric indicates that the load on storage device 12 is low and / or the estimated idle time of memory module 122 is long, the memory control circuit 23 may increase the window length of the target time window for performing the backup operation. Conversely, if at least one reference metric indicates that the load on storage device 12 is high and / or the estimated idle time of memory module 122 is short, the memory control circuit 23 may decrease the window length of the target time window for performing the backup operation.

[0071] In one embodiment, the memory control circuit 23 may further determine (or adjust) the total amount of data to be backed up within the target time window based on the window length of the target time window (and / or at least one reference indicator). For example, this total amount of data may be positively correlated with the window length of the target time window. That is, the longer the window length of the target time window, the more the memory control circuit 23 may increase the total amount of data to be backed up within the target time window. Conversely, the shorter the window length of the target time window, the less the total amount of data to be backed up within the target time window.

[0072] In one embodiment, the memory control circuit 23 may further determine the data type of the data to be backed up within the target time window based on the window length of the target time window (and / or at least one reference indicator). For example, the memory control circuit 23 may determine, based on the window length of the target time window (or at least one reference indicator), whether to back up only the first type of data (e.g., hot data) or to back up both the first type of data and the second type of data (e.g., cold data) simultaneously within the target time window. For example, when the estimated window length of the target time window is less than a preset time length, the memory control circuit 23 may determine the backup rule corresponding to the target time window to back up only the first type of data (e.g., hot data). Alternatively, when the estimated window length of the target time window is not less than the preset time length, the memory control circuit 23 may determine the backup rule corresponding to the target time window to back up both the first type of data and the second type of data (e.g., cold data) simultaneously.

[0073] Figure 4 This is a schematic diagram illustrating the execution of a backup operation according to backup rules, as shown in an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, the memory control circuit 23 may determine (or adjust) a backup rule 41 for the data to be backed up based on at least one reference index. Subsequently, the memory control circuit 23 may select entity units (also referred to as target entity units) 401(1)-401(E) to be backed up from the data area 31 according to the backup rule 41, and / or back up the data (i.e. the data to be backed up) stored in entity units 401(1)-401(E) to the backup area 33.

[0074] In other words, in Figure 4 In the embodiments described, backup rule 41 can be used to influence the selection strategy of the memory control circuit 23 for the entity units 401(1)-401(E) to be backed up, and / or the data backup strategy for backing up the data (i.e., the data to be backed up) stored in the entity units 401(1)-401(E) to the backup area 33. For example, according to backup rule 41, the memory control circuit 23 can preferentially select entity units containing first type of data from the data area 31 as target entity units to prioritize the backup of the first type of data, and / or can dynamically control the data backup ratio for entity units containing different types of data in the target entity units, etc. The relevant operational details have been described above and will not be repeated here.

[0075] Figure 5 This is a schematic diagram illustrating the execution of a backup operation according to backup rules, as shown in an embodiment of the present invention. Please refer to... Figure 5In one embodiment, it is assumed that entity units 501 and 502 in data area 31 store a first type of data (e.g., hot data) and a second type of data (e.g., cold data), respectively. The memory control circuit 23 can then perform backup according to a determined backup rule (e.g., ...). Figure 4 Backup rule 41) stipulates that within the target time window, the ratio of first-type data to second-type data in the backup data should be controlled at 3:1. That is, whenever three data entries (i.e., first-type data) are backed up from entity unit 501 to entity unit 511 in backup area 33, one corresponding data entry (i.e., second-type data) should be backed up from entity unit 502 to entity unit 512 in backup area 33 to comply with the determined backup rule. It should be noted that... Figure 5 In the embodiments, the ratio of the first type of data to the second type of data can also be 2:1, 4:1 or other ratios, which are not limited by the present invention.

[0076] Figure 6 This is a schematic diagram illustrating the execution of a backup operation according to backup rules, as shown in an embodiment of the present invention. Please refer to... Figure 6 In one embodiment, between time points T(1) and T(2), assuming that memory module 122 is relatively busy, then according to the determined backup rules (e.g., Figure 4 According to backup rule 41), the memory control circuit 23 can set (e.g., shorten) the window length of the target time window 61 used to perform the backup operation to ΔT(1). Simultaneously, the memory control circuit 23 can, according to the determined backup rule (e.g., ... Figure 4 Backup rule 41 is used to determine how to perform the backup operation within the target time window 61. The relevant operational details have been described above and will not be repeated here.

[0077] On the other hand, between time points T(3) and T(4), assuming that memory module 122 is relatively idle, then according to the determined backup rules (e.g. Figure 4 According to backup rule 41), the memory control circuit 23 can set (e.g., extend) the window length of the target time window 62 used to perform the backup operation to ΔT(2) (ΔT(2) is greater than ΔT(1)). Simultaneously, the memory control circuit 23 can, according to the determined backup rule (e.g., ... Figure 4 Backup rule 41 is used to determine how to perform the backup operation within the target time window 62. The relevant operational details have been described above and will not be repeated here.

[0078] In one embodiment, the memory control circuit 23 can establish a bit mapping table. This bit mapping table can record multiple bits. The multiple bits can each correspond to multiple data entries in the data to be backed up. In response to the fact that at least a portion of the data to be backed up (e.g., the first data) has been backed up in the backup operation, the memory control circuit 23 can update the bit corresponding to the first data (also referred to as the first bit) among the multiple bits. Thus, the memory control circuit 23 can efficiently manage and / or perform backup and / or restore operations according to this bit mapping table.

[0079] Figure 7 This is a schematic diagram illustrating the execution of backup operations and the management of the backup status of entity units through a bit mapping table, according to an embodiment of the present invention. Please refer to... Figure 7 In one embodiment, the memory control circuit 23 can establish a bit mapping table 71. Multiple bits in the bit mapping table 71 can be used to record multiple status codes corresponding to entity units 701(1)-701(N). For example, the status code corresponding to entity unit 701(i) can reflect whether the data stored in entity unit 701(i) (i.e., the data to be backed up) has been backed up completely. Similarly, the status codes in the bit mapping table 71 can respectively reflect the data backup status corresponding to entity units 701(1)-701(N). Furthermore, assuming that the initial value of multiple bits (i.e., status codes) in the bit mapping table 71 is all "0", it indicates that the data stored in entity units 701(1)-701(N) has not been backed up.

[0080] In one embodiment, it is assumed that the memory control circuit 23 selects physical cell 701(i) from physical cells 701(1)-701(N) for backup (that is, backs up the data stored in physical cell 701(i) to...). Figure 3 Backup area 33). For example, a backup operation performed on entity unit 701(i) includes backing up data stored in entity unit 701(i) to entity unit 701(j).

[0081] After completing the backup operation for entity cell 701(i), the memory control circuit 23 can update the bit map table 71 to change the bit (i.e., status code) corresponding to entity cell 701(i) from "0" to "1". Thus, the updated bit map table 71 reflects that the backup operation for entity cell 701(i) has been completed.

[0082] On the other hand, assuming that entity unit 701(i) is currently mapped to logic unit 702(i) (i.e., the data currently stored in entity unit 701(i) belongs to logic unit 702(i)), the memory control circuit 23 can retain the mapping relationship between entity unit 701(i) and logic unit 702(i) in the mapping table 72. Furthermore, in response to the data stored in entity unit 701(i) being backed up to entity unit 701(j), the memory control circuit 23 can record the mapping relationship between entity unit 701(j) and logic unit 702(i) in the mapping table 73. However, it should be noted that before performing a restore operation on entity unit 701(j), the mapping relationship between entity unit 701(j) and logic unit 702(i) in the mapping table 73 will be in an inactive state.

[0083] Figure 8 This is a schematic diagram illustrating the execution of a restore operation and the management of the backup status of an entity unit via a bit mapping table, according to an embodiment of the present invention. Please refer to... Figure 8 In one embodiment, after performing a backup operation on entity unit 701(i), memory control circuit 23 can perform a restore operation on entity unit 702(i). For example, in this restore operation, memory control circuit 23 can remove the mapping relationship between entity unit 701(i) and logic unit 702(i) in mapping table 72, and enable the mapping relationship between entity unit 701(j) and logic unit 702(i) in mapping table 73.

[0084] After enabling the mapping relationship between entity unit 701(j) and logic unit 702(i) in mapping table 73, the mapping relationship between entity unit 701(j) and logic unit 702(i) in mapping table 73 can be used to replace the mapping relationship between entity unit 701(i) and logic unit 702(i) in mapping table 72. Subsequently, memory control circuit 23 can access entity unit 701(j) according to the mapping relationship between entity unit 701(j) and logic unit 702(i) in mapping table 73 to read, update, or delete data belonging to logic unit 702(i).

[0085] Furthermore, after completing the restoration operation for entity 701(j), the memory control circuit 23 can set the bit (i.e., status code) corresponding to entity 701(j) in the bit map table 71 to "0". When the next backup operation is performed on entity 701(j), the memory control circuit 23 can set the bit (i.e., status code) corresponding to entity 701(j) in the bit map table 71 to "1".

[0086] In one embodiment, the memory control circuit 23 can quickly determine the bit mapping table 71 by maintaining, updating, and querying the bit mapping table 71. Figure 3 The memory control circuit 23 checks whether the data stored in each or at least part of the physical units in data area 31 has been backed up. If the information in bitmap table 71 indicates that the data stored in a certain physical unit has not been backed up, the memory control circuit 23 can back up this data according to dynamically determined backup rules. However, if the information in bitmap table 71 indicates that the data stored in a certain physical unit has already been backed up, the memory control circuit 23 can skip this physical unit directly in the next backup operation to avoid repeatedly backing up the same data.

[0087] In one embodiment, the memory control circuit 23 can acquire at least one evaluation metric. The at least one evaluation metric can reflect the backup status. Figure 3 The validity of specific data (also known as backed-up data) in backup area 33. Figure 7 For example, the backed-up data may include data backed up from entity unit 701(i) to entity unit 701(j) through a backup operation.

[0088] In one embodiment, at least one evaluation metric may include at least one of an age metric, a data change metric, a storage cost metric, and a restore success metric, as explained below:

[0089] (1) Age indicator, which reflects the storage duration of backed-up data. This age indicator reflects how long has passed since the backed-up data was backed up to backup area 33 (i.e., storage duration, such as hours or days). The storage duration of backed-up data is negatively correlated with the validity (or value) of the backed-up data. That is, the longer the storage duration of backed-up data, the lower the validity (or value) of the backed-up data.

[0090] (2) Data Change Indicators, which reflect the data change status of backed-up data. These indicators show the number or frequency at which the backed-up data (or data belonging to the same logical unit as the backed-up data) has been updated since it was backed up to backup area 33. This number or frequency is negatively correlated with the validity (or value) of the backed-up data. That is, the higher the number or frequency, the lower the validity (or value) of the backed-up data.

[0091] (3) Storage cost metric, which reflects the storage cost of backed-up data. This storage cost metric reflects the cost required to store backed-up data. For example, this cost can be expressed in terms of the storage space occupied by the backed-up data, but the present invention is not limited to this. Any parameter that can reflect the storage cost of backed-up data can be used as this storage cost metric. The storage cost of backed-up data is negatively correlated with the validity (or value) of the backed-up data. That is, the higher the storage cost of the backed-up data (e.g., the more storage space the backed-up data occupies), the lower the validity (or value) of the backed-up data.

[0092] (4) Restore Success Indicator: This indicator reflects whether the backed-up data has been used in a successful restore operation. This indicator shows whether the backed-up data has been used in at least one successful restore operation. If yes (i.e., the backed-up data has been used in at least one successful restore operation), the validity (or value) of the backed-up data is higher. If no (i.e., the backed-up data has not been used in at least one successful restore operation or the backed-up data has experienced a restore failure), the validity (or value) of the backed-up data is lower.

[0093] In one embodiment, the memory control circuit 23 may determine whether to delete backed-up data based on at least one evaluation metric. For example, based on at least one evaluation metric, the memory control circuit 23 may identify backed-up data with the lowest or relatively low validity from the backup area 33. The memory control circuit 23 may then delete this backed-up data with the lowest or relatively low validity.

[0094] In one embodiment, the memory control circuit 23 can obtain a validity parameter corresponding to a specific backed-up data according to the following formulas (1)-(5). This validity parameter reflects the validity of the specific backed-up data. The memory control circuit 23 can determine whether to delete this specific backed-up data based on this validity parameter.

[0095] S1 = 1 / (1 + P1) (1)

[0096] S2 = 1 / (1 + P2) (2)

[0097] S3 = 1 / (1 + P3) (3)

[0098] S4 = P4 (4)

[0099] S = S1 × W1 + S2 × W2 + S3 × W3 + S4 × W4 (5)

[0100] In formulas (1)-(5), P1 corresponds to the age indicator, P2 corresponds to the data change indicator, P3 corresponds to the storage cost indicator, and P4 corresponds to the restore success indicator. P1, P2, and P3 can be parameter values ​​representing the storage duration of the backed-up data, the data change status of the backed-up data, and the storage cost of the backed-up data, respectively. P4 can be "1" (indicating that the backed-up data has been used for at least one successful restore operation) or "0" (indicating that the backed-up data has not been used for at least one successful restore operation or that the backed-up data has experienced a restore failure). Furthermore, S represents the validity parameter corresponding to a specific backed-up data.

[0101] In one embodiment, the memory control circuit 23 can sort the backed-up data according to validity parameters corresponding to multiple backed-up data entries, from largest to smallest or smallest to largest, to obtain a sorting result. Then, the memory control circuit 23 can prioritize deleting the backed-up data with the lowest or relatively low validity based on this sorting result. As a result, usable space in the backup area 33 can be appropriately freed up.

[0102] In one embodiment, the memory control circuit 23 can automatically detect whether a fault event or an abnormal event is about to occur. In response to an impending fault event or abnormal event, the memory control circuit 23 can initiate a backup operation (also known as an emergency backup operation).

[0103] In one embodiment, the memory control circuit 23 may record a triggering factor for initiating the (emergency) backup operation based on the type of the detected impending fault or abnormal event. For example, this triggering factor may include:

[0104] (1) The temperature of storage device 12 is detected to be too high;

[0105] (2) At least one read error was detected for specific data;

[0106] (3) A firmware code error was detected for storage device 12.

[0107] It should be noted that the above-mentioned triggering factors can be adjusted according to practical needs, and this invention does not impose any limitations on them.

[0108] In one embodiment, by triggering a preventative (emergency) backup operation, the memory control circuit 23 can attempt to perform an emergency backup (also known as a preventative backup) of at least a portion of the data in the memory module before a serious system failure or error actually occurs. Thus, even if a more serious system failure or error subsequently occurs, after the storage device 12 is restarted, the memory control circuit 23 can perform a restore operation based on the backup data obtained from the previous preventative backup to attempt to restore at least a portion of the data in the storage device 12 to its normal state before the failure or error occurred.

[0109] In one embodiment, before performing the restore operation, the memory control circuit 23 may determine at least one backed-up data (also referred to as the second target data) from multiple backed-up data (also referred to as candidate backed-up data) in the backup area 33 according to a recorded trigger factor. Then, the memory control circuit 23 may perform the restore operation based on the second target data. For operational details regarding the restore operation, please refer to... Figure 8 The embodiments are not repeated here.

[0110] In one embodiment, before performing the restore operation, the memory control circuit 23 may determine the cause of a previously occurring fault or abnormal event. The memory control circuit 23 may compare this cause with a trigger factor corresponding to at least one backed-up data in the backup area 33 to obtain a comparison result. Then, based on this comparison result, the memory control circuit 23 may determine the backed-up data whose trigger factor matches the cause as second target data. The memory control circuit 23 may then perform a restore operation based on the second target data to attempt to restore at least a portion of the data in the storage device 12 to its normal state before the fault or error occurred.

[0111] In one embodiment, it is assumed that the cause of the previous fault or abnormal event was that the temperature of the storage device 12 was too high (e.g., the temperature was above a temperature threshold), resulting in a system failure. After the storage device 12 is restarted, the memory control circuit 23 can determine the backed-up data with the trigger factor of type (1) (detection of excessive temperature of storage device 12) as the second target data based on the comparison results described above.

[0112] Alternatively, suppose the cause of the previous fault or abnormal event was that the number of read errors for specific data on storage device 12 was too frequent (e.g., the number of read errors exceeded a threshold), causing the system to be unable to read the necessary data and thus malfunctioning. After storage device 12 is restarted, memory control circuit 23 can determine the backed-up data with trigger factor of type (2) (at least one read error for specific data was detected) as the second target data based on the comparison results described above.

[0113] Alternatively, suppose that the cause of the previous fault or abnormal event was a firmware error in the storage device 12, which caused the storage device 12 to malfunction. After the storage device 12 is restarted, the memory control circuit 23 can determine the backed-up data with the trigger factor of type (3) (a firmware error was detected for the storage device 12) as the second target data based on the comparison results described above.

[0114] In one embodiment, if the comparison results show that no matching backed-up data can be obtained, the memory control circuit 23 can directly determine the backed-up data whose backup time is closest to the current time as the second target data. For example, each piece of backed-up data can be bound to a timestamp. This timestamp can reflect the backup time of the corresponding backed-up data (i.e., the creation time of the backed-up data).

[0115] After determining the second target data, the memory control circuit 23 can perform a restoration operation based on the second target data. Thus, for fault events or abnormal events of different causes, at least a portion of the data in the storage device 12 can be restored to the normal state before the fault or error occurred (or during emergency backup).

[0116] In one embodiment, the memory control circuit 23 can implement or replace the decisions involved in any of the above-described operational behaviors through an artificial intelligence model. Thus, the self-learning capability of the artificial intelligence model can continuously optimize the relevant decision logic, thereby improving the efficiency of backup and / or restore operations.

[0117] Figure 9 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 9 In step S901, at least one reference indicator is obtained, including a popularity indicator that reflects the popularity distribution of the data to be backed up. In step S902, the backup rules for the data to be backed up are adjusted based on the at least one reference indicator. In step S903, the backup operation for the data to be backed up is performed in the storage module according to the backup rules.

[0118] However, Figure 9 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 9 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 9 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0119] In summary, the memory management method and storage device proposed in this invention can measure the current operating status of the storage device through various reference indicators, thereby dynamically determining or adjusting the backup rules used to perform backup operations (e.g., backing up only data that meets the conditions and / or adjusting backup rules for different types of data). Furthermore, by combining emergency backup with trigger factors and subsequent restore mechanisms, at least a portion of the data in the storage device can be accurately restored to its normal state before the system failure or error occurred, without blindly restoring all data in the entire system or storage device.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For use in a storage device, wherein the storage device includes a memory module, and the memory management method includes: Obtain at least one reference indicator, wherein the at least one reference indicator includes a popularity indicator, which reflects the popularity distribution of the data to be backed up; Adjust the backup rules for the data to be backed up based on the at least one reference indicator; and According to the backup rules, a backup operation is performed on the data to be backed up in the memory module.

2. The memory management method according to claim 1, wherein the step of adjusting the backup rule for the data to be backed up according to the at least one reference indicator includes: The backup frequency for the first target data in the data to be backed up is determined based on the at least one reference indicator.

3. The memory management method according to claim 1, wherein the step of adjusting the backup rule for the data to be backed up according to the at least one reference indicator includes: Based on the at least one reference metric, adjust the ratio of the first type of data to the second type of data that are backed up within the target time window during the execution of the backup operation.

4. The memory management method according to claim 1, wherein the step of adjusting the backup rule for the data to be backed up according to the at least one reference indicator includes: The window length of the target time window used to perform the backup operation is adjusted according to the at least one reference indicator.

5. The memory management method according to claim 1, wherein the at least one reference indicator further includes a load indicator, and the load indicator reflects the load level of the memory device.

6. The memory management method according to claim 1, further comprising: A bit mapping table is established, which records multiple bits, and the multiple bits correspond to multiple data entries in the data to be backed up; as well as In response to the fact that the first data in the data to be backed up has been backed up in the backup operation, the first bit in the plurality of bits corresponding to the first data is updated.

7. The memory management method according to claim 1, further comprising: Obtain at least one evaluation metric, wherein the at least one evaluation metric reflects the effectiveness of the backed-up data; as well as Based on at least one of the evaluation metrics, determine whether to delete the backed-up data.

8. The memory management method according to claim 7, wherein the at least one evaluation index includes at least one of an age index, a data change index, a storage cost index, and a restore success index. The age indicator reflects the storage duration of the backed-up data. The data change metrics reflect the data change status of the backed-up data. The storage cost metric reflects the storage cost of the backed-up data, and The restore success metric reflects whether the backed-up data was previously used to successfully perform a restore operation.

9. The memory management method according to claim 1, further comprising: Record the triggering factor used to initiate the backup operation; as well as Based on the triggering factor, a second target data is determined from multiple candidate backed-up data; as well as Based on the second target data, perform the restoration operation.

10. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the memory management method according to any one of claims 1-9.

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