High-speed data path optimization method and device, computer equipment and storage medium

Abstract

The embodiment of the invention provides an optimization method and device of a high-speed data path, computer equipment and a storage medium. The method comprises the steps that cache spaces of a ping-pong register and an output register are set in a buffer; if the cache space is empty, writing input data into the cache space, modifying an input write fifo interface and a fifo full flag bit interface into an input handshake interface, and modifying an output read fifo interface and a fifo empty flag bit interface into an output handshake interface; taking the maximum storage capacity of the internal effective count fifo as an additional newly-added output interface; if the fifo storage space is full, actively outputting data in the storage space, setting a stack cache space in an arbiter, taking the requests input at the same time as a request group, and putting the request group into the stack cache space according to an input sequence; and arbitration sorting is carried out on the request group, so that the problems of interface conversion, data routing and the like can be solved by combining an optimized buffer, a first-in first-out queue and an arbiter.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a method, apparatus, computer device, and storage medium for optimizing high-speed data paths. Background Technology

[0002] Current hot fields such as AI, 6G and autonomous driving all have computing power intensive requirements, and the mainstream solutions in the market are multi-core designs represented by GPUs and GPGPUs. In multi-core designs, the data supply, thread data interaction and inter-core data interaction of multiple computing units within the core are all complex and ever-changing data transmission and data processing requirements. How to efficiently meet these requirements is extremely important and urgent.

[0003] While related designs rely on buffers (buf), first-in-first-out queues (FIFO), and arbiters (arbiters), they suffer from several shortcomings: incomplete pipelining of detailed timing control leads to transmission efficiency losses; traditional interface forms lack flexibility in interface transmission control; sequentiality is lost during arbitration queuing; and non-uniform interface forms result in development and verification costs and insufficient timeliness for implementation when requirements are adjusted. Therefore, comprehensively addressing these issues is crucial for balancing the performance and development costs of interconnect implementations in high-speed data path processing. Summary of the Invention

[0004] This application provides a method, apparatus, computer device, and storage medium for optimizing high-speed data paths.

[0005] A first aspect of this application provides a method for optimizing a high-speed data path, comprising: Set up a ping-pong register and an output register in the buffer, and construct three buffer spaces corresponding to the ping-pong register and the output register; Given input data, determine if there is any empty space in the cache. If there is space in the cache, receive input data and write the input data into the cache according to preset rules.

[0006] In an optional embodiment of this application, the cache space includes a P cache space, a B cache space, and an output register. The P cache space and the B cache space are connected in parallel, and both the P cache space and the B cache space are connected to the output register. The step of writing input data into the cache space according to a preset principle includes: Whether to write input data to the output register depends on the data storage status of the output register; If it is impossible to write input data to the output register, write data alternately from the P buffer space to the P buffer space or the B buffer space. If the output register is free, data is alternately transferred from the P cache space and the B cache space to the output register, starting from the P cache space.

[0007] In an optional embodiment of this application, the method further includes: By redefining the interfaces, the input write first-in-first-out queue FIFO interface and the FIFO full flag interface are modified into input handshake interfaces, and the output read FIFO interface and the FIFO empty flag interface are modified into output handshake interfaces. The maximum storage capacity of the internal effective count FIFO is used as an additional output interface; Given input data, determine whether the storage space of the first-in-first-out queue is full; Receive input data when the storage space of the first-in-first-out queue is not full; If the storage space of the first-in-first-out queue is not empty, actively output the stored data in the storage space.

[0008] In an optional embodiment of this application, the method further includes: Set up a stack buffer in the arbitrator to record requests that come in simultaneously within each clock cycle as a group of requests. The request groups are placed into the stack cache space according to the order in which they were entered. If the stack cache is not empty, a request group data is popped and transmitted to the arbitration core for arbitration sorting. The arbitration result is output. During the arbitration process, if the corresponding request in the request group is finished being processed, the corresponding bit of the request is cleared until the bit of the last request in the current request group is cleared. Then the next request group data is popped from the stack cache.

[0009] In an optional embodiment of this application, the method further includes: During the interface conversion process, the input data is buffered to complete interface simplification and timing processing; The data output from the buffer is partially buffered by a first-in-first-out queue. Data output from the first-in-first-out (FIFO) queue is selectively passed through the FIFO queue and buffer after being converted by the interface.

[0010] In an optional embodiment of this application, the method further includes: During data processing, multiple out-of-order input data are split and buffered to complete interface simplification and timing processing. The out-of-order data output from the buffer is stored in multiple first-in-first-out queues, which serve as the operation space for out-of-order recovery. The data output from the first-in-first-out queue is output in a preset order or after passing through an arbitrator.

[0011] In an optional embodiment of this application, the method further includes: During the data routing process, the input data first passes through a buffer to complete the interface processing, and the data output from the buffer is stored in a first-in-first-out queue. If the preset data accumulation requirement is met in the first-in-first-out queue, data routing is completed through multiple cascaded arbitrators. Among them, buffers or first-in-first-out queues are selectively inserted between different cascaded arbitrators for data processing and timing optimization. Data that has completed data routing is output after passing through a buffer or a first-in-first-out queue.

[0012] A second aspect of this application provides an optimization apparatus for a high-speed data path, comprising: The module is used to set up the ping-pong register and the output register in the buffer, and to build the three buffer spaces corresponding to the ping-pong register and the output register. The judgment module is used to determine whether there is empty space in the cache when there is input data; The write module is used to receive input data and write it into the cache space according to preset rules when the cache space is empty.

[0013] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above-mentioned high-speed data path optimization methods.

[0014] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the high-speed data path optimization method as described in any of the preceding claims.

[0015] Compared with the prior art, the technical solutions provided in this application have at least some or all of the following advantages: The high-speed data path optimization method described in this application sets up a ping-pong register and an output register in the buffer, constructing three buffer spaces corresponding to the ping-pong register and the output register; when input data exists, it is determined whether there is empty space in the buffer space; when there is empty space in the buffer space, the input data is received and written into the buffer space according to a preset principle, which can achieve the timing control effect of pausing and resuming at any time in the continuous pipeline of the input and output handshake interface, thus meeting the data transmission efficiency requirements. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart illustrating a method for optimizing a high-speed data path according to an embodiment of this application; Figure 2 An optimized buffer implementation scheme and workflow diagram provided for one embodiment of this application; Figure 3 An optimized FIFO implementation scheme and workflow diagram provided in one embodiment of this application; Figure 4 An optimized arbiter implementation scheme and workflow diagram provided in one embodiment of this application; Figure 5 This is a schematic diagram of an interface conversion and combination scheme provided in one embodiment of this application; Figure 6 This is a schematic diagram of a data routing combination scheme provided in one embodiment of this application; Figure 7 This is a schematic diagram of a data processing combination scheme provided in one embodiment of this application; Figure 8 This is a schematic diagram of an optimized component combination provided in one embodiment of this application; Figure 9 A schematic diagram of the structure of a high-speed data path optimization device provided in one embodiment of this application; Figure 10 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0017] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0018] Please see Figure 1 The high-speed data path optimization method provided in this application includes the following steps S100~S300: S100 sets up a ping-pong register and an output register in the buffer, and constructs three buffer spaces corresponding to the ping-pong register and the output register; S200, when input data exists, determines whether there is empty space in the buffer; When the buffer space is empty, the S300 receives input data and writes the input data into the buffer space according to preset principles.

[0019] In an optional embodiment of this application, different forms of input are first simplified into a handshake interface (only valid information and valid flag signals are retained). Then, a ping-pong register and an output register are designed to form a buffer space of three units. The control is implemented according to the principle that the input can be received as long as the buffer space is empty, and the input and ping-pong registers are sent to the output register as long as they are not empty. In addition, a parameterized implementation is adopted, which can achieve the timing control effect of pausing and resuming at any time in the continuous pipeline of the input and output handshake interface, thus meeting the transmission efficiency requirements.

[0020] In an optional embodiment of this application, in step S300, the cache space includes a P cache space, a B cache space, and an output register. The P cache space and the B cache space are connected in parallel, and both the P cache space and the B cache space are connected to the output register. The step of writing input data into the cache space according to a preset principle includes: Whether to write input data to the output register depends on the data storage status of the output register; If it is impossible to write input data to the output register, write data alternately from the P buffer space to the P buffer space or the B buffer space. If the output register is free, data is alternately transferred from the P cache space and the B cache space to the output register, starting from the P cache space.

[0021] In an optional embodiment of this application, such as Figure 2 As shown, the P buffer space Pbuf, the B buffer space Bbuf, and the output register outreg represent three registers: the ping-pong register and the output register. Inputs are written to one of these three registers under the control of the control logic. Inputs and the ping-pong register are selectively written to outreg under control. The control implementation can be described as follows: inputs are preferentially written directly to outreg until the downstream register of outreg fails to retrieve them in time. Then, starting from Pbuf, they are alternately written to the ping-pong register for temporary storage. Outputs always follow the receiving order; that is, after outreg resumes reception, if the ping-pong register is not empty, it starts from Pbuf and alternately passes data from the ping-pong register to outreg. Inputs are triggered upstream; reception stops when all three internal spaces are full. Outputs are triggered by the control logic; when both inputs and the ping-pong register are detected to be non-empty, outputs are actively sent to outreg.

[0022] In an optional embodiment of this application, the method further includes: S400, through interface redefinition, modifies the input write first-in-first-out queue FIFO interface and FIFO full flag interface into input handshake interface, and modifies the output read FIFO interface and FIFO empty flag interface into output handshake interface; The S500 uses the maximum storage capacity of the internal effective count FIFO as an additional output interface. S600, when input data exists, determines whether the storage space of the first-in-first-out queue is full; The S700 receives input data when the storage space of the first-in-first-out queue is not full; and actively outputs the stored data in the storage space when the storage space of the first-in-first-out queue is not empty.

[0023] In an optional embodiment of this application, in the first-in-first-out queue, a handshake-style input / output interface is first designed and an output interface for identifying the internal capacity is added. The content storage space is parameterized and then controlled according to the principle that data can be received when the storage space is not full and actively output when it is not empty. This allows the timing control to meet the transmission efficiency in the full pipeline transmission of the interface, and also allows the downstream receiving side to perform more flexible reception control (such as multiplexing of a single data, selecting data for use, etc.) through the added capacity interface.

[0024] In an optional embodiment of this application, such as Figure 3 As shown, by redefining the interface, the input write FIFO interface and fifo_ful (NOT) are modified into input handshake interfaces, and the output read FIFO interface and fifo_empty (NOT delayed by one clock cycle) interface are modified into output handshake interfaces; in addition, the internal valid count fifo_capacity is introduced as an output interface, and the parameterized storage is implemented in the traditional FIFO method.

[0025] In an optional embodiment of this application, the method further includes: In the S800, a stack buffer is set up in the arbitrator. Requests that are entered simultaneously within each clock cycle are recorded as a group of requests. The request groups are then placed into the stack buffer according to their input order. In the S900, when the stack cache space is not empty, a request group data is popped and transmitted to the arbitration core for arbitration sorting, and the arbitration result is output. During the arbitration process, when the corresponding request in the request group is finished, the corresponding bit of the request is cleared until the bit of the last request in the current request group is cleared, and the next request group data is popped from the stack cache space.

[0026] In an optional embodiment of this application, a stack buffer space is first designed. Requests arriving simultaneously within each clock cycle are recorded as a request group (identified by a multi-bit signal) and pushed onto and popped off the stack in the order of arrival. The popped request groups are then sorted by an arbitration algorithm (with a replaceable part). Furthermore, the output interface is designed with parameters to control how many cycles it takes to output, based on a pipelined architecture. Thus, the stack space enables the recording of request sequences within a larger and more accurate time window, the replaceable arbitration algorithm mechanism adapts to different arbitration needs, and the output interface control provides more flexible interface timing control.

[0027] In an optional embodiment of this application, such as Figure 4 As shown, the arbitration core in the diagram represents the implementation of a certain arbitration rule, such as a polling rule. An optimized design is added to it: First, multiple inputs (requests in the form of single-cycle pulses) are processed in single clock cycles. Requests within the same cycle are concatenated bit-wise into a multi-bit data group, corresponding to the request group shown in the diagram. These are then sequentially placed into the stack space. When the stack space is not empty, a request group data is popped and sent to the arbitration core for arbitration sorting. The arbitration result is output (in level format, maintained until the current request ends). During arbitration, the corresponding bit within each request group is cleared to 0 when the request processing ends. This process continues until the current request group ends. When a request is cleared to 0, the stack space will pop the next request group data, and so on to implement the entire arbitration process; the direction of the arrow in the diagram is the workflow; in addition, there is the interface implementation. The upstream handshake VLD signal is first processed by the level-to-pulse conversion shown in the diagram to form a valid request. Then, when arbitration permission is obtained, it is ANDed with the downstream RDD signal and returned as the upstream RDD input; after that, the upstream and downstream may conduct several handshake transmissions of request data until the downstream internal receive count reaches the end of the current request (req_end), and outputs it to the arbiter to end the current request, allowing the arbiter to enter the next round of request arbitration process.

[0028] The high-speed data path optimization method proposed in this application designs three optimization components, each with independent yet complementary functions. In data transmission and processing scenarios, different combinations can be used to quickly meet the requirements. At the same time, the parameterization and modularization of the three components greatly simplifies the verification process while enabling rapid design implementation, reducing the task of comprehensive verification required in general designs to the verification of interface links. Thus, it provides an efficient and cost-effective solution for high-speed data transmission and processing in large-scale data designs.

[0029] In an optional embodiment of this application, the method further includes: During the interface conversion process, the input data is buffered to complete interface simplification and timing processing; The data output from the buffer is partially buffered by a first-in-first-out queue. Data output from the first-in-first-out (FIFO) queue is selectively passed through the FIFO queue and buffer after being converted by the interface.

[0030] In an optional embodiment of this application, during the interface conversion process, the input data is buffered to complete interface processing and request information extraction and temporary storage, and then sent to a first-in-first-out queue for temporary storage to meet the requirements of input interface pipeline and outstanding advance processing. After necessary conversion processing, it is output after passing through an optional first-in-first-out queue and buffer to meet the requirements of output interface timing, pipeline and outstanding advance processing.

[0031] In an optional embodiment of this application, in the interface conversion scenario, the downstream reception is uncertain, so the upstream request must be buffered by a first-in-first-out (FIFO) queue. At this time, the FIFO queue also serves as hardware support for the outstanding or pipelined requirements of the input end. For internal interfaces, their interface forms may be diverse. In this case, a buffer is used to unify and simplify the interface to the next step. In this way, by applying the buffer and the FIFO queue in the transmission conversion path, the entire conversion process is ensured to be fully pipelined to meet the transmission efficiency requirements. At the same time, the storage space of the FIFO queue is used to support the outstanding function, thereby further improving the transmission efficiency.

[0032] In an optional embodiment of this application, the method further includes: During data processing, multiple out-of-order input data are split and buffered to complete interface simplification and timing processing. The out-of-order data output from the buffer is stored in multiple first-in-first-out queues, which serve as the operation space for out-of-order recovery. The data output from the first-in-first-out queue is output in a preset order or after passing through an arbitrator.

[0033] In an optional embodiment of this application, during the data processing, taking out-of-order data recovery as an example, several first-in-first-out (FIFO) queues are selected as the operating space, and data flags are mapped to FIFO queues. After being processed by the buffer interface on the receiving side, the data is received and temporarily stored in the corresponding FIFO queue in an out-of-order manner. On the output side, the output of the FIFO queue is completed by an optional arbitrator or a fixed order, thereby completing the data order recovery.

[0034] In an optional embodiment of this application, in a data processing scenario, the core of the first-in-first-out queue caching capability is supplemented by the buffer interface processing capability, which is applied to a processing path. The intersection of multiple processing paths naturally leads to an arbitration scenario. At this time, an appropriate arbitration rule core can be selected according to the requirements, and the optimized design of this application can be used to ensure the correctness of the arbitration during the expected working period.

[0035] In an optional embodiment of this application, the method further includes: During the data routing process, the input data first passes through a buffer to complete the interface processing, and the data output from the buffer is stored in a first-in-first-out queue. If the preset data accumulation requirement is met in the first-in-first-out queue, data routing is completed through multiple cascaded arbitrators. Among them, buffers or first-in-first-out queues are selectively inserted between different cascaded arbitrators for data processing and timing optimization. Data that has completed data routing is output after passing through a buffer or a first-in-first-out queue.

[0036] In an optional embodiment of this application, during the data routing process, the input first passes through a buffer to complete interface processing, and then is sent to a first-in-first-out queue for temporary storage to meet possible data accumulation requirements; then, it passes through several cascaded arbitrators to complete data routing, and buffers or first-in-first-out queues can be inserted between the cascaded arbitrators to perform possible data processing and timing optimization; finally, it is output after passing through an optional first-in-first-out queue and buffer.

[0037] In an optional embodiment of this application, in a data routing scenario, requests from multiple parties may have different request interfaces in typical scenarios, and the transmitted data may be supplied in a pulsed manner. In this case, a buffer is used to unify and simplify the interface, a first-in-first-out queue is used to complete the smooth caching of data, and then an arbitrator is used to ensure that requests within a certain time window can be arbitrated and sorted according to the expected arbitration rules. Finally, the output stage can be supplemented by adding a first-in-first-out queue or a buffer according to the timing requirements.

[0038] In one optional embodiment of this application, the three optimized components—buf (buffer optimized), FIFO (first-in-first-out queue optimized), and arbiter optimized—can be combined into various implementation schemes, such as... Figures 5 to 8 As shown.

[0039] exist Figure 5 In the interface conversion combination scheme, the upstream input first passes through a buffer to complete interface simplification and timing processing, then passes through a first-in-first-out queue to buffer a certain amount of data to optimize transmission efficiency, and after interface conversion, it selectively passes through a first-in-first-out queue / first-in-first-out queue to meet the timing requirements of the output side.

[0040] exist Figure 6 In the data routing combination scheme, the upstream input is buffered to simplify the interface and handle timing. Then, a certain amount of data is buffered by a first-in-first-out queue to improve transmission efficiency while hiding the arbitration waiting overhead. Afterwards, there may be multi-cascaded arbitrators in complex situations. The arbitrators will pass through a first-in-first-out queue / buffer to meet the timing and transmission efficiency requirements. Finally, the arbitrator output passes through a first-in-first-out queue / buffer to meet the timing requirements of the output side.

[0041] exist Figure 7 In the data processing combination scheme, there are various data processing methods. Taking out-of-order recovery as an example, multiple out-of-order inputs are first split and buffered to complete interface simplification and timing processing, and the first-in-first-out queue is used as the operation space for out-of-order recovery. Then, the request generation stage means that a single-cycle pulse is generated as a request when a certain path is ready to complete (corresponding to the aforementioned level to pulse stage). The arbitration core is redefined according to the design requirements. For example, for out-of-order recovery, this is the expected return sequence generation logic.

[0042] Figure 8 It is a schematic diagram showing the combination of buffer optimization (buf), first-in-first-out queue optimization (fifo), and arbiter optimization (arbiter), which includes various possible combinations.

[0043] The high-speed data path optimization method of this application can quickly implement a specific solution by selecting a combination of the three optimization components mentioned above that meets the requirements. Furthermore, the implementation scheme based on the combination of the three optimization components can be used for interconnection implementation in high-speed data path processing inside the chip, providing an efficient and cost-effective implementation scheme that meets the diverse requirements for interconnection implementation in high-speed data path processing.

[0044] The high-speed data path optimization method of this application addresses the core requirements for high-speed data path implementation in current large-scale data processing chips, which include transmission efficiency, rapid adjustment to meet diverse needs, and rapid verification of complex paths. This method can ensure theoretically limit transmission efficiency through three optimized components, and the parameterized and unified interface design of the components can be flexibly combined to meet design requirement adjustments. The implementation scheme based on verified component combinations greatly simplifies the verification workload. Thus, an implementation scheme that balances efficiency, adjustability, implementation speed, and simplified verification is formed.

[0045] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0046] Please see Figure 9 One embodiment of this application provides a high-speed data path optimization device 900, comprising: Module 910 is used to set up the ping-pong register and the output register in the buffer, and to build the three buffer spaces corresponding to the ping-pong register and the output register. The judgment module 920 is used to determine whether there is empty space in the cache space when there is input data; The write module 930 is used to receive input data and write the input data into the buffer space according to preset principles when the buffer space is empty.

[0047] In an optional embodiment of this application, the apparatus further includes: Modify module 940 to redefine the interface by changing the input write first-in-first-out queue FIFO interface and the FIFO full flag interface to input handshake interfaces, and the output read FIFO interface and the FIFO empty flag interface to output handshake interfaces; and add the internal valid count FIFO maximum storage capacity as an additional output interface. The judgment module 920 is used to determine whether the storage space of the first-in-first-out queue is full when there is input data. The receiving module 950 is used to receive input data when the storage space of the first-in-first-out queue is not full; Output module 960 is used to actively output the stored data in the storage space when the storage space of the first-in-first-out queue is not empty.

[0048] In an optional embodiment of this application, the apparatus further includes: Setting module 970 is used to set up stack buffer space in the arbitrator, and to record requests that are entered simultaneously in each cycle as a group of requests in clock cycles. Module 980 is used to place request groups into the stack cache space according to the input order of the request groups; Arbitration module 990 is used to pop a request group data when the stack cache space is not empty, transmit it to the arbitration core for arbitration sorting, and output the arbitration result. During the arbitration process, when the corresponding request in the request group is finished, the corresponding bit of the request is cleared until the bit of the last request in the current request group is cleared, and then the next request group data is popped from the stack cache space.

[0049] For specific limitations regarding the aforementioned device 900, please refer to the limitations of the optimization method for high-speed data paths described above, which will not be repeated here. Each module in the aforementioned device 900 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the operations corresponding to each module.

[0050] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 10 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the high-speed data path optimization method described above. This includes: a memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the high-speed data path optimization method described above.

[0051] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can implement any step of the above-described method for optimizing high-speed data paths.

[0052] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0053] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0056] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0057] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for optimizing a high-speed data path, characterized in that, include: Set up a ping-pong register and an output register in the buffer, and construct three buffer spaces corresponding to the ping-pong register and the output register; Given input data, determine if there is any empty space in the cache. If there is space in the cache, receive input data and write the input data into the cache according to preset rules.

2. The method according to claim 1, characterized in that, The buffer space includes a P buffer space, a B buffer space, and an output register. The P buffer space and the B buffer space are connected in parallel, and both the P buffer space and the B buffer space are connected to the output register. The step of writing input data into the buffer space according to a preset principle includes: Whether to write input data to the output register depends on the data storage status of the output register; If it is impossible to write input data to the output register, write data alternately from the P buffer space to the P buffer space or the B buffer space. If the output register is free, data is alternately transferred from the P cache space and the B cache space to the output register, starting from the P cache space.

3. The method according to claim 1, characterized in that, The method further includes: By redefining the interfaces, the input write first-in-first-out FIFO interface and the FIFO full flag interface are modified into input handshake interfaces, and the output read FIFO interface and the FIFO empty flag interface are modified into output handshake interfaces. The maximum storage capacity of the internal effective count FIFO is used as an additional output interface; Given input data, determine whether the storage space of the first-in-first-out queue is full; Receive input data when the storage space of the first-in-first-out queue is not full; If the storage space of the first-in-first-out queue is not empty, actively output the stored data in the storage space.

4. The method according to claim 3, characterized in that, The method further includes: Set up a stack buffer in the arbitrator to record requests that come in simultaneously within each clock cycle as a group of requests. The request groups are placed into the stack cache space according to the order in which they were entered. If the stack cache is not empty, a request group data is popped and transmitted to the arbitration core for arbitration sorting. The arbitration result is output. During the arbitration process, if the corresponding request in the request group is finished being processed, the corresponding bit of the request is cleared until the bit of the last request in the current request group is cleared. Then the next request group data is popped from the stack cache.

5. The method according to claim 3, characterized in that, The method further includes: During the interface conversion process, the input data is buffered to complete interface simplification and timing processing; The data output from the buffer is partially buffered by a first-in-first-out queue. Data output from the first-in-first-out (FIFO) queue is selectively passed through the FIFO queue and buffer after being converted by the interface.

6. The method according to claim 4, characterized in that, The method further includes: During data processing, multiple out-of-order input data are split and buffered to complete interface simplification and timing processing. The out-of-order data output from the buffer is stored in multiple first-in-first-out queues, which serve as the operation space for out-of-order recovery. The data output from the first-in-first-out queue is output in a preset order or after passing through an arbitrator.

7. The method according to claim 4, characterized in that, The method further includes: During the data routing process, the input data first passes through a buffer to complete the interface processing, and the data output from the buffer is stored in a first-in-first-out queue. If the preset data accumulation requirement is met in the first-in-first-out queue, data routing is completed through multiple cascaded arbitrators. Among them, buffers or first-in-first-out queues are selectively inserted between different cascaded arbitrators for data processing and timing optimization. Data that has completed data routing is output after passing through a buffer or a first-in-first-out queue.

8. A high-speed data path optimization device, characterized in that, include: The module is used to set up the ping-pong register and the output register in the buffer, and to build the three buffer spaces corresponding to the ping-pong register and the output register. The judgment module is used to determine whether there is empty space in the cache when there is input data; The write module is used to receive input data and write it into the cache space according to preset rules when the cache space is empty.

9. A computer device, comprising: A memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the optimization method for the high-speed data path according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the optimization method for the high-speed data path according to any one of claims 1 to 7.

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