Repeated assignment statement processing method, electronic equipment and medium
By setting preset interface call instructions in the compiler and performing batch memory copy operations during the simulation phase, the problems of long compilation time and low simulation efficiency caused by large-scale repetitive assignment statements are solved, achieving efficient compilation and simulation performance optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI UNIVISTA IND SOFTWARE GRP CO LTD
- Filing Date
- 2026-04-13
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies suffer from low compilation and simulation efficiency when handling large-scale repetitive assignment statements, resulting in the compiler generating redundant intermediate code and the simulator incurring high runtime overhead, which limits the application of System Verilog in complex SoC verification and large-scale IP design.
During the compiler's syntax analysis phase, information about repeated assignments is obtained, and preset interface call instructions are set during the compilation process. During the simulation phase, batch memory copy operations are performed through the preset interface to replace element-by-element assignment, thereby reducing compilation complexity and simulation overhead.
The compilation efficiency was optimized through a pre-defined interface, which reduced simulation performance, supported multiple container types, and improved the system's scalability.
Smart Images
Figure CN122019017A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design and verification technology, and in particular to a method for processing repeated assignment statements, an electronic device, and a medium. Background Technology
[0002] In hardware description languages such as System Verilog, when using the assignment pattern to repeatedly assign values to containers such as large arrays, the traditional implementation faces at least the following disadvantages: (1) For large-scale repeated assignment statements, the traditional compiler adopts a syntax expansion strategy to generate a large amount of redundant intermediate code. For example, for an assignment statement of the form q = '{10000{4'b1101}}, the traditional compiler will expand it into independent assignment statements with a number of container elements (such as q[0] = 4'b1101, q[1] = 4'b1101, ..., q
[9999] = 4'b1101), which results in: the compilation time increases linearly with the array size, the compilation time of large-scale designs increases significantly, the abstract syntax tree (AST) and intermediate representation (IR) expand rapidly, the burden of subsequent optimization stages increases, and the compilation efficiency is low. (2) The simulator needs to execute tens of thousands of assignment operations one by one, causing unnecessary runtime overhead. Each assignment may trigger simulation event scheduling, resulting in reduced simulation efficiency, inefficient memory access mode, and poor simulation performance. (3) The generated intermediate code is large in size, increasing storage and transmission costs, and cannot handle ultra-large arrays (such as million-bit wide registers), which limits the application of System Verilog in complex SoC verification and large-scale IP design, resulting in poor scalability. Therefore, how to intelligently handle repeated assignment statements and improve compilation efficiency, simulation performance, and scalability has become an urgent technical problem to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide a method, electronic device, and medium for handling repeated assignment statements, which improves compilation efficiency, simulation performance, and scalability.
[0004] According to a first aspect of the present invention, a method for processing repeated assignment statements is provided, comprising: Step S1: During the compiler's syntax analysis phase, obtain the information about duplicate assignments to be processed in the source code {A1, A2, ..., A...}. j ,...,A J}, where A j For the j-th duplicate assignment information to be processed, A j ={A1 j A2 j A3 j A4 j}, A1j For A j The corresponding target variable, A2 j For A j The corresponding number of reassignments, A3 j For A j The corresponding duplicate value, A4 j For A j The corresponding target variable type; Step S2: During the compilation process, if A2 j Greater than the preset threshold and A4 j To pre-optimize the element type, then based on the corresponding A j Execute step S3; Step S3, for A j Set preset interface call instructions; Step S4: During the simulation, when execution reaches A... j When calling the corresponding preset interface, A1 j A2 j A3 j A4 passes in a preset interface, based on A3. j and A4 j Generate A3 j The standard memory data block for each element in the A1 standard memory is based on A1. j The corresponding starting position and A2 j Store the corresponding standard memory data blocks to each corresponding target storage location.
[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.
[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.
[0007] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the method, electronic device, and medium for processing repeated assignment statements provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: This invention, by setting a preset interface, avoids directly expanding repeated assignment statements with a number of repetitions exceeding a preset threshold during the compilation phase. Instead, it sets corresponding preset interface call instructions. During the simulation phase, the repeated assignment operation is executed based on the preset interface call instructions, reducing the compilation complexity of repeated assignment statements from O(N) to O(1). This avoids the generation and parsing of massive assignment instructions, and the larger N is, the more significant the optimization effect. This invention uses batch memory copy operations to replace element-by-element assignment, reducing the number of instruction executions and simulation event scheduling during the simulation process. It eliminates the need to store massive amounts of expanded instructions and intermediate data, reducing memory consumption and optimizing simulation performance. Furthermore, this invention supports multiple container types and can be extended to support repeated assignments of complex data types. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 The flowchart illustrates the method for handling repeated assignment statements provided in this embodiment of the invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] This invention provides a method for handling repeated assignment statements, such as... Figure 1 As shown, it includes: Step S1: During the compiler's syntax analysis phase, obtain the information about duplicate assignments to be processed in the source code {A1, A2, ..., A...}. j ,...,A J}, where A j For the j-th duplicate assignment information to be processed, A j ={A1 j A2 j A3 j A4 j}, A1 j For A j The corresponding target variable, A2 j For A jThe corresponding number of reassignments, A3 j For A j The corresponding duplicate value, A4 j For A j The corresponding target variable type.
[0012] Specifically, the source code can be System Verilog code. The target variable type includes arrays, queues, and unions. The arrays include container types such as static arrays and dynamic arrays. Static arrays include one-dimensional arrays and multi-dimensional arrays, while dynamic arrays are arrays of variable length.
[0013] Step S2: During the compilation process, if A2 j Greater than the preset threshold and A4 j To pre-optimize the element type, then based on the corresponding A j Proceed to step S3.
[0014] Specifically, the preset optimization variable type can include arrays and queues. It should be noted that if A2 is not satisfied... j Greater than the preset threshold and A4 j If the element type is preset to be optimized, the duplicate assignment statements to be processed can be processed directly in the traditional expansion method. All existing methods of directly expanding duplicate assignment statements to be processed fall within the protection scope of this invention, and will not be elaborated here.
[0015] Step S3, for A j Set the preset interface call command.
[0016] It should be noted that if A2 j Greater than the preset threshold and A4 j To optimize the element type, the traditional expansion operation is not performed. Instead, during compilation, a preset interface call instruction is set. The preset interface is a built-in function, and its parameter list includes the target variable, the number of repetitions, the repetition value, and the target variable type. The preset interface is used to selectively perform efficient memory copy operations based on the input parameters. During the compilation phase, through instruction substitution, the operation that originally required generating N assignment instructions is simplified to a single function call instruction, reducing the code size from O(N) to O(1). This significantly reduces the compiler's workload in syntax analysis and instruction generation, improving compilation efficiency. Step S4: During the simulation, when execution reaches A... j When calling the corresponding preset interface, A1 j A2 j A3 j A4 passes in a preset interface, based on A3. j and A4 j Generate A3j The standard memory data block for each element in the A1 standard memory is based on A1. j The corresponding starting position and A2 j Store the corresponding standard memory data blocks to each corresponding target storage location.
[0017] It should be noted that during the runtime phase, the memory copy operation is based on hardware-optimized block transfer instructions, with a time complexity of O(1) (batch transfer), rather than the traditional element-by-element assignment O(N). Especially when N is large, this can significantly reduce the number of instruction executions and memory access overhead, thereby improving simulation speed. This embodiment of the invention improves the processing efficiency of repetitive statements through a two-layer optimization mechanism of compile-time conversion and runtime memory copy.
[0018] As one embodiment, step S1 includes: Step S11: During the syntax analysis phase of the compiler, obtain the duplicate assignment statements to be processed in the source code. If the duplicate assignment statements to be processed are single-level single-value duplicate types or single-level multi-value duplicate types, then execute step S13. If the duplicate assignment statements to be processed are nested duplicate types, then execute step S12.
[0019] The single-level, single-value repetition type is in the form '{N{value}}', where N is the number of repetitions and value is the repetition value. The single-level, multi-value repetition type is in the form '{N{{value1,value2,...,value}}'. i ,...,value X The form is}}}, where N is the number of repetitions and value is}}}. i A3 j The corresponding i-th repeated value, where i ranges from 1 to X, and X is A3. j The corresponding number of repeating values. Nested repeating types are {M{'{N{VL}}}}, where M and N are the number of repetitions, and VL is the repeating value corresponding to the nested repeating type. VL can be value, or it can be value1, value2, ..., value i ,...,value X .
[0020] Step S12: Convert the nested repeating type of the unprocessed repeating assignment statement into a single-level single-value repeating type or a single-level multi-value repeating type repeating assignment statement, and then execute step S13.
[0021] It should be noted that all existing methods of decomposing nested repeating type repetitive assignment statements into single-level single-value repeating type or single-level multi-value repeating type repetitive assignment statements fall within the protection scope of this invention, and will not be elaborated further here.
[0022] Step S13: Obtain A1 corresponding to the duplicate assignment statement to be processed. n A2 n A3 n A4 n Generate the corresponding A n Based on all A n Generate {A1,A2,...,A n ,...,A N}
[0023] Specifically, the process involves first reading the source file, then generating lexical units based on lexical analysis, and finally constructing an abstract syntax tree based on syntax analysis. Each node in the abstract syntax tree is traversed; if it's an assignment statement, the subtree of the assignment expression is traversed; if it's a repeated assignment pattern, it's first determined whether it's a nested repeated type. If so, the nested repeated type needs to be converted to a single-level single-value repeated type or a single-level multi-value repeated type. Then, the corresponding target variable A1 and the number of repeated assignments A2 are extracted. n Duplicate value A3 n Target variable type A4 n Generate the corresponding A n .
[0024] As one embodiment, in step S4, the step based on A3 j and A4 j Generate A3 j The standard memory data block for each element includes: Step S41: Call the preset interface to transfer A3 j Each element in the array is converted to an A4 value. j Generate A3 based on the memory storage format that matches the corresponding element type. j Each element in the standard memory data block corresponds to A4 j The corresponding element type can be any of the basic Verilog types, specifically including four-state logic types and two-state logic types.
[0025] Among them, A3 j Each element in the array is converted to an A4 value. j The corresponding memory storage format for matching element types specifically includes memory alignment processing and sign bit extension processing, etc., for A3 j Each element in the format is then formatted to obtain the corresponding standard memory data block.
[0026] As one embodiment, in step S4, based on A1 j The corresponding starting position and A2 j Store the corresponding standard memory data blocks to each corresponding target storage location, including: Step S42, if Aj For a single-level, single-value repeating type, the corresponding standard memory data block is stored in each corresponding target storage location using a single-value filling method.
[0027] Step S43, if A j If it is a single-level multi-valued repeating type, then A3 j The corresponding way to obtain the multi-value sequence {value1, value2, ..., value} is to retrieve the multi-value sequence {value1, value2, ..., value}. i ,...,value X}, value i A3 j The corresponding i-th repeated value, where i ranges from 1 to X, and X is A3. j The corresponding number of duplicate values.
[0028] Step S44: Based on value1, value2, ..., value i ,...,value X The order alternates between each value i The corresponding standard memory data blocks are stored in each corresponding target storage location.
[0029] Among them, based on value1, value2, ..., value i ,...,value X The alternating order refers specifically to storing the standard memory data block corresponding to value1 in the first target storage location, starting with value1, then storing the standard memory data block corresponding to value2 in the second target storage location, and so on, until value1 is stored in the first target storage location. X The corresponding standard memory data block is stored in the Xth target storage location. Then, starting from value1, the standard memory data block corresponding to value1 is stored in the (X+1)th target storage location, the standard memory data block corresponding to value2 is stored in the (X+2)th target storage location, and so on. X The corresponding standard memory data block is stored in the 2×Xth target storage location. Then, starting from value1, the standard memory data block corresponding to value1 is stored in the 2X+1th target storage location... until the repetition count is met. In step S44, the elements can be filled sequentially according to their storage offsets.
[0030] As one example, if A3 j If the length of the corresponding element data is less than a preset length threshold, then in steps S42 and S44, the standard memory data block is stored in each corresponding target storage location by direct assignment. The preset length threshold can specifically be set to 64 bits. If A3j If the length of the corresponding element data is greater than the preset length threshold, then in steps S42 and S44, the standard memory data block is stored to each corresponding target storage location by means of memory copying.
[0031] As one embodiment, in steps S42 and S44, based on the starting address of the target variable, the next target storage location is automatically located through an address increment mechanism until A2 is located. j This avoids redundant operations of assigning values element by element, up to the target storage location.
[0032] This invention, through the setting of a preset interface, avoids directly expanding repeated assignment statements with a number of repetitions exceeding a preset threshold during the compilation phase. Instead, it sets corresponding preset interface call instructions. During the simulation phase, the repeated assignment operation is executed based on the preset interface call instructions, reducing the compilation complexity of repeated assignment statements from O(N) to O(1). This avoids the generation and parsing of massive assignment instructions, and the larger N is, the more significant the optimization effect. This invention uses batch memory copy operations to replace element-by-element assignment, reducing the number of instruction executions and simulation event scheduling during the simulation process. It eliminates the need to store massive amounts of expanded instructions and intermediate data, reducing memory consumption and optimizing simulation performance. Furthermore, this invention supports multiple container types and can be extended to support repeated assignments of complex data types.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0034] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0035] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.
[0036] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.
[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A method for handling repeated assignment statements, characterized in that, include: Step S1: During the compiler's syntax analysis phase, obtain the information about duplicate assignments to be processed in the source code {A1, A2, ..., A...}. j ,...,A J }, where A j For the j-th duplicate assignment information to be processed, A j ={A1 j A2 j A3 j A4 j }, A1 j For A j The corresponding target variable, A2 j For A j The corresponding number of reassignments, A3 j For A j The corresponding duplicate value, A4 j For A j The corresponding target variable type; Step S2: During the compilation process, if A2 j Greater than the preset threshold and A4 j To pre-optimize the element type, then based on the corresponding A j Execute step S3; Step S3, for A j Set preset interface call instructions; Step S4: During the simulation, when execution reaches A... j When calling the corresponding preset interface, A1 j A2 j A3 j A4 passes in a preset interface, based on A3. j and A4 j Generate A3 j The standard memory data block for each element in the A1 standard memory is based on A1. j The corresponding starting position and A2 j Store the corresponding standard memory data blocks to each corresponding target storage location.
2. The method according to claim 1, characterized in that, Step S1 includes: Step S11: During the syntax analysis phase of the compiler, obtain the duplicate assignment statements to be processed in the source code. If the duplicate assignment statements to be processed are single-level single-value duplicate types or single-level multi-value duplicate types, then execute step S13. If the duplicate assignment statements to be processed are nested duplicate types, then execute step S12. Step S12: Convert the nested repeating type of the unprocessed repeating assignment statement into a single-level single-value repeating type or a single-level multi-value repeating type repeating assignment statement, and then execute step S13; Step S13: Obtain A1 corresponding to the duplicate assignment statement to be processed. n A2 n A3 n A4 n Generate the corresponding A n Based on all A n Generate {A1,A2,...,A n ,...,A N } 3. The method according to claim 1, characterized in that, The target variable type includes arrays, queues, and unions, and the arrays include static arrays and dynamic arrays.
4. The method according to claim 1, characterized in that, The preset optimization variable types include arrays and queues.
5. The method according to claim 1, characterized in that, In step S4, the step based on A3 j and A4 j Generate A3 j The standard memory data block for each element includes: Step S41: Call the preset interface to transfer A3 j Each element in the array is converted to an A4 value. j Generate A3 based on the memory storage format that matches the corresponding element type. j Each element in the standard memory data block corresponds to A4 j The corresponding element types include four-state logic types and two-state logic types.
6. The method according to claim 5, characterized in that, In step S4, based on A1 j The corresponding starting position and A2 j Store the corresponding standard memory data blocks to each corresponding target storage location, including: Step S42, if A j For a single-level single-value repeating type, the corresponding standard memory data block is stored in each corresponding target storage location using the single-value filling method. Step S43, if A j If it is a single-level multi-valued repeating type, then A3 j The corresponding way to obtain the multi-value sequence {value1, value2, ..., value} is to retrieve the multi-value sequence {value1, value2, ..., value}. i ,...,value X }, value i A3 j The corresponding i-th repeated value, where i ranges from 1 to X, and X is A3. j The corresponding number of duplicate values; Step S44: Based on value1, value2, ..., value i ,...,value X The order alternates between each value i The corresponding standard memory data blocks are stored in each corresponding target storage location.
7. The method according to claim 6, characterized in that, If A3 j If the length of the corresponding element data is less than the preset length threshold, then in steps S42 and S44, the standard memory data block is stored to each corresponding target storage location by direct assignment. If A3 j If the length of the corresponding element data is greater than the preset length threshold, then in steps S42 and S44, the standard memory data block is stored to each corresponding target storage location by means of memory copying.
8. The method according to claim 6, characterized in that, In steps S42 and S44, based on the starting address of the target variable, the next target storage location is automatically located through an address increment mechanism until A2 is located. j Until the target storage location is reached.
9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method as described in any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method as described in any one of claims 1-8.