High-speed mode detection method and device of USB equipment, electronic equipment and storage medium

Abstract

The invention provides a high-speed mode detection method and device for USB equipment, electronic equipment and a storage medium, and the method comprises the steps: carrying out the matching of parallel detection, a serial state machine and comprehensive judgment logic, and combining SE0 state detection, J state detection, signal edge quality detection, dual-time window constraint and a self-adaptive threshold adjustment mechanism, thereby achieving the high-speed mode detection of the USB equipment. The identification accuracy of the high-speed handshake signal can be improved, and misjudgment and missed judgment caused by ringing, reflection and noise are reduced, so that the reliability, the anti-interference capability and the environment adaptability of the high-speed mode detection of the USB equipment are improved.

Description

Technical Field

[0001] This disclosure relates to the field of USB communication interface detection technology, and more specifically, to a method, apparatus, electronic device, and storage medium for detecting high-speed mode of a USB device. Background Technology

[0002] With the widespread use of USB interfaces in various electronic devices, the reliability of connection establishment, speed identification, and mode switching between USB devices and hosts directly affects the data transmission performance and system compatibility of the devices. For USB devices, after connecting to a host, it is usually necessary to detect the bus status to identify the communication mode supported by the currently connected host, and accordingly complete the subsequent data link initialization and transmission parameter configuration. High-speed mode detection is a crucial prerequisite for a USB device to enter high-speed communication mode normally. Therefore, accurately identifying whether the host has high-speed communication capabilities has become one of the key issues in the design of USB device interface circuits.

[0003] Existing high-speed handshake detection schemes typically start a fixed-duration timeout counter after detecting a bus reset state, and determine whether the bus has entered the J state within a preset time to infer whether the host supports high-speed mode. Some schemes use level comparators to directly compare the levels of D+ and D-, determining the J state when a preset high-low level relationship is met. While these schemes have relatively simple circuit structures, they mostly rely on a single judgment condition and lack the ability to dynamically adjust according to the actual noise environment. Therefore, in high-noise environments, impedance mismatch environments, or power fluctuation environments, the detection accuracy and stability are poor, making it difficult to meet the reliability requirements of high-speed USB devices for host mode recognition. Summary of the Invention

[0004] This disclosure provides at least one method, apparatus, electronic device, and storage medium for detecting high-speed modes of USB devices. By combining parallel detection, serial state machine, and comprehensive judgment logic, along with SEO state detection, J state detection, signal edge quality detection, dual time window constraints, and adaptive threshold adjustment mechanisms, it can improve the accuracy of high-speed handshake signal recognition and reduce false and false judgments caused by ringing, reflection, and noise. This improves the reliability, anti-interference capability, and environmental adaptability of high-speed mode detection for USB devices.

[0005] This disclosure provides a method for detecting high-speed mode of a USB device, including: The differential signal of the USB bus is acquired and the differential signal is detected in parallel to obtain the SEO state detection result, J state detection result and signal quality detection result; When the SE0 state is detected, a first time window is started to verify the duration of the SE0 state in order to determine whether the SE0 state meets the preset reset judgment condition. If the preset reset determination condition is met in the SE0 state, it is detected whether the USB bus has entered the J state, and when the J state is detected, a second time window is started to verify the duration of the J state. The signal edge quality corresponding to the J state is detected to determine whether the J state is a valid handshake signal; Based on the duration verification results of the SEO state, the duration verification results of the J state, and the quality detection results of the signal edge, the system determines whether the current host supports high-speed mode according to the preset state determination logic and outputs the high-speed mode detection result.

[0006] In one optional implementation, the differential signal is detected in parallel, specifically including: USB bus signals are received via a differential receiver; The USB bus is detected to be in the SE0 state via a separate SE0 state detection channel. The USB bus is detected to be in J state by an independent J state detection channel. The J state detection channel is set with hysteresis when performing J state detection to reduce the influence of the ringing signal on the J state determination. The edge rate information of the corresponding edge of the USB bus is detected through an independent signal quality monitoring channel.

[0007] In one optional implementation, verifying the duration of the J state specifically includes: When state J is detected within the first time window, the second time window is started; Determine whether the duration of state J is within a second preset time range; When the duration of state J is within the second preset time range, the timing detection result of state J is determined to be valid.

[0008] In one optional implementation, the signal edge quality corresponding to the J state is detected, specifically including: High-speed sampling is initiated when a signal edge is detected. Acquire waveform data within a preset time range before and after the signal edge; The edge time is calculated based on the waveform data, wherein the edge time is the time corresponding to the signal amplitude changing from 10% to 90%; The edge time is compared with a preset edge threshold to output a signal quality detection result. When the edge time is not greater than the preset edge threshold, the corresponding signal is determined to be a valid signal. When the edge time is greater than the preset edge threshold, the corresponding signal is determined to be a pseudo signal.

[0009] In one optional implementation, the preset state determination logic includes: The host is determined to support high-speed mode only when the SE0 state meets the reset determination condition, the J state meets the duration determination condition, and the signal edge quality meets the validity determination condition. If any of the above conditions are not met, the host is determined to not support high-speed mode or the test is invalid.

[0010] In one optional implementation, the method further includes: The number of J state pulses is counted during the SE0 state detection period; The number of J-state pulses is used to determine whether the current environment is a high-noise environment. When the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted.

[0011] In one optional implementation, the method further includes: When the number of J state pulses exceeds a preset threshold, the current environment is determined to be a high-noise environment. When the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted from the first lower limit threshold to the second lower limit threshold, wherein the first lower limit threshold is less than the second lower limit threshold. When the low noise condition is met for multiple consecutive detection cycles, the adjusted lower limit threshold of the second time window will be restored to the initial threshold. When multiple consecutive detection cycles are all low noise, the lower limit threshold of the second time window is restored to the first lower limit threshold.

[0012] This disclosure also provides a high-speed mode detection device for a USB device, comprising: The detection module is used to acquire the differential signal of the USB bus and perform parallel detection on the differential signal to obtain the SEO state detection result, the J state detection result, and the signal quality detection result. The first determination module is used to start a first time window when the SE0 state is detected, and to verify the duration of the SE0 state in order to determine whether the SE0 state meets the preset reset determination condition. The second determination module is used to detect whether the USB bus has entered the J state when the SEO state meets the preset reset determination condition, and to start a second time window when the J state is detected to verify the duration of the J state. The third determination module is used to detect the signal edge quality corresponding to the J state in order to determine whether the J state is a valid handshake signal. The result output module is used to determine whether the current host supports high-speed mode based on the duration verification result of the SEO state, the duration verification result of the J state, and the quality detection result of the signal edge, according to a preset state determination logic, and output the high-speed mode detection result.

[0013] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the high-speed mode detection method for the USB device described above, or any possible implementation of the high-speed mode detection method for the USB device described above, are performed.

[0014] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the high-speed mode detection method for the USB device described above, or any possible implementation of the high-speed mode detection method for the USB device described above.

[0015] This disclosure also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implements the steps of the above-described high-speed mode detection method for USB devices, or any possible implementation of the above-described high-speed mode detection method for USB devices.

[0016] This disclosure provides a method, apparatus, electronic device, and storage medium for high-speed mode detection of USB devices. By combining parallel detection, serial state machine, and comprehensive judgment logic, along with SEO state detection, J state detection, signal edge quality detection, dual time window constraints, and adaptive threshold adjustment mechanisms, it can improve the accuracy of high-speed handshake signal recognition and reduce false and missed detections caused by ringing, reflection, and noise. This improves the reliability, anti-interference capability, and environmental adaptability of high-speed mode detection for USB devices.

[0017] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0019] Figure 1 A flowchart of a high-speed mode detection method for a USB device provided in an embodiment of this disclosure is shown; Figure 2 A schematic diagram of a high-speed mode detection device for a USB device provided in an embodiment of this disclosure is shown; Figure 3 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0023] Research has revealed that existing high-speed handshake detection schemes typically start a fixed-duration timeout counter after detecting a bus reset state, and determine whether the bus has entered the J state within a preset time to infer whether the host supports high-speed mode. Some schemes use level comparators to directly compare the levels of D+ and D-, determining the J state when a preset high-low level relationship is met. While these schemes have relatively simple circuit structures, they mostly rely on a single judgment condition and lack the ability to dynamically adjust according to the actual noise environment. Consequently, in high-noise environments, impedance mismatch environments, or power fluctuation environments, the detection accuracy and stability are poor, making it difficult to meet the reliability requirements of high-speed USB devices for host mode recognition.

[0024] Based on the above research, this disclosure provides that existing high-speed handshake detection schemes typically start a fixed-duration timeout counter after detecting a bus reset state, and determine whether the bus has entered the J state within a preset time to infer whether the host supports high-speed mode. Some schemes also use level comparators to directly compare the levels of D+ and D-, determining the J state when a preset high-low level relationship is met. While these schemes have relatively simple circuit structures, they mostly rely on a single judgment condition and lack the ability to dynamically adjust according to the actual noise environment. Therefore, in high-noise environments, impedance mismatch environments, or power fluctuation environments, the detection accuracy and stability are poor, making it difficult to meet the reliability requirements of high-speed USB devices for host mode recognition.

[0025] To facilitate understanding of this embodiment, a high-speed mode detection method for a USB device disclosed in this disclosure will first be described in detail. The execution entity of the high-speed mode detection method for a USB device provided in this disclosure is generally a computer device with certain computing capabilities. This computer device may include, for example, a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, the high-speed mode detection method for the USB device can be implemented by the processor calling computer-readable instructions stored in memory.

[0026] See Figure 1 The diagram shows a flowchart of a high-speed mode detection method for a USB device according to an embodiment of this disclosure. The method includes steps S101 to S105, wherein: S101. Acquire the differential signal of the USB bus and perform parallel detection on the differential signal to obtain the SEO state detection result, J state detection result and signal quality detection result.

[0027] In practice, the differential signals of the USB bus are first acquired, and then the differential signals are detected in parallel to obtain the SEO state detection result, J state detection result, and signal quality detection result. Specifically, the USB bus includes D+ signal lines and D- signal lines, which together carry the differential transmission signals between the device and the host.

[0028] To improve the accuracy of subsequent high-speed mode detection, this embodiment does not rely solely on single-level detection or single-time detection methods for judgment. Instead, it first synchronously acquires the bus signals on the D+ and D- signal lines, and then sends the acquired differential signals into multiple parallel detection channels to jointly analyze the current bus behavior from multiple dimensions such as bus status, level relationship, and edge quality.

[0029] Specifically, the differential signal is preferably preprocessed by a differential receiver. This differential receiver can differentially receive and shape the D+ and D- signals, and suppress common-mode interference components, thereby outputting a bus status characterization signal that is more suitable for subsequent logic identification. In some embodiments, the differential receiver may employ a high common-mode rejection ratio structure to reduce the impact of external noise, power supply disturbances, and wiring coupling on the detection results, so that subsequent SEO status detection, J status detection, and signal quality detection can all be based on a relatively stable input signal.

[0030] During parallel detection, the differential signal is fed into at least the SE0 state detection module, the J state detection module, and the signal quality monitoring module. The SE0 state detection module determines whether the USB bus is currently in the SE0 state. The SE0 state is generally understood as a bus state where both the D+ and D- signal lines are at a low level. By detecting the combination of D+ and D- levels, the SE0 state detection module outputs a corresponding SE0 state detection result, indicating whether a bus reset-related candidate state has been detected at the current moment.

[0031] Because this detection channel is set up independently, it can identify the reset start state in advance without relying on the J state detection result or other timing judgment results, thus providing a basis for subsequent timing window judgment.

[0032] Simultaneously, the differential signal is also sent to the J-state detection module. The J-state detection module is used to determine whether the USB bus has entered the J-state. Since the J-state is one of the important states in the subsequent high-speed handshake identification, in this embodiment, the J-state detection is separated from the conventional single-level comparison logic and operated in parallel as a dedicated detection channel.

[0033] In practical implementation, the J-state detection module can output the J-state detection result based on the high / low level relationship between D+ and D-. Preferably, the J-state detection module can be equipped with a hysteresis determination mechanism to suppress short-term false triggering caused by bus ringing, reflection, or instantaneous fluctuations. That is, even if the differential signal briefly meets the level relationship corresponding to the J-state due to ringing at certain moments, as long as it does not meet the hysteresis determination condition, it can avoid being directly identified as a valid J-state, thereby improving the anti-interference capability of subsequent host mode determination.

[0034] In addition to the two state detection channels mentioned above, this embodiment also sends the differential signal to a signal quality monitoring module to obtain the signal quality detection result. Unlike simply determining whether a J state exists, the signal quality monitoring module further focuses on whether the detected state transition corresponds to a real and valid bus signal, especially monitoring the signal edge characteristics.

[0035] In practical implementation, the signal quality monitoring module can initiate high-speed sampling when a transition in the bus signal is detected, acquiring waveforms near the edge and calculating the change time of the corresponding edge. For example, the time it takes for the signal amplitude to change from a preset low ratio to a preset high ratio can be calculated based on the sampled waveform data, and this time can be used as the edge time parameter. Then, the edge time parameter is compared with a preset threshold. When the edge time meets the preset requirements, the signal quality is determined to be valid; otherwise, it can be regarded as a spurious signal caused by reflection, ringing, or noise.

[0036] It should be noted that the SE0 state detection, J state detection, and signal quality detection described above are not performed sequentially, but rather in parallel for the USB bus differential signals acquired at the same time. In other words, after the bus signal is input, each detection module can simultaneously extract and judge different features of the differential signal, and output the SE0 state detection result, J state detection result, and signal quality detection result respectively.

[0037] This approach shortens the detection response time, meeting the detection requirements under conditions of rapid changes in USB bus status. It also enables subsequent state machines or comprehensive judgment logic to simultaneously acquire multiple detection information, allowing for a more comprehensive and reliable judgment of the bus status.

[0038] Furthermore, in some embodiments, the SEO state detection result can be output in the form of a binary flag, status code, or register flag to indicate whether an SEO state is currently detected; the J state detection result can also be output in the form of a binary flag, status code, or register flag to indicate whether a J state is currently detected; the signal quality detection result can be output in the form of a valid / invalid flag, edge time parameter comparison result, or quality level identifier. Subsequent detection logic can then use these detection results to further perform a comprehensive judgment on the SEO duration, the J state timing relationship, and the high-speed host capability.

[0039] In this embodiment, the USB bus differential signal is first detected in parallel through multiple channels. Based on the bus status detection, a signal quality detection mechanism is further introduced. This not only obtains the SEO status detection result and the J status detection result, but also obtains the signal quality detection result that reflects the authenticity of the edge. This provides a more sufficient basis for judgment for subsequent high-speed mode detection, and improves the detection accuracy and anti-interference capability.

[0040] S102. When the SE0 state is detected, a first time window is started to verify the duration of the SE0 state in order to determine whether the SE0 state meets the preset reset judgment condition.

[0041] In specific implementation, upon detecting the SE0 state, a first time window is initiated to verify the duration of the SE0 state, thereby determining whether the SE0 state meets the preset reset judgment conditions. Specifically, the SE0 state detection module in the aforementioned parallel detection module continuously monitors the state of the D+ and D- signals of the USB bus. When both the D+ and D- signals are detected to be low, it can be determined that the current bus has entered the SE0 state. Since the SE0 state typically corresponds to a critical state in the USB bus reset process, upon detecting this state, it is not immediately recognized as a valid reset. Instead, the state is further continuously verified in conjunction with the time dimension to avoid misjudging bus transient disturbances, short-term glitches, or other abnormal low-level states as reset signals.

[0042] Specifically, when the SEO state detection module outputs a detection result indicating that an SEO state has been detected, the control logic triggers the opening of the first time window and begins timing the duration of the SEO state. This first time window corresponds to a preset range of valid SEO durations and is used to determine the stability and validity of the current SEO state. In other words, after the first time window opens, the system does not only determine whether an SEO state has occurred, but further determines whether the SEO state persists within the preset time range. If the SEO state is interrupted, changes direction, or its duration does not meet the preset requirements during its duration, it indicates that the SEO state is more likely to be due to bus noise, transient interference, or non-standard reset behavior, and in this case, it is not treated as a valid reset state.

[0043] In some implementations, the first time window can be set as a T_SEO time window. The lower limit of the T_SEO time window is used to ensure that the detected SEO state has a sufficient duration to meet the stability requirements of the reset state; its upper limit is used to limit the waiting range to prevent continuous waiting in non-target situations, which would affect the efficiency of subsequent mode determination.

[0044] Preferably, the first time window can be set to 1.0ms to 2.5ms. The reasons for this setting are as follows: First, the USB reset process usually requires the SEO state to be maintained for a certain period of time. If the duration is too short, it is more likely to be a transient interference rather than a real reset. Second, by setting an upper limit on the time, the detection process can be ineffectively extended under full-speed host or abnormal bus conditions, thereby balancing detection accuracy and detection efficiency.

[0045] Furthermore, the verification process for the duration of the SEO state may include the following: upon detecting the start of the SEO state, a first moment is recorded, and the timing unit is started; during subsequent continuous sampling or continuous detection, it is continuously determined whether the D+ and D- signals still maintain the SEO state; when the SEO state is detected to end, a second moment is recorded, and the actual duration of the SEO state is determined based on the time interval between the first and second moments; then, the actual duration is compared with a preset reset judgment condition to output the corresponding verification result. If the actual duration is within a preset first time range, the current SEO state is determined to meet the preset reset judgment condition; if the actual duration is less than the lower time limit, or exceeds the upper time limit, or if a state discontinuity occurs during detection, the current SEO state is determined not to meet the preset reset judgment condition.

[0046] In a preferred implementation, when the duration of the SEO state reaches the lower threshold of the first time window but does not exceed the upper threshold, the SEO state can be determined as a valid reset candidate state, and subsequent detection logic is allowed to continue monitoring and determining the J state. In other words, the system only enters the subsequent high-speed handshake-related timing detection process after the preceding SEO state has passed the duration verification.

[0047] This allows for the addition of a reset validity screening mechanism at the front end of the high-speed mode detection process, which eliminates abnormal signals that do not meet the basic timing requirements for reset in advance, thereby reducing false triggering in subsequent J-state detection and high-speed mode determination.

[0048] It should also be noted that the verification function of the first time window is not only to determine whether the SEO state exists, but also to determine whether the SEO state constitutes a valid prerequisite for subsequent high-speed handshake detection. In some existing detection methods, subsequent J-state monitoring is initiated directly after the SEO state is detected, lacking independent verification of the duration of the SEO state itself. This easily leads to misinterpreting short-duration noise pulses as the reset starting point, resulting in subsequent misjudgments of the J state. This embodiment, by initiating the first time window upon detecting the SEO state, separately verifies the duration of the SEO state, improving the rigor of timing judgment from the source of the detection process.

[0049] Furthermore, in some embodiments, the preset reset determination condition may also include a state continuity condition, that is, requiring that the SEO state remain continuously valid within a preset sampling accuracy within the first time window, rather than relying solely on the cumulative duration. For example, during timing, if the D+ or D- signal is detected to briefly return to a non-low level state, it can be determined that the continuity of the current SEO state has been disrupted, and the detection result is set to invalid, thereby further improving the accuracy and anti-interference capability of the reset state determination.

[0050] In this embodiment, after detecting the SEO state, a first time window is first activated to verify the duration of the SEO state. Then, based on the verification result, it is determined whether the preset reset judgment condition is met. This ensures that the subsequent high-speed mode detection is based on a real, stable, and legal reset state, which helps to reduce the impact of bus noise, transient interference, and abnormal timing on the detection results and improves the reliability of high-speed mode detection of USB devices.

[0051] S103. If the preset reset judgment condition is met in the SEO state, detect whether the USB bus has entered the J state, and start the second time window when the J state is detected to verify the duration of the J state.

[0052] In a specific implementation, if the SEO state meets the preset reset judgment condition, it is detected whether the USB bus has entered the J state, and when the J state is detected, a second time window is started to verify the duration of the J state.

[0053] Specifically, after the aforementioned first time window verifies and confirms that the current SE0 state meets the preset reset judgment conditions, it indicates that the USB bus has entered the legal reset stage. Therefore, on this basis, subsequent bus state changes can continue to be monitored to determine whether the host has issued a J state signal for high-speed negotiation.

[0054] In other words, this step does not directly perform high-speed determination whenever J state is detected. Instead, it performs timing correlation detection on subsequent J states only after the preceding SE0 state has been confirmed as a valid reset state, thereby ensuring that J state detection has clear and reliable preconditions.

[0055] In practice, after determining that the SE0 state meets the preset reset judgment conditions, the control logic can switch the detection process to the J state monitoring stage and continuously receive the detection results from the J state detection module to determine whether the current USB bus has changed from the SE0 state to the J state. Since the J state is one of the key states in the high-speed handshake process, the occurrence of the J state not only needs to meet the corresponding bus level relationship, but also needs to form a correct timing connection relationship with the aforementioned SE0 state.

[0056] In other words, this embodiment focuses not on isolated J states, but on J states that occur after a valid SEO state and correspond to the reset process. This contextualized detection method avoids mistaking irrelevant noise pulses, random disturbances, or abnormal transitions as part of the high-speed handshake signal.

[0057] When the USB bus enters the J state, a second time window is activated to verify the duration of the J state. Specifically, after the J state detection module outputs a detection result indicating that the J state has been detected, the control logic triggers the opening of the second time window and begins timing the duration of the J state. The second time window is used to determine whether the current J state meets the duration requirement corresponding to the high-speed handshake signal.

[0058] Because bus ringing, reflections caused by impedance mismatch, and glitches in high-noise environments can create a level combination similar to the J state within a short period, relying solely on the presence or absence of the J state for judgment can easily lead to misjudgments. Therefore, this embodiment further constrains the duration of the J state through a second time window to improve the accuracy of recognizing genuine handshake signals.

[0059] In some implementations, the second time window can be set as a T_J time window to define the effective duration range of the J state. Preferably, the second time window can correspond to a time range of 80μs to 120μs. The lower limit is used to exclude pseudo-J state signals with excessively short durations, and the upper limit is used to prevent the bus state that has been abnormally maintained for a long time from being mistaken for a valid handshake signal.

[0060] In other words, only when the detected J-state duration is within the preset range corresponding to the second time window can the current J-state be considered to conform to the basic characteristics of a high-speed handshake signal in terms of timing. If the detected J-state duration is lower than the lower limit, it indicates that the J-state is more likely to be caused by ringing, reflection, or short-term noise; if the duration exceeds the upper limit, it indicates that the current signal may have abnormal holding, timing mismatch, or other non-standard bus behavior, and should not be directly used as a basis for a valid high-speed handshake.

[0061] Furthermore, the verification process for the duration of state J may include: recording the start time when the start of state J is detected and starting the timing unit; continuously determining whether the USB bus maintains state J during subsequent detection; recording the end time when state J ends and determining the actual duration of state J based on the time difference between the start and end times; then comparing the actual duration with a preset duration range corresponding to the second time window to output the verification result of state J duration. When the actual duration is within the preset range, it is determined that the current state J meets the duration determination condition; when the actual duration does not fall within the preset range, it is determined that the current state J does not meet the duration determination condition.

[0062] In some implementations, the activation condition of the second time window can be tied to the verification result of the first time window. That is, the system only allows the second time window to be activated when state J is detected if the SEO state corresponding to the first time window passes the verification. If the aforementioned SEO state fails the reset determination, the duration verification result corresponding to the second time window will not be activated or recognized even if state J is subsequently detected.

[0063] This allows the T_SEO time window and the T_J time window to form a series constraint relationship, with the former ensuring the legality of the reset start point and the latter ensuring the accuracy of the handshake signal duration, thus forming a progressive timing verification mechanism.

[0064] Furthermore, in some implementations, the detection of the J state can be further judged in conjunction with state continuity. For example, during the timing process of the second time window, the J state is required to remain continuous and valid under a preset detection accuracy; if the J state is interrupted, rapidly flips, or is obviously unstable during the timing process, it can be determined that the continuity of the current J state does not meet the requirements, and the verification result of the duration of the current J state is set to invalid.

[0065] It should also be noted that the verification of the duration of the J state in this step is essentially a fine-tuning of the timing characteristics of the high-speed handshake signal. Compared with simply setting a single lower threshold and directly determining validity as long as the duration of the J state is detected to be greater than a certain value, this embodiment sets an independent second time window and introduces both lower and upper limits. This not only eliminates short-term spurious signals but also avoids misjudgments caused by abnormally long states, thus making the detection logic more complete.

[0066] In this embodiment, after confirming that the SEO state meets the preset reset judgment conditions, the system monitors whether the USB bus enters the J state. When the J state is detected, a second time window is started to verify the duration of the J state. This ensures that the J state used for high-speed mode determination not only matches the effective reset process in timing but also meets the preset requirements in duration, providing a reliable basis for subsequent comprehensive judgment based on signal quality detection results.

[0067] S104. Detect the signal edge quality corresponding to the J state to determine whether the J state is a valid handshake signal.

[0068] In this embodiment, the signal edge quality corresponding to the J state is detected to determine whether the J state is a valid handshake signal. Specifically, in the aforementioned steps, it has been confirmed that the J state appears after the SEO state that meets the preset reset judgment condition, and the duration of the J state itself meets the duration requirement corresponding to the second time window. However, the order of state appearance and duration alone are not enough to completely eliminate pseudo J state signals caused by bus ringing, impedance mismatch reflection, transient glitches, or high noise disturbances. Therefore, this embodiment further introduces a detection mechanism for the signal edge quality corresponding to the J state. From the perspective of signal waveform change characteristics, it re-determines whether the current J state belongs to a real and valid high-speed handshake signal, so as to improve the reliability and anti-interference capability of the high-speed mode detection process.

[0069] Specifically, the signal edge quality detection can be performed by the aforementioned signal quality monitoring module. This signal quality monitoring module can work in parallel with the SE0 state detection module and the J state detection module, and when a switch from SE0 to J state is detected, or an edge transition corresponding to J state is detected, the signal waveform near the corresponding edge is acquired and analyzed. Unlike focusing primarily on the high or low level at a certain moment, this embodiment further focuses on the edge change process when the signal transitions from one state to another, reflecting whether the signal has the transmission characteristics of a true handshake signal through the edge steepness, edge transition time, or edge integrity.

[0070] In some implementations, the signal quality monitoring module can automatically activate the high-speed sampling unit when a signal edge is detected, and sample waveform data within a preset time range before and after the edge. Preferably, the sampling rate of the high-speed sampling unit can be set to greater than or equal to 100MHz to ensure sufficient time resolution for high-speed bus edge details; furthermore, waveforms within a 200ns range before and after the edge can be acquired to obtain a more complete edge change process.

[0071] Generally speaking, a genuine and effective high-speed handshake signal usually has a relatively clear and rapid edge change characteristic, while a spurious signal formed by reflection, ringing or noise is more likely to show edge tailing, slow transition or waveform distortion. Therefore, by calculating the edge time, it is possible to effectively distinguish between real signals and spurious signals.

[0072] After obtaining the edge time parameter, it is further compared with a preset edge threshold to determine whether the signal quality corresponding to the current J state meets the requirements for a valid handshake. In some embodiments, the preset edge threshold can be set to 20ns. When the edge time is less than or equal to 20ns, it can be determined that the current edge change rate meets the preset requirements, and the corresponding J state has good signal quality, thus it is considered a valid handshake signal; when the edge time is greater than 20ns, it indicates that the edge transition process is slow, which may be affected by bus reflection, ringing, line parasitic parameters, or noise disturbance. In this case, the current J state can be determined as a spurious signal or an invalid handshake signal.

[0073] Furthermore, in some embodiments, the edge quality detection can output not only a simple valid / invalid result, but also a corresponding edge time value, edge quality level, or edge anomaly flag. For example, signals with edge times less than a first threshold can be marked as high-quality signals, signals with edge times between the first and second thresholds can be marked as suspicious signals, and signals with edge times exceeding the second threshold can be marked as invalid signals. Subsequent comprehensive judgment logic can employ different strategies based on different quality levels, such as directly passing, further verification, or direct rejection. This allows the overall detection strategy to have greater flexibility and scalability.

[0074] Furthermore, in some implementations, edge quality detection can be combined with additional characteristics such as the continuity, monotonicity, or ringing amplitude of the edge waveform for comprehensive analysis. For example, if the sampled waveform exhibits obvious multiple oscillations, overshoot, or amplitude jumps during edge changes, even if the final calculated edge time barely falls within the threshold range, it can still be marked as a suspicious or invalid signal using additional rules.

[0075] It should be noted that the signal edge quality detection in this step is not performed in isolation, but rather constitutes a progressive decision process together with the aforementioned SEO state detection and J state duration verification. That is to say, edge quality is only further detected when the current J state occurs after a valid SEO state and its duration meets the second time window requirement; and the edge quality detection result can serve as one of the important inputs for subsequent comprehensive decision logic.

[0076] In this embodiment, the signal edge quality corresponding to the J state is detected through the above method, and the J state is determined as a valid handshake signal based on the detection result. Thus, a waveform quality verification mechanism is further introduced on the basis of the J state timing verification, providing a more reliable basis for the comprehensive output of the subsequent high-speed mode detection results. This is beneficial to improving the accuracy, stability and anti-interference capability of high-speed mode detection of USB devices.

[0077] S105. Based on the duration verification result of the SEO state, the duration verification result of the J state, and the quality detection result of the signal edge, determine whether the current host supports high-speed mode according to the preset state determination logic, and output the high-speed mode detection result.

[0078] In specific implementation, based on the duration verification results of the SEO state, the duration verification results of the J state, and the signal edge quality detection results, the system determines whether the current host supports high-speed mode according to a preset state determination logic, and outputs the high-speed mode detection result. Specifically, after the aforementioned steps, the system has obtained the verification results of whether the SEO state is a valid reset state, the verification results of whether the J state meets the preset handshake duration requirement, and the detection results of whether the corresponding edge of the J state has valid signal quality characteristics.

[0079] To avoid making biased judgments based on a single detection result, this embodiment inputs the above multiple detection results into a comprehensive judgment logic. The comprehensive judgment logic then makes a unified judgment on whether the current host has the capability to support high-speed mode based on preset state judgment rules, thereby making the final output detection result more accurate and reliable.

[0080] Specifically, the preset state determination logic can be understood as a set of determination rules that perform correlation analysis on multiple detection conditions, and can also be implemented through state machine logic, combinational logic circuits, timing control logic, or programmable control units. In a typical implementation, the comprehensive determination logic requires that: only when the duration verification result of the aforementioned SEO state indicates that the SEO state meets the preset reset determination condition, and the duration verification result of the J state indicates that the J state meets the preset time window requirement, and the signal edge quality detection result indicates that the edge quality corresponding to the current J state meets the valid handshake signal requirement, is it determined that the current host supports high-speed mode.

[0081] In some implementations, the preset state determination logic can be further manifested as a verification of the integrity of the state sequence. In other words, it not only requires the existence of the SE0 state, the J state, and valid edge quality, but also requires these conditions to appear in a preset order. Specifically, this can be expressed as follows: first, the SE0 state is detected, and its duration is verified to meet the valid reset condition through a first time window; then, the J state is detected based on the valid SE0 state, and its duration is verified to meet the handshake signal requirements through a second time window; finally, it is confirmed that the edge quality corresponding to the J state meets the preset threshold condition. Only when the above state sequence and corresponding conditions all meet the requirements is the current detection process recognized as a valid high-speed mode handshake detection process.

[0082] Furthermore, in some implementations, if the duration verification result of the SEO state indicates that the SEO state does not meet the preset reset judgment condition, the comprehensive judgment logic can directly terminate the current high-speed mode detection process, outputting a result that the current host does not support high-speed mode or that the current detection is invalid, and no longer accept the subsequent J state detection results. Similarly, if the SEO state meets the reset condition, but the duration verification result of the J state indicates that the J state does not meet the preset time window requirement, the comprehensive judgment logic can also deny the current high-speed mode detection. Furthermore, even if the timing verification of both the SEO state and the J state meets the requirements, if the signal edge quality detection result indicates that the corresponding edge time exceeds a preset threshold, or that the edge waveform has obvious abnormalities, the current J state can also be identified as an invalid handshake signal, and a result indicating that high-speed mode is not supported or the detection has failed can be output.

[0083] In a preferred embodiment, the comprehensive judgment logic can be implemented using a serial state machine combined with parallel detection result input. Specifically, the parallel detection module outputs the SEO state detection result, J state detection result, and signal quality detection result, respectively, while the state machine receives and processes each detection result in stages according to a preset state transition path. For example, the state machine may include multiple logical states such as idle state, SEO detection state, SEO verification passed state, J state detection state, J state verification state, edge quality confirmation state, and final result output state. The state machine reads the corresponding detection results in different logical states and decides whether to transition to the next state based on each detection result and its time relationship. When the state transitions to the result output state, a high-speed mode detection conclusion is given based on the aforementioned multiple detection results.

[0084] When outputting the high-speed mode detection result, the detection result can be represented in various forms. For example, in some embodiments, a binary detection flag can be output to characterize whether the current host supports high-speed mode; when the detection result indicates that high-speed mode is supported, the USB device can be driven to switch to the corresponding high-speed communication configuration process; when the detection result indicates that high-speed mode is not supported, the device can be kept working in full-speed mode or other compatible modes.

[0085] In other implementations, the high-speed mode detection result may also include a failure reason identifier, such as marked as "SE0 verification failed", "J state time mismatch" or "edge quality unqualified", to facilitate subsequent debugging analysis, anomaly diagnosis or threshold optimization.

[0086] Furthermore, in some implementations, after the comprehensive judgment logic outputs a detection result indicating that the current host supports high-speed mode, the system can further trigger subsequent high-speed initialization procedures, such as switching the corresponding transceiver operating mode, configuring corresponding high-speed communication parameters, or initiating the subsequent high-speed link establishment process. Conversely, when the comprehensive judgment logic outputs a detection result indicating that the current host does not support high-speed mode, the system can maintain its original low-speed or full-speed operating mode, or re-enter the next round of detection preparation state.

[0087] As one possible implementation, the number of J state pulses is counted during the SEO state detection; the number of J state pulses is used to determine whether the current environment is a high-noise environment; when the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted.

[0088] In this embodiment, the number of J-state pulses is counted during the SEO state detection period; the number of J-state pulses is used to determine whether the current environment is a high-noise environment; if the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted. Specifically, although the aforementioned verification of SEO state duration, J-state duration, and edge quality detection can effectively distinguish between valid high-speed handshake signals and abnormal pseudo-signals, in actual application environments, the USB bus may still be affected by strong electromagnetic interference, impedance mismatch reflections, power supply ripple disturbances, and unstable connector contacts, resulting in a large number of short-duration J-state pulses during the SEO state detection period. These J-state pulses are often not real high-speed handshake signals, but rather instantaneous state jumps caused by noise coupling, waveform ringing, or reflection. If a fixed judgment threshold is still used, the probability of misjudgment may increase in high-noise environments. Therefore, this embodiment further introduces an adaptive threshold adjustment mechanism based on noise levels to enhance the detection stability and anti-interference capability of the system in complex environments.

[0089] Specifically, during the SEO state detection period, in addition to timing and verifying the duration of the SEO state, the control logic also simultaneously monitors the output of the J state detection module to count the number of J state pulses occurring during the duration of the SEO state. The number of J state pulses referred to here can be understood as the number of pulse events on the USB bus that briefly meet the J state determination condition during the SEO state period. In other words, if the J state detection module briefly outputs a signal indicating that the J state has been detected while the system is originally in the SEO state detection process, this event can be recorded as one J state pulse.

[0090] In some implementations, to avoid repeatedly counting the continuous jitter process as multiple pulse events, the counting of the number of J-state pulses can be combined with the minimum pulse interval or pulse de-jitter rules. For example, when the interval between two adjacent J-state detection results is less than a preset time threshold, they can be regarded as the same pulse event; only when adjacent pulses meet a preset separation condition are they counted as different J-state pulses.

[0091] After counting the number of J-state pulses, the system determines whether the current environment is a high-noise environment based on the number of J-state pulses. Specifically, the system compares the counted number of J-state pulses with a preset noise threshold to output the environmental noise judgment result. In a preferred embodiment, when the number of J-state pulses is greater than 3, the current environment is determined to be a high-noise environment; when the number of J-state pulses is less than or equal to 3, the current environment is determined to be a non-high-noise environment or a normal noise environment.

[0092] When the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted. Specifically, the second time window corresponds to the time range for verifying the duration of the J state, and its lower limit threshold is used to exclude pseudo-J state signals with excessively short durations. In normal environments, this lower limit threshold can be set as a relatively basic judgment threshold to balance detection sensitivity and recognition accuracy; however, in high-noise environments, since the probability of short-duration pseudo-J state signals occurring increases significantly, maintaining the original low lower limit threshold could easily cause some noise pulses to falsely meet the judgment condition in terms of duration.

[0093] In a preferred embodiment, when the current environment is determined to be a high-noise environment, the lower threshold of the second time window can be increased from 80μs to 100μs. That is, after entering a high-noise environment, only if the duration of a subsequently detected J state reaches 100μs or more and does not exceed the upper threshold of the second time window is the J state considered to meet the duration requirements of a valid handshake signal. By raising the lower threshold, short-duration pulses, ringing signals, and reflection disturbances caused by the high-noise environment can be further filtered out, thereby reducing the false positive rate.

[0094] Furthermore, in some implementations, the adjustment of the lower limit threshold of the second time window may only take effect within the current detection cycle, or it may remain effective for several consecutive detection cycles until the noise level returns to normal. For example, the system may recount the number of J state pulses during the SEO detection period after each detection cycle and update the environmental noise judgment result; if subsequent detections indicate that the bus environment has returned to a normal noise level, the lower limit threshold of the second time window may be restored to the initial setting value.

[0095] In some preferred embodiments, a threshold recovery mechanism can also be set. Specifically, when multiple consecutive detection cycles are determined to be in a low-noise environment, the control logic can restore the previously increased lower threshold of the second time window to the default threshold. For example, when three consecutive detection cycles are in a low-noise environment, the lower threshold of the second time window can be restored from 100μs to 80μs.

[0096] It should be noted that in this step, the environmental noise level is reflected by counting the number of J-state pulses during the SE0 state detection period. Essentially, this utilizes the abnormal bus transitions during the reset detection phase as a basis for environmental quality assessment. Since the SE0 state should be a relatively stable low-level state, frequent detection of J-state pulses during this period likely indicates strong interference in the current bus environment. Therefore, identifying the noise environment based on this statistical result and adjusting the lower threshold of the second time window accordingly ensures that subsequent verification of the J-state duration better reflects the characteristics of the actual environment.

[0097] This disclosure provides a high-speed mode detection method for USB devices. By combining parallel detection, serial state machine, and comprehensive judgment logic, along with SEO state detection, J state detection, signal edge quality detection, dual time window constraints, and adaptive threshold adjustment mechanism, it can improve the accuracy of high-speed handshake signal recognition and reduce false and missed detections caused by ringing, reflection, and noise. This improves the reliability, anti-interference capability, and environmental adaptability of high-speed mode detection for USB devices.

[0098] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0099] Based on the same inventive concept, this disclosure also provides a high-speed mode detection device for a USB device corresponding to the high-speed mode detection method for a USB device. Since the principle of the device in this disclosure for solving the problem is similar to the high-speed mode detection method for a USB device described above, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0100] Please see Figure 2 , Figure 2 This is a schematic diagram of a high-speed mode detection device for a USB device provided in an embodiment of this disclosure. Figure 2 As shown in the figure, the high-speed mode detection device 200 for USB devices provided in this embodiment includes: The detection module 210 is used to acquire the differential signal of the USB bus and perform parallel detection on the differential signal to obtain the SEO state detection result, the J state detection result, and the signal quality detection result.

[0101] The first determination module 220 is used to start a first time window when the SE0 state is detected, and to verify the duration of the SE0 state in order to determine whether the SE0 state meets the preset reset determination condition.

[0102] The second determination module 230 is used to detect whether the USB bus has entered the J state when the SEO state meets the preset reset determination condition, and to start a second time window when the J state is detected to verify the duration of the J state.

[0103] The third determination module 240 is used to detect the signal edge quality corresponding to the J state in order to determine whether the J state is a valid handshake signal.

[0104] The result output module 250 is used to determine whether the current host supports high-speed mode based on the duration verification result of the SEO state, the duration verification result of the J state, and the quality detection result of the signal edge, according to a preset state determination logic, and output the high-speed mode detection result.

[0105] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0106] This disclosure provides a high-speed mode detection device for USB devices. By combining parallel detection, serial state machine, and comprehensive judgment logic, along with SEO state detection, J state detection, signal edge quality detection, dual time window constraints, and adaptive threshold adjustment mechanism, it can improve the accuracy of high-speed handshake signal recognition and reduce false and missed detections caused by ringing, reflection, and noise. This improves the reliability, anti-interference capability, and environmental adaptability of high-speed mode detection for USB devices.

[0107] Corresponding to Figure 1 The present disclosure also provides an electronic device 300, such as a high-speed mode detection method for USB devices. Figure 3 The diagram shown is a structural schematic of an electronic device 300 provided in an embodiment of this disclosure, including: Processor 31, memory 32, and bus 33; memory 32 is used to store execution instructions, including main memory 321 and external memory 322; the main memory 321, also called internal memory, is used to temporarily store the computational data in processor 31, as well as the data exchanged with external memory 322 such as hard disk. Processor 31 exchanges data with external memory 322 through main memory 321. When the electronic device 300 is running, processor 31 and memory 32 communicate through bus 33, enabling processor 31 to execute... Figure 1 The steps of the high-speed mode detection method for USB devices.

[0108] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the high-speed mode detection method for a USB device described in the above-described method embodiments. The storage medium can be either volatile or non-volatile computer-readable storage.

[0109] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the high-speed mode detection method for USB devices described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0110] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0111] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0112] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0113] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0114] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0115] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for detecting high-speed mode of a USB device, characterized in that, include: The differential signal of the USB bus is acquired and the differential signal is detected in parallel to obtain the SEO state detection result, J state detection result and signal quality detection result; When the SE0 state is detected, a first time window is started to verify the duration of the SE0 state in order to determine whether the SE0 state meets the preset reset judgment condition. If the preset reset determination condition is met in the SE0 state, it is detected whether the USB bus has entered the J state, and when the J state is detected, a second time window is started to verify the duration of the J state. The signal edge quality corresponding to the J state is detected to determine whether the J state is a valid handshake signal; Based on the duration verification results of the SEO state, the duration verification results of the J state, and the quality detection results of the signal edge, the system determines whether the current host supports high-speed mode according to the preset state determination logic and outputs the high-speed mode detection result.

2. The method according to claim 1, characterized in that, Parallel detection of the differential signal specifically includes: USB bus signals are received via a differential receiver; The USB bus is detected to be in the SE0 state via a separate SE0 state detection channel. The USB bus is detected to be in J state by an independent J state detection channel. The J state detection channel is set with hysteresis when performing J state detection to reduce the influence of the ringing signal on the J state determination. The edge rate information of the corresponding edge of the USB bus is detected through an independent signal quality monitoring channel.

3. The method according to claim 1, characterized in that, Verification of the duration of state J specifically includes: When state J is detected within the first time window, the second time window is started; Determine whether the duration of state J is within a second preset time range; When the duration of state J is within the second preset time range, the timing detection result of state J is determined to be valid.

4. The method according to claim 1, characterized in that, The signal edge quality corresponding to the J state is detected, specifically including: High-speed sampling is initiated when a signal edge is detected. Acquire waveform data within a preset time range before and after the signal edge; The edge time is calculated based on the waveform data, wherein the edge time is the time corresponding to the signal amplitude changing from 10% to 90%; The edge time is compared with a preset edge threshold to output a signal quality detection result. When the edge time is not greater than the preset edge threshold, the corresponding signal is determined to be a valid signal. When the edge time is greater than the preset edge threshold, the corresponding signal is determined to be a pseudo signal.

5. The method according to claim 1, characterized in that, The preset state determination logic includes: The host is determined to support high-speed mode only when the SE0 state meets the reset determination condition, the J state meets the duration determination condition, and the signal edge quality meets the validity determination condition. If any of the above conditions are not met, the host is determined to not support high-speed mode or the test is invalid.

6. The method according to claim 1, characterized in that, The method further includes: The number of J state pulses is counted during the SE0 state detection period; The number of J-state pulses is used to determine whether the current environment is a high-noise environment. When the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted.

7. The method according to claim 6, characterized in that, The method further includes: When the number of J state pulses exceeds a preset threshold, the current environment is determined to be a high-noise environment. When the current environment is determined to be a high-noise environment, the lower limit threshold of the second time window is adjusted from the first lower limit threshold to the second lower limit threshold, wherein the first lower limit threshold is less than the second lower limit threshold. When the low noise condition is met for multiple consecutive detection cycles, the adjusted lower limit threshold of the second time window will be restored to the initial threshold. When multiple consecutive detection cycles are all low noise, the lower limit threshold of the second time window is restored to the first lower limit threshold.

8. A high-speed mode detection device for a USB device, characterized in that, include: The detection module is used to acquire the differential signal of the USB bus and perform parallel detection on the differential signal to obtain the SEO state detection result, the J state detection result, and the signal quality detection result. The first determination module is used to start a first time window when the SE0 state is detected, and to verify the duration of the SE0 state in order to determine whether the SE0 state meets the preset reset determination condition. The second determination module is used to detect whether the USB bus has entered the J state when the SEO state meets the preset reset determination condition, and to start a second time window when the J state is detected to verify the duration of the J state. The third determination module is used to detect the signal edge quality corresponding to the J state in order to determine whether the J state is a valid handshake signal. The result output module is used to determine whether the current host supports high-speed mode based on the duration verification result of the SEO state, the duration verification result of the J state, and the quality detection result of the signal edge, according to a preset state determination logic, and output the high-speed mode detection result.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the high-speed mode detection method for a USB device as described in any one of claims 1 to 7 are performed.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the high-speed mode detection method for a USB device as described in any one of claims 1 to 7.

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