High-precision random calculation method based on binary partial product and multiplier

Abstract

The invention belongs to the field of heterogeneous approximate calculation, and relates to a high-precision random calculation method based on a binary partial product and a multiplier. The high-precision random calculation method based on the binary partial product directly uses the weight of a bit corresponding to a binary number to generate a random bit stream. Bit streams are combined in a uniform distribution mode, phase and sum are carried out bit by bit, and all phase and results are added to obtain the random calculation multiplier with the optimal precision. According to the method, binary weights are combined, a shifting and splicing mode is used for replacing addition, partial product addition is used for achieving random calculation, and an approximate parallel counter is adopted for optimization. The multiplier provided by the invention fully combines the advantages of random calculation and binary calculation, the hardware cost is less than half of that of a binary multiplier, and the delay is lower. When the provided multiplier is applied to neural network reasoning, the precision of model loss can be almost ignored.

Description

Technical Field

[0001] This invention belongs to the field of heterogeneous approximation computation, and in particular relates to a high-precision random computation method and multiplier based on binary partial product. Background Technology

[0002] Stochastic computing is an approximate computation method that uses a random bitstream with weights of 1 to represent numerical values. For example... Figure 1 As shown in (a), the random bit stream is obtained by comparing random numbers generated by a Stochastic Number Generator (SNG) with the actual binary number. When the generated random number is less than the actual number, the random bit stream is output as "1". The value represented by the random bit stream is the number of "1"s divided by the bit stream length. Given these characteristics, random computation is also called probability computation, where the input and output represent the probability that the random number sequence is smaller than the actual value. Therefore, the longer the random bit stream, the closer the result is to the true probability, and the higher the accuracy. N-bit operations generally correspond to a bit stream length of 2. N In practical applications, adjustments can be made according to the required precision. Different random number sequences generated by different SNGs will also affect the precision of random computation. Currently, low-difference SNGs are mainly used, which can achieve high precision when the random bit stream is short. The operational unit of random computation is extremely simple, requiring only one AND gate to complete the multiplication operation. Figure 1 The example of multiplication based on random computation is shown, where a 3-bit binary number is transformed into a random bit stream of length 8 to participate in the operation. For example, when A is 4, the corresponding bit stream is {1,0,1,0,0,0,1,1}, and the corresponding probability value P(A) is 4 / 8. After ANDing with the random bit stream of B, we get P(AB) = P(A) & P(B) = 4 / 8 × 4 / 8 = {0,0,1,0,0,0,1,0} = 2 / 8.

[0003] While random computation offers advantages such as small size and low power consumption, practical applications typically require converting binary numbers into random bitstreams, performing calculations, and then converting them back to binary. Therefore, the hardware overhead of conversion units such as SNGs, comparators, and counters must be considered in practical applications. Furthermore, the length of the random bitstream in random computation determines the computation cycle, resulting in a relatively long time required to complete a single calculation. These characteristics present challenges for random computation in practical applications. Summary of the Invention

[0004] To address the aforementioned problems, this invention aims to construct a multiplier that combines the advantages of binary computation and random computation, and can directly implement random computation by adding binary partial products, making it directly applicable to binary computation systems. Furthermore, a two-layer approximate parallel counter is proposed to further optimize hardware resources.

[0005] To achieve the above-mentioned objectives, the technical solution of the present invention includes the following: A high-precision random computation method based on binary partial product includes the following steps: Obtain the two input multipliers A and B, and generate parallel random bit streams based on the binary weights of A and B respectively; The random bit stream generated by multiplier A is fixed, and the parallel random bit stream generated by multiplier B is combined with the random bit stream of multiplier A according to the uniform distribution rule and bitwise ANDed to obtain the optimal random calculation combination. Perform an AND operation on the best combination of random computations, and then shift and concatenate the results of the same AND gate to form a binary number. The resulting binary number is mapped to a partial product of binary multiplication, and the multiplication result is obtained by adding the partial products together.

[0006] Furthermore, when adding the binary partial products, it was found that a large number of bits with a weight of 1 were added. Approximate parallel counters (using AND gates and OR gates alternately to replace full adders) can be used to further reduce resource consumption.

[0007] Furthermore, the parallel random bitstream generated based on the binary weights of A and B is generated directly by connecting the weights carried by the bits of the multiplier (represented as wires in hardware). For example, when A is... At this time The weight is , The weight is , The weight is , The weight is The corresponding generated random bit stream is Generally, when A is At that time, among them The weight is Where i is 1, 2, ..., n, the generated random bit stream contains indivual That is, sequentially containing indivual , indivual , ..., indivual Similarly, when B is At that time, among them The weight is Where i is 1, 2, ..., n, the generated random bit stream contains indivual That is, sequentially containing indivual , indivual , ..., indivual .

[0008] Furthermore, the uniform allocation rule means that the order of B's ​​random bitstream needs to correspond to the number of bits in A's random bitstream, and the bits are evenly distributed. For example, when the random bitstream generated by A is fixed as follows... At that time, A had 8. , correspondingly allocated to 4 2 1 And one 4 of A Then it is assigned to 2. 1 and 1 2 of A Assigned to 1 and 1 1 of A Assigned to 1 According to this uniform distribution rule, the final order of the random bit stream of B is as follows: This allows us to obtain the current optimal combination of random computations. Generally, when the random bitstream of A is fixed at... At this time, B is That is, A's indivual Distributed to indivual , indivual ...1 and 1 , indivual Assigned to indivual , indivual ...1 and 1 ..., the last one Assigned to .

[0009] Furthermore, after obtaining the optimal combination of random computations, the optimal combination of random computations will be... and Corresponding AND (e.g.) and , and , and , and , ..., and ), and statistically analyze the results of identical AND gates. According to the combination rules, we can see that... Since most numbers are multiples of 2, we can use bit shifting to replace addition and form binary numbers (i.e., perform shifting and concatenation). Then, we can map the binary numbers to the partial products of binary multiplication (e.g., if the AND result has 4...). 2 1 Addition can be expressed as Shift left by 2 bits. Shift left by 1 bit, Shifting left by 0 bits allows the final result to be concatenated into a binary number. ,in The weight is , Corresponding to The partial product obtained by ANDing with B By shifting right by 1 bit, random calculations can be directly performed using the partial product of the corresponding binary multiplication. The multiplication result is obtained by adding the partial products. Furthermore, to address the issue of too many bits with a weight of 1 in the final accumulated partial product, an approximate parallel counter with alternating AND and OR gates can be used to replace the full adder, further reducing hardware consumption. When 1 and 0 are ANDed, 0 is obtained, resulting in a "-1" error; when 0 and 1 are ORed, 1 is obtained, resulting in a "+1" error. The alternation of AND and OR gates enables error compensation.

[0010] Corresponding to the above-mentioned serial high-precision random calculation method, the present invention also provides a high-precision random calculation multiplier based on binary partial product: the multiplier is divided into a random bit stream generation module, a partial product representation random calculation module, and may further include an approximately parallel counter module; The random bit stream generation module obtains two input multipliers A and B, and directly generates a parallel random bit stream based on the binary weight bits. The partial product represents the random calculation module using a uniform distribution rule to combine two parallel random bit streams of input and perform bitwise AND. After shifting and concatenating the same AND gate results (shifting and concatenating the original multiple bits with a weight of 1), the corresponding binary numbers in the binary partial product are obtained. The binary numbers are then added together to obtain the multiplication result. The approximate parallel counter module approximates the accumulation of multiple bits with a weight of 1 in the partial product, and uses AND gates and OR gates alternately to replace the full adder, making the multiplier more suitable for resource-constrained scenarios while not significantly reducing accuracy.

[0011] Furthermore, the partial product of an n-bit binary multiplier for Where i is 1 to 8, the following formula is used to represent an n-bit random multiplier: in, This indicates that the result of a random multiplication is calculated.

[0012] Compared with the prior art, the present invention has at least the following technical advantages: 1) The new multiplier scheme proposed in this invention can directly use the partial product of binary numbers to achieve random calculation.

[0013] 2) The multiplier proposed in this invention can be directly used in binary computing systems.

[0014] 3) The multiplier proposed in this invention maintains high accuracy while having low hardware cost and low latency.

[0015] 4) The approximate parallel counter scheme proposed in this invention can further reduce the hardware consumption of the proposed multiplier, with no significant decrease in accuracy, and can be easily extended to arbitrary bit widths, satisfying the vast majority of applications. Attached Figure Description

[0016] Figure 1 This is a flowchart of the steps of the high-precision random calculation method based on binary partial product of the present invention.

[0017] Figure 2 These are schematic diagrams of traditional random computation and binary weight-based random computation, where (a) is traditional random computation and (b) is an example diagram of binary weight-based random computation.

[0018] Figure 3 This is a module composition diagram of the high-precision random calculation multiplier based on binary partial product of the present invention.

[0019] Figure 4 This is a schematic diagram of an 8-bit multiplier that uses partial product to perform random computation. The compressor refers to a parallel counter or an approximately parallel counter.

[0020] Figure 5This is a schematic diagram of a two-layer approximately parallel counter. X0~X15 represent 16 input signals, each of which represents a binary bit, which can be 0 or 1; FA represents a full adder, and CPRS[0], CPRS[1], and CPRS[2] represent the 3-bit compressed result output after the 16 input signals are compressed.

[0021] Figure 6 This is a schematic diagram showing the one-to-one correspondence between the inputs and partial products of a parallel counter. The inputs of the parallel counter are all bits with a weight of 1 during random calculation, represented by partial products. Detailed Implementation

[0022] To make the objectives, contents, and advantages of this invention clearer and more apparent, and to enable those skilled in the art to understand this invention, the invention will now be described in further detail with reference to the accompanying drawings.

[0023] This invention provides a high-precision random calculation method based on binary partial product, such as... Figure 1 As shown, it includes the following steps: Step 1: Obtain the two input multipliers A and B, and generate a parallel random bit stream based on the binary weights of A and B.

[0024] Figure 2 In (a), the traditional random computation method is used, which uses SNG and comparators to generate a random bit stream.

[0025] Figure 2 The upper part of section (b) uses the weighted method of this invention to generate a random bit stream. This generation method is a pseudo-random method. Taking 3 bits A=4='100' as an example, when it is transformed into a fixed random bit stream: ={0,0,0,1,1,1,1}, then P(A)=4 / 8.

[0026] Step 2: Fix the random bit stream generated by multiplier A, and combine the parallel random bit stream generated by multiplier B with the random bit stream of multiplier A according to the uniform distribution rule and perform bitwise AND to obtain the optimal random calculation combination.

[0027] Figure 2 Figure (b) shows the optimal combination for random computation of 3-bit and 4-bit multipliers. The optimal combination corresponds to the best precision obtained by the current random computation multiplication when ANDed. In fact, the optimal combination of 3-bit, 4-bit, 5-bit...n-bit multipliers all follow the uniform distribution rule to obtain the best precision.

[0028] When the random bit stream of 3 bits A is fixed as At this time, B should be That is, the four of A Distributed to 2 1 and 1 2 of A Assigned to 1 and 1 1 of A Assigned to 1 .

[0029] When the 4-bit random bit stream A is fixed as At this time, B should be That is, the 8 of A Distributed to 4 2 1 And one 4 of A Then it is assigned to 2. 1 and 1 2 of A Assigned to 1 and 1 The last one of A Assigned to 1 .

[0030] When the random bit stream of the input A of the n-bit multiplier is fixed as At this time, B should be That is, A's indivual Distributed to indivual , indivual ...1 and 1 , indivual Assigned to indivual , indivual ...1 and 1 ..., the last one Assigned to .

[0031] Step 3: Perform an AND operation on the best random calculation combination, and shift and concatenate the results of the same AND gate to form a binary number.

[0032] According to the above uniform distribution rule, the optimal combination can be obtained. At the same time, due to its uniform distribution, the number of its many AND results is a power of 2, which can be combined with binary weights to replace addition with shifting.

[0033] Step 4: Match the resulting binary number with the partial products of binary multiplication, and obtain the multiplication result by adding the partial products.

[0034] By associating the binary number generated in step 3 with the partial product in the binary representation, random computation can be achieved using the binary partial product. The expression for generating the partial product is: At that time, an n-bit random multiplier can be represented as follows: in, This indicates that the result of a random multiplication is calculated. This indicates a partial product.

[0035] This invention provides a high-precision random multiplier based on binary partial product, such as... Figure 3 As shown, it includes: The random bit stream generation module is responsible for obtaining the two input multipliers A and B, and generating parallel random bit streams based on the binary weights of A and B. The partial product represents the random computation module, which is used to fix the random bit stream generated by multiplier A, combine the parallel random bit stream generated by multiplier B with the random bit stream of multiplier A according to the uniform distribution rule and perform bitwise AND to obtain the optimal random computation combination, perform AND on the optimal random computation combination, shift and concatenate the same AND gate results to form a binary number, match the formed binary number with the partial product of binary multiplication, and obtain the multiplication result by adding the partial products.

[0036] The aforementioned random computation multiplier may further include an approximate parallel counter module, which is responsible for replacing the full adder with an approximate parallel counter that uses alternating AND and OR gates to approximate the accumulation of multiple bits with a weight of 1 in the partial product.

[0037] An example of an 8-bit multiplier based on the method of this invention is provided below.

[0038] 8-bit multiplier such as Figure 4 As shown. It uses partial product to represent random calculation, corresponding to the formula above. The weight of the gray area is 2. 0 The bits after the dashed line are the discarded bits. The final result of the multiplication is 8 bits, and the corresponding bit stream length for 8 bits is 2. 8 The results were consistent.

[0039] Figure 5 , Figure 6This paper proposes a two-layer approximate parallel counter. The first layer of the approximate parallel counter consists of gates ①~⑧, which use alternating OR and AND gates to replace the full adder. OR will produce a "+1" error (when the input is 0 or 1, the output is 1, resulting in an error of +1, i.e., adding an extra 1), while AND will produce a "-1" error (when the input is 0 or 1, the output is 0, resulting in an error of -1, i.e., adding an insufficient 1). Therefore, alternating AND and OR gates can achieve error compensation. The second layer of the approximate parallel counter (using all OR gates) takes the results from gates ③~⑧ in the first layer as input and outputs the input of the full adder. Figure 6 The diagram illustrates the input method for an approximate parallel counter, showing that the optimal accuracy can be obtained by inputting the counter as shown in the figure.

[0040] When using an approximate parallel counter, hardware consumption is lower. Even without using an approximate parallel counter, the proposed multiplier based on binary partial product for random computation still outperforms the binary multiplier in terms of hardware performance.

[0041] For example, if A is 128 and B is 255, then A = '10000000' and B = '11111111'. =('1111111'+0...+0)+('1'+0...+0)=127+1=128. AB=128×255=32640. =128 / 256=0.5, P(AB)=32640 / 256 / 256=0.498046875. The error is 0.001953125. When using 2-layer APC optimization, =126+1=127 / 256=0.49609375, and the error is 0.001953125.

[0042] In summary, this invention optimizes the long computation cycle required for random multiplication operations and the significant overhead of the SNG, comparators, and counters used in practical applications. Its advantages are: 1) The proposed multiplier scheme uses binary partial product to achieve random computation, which has a lower hardware cost.

[0043] 2) The proposed multiplier can be directly applied to binary systems and can complete the calculation in just one clock cycle.

[0044] 3) The proposed two-layer approximate parallel counter can further optimize the hardware consumption of the multiplier and reduce latency.

[0045] 4) The proposed multiplier and its optimized version of the approximate parallel counter can be easily extended to arbitrary bits and are suitable for a variety of application scenarios.

[0046] The high-precision random computation method and multiplier based on binary partial product of this invention can be used in various image algorithms and inference of various neural networks. For example, when used for neural network inference, the multiply-accumulate unit built using the method of this invention is used for inference of the quantized neural network, and the accuracy loss of the model is almost negligible.

[0047] Although specific embodiments of the invention have been disclosed for illustrative purposes to aid in understanding and implementing the invention, those skilled in the art will understand that various substitutions, variations, and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the content disclosed in the preferred embodiments, and the scope of protection claimed by the invention is defined by the claims.

Claims

1. A high-precision random calculation method based on binary partial product, characterized in that, Includes the following steps: Obtain the two input multipliers A and B, and generate parallel random bit streams based on the binary weights of A and B; The random bit stream generated by multiplier A is fixed, and the parallel random bit stream generated by multiplier B is combined with the random bit stream of multiplier A according to the uniform distribution rule and bitwise ANDed to obtain the optimal random calculation combination. Perform an AND operation on the best combination of random calculations, and then shift and concatenate the results of the same AND gate to form a binary number. The resulting binary number is mapped to a partial product of binary multiplication, and the multiplication result is obtained by adding the partial products together.

2. The method according to claim 1, characterized in that, The generation of parallel random bitstreams based on the binary weights of A and B includes: When A is At that time, among them The weight is Where i is 1, 2, ..., n, the generated random bitstream contains indivual That is, sequentially containing indivual , indivual , ..., indivual ; When B is At that time, among them The weight is Where i is 1, 2, ..., n, the generated random bitstream contains indivual That is, sequentially containing indivual , indivual , ..., indivual .

3. The method according to claim 1, characterized in that, The uniform distribution rule includes: When the random bit stream of A is fixed as When, B is That is, A's indivual Distributed to indivual , indivual ...1 and 1 , indivual Assigned to indivual , indivual ...1 and 1 ..., the last one Assigned to .

4. The method according to claim 1, characterized in that, The method of adding partial products to obtain the multiplication result includes: replacing the full adder with an approximately parallel counter that alternates between AND and OR gates, and approximately accumulating multiple bits with a weight of 1 in the partial product.

5. The method according to claim 4, characterized in that, In the approximate parallel counter, ANDing 1 with 0 results in 0, generating a "-1" error; ORing 0 with 1 results in 1, generating a "+1" error. Error compensation is achieved by alternating AND and OR gates.

6. A high-precision random multiplication multiplier based on binary partial product, characterized in that, include: The random bit stream generation module is responsible for obtaining the two input multipliers A and B, and generating parallel random bit streams based on the binary weights of A and B. The partial product represents the random computation module, which is used to fix the random bit stream generated by multiplier A, combine the parallel random bit stream generated by multiplier B with the random bit stream of multiplier A according to the uniform distribution rule and perform bitwise AND to obtain the optimal random computation combination, perform AND on the optimal random computation combination, shift and concatenate the same AND gate results to form a binary number, match the formed binary number with the partial product of binary multiplication, and obtain the multiplication result by adding the partial products.

7. The random computation multiplier according to claim 6, characterized in that, It also includes an approximate parallel counter module, which is responsible for replacing the full adder with an approximate parallel counter that uses alternating AND and OR gates to approximate the accumulation of multiple bits with a weight of 1 in the partial product.

8. The random computation multiplier according to claim 6, characterized in that, Partial product of an n-bit binary multiplier for Where i is 1 to 8, the following formula is used to represent an n-bit random multiplier: in, This indicates that the result of a random multiplication is calculated.

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