High-power MEMS switching system and method based on time sequence collaborative arc suppression

Abstract

The invention belongs to the related technical field of micromotors, and discloses a high-power MEMS switching system and method based on time sequence collaborative arc suppression. The system comprises a load circuit, an electric arc suppression module and a time sequence control circuit, the electric arc suppression module is composed of an LC arc extinguishing branch and a capacitor charging and discharging branch, and the LC arc extinguishing branch is connected to the two ends of an MEMS main switch in parallel and used for establishing a near-zero voltage environment at the moment of switch on-off; the sequential control circuit adopts a full-hardware logic architecture, generates multiple paths of control signals with an accurate delay relation, and cooperatively controls capacitor pre-charging, resonant commutation and main switch action. The LC resonance commutation is actively triggered before the main switch contact is mechanically closed or separated, and the load current is forcibly transferred, so that arc-free connection and disconnection are realized. The problem that arc suppression is difficult in the breaking process of the high-power micro-electro-mechanical switch is effectively solved, the reliability of the switch is improved, and the service life of the switch is prolonged.

Description

Technical Field

[0001] This invention belongs to the field of micro-motor technology, and more specifically, relates to a high-power MEMS switching system and method based on time-series coordinated arc suppression. Background Technology

[0002] High-power circuit switching technology has evolved from traditional electromechanical relays to solid-state relays, and then to microelectromechanical system (MEMS) switches. Traditional electromechanical relays rely on mechanical contacts to switch circuits on and off. While offering good conduction characteristics, they suffer from inherent drawbacks such as large size, slow response speed, and susceptibility to arcing. Solid-state relays utilize semiconductor technology, solving the problem of mechanical wear, but face new challenges such as high conduction losses, leakage current during shutdown, and the need for complex heat dissipation designs. MEMS switches are considered the next-generation technology combining the advantages of both. However, when applied to high-voltage, high-current scenarios, the arcing generated during switching becomes a core technological bottleneck restricting their reliability and lifespan.

[0003] Traditional electromechanical relays are slow to respond and prone to arcing; solid-state relays suffer from high conduction losses and leakage current during turn-off. Existing microelectromechanical switching technology lacks precise active control for arc suppression. Particularly in timing control, it cannot achieve precise synchronization of multiple channels, resulting in incomplete current transfer and poor arc extinguishing performance. Furthermore, existing solutions lack adaptability to complex operating conditions and cannot dynamically adjust protection parameters according to load characteristics.

[0004] Furthermore, some arc-extinguishing schemes based on passive devices (such as balanced diode bridges) are essentially a "passive response" mechanism. Their operation relies on fault detection and has an inherent delay; more importantly, their circuit principle determines that they can usually only provide protection for the "breaking process" and are difficult to effectively suppress arcing during the "connection process," thus failing to achieve comprehensive protection for a complete on-off cycle.

[0005] The aforementioned problems severely limit the application of high-power MEMS switches in applications with extremely high reliability requirements (such as aerospace and smart grids), highlighting the urgent need for a new system architecture and method that can actively and precisely control the entire switching process and suppress electric arcs at the source. Summary of the Invention

[0006] To address the above-mentioned deficiencies or improvement needs of existing technologies, this invention provides a high-power MEMS switching system and method based on time-coordinated arc suppression, solving the problem of difficult arc suppression in high-power circuit switching.

[0007] To achieve the above objectives, according to one aspect of the present invention, a high-power MEMS switching system based on timing-coordinated arc suppression is provided. The system includes a load circuit, an arc suppression module, and a timing control circuit, wherein: The load circuit includes a main power supply, a load, and a third switch, which are connected in series to form a loop. The arc suppression module is used to prevent arcing in the third switch; the arc suppression module includes an LC arc extinguishing branch and a capacitor charging and discharging branch, wherein: The LC arc-extinguishing branch is connected in parallel across the two ends of the third switch to establish and maintain an approximately zero potential range far below the breakdown voltage across the two ends of the third switch contacts. The LC arc-extinguishing branch includes a rectifier circuit, an inductor, a diode, a second switch, and a capacitor connected in sequence. The capacitor charging and discharging branch provides an initial preset voltage to the capacitor. The capacitor charging and discharging branch includes an auxiliary power supply and a first switch, with the first switch disposed between the capacitor and the auxiliary power supply. The timing control circuit is connected to the first switch, the second switch, and the third switch simultaneously. It is used to determine whether the current electrical signal jumps to a high level or a low level, and to control the opening and closing of the first switch, the second switch, and the third switch according to the determination result.

[0008] The LC arc extinguishing branch is a single-stage or multi-stage resonant network structure.

[0009] The timing control circuit judges and processes a single input signal and outputs three coordinated control signals with specific delays and logical relationships. The timing control circuit module adopts a full hardware logic architecture, including three types of components: monostable multivibrators, logic gates, and D flip-flops.

[0010] The third switch is a MEMS switch.

[0011] The first and second switches are MOSFET switches, fast switches, or a combination of MOSFET and IGBT devices.

[0012] According to another aspect of the present invention, an arc suppression method utilizing the system described above is provided, the method comprising the following steps: The timing control circuit determines whether a transition has occurred in the current signal. When the signal transitions to a high level, the arc suppression steps are as follows: The timing control circuit generates a Gc signal transition, which drives the first switch to change from closed to open, charging the pulse capacitor to a preset voltage. After the capacitor is fully charged, the timing control circuit generates a GMOS signal transition, which drives the second switch to close from open. The current from the main power supply returns to the negative terminal of the main power supply through the LC arc extinguishing branch, establishing a low-impedance bypass for the load current. The voltage across the third switch approaches zero. After a preset fixed delay, the timing control circuit generates a Gmems signal transition, driving the third main switch to close. The current from the main power supply returns to the negative terminal through the load and the third switch. At this time, the load current has been shunted through the bypass. The third switch closes when the voltage at both ends is close to zero, eliminating the arc during the connection process. When the signal transitions to a low level, the arc suppression steps are as follows: The timing control circuit first generates a Gc signal transition, driving the first switch to change from closed to open; Next, the timing control circuit generates a GMOS signal transition, driving the second switch to close from open. The current from the main power supply returns to the negative terminal of the main power supply through the LC arc extinguishing branch. The LC resonant network is triggered, generating a current pulse that transfers the load current from the third switch. The voltage across the third switch approaches zero. After a preset fixed delay, the timing control circuit generates a Gmems signal transition, driving the third switch to open. The switch contacts safely separate under the established zero voltage condition, suppressing the interruption arc.

[0013] More preferably, during the Gmems signal transition generated by the timing control circuit after a preset fixed delay, the fixed delay is calculated based on the characteristics of the capacitor and inductor.

[0014] More preferably, the formula for calculating the fixed delay is as follows:

[0015] Where t is a fixed delay, L is the inductance value, and C is the capacitance value.

[0016] More preferably, the preset voltage of the capacitor satisfies the following conditions:

[0017] Where V is the preset voltage of the capacitor, and I load L is the load current, C is the inductance value, and C is the capacitance value.

[0018] According to another aspect of the present invention, an arc suppression system is provided, the system including an actuator for performing the arc suppression method described above.

[0019] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art: 1. This invention employs a fully hardware-based centralized timing control circuit to generate multiple coordinated control signals with precise delay relationships. It accurately schedules the operation timing of the capacitor charging and discharging circuit and the arc-extinguishing power circuit. At the critical moment when the MEMS main switch is turned on and off, it actively creates and maintains zero-voltage operating conditions during the dual processes of turning on and off the MEMS main switch, thereby fundamentally suppressing the generation of electric arcs.

[0020] 2. The timing control circuit of the present invention is a pure hardware architecture that generates multiple control signals with fixed and precise delay relationships, thereby ensuring strict microsecond-level timing matching between energy transfer and mechanical action, and providing a core guarantee for forming a reliable zero-voltage window.

[0021] 3. The all-hardware, software-free control method of the arc suppression system of the present invention naturally has the characteristics of fast response speed, good determinism, and strong anti-electromagnetic interference capability. At the same time, its architecture based on standard logic and passive components has clear modules, providing a solid technical foundation for realizing high-density integration or single-chip implementation of the system in high-reliability application scenarios such as aerospace and smart grids.

[0022] 4. This invention is particularly applicable to fields such as aerospace, new energy equipment, smart grids, and high-end industrial drives, which have stringent requirements for switching speed, arc suppression capability, and operational reliability, and provides a feasible technical path for achieving high system integration and single-chip implementation. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a high-power MEMS switching system based on time-coordinated arc suppression constructed according to a preferred embodiment of the present invention.

[0024] Figure 2 This is a flowchart of the arc suppression process constructed according to a preferred embodiment of the present invention.

[0025] Figure 3 It is a timing control diagram constructed according to a preferred embodiment of the present invention.

[0026] Figure 4 This is a voltage waveform variation diagram constructed according to a preferred embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the timing control circuit constructed according to a preferred embodiment of the present invention.

[0028] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 1-Main power supply, 2-Load, 3-Third switch, 4-Rectifier circuit, 5-Inductor, 6-Diode, 7-Second switch, 8-Capacitor, 9-First switch, 10-Auxiliary power supply, 11-Timing control circuit. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0030] like Figure 1 As shown, the high-power microelectromechanical switching system and method of the present invention, the core of this system lies in the precise scheduling of the capacitor charging and discharging branch and the LC arc extinguishing branch through a centralized timing coordination control circuit, i.e., timing drive circuit, to actively create and maintain a zero-voltage environment for the third switch 3 at the precise moment of its on / off action, thereby achieving arc-free operation.

[0031] The system includes a load circuit, an arc suppression module, and a timing control circuit, wherein: The load circuit includes main power supply 1, load 2 and third switch 3, which are connected in series to form a loop; The arc suppression module is used to prevent arcing in the third switch; the arc suppression module includes an LC arc extinguishing branch and a capacitor charging and discharging branch, wherein: An LC arc-extinguishing branch is connected in parallel across the two ends of the third switch to establish and maintain an approximately zero potential range far below the breakdown voltage across the two ends of the third switch contacts. The LC arc-extinguishing branch includes a rectifier circuit 4, an inductor 5, a diode 6, a second switch 7, and a capacitor 8 connected in sequence. The capacitor charging and discharging branch provides an initial preset voltage to the capacitor. The capacitor charging and discharging branch includes an auxiliary power supply 10 and a first switch 9, with the first switch 9 disposed between the capacitor 8 and the auxiliary power supply 10. The timing control circuit 11 is connected to the first switch 9, the second switch 7 and the third switch 3 at the same time. It is used to determine whether the current electrical signal jumps to a high level or a low level, and to control the opening and closing of the first switch, the second switch and the third switch according to the determination result.

[0032] The core of the timing control circuit is based on a monostable multivibrator and an RC delay network. It is used to receive external trigger signals and generate three control signals with fixed delay relationships: the switching control signal (Gc) of the capacitor charging and discharging branch, the switching control signal (Gmos) of the LC arc extinguishing branch, and the control signal (Gmems) of the load circuit switch.

[0033] The capacitor charging and discharging branch is used to control the charging and discharging of the capacitor, and includes an auxiliary power supply 10 and a first switch 9.

[0034] The rectifier circuit 4 is the core of dynamic commutation and voltage clamping. It provides an alternative path for the load current with zero voltage clamping at the moment of switching on and off, thereby forcibly transferring the current from the MEMS switch, while clamping the voltage across the MEMS switch at a very low forward voltage drop level.

[0035] Inductor 5, together with capacitor, determines the resonant frequency, thereby precisely controlling the rise rate, peak value, and pulse width of the pulse current, ensuring that the pulse current has the amplitude and timing characteristics required to drive commutation.

[0036] In the initial stage, capacitor 8 is pre-charged to a predetermined voltage as the initial energy source for resonance. During the resonant commutation stage, it generates pulse current through discharge. The capacitance value directly affects the peak value and duration of the pulse current. In the later stages of current transfer and turn-off, it absorbs and stores the remaining energy transferred from the load inductance.

[0037] Diode 6 is used for unidirectional conduction and state-locked switching. During the resonant commutation phase, it ensures that the pulse current flows in a predetermined half-wave sinusoidal form. After the current crosses zero, it immediately cuts off due to its fast reverse recovery characteristic, thereby precisely terminating the resonant process and locking the reverse charging voltage across the capacitor to prevent energy feedback and ensure unidirectional energy absorption.

[0038] The timing control circuit 11 is used for decomposing a single input signal and generating multiple timing sequences. This timing control circuit module adopts a fully hardware logic architecture, including monostable multivibrators, logic gates, and D flip-flops. In one embodiment of the invention, it is constructed by cascading multiple levels of 74HC123 monostable multivibrator chips, combined with 74HC32 OR gates and 74HC74D flip-flops. Figure 5As shown, the timing control circuit includes cascaded monostable multivibrators, logic gates, and D flip-flops. These multi-stage monostable multivibrators are cascaded sequentially and interconnected with corresponding logic elements, forming a multi-channel signal link with progressively delayed delays. The input trigger signal is first processed by the preceding monostable multivibrator link to generate a pulse signal with a preset delay. This signal is directly output as the first level control signal and simultaneously serves as the trigger source for subsequent links. This trigger source drives the subsequent flip-flops and logic gate units to work together, generating a second control signal with an independently adjustable pulse width. Further, the output signal of a specific monostable multivibrator in the link is selected as the clock input for the D flip-flop, causing it to flip at the effective edge trigger state, thereby generating a third level control signal with state retention functionality. Through this cascading and combination method, the three output signals are precisely matched in timing, sequentially controlling the switching actions in the arc suppression module to ensure precise coordination between the commutation process and the mechanical separation action. The LC arc extinguishing branch includes a resonant inductor, a pre-charged capacitor, a MOSFET for the second switch, and a current path control network composed of diodes, etc.

[0039] Based on Pascal's Law, when the gap between the third switch contacts is on the order of micrometers, maintaining the voltage across it below the dielectric breakdown threshold is crucial for suppressing arc generation. In this invention, the timing control circuit first controls the capacitor charging / discharging branch to pre-charge the pulse capacitor. The preset voltage value of the capacitor needs to satisfy the following:

[0040] Where V is the pre-charge voltage, I load L is the load current, C is the inductance value, and C is the capacitance value.

[0041] After the capacitor is fully charged, the LC arc-extinguishing branch is activated, causing the pre-charged capacitor to discharge through the resonant network. This generates a half-wave sinusoidal pulse current with an amplitude higher than the peak load current and precise timing (the pulse must trigger before the mechanical contact of the third switch). The error is within microseconds. This pulse can cancel the load current flowing through the third switch within microseconds, thus actively establishing and maintaining an approximately zero potential range, far below the breakdown voltage, at the two ends of the switch contacts—the "zero-voltage window." The mechanical switching action of the third switch is strictly limited to this window, thereby suppressing the generation of an electric arc. After the system completes its operation, the residual energy in the load circuit is absorbed by the capacitor through the attenuating resonant circuit composed of the load, pulse inductor, and pulse capacitor. Energy dissipation is actively managed through optimized design of the resonant parameters (such as the selection of capacitors and inductors).

[0042] The timing control circuit can use a digital signal processor to achieve more flexible delay adjustment through software programming; In terms of arc extinguishing circuits, a multi-stage resonant network structure can be adopted, and a stepped current transfer mechanism can be used to adapt to higher power application scenarios. In terms of switching topology, MOSFET and IGBT devices can be used in combination to fully utilize their respective advantages to build a hybrid arc extinguishing system.

[0043] The working process of the above system is described below.

[0044] like Figure 2 As shown, during system operation, the timing control circuit receives external commands and generates three control signals with precise delay relationships in parallel. These signals drive the second and third switches in the capacitor charging / discharging branch and the LC arc-extinguishing branch, respectively. Through the mandatory timing logic of "capacitor charging first, arc-extinguishing circuit conducting first, and third switch operating later," the system ensures that the voltage across the switch contacts is always actively clamped to near zero volts before and after the contacts close or open, thereby completely eliminating the voltage conditions that cause arcing during high-power switching. Specifically: (1) When the timing control circuit determines that the external trigger signal changes from low level to high level, the system starts the conduction process, and its timing is as follows: Figure 3 As shown, the specific steps are as follows: Capacitor pre-charging: In the initial power-on state of the system, the first switch remains closed, and the auxiliary power supply continuously charges the capacitor to the preset voltage; after the trigger signal t2-t1 interval is detected, the timing control circuit first generates a control signal, causing the Gc signal to jump, driving the first switch of the capacitor charging branch to open, disconnecting the pre-charged pulse capacitor from the auxiliary power supply 10, and keeping the pulse capacitor at the preset voltage.

[0045] The second switch is turned on: After the first switch cuts off the t3-t2 interval (t3-t2>the response time of the first switch), the timing control circuit generates a control signal, which causes the Gmos signal to jump, driving the second switch in the LC arc extinguishing branch to turn on, thus establishing a low-impedance bypass for the load current.

[0046] The third switch closes at zero voltage: After the second switch is reliably turned on and the interval t4-t3 has elapsed, and after a preset fixed delay t=t4-t3≈(2π√LC) / 4, the timing control circuit generates a control signal, causing the Gmems signal to change and driving the third main switch to close. During this process, the load current is shunted through the bypass, and the third switch closes under conditions where the voltage across its terminals is close to zero, eliminating the arcing during the connection process.

[0047] State recovery: After the third switch is reliably closed, and after an interval of t5-t4 (t5-t4 > the response time of the third switch), the timing control circuit controls the second switch to open (GMOS signal recovery), and the first switch closes to reset the pulse capacitor circuit (Gc signal recovery). The load current is completely transferred to the third main switch, completing the switch conduction process. The system enters the steady state of "switch closed" and waits for the shutdown command.

[0048] (2) When the external trigger signal changes from high level to low level, the system starts the shutdown process, and its timing is as follows: Figure 3 As shown, the specific steps are as follows: Capacitor standby: After detecting the trigger signal t8-t7 interval, the timing control circuit first generates a control signal, causing the Gc signal to jump, opening the first switch of the driving capacitor charging branch, disconnecting the pre-charged pulse capacitor from the auxiliary power supply 10, and entering the standby state.

[0049] The second switch is turned on: After the first switch cuts off the t9-t8 interval (t9-t8>the response time of the first switch), the timing control circuit generates a generation control signal, which causes the Gmos signal to jump, driving the second switch in the LC arc extinguishing branch to turn on. The LC resonant network is triggered, generating a pulse current to quickly transfer the load current from the third switch.

[0050] The third switch is turned off at zero voltage: after the second switch is reliably turned on, t 10 After the -t9 interval, a preset fixed delay t=t is passed. 10 -t9≈(2π√LC) / 4, the timing control circuit generates a control signal, causing the Gmems signal to change, driving the third main switch to turn off. The switch contacts safely separate under the established zero voltage condition, suppressing the interruption arc.

[0051] The formula for calculating fixed delay is as follows:

[0052] Where t is a fixed delay, T is the LC resonant period, L is the inductance of the inductor, and C is the capacitance of the capacitor.

[0053] Circuit reset: After the third switch is completely disconnected (i.e., t) 11 -t 10 >Third switch response time), the timing control circuit sequentially controls the second switch to open (Gmos signal recovery) and the first switch to close to reset the pulse capacitor circuit (Gc signal recovery).

[0054] In one embodiment of the present invention, the above system, after experimental verification, has achieved a breakthrough over traditional solutions in key performance aspects based on the design scheme of the aforementioned timing control architecture and LC resonant network working in concert. In a specific experimental verification, the following results were observed: like Figure 4 As shown, the system exhibits extremely fast dynamic response capability in terms of voltage suppression. Experimental data demonstrates that the arc-extinguishing circuit can achieve current transfer within approximately 1.7 microseconds and rapidly suppress the voltage across the MEMS switch contacts from approximately 724mV to approximately 12mV, achieving a voltage suppression rate of 98.3%. Subsequently, the voltage is stably maintained below 40mV for over 12.8 microseconds. This protection window completely covers and exceeds the response time of the target switch, thereby eliminating the voltage conditions necessary for arcing at its source.

[0055] In terms of timing control, its synchronization accuracy and the reliability of the protection window have been rigorously verified. Tests show that the synchronization error between the three control signals is stable in the sub-microsecond range (less than 1 microsecond, with a relative error of less than 5%). The zero-voltage protection window generated by the system remains stable under a wide range of load conditions, and its width completely covers and is slightly larger than the complete mechanical action time of the MEMS switch, providing sufficient and reliable safety margin for the switch.

[0056] In summary, experimental data confirm that this invention effectively solves the arc suppression problem of high-power MEMS switches through its core mechanism of "active timing to create zero-voltage conditions." Its overall performance, particularly its comprehensive protection capabilities during both switching processes, establishes a clear advantage over existing technologies, providing a reliable technical foundation for MEMS switches in more demanding power electronics applications.

[0057] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-power MEMS switching system based on time-sequential collaborative arc suppression, characterized in that, The system includes a load circuit, an arc suppression module, and a timing control circuit, wherein: The load circuit includes a main power supply (1), a load (2) and a third switch (3), which are connected in series to form a loop; The arc suppression module is used to prevent arcing in the third switch; the arc suppression module includes an LC arc extinguishing branch and a capacitor charging and discharging branch, wherein: The LC arc extinguishing branch is connected in parallel across the two ends of the third switch to establish and maintain an approximately zero potential range far below the breakdown voltage across the two ends of the third switch contacts. The LC arc extinguishing branch includes a rectifier circuit (4), an inductor (5), a diode (6), a second switch (7), and a capacitor (8) connected in sequence. The capacitor charging and discharging branch provides an initial preset voltage to the capacitor. The capacitor charging and discharging branch includes an auxiliary power supply (10) and a first switch (9). The first switch (9) is disposed between the capacitor (8) and the auxiliary power supply (10). The timing control circuit (11) is connected to the first switch (9), the second switch (7) and the third switch (3) at the same time. It is used to determine whether the current electrical signal jumps to a high level or a low level, and to control the opening and closing of the first switch, the second switch and the third switch according to the result of the determination.

2. The high-power MEMS switching system based on time-coordinated arc suppression as described in claim 1, characterized in that, The LC arc extinguishing branch is a single-stage or multi-stage resonant network structure.

3. A high-power MEMS switching system based on time-coordinated arc suppression as described in claim 1, characterized in that, The timing control circuit (11) judges and processes a single input signal and outputs three coordinated control signals with specific delays and logical relationships. The timing control circuit module adopts a full hardware logic architecture, including three types of components: monostable multivibrators, logic gates, and D flip-flops.

4. A high-power MEMS switching system based on time-coordinated arc suppression as described in claim 1, characterized in that, The third switch (3) is a MEMS switch.

5. A high-power MEMS switching system based on time-coordinated arc suppression as described in claim 1, characterized in that, The first switch (9) and the second switch (7) are MOSFET switches, fast switches or a combination of MOSFET and IGBT devices.

6. A method for suppressing electric arc using the system according to any one of claims 1-5, characterized in that, The method includes the following steps: The timing control circuit determines whether a transition has occurred in the current signal. When the signal transitions to a high level, the arc suppression steps are as follows: The timing control circuit generates a Gc signal transition, which drives the first switch to change from closed to open, charging the pulse capacitor to a preset voltage. After the capacitor is fully charged, the timing control circuit generates a GMOS signal transition, which drives the second switch to close from open. The current from the main power supply returns to the negative terminal of the main power supply through the LC arc extinguishing branch, establishing a low-impedance bypass for the load current. The voltage across the third switch approaches zero. After a preset fixed delay, the timing control circuit generates a Gmems signal transition, driving the third main switch to close. The current from the main power supply returns to the negative terminal through the load and the third switch. At this time, the load current has been shunted through the bypass. The third switch closes when the voltage at both ends is close to zero, eliminating the arc during the connection process. When the signal transitions to a low level, the arc suppression steps are as follows: The timing control circuit first generates a Gc signal transition, driving the first switch to change from closed to open; Next, the timing control circuit generates a GMOS signal transition, driving the second switch to close from open. The current from the main power supply returns to the negative terminal of the main power supply through the LC arc extinguishing branch. The LC resonant network is triggered, generating a current pulse that transfers the load current from the third switch. The voltage across the third switch approaches zero. After a preset fixed delay, the timing control circuit generates a Gmems signal transition, driving the third switch to open. The switch contacts safely separate under the established zero voltage condition, suppressing the interruption arc.

7. The arc suppression method as described in claim 6, characterized in that, During the Gmems signal transition generated by the timing control circuit after a preset fixed delay, the fixed delay is calculated based on the characteristics of the capacitor and inductor.

8. The arc suppression method as described in claim 6 or 7, characterized in that, The formula for calculating the fixed delay is as follows: Where t is a fixed delay, L is the inductance value, and C is the capacitance value.

9. The arc suppression method as described in claim 8, characterized in that, The preset voltage of the capacitor satisfies the following conditions: Where V is the preset voltage of the capacitor, and I load L is the load current, C is the inductance value, and C is the capacitance value.

10. An arc suppression system, characterized in that, The system includes an actuator for performing the arc suppression method as described in claims 6-9.

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