Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element which comprises a substrate, a semiconductor channel layer, a semiconductor barrier layer, a source electrode, a gate electrode and a drain stack layer. The drain stack layer comprises a first drain layer which comprises a first body part and a first extension part, and the bottom surface of the first extension part is higher than the top surface of the first body part. The second drain electrode layer is arranged on the first drain electrode layer and comprises a second body part and a second extension part, in the first direction, the length of the second drain electrode layer is larger than that of the first drain electrode layer, and the top surface of the second extension part is higher than that of the second body part. And the third drain electrode layer is arranged on the second drain electrode layer and comprises a third body part and a third extension part. The invention further discloses a manufacturing method of the semiconductor element.

Description

Technical Field

[0001] This invention relates to a semiconductor element, and more particularly to a semiconductor element for withstanding high voltage and a method for manufacturing the same. Background Technology

[0002] In semiconductor technology, III-V group semiconductor compounds can be used in various integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are transistors with a two-dimensional electron gas (2DEG), which is located near the junction between two materials with different band gaps (i.e., a heterojunction). Because HEMTs do not use doped regions as carrier channels but rather use 2DEGs, they possess several attractive characteristics compared to existing metal-oxide-semiconductor (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies. Existing HEMTs can include a compound semiconductor channel layer, a compound semiconductor barrier layer, a compound semiconductor capping layer, and a gate electrode stacked sequentially. By applying a bias voltage to the compound semiconductor capping layer using the gate electrode, the concentration of the two-dimensional electron gas in the compound semiconductor channel layer beneath the capping layer can be controlled, thereby controlling the switching of the HEMT. In addition, existing HEMTs also include field plates to regulate the electric field distribution, thereby improving the HEMT's breakdown voltage.

[0003] However, when a field plate is set in a HEMT, the field plate usually has a undulating topography, which often causes structural defects in the interlayer dielectric layer adjacent to the field plate, thus reducing the withstand voltage capability of the HEMT. Summary of the Invention

[0004] In view of this, it is necessary to propose an improved semiconductor device and its manufacturing method to improve the shortcomings of existing semiconductor devices.

[0005] According to an embodiment of the present invention, a semiconductor device is provided, including a substrate; a semiconductor channel layer and a semiconductor barrier layer disposed on the substrate; a gate electrode disposed on the semiconductor barrier layer; a first interlayer dielectric layer disposed on the semiconductor barrier layer and the gate electrode; a source electrode disposed on one side of the gate electrode; and a drain stack layer disposed on the other side of the gate electrode and laterally separated from the gate electrode. The drain stack layer includes: a first drain layer including a first body portion and a first extension portion, the first extension portion covering the first interlayer dielectric layer, and the bottom surface of the first extension portion being higher than the top surface of the first body portion; a second drain layer disposed on the first drain layer and including a second body portion and a second extension portion, the second extension portion covering the second interlayer dielectric layer, wherein, in a first direction, the length of the second drain layer is greater than the length of the first drain layer, and the top surface of the second extension portion is higher than the top surface of the second body portion; and a third drain layer disposed on the second drain layer and including a third body portion and a third extension portion.

[0006] According to other embodiments of the present invention, a method for manufacturing a semiconductor device is proposed, comprising the following steps: providing a substrate, the substrate comprising, from bottom to top, a substrate, a semiconductor channel layer and a semiconductor barrier layer; forming a gate electrode on the semiconductor barrier layer; forming a first interlayer dielectric layer covering the gate electrode; forming a source electrode on one side of the gate electrode; forming a first drain layer on the other side of the gate electrode, wherein the first drain layer includes a first body portion and a first extension portion, and the first extension portion covers a portion of the first interlayer dielectric layer; and forming a second drain layer on the first drain layer, wherein the second drain layer includes a second body portion and a second extension portion, and the second extension portion covers the second interlayer dielectric layer, wherein, in a first direction, the length of the second drain layer is greater than the length of the first drain layer, and the top surface of the second extension portion is higher than the top surface of the second body portion.

[0007] According to the above embodiments, the drain stack layer includes a first drain layer, a second drain layer, and a third drain layer, and the second extension of the second drain layer covers and extends over the extension of the first drain layer. By staggering the ends of the extensions of these drain layers, the electric field peak near the tip of the drain stack layer can be effectively reduced to improve the withstand voltage capability of the semiconductor device during chip testing. It can also make each drain layer have a flatter surface morphology, which can effectively reduce structural defects such as voids in the adjacent interlayer metal dielectric layer, and further improve the semiconductor device's ability to withstand high voltage. Attached Figure Description

[0008] To facilitate understanding of the following text, please refer to the accompanying drawings and detailed textual descriptions while reading this invention. Specific embodiments described herein, along with corresponding drawings, are used to explain the detailed implementation of the invention and to elucidate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 2 This is an enlarged cross-sectional schematic diagram of a partial region of a semiconductor device according to an embodiment of the present invention. Figure 3 This is an enlarged cross-sectional schematic diagram of a partial region of a semiconductor device according to an embodiment of the present invention. Figure 4 This is an enlarged cross-sectional schematic diagram of a partial region of a semiconductor device according to an embodiment of the present invention. Figure 5 This is an enlarged cross-sectional schematic diagram of a partial region of a semiconductor device according to an embodiment of the present invention. Figures 6 to 10 These are cross-sectional schematic diagrams illustrating various stages of the manufacturing of semiconductor devices, based on some embodiments.

[0009] Explanation of icon numbers: 10… Semiconductor Devices 101…base 102… Buffer layer 103… Semiconductor Channel Layer 104… Semiconductor barrier layer 105… Semiconductor capping layer 106…passivation layer 110… Semiconductor layer 112a…Two-dimensional electron gas region 112b…Two-dimensional electron gas cutoff region 120… Gate opening 130…Source Opening 140…drain opening 150… Bottom Dielectric Layer 151…First interlayer dielectric layer 152…Second interlayer dielectric layer 152P lifting zone 153…Third interlayer dielectric layer 154… Fourth interlayer dielectric layer 154B…bottom surface 154T…top surface 160… Interlayer metal dielectric layer 200…gate electrode 300…Source Electrode 310…First Source Layer 320…Second source layer 330…Third source layer 400…Drain Stack Layer 410…First Drain Layer 411…First Ontology Department 411T, 421T… Top surface 412…First Extension 412B, 422B…bottom 412E, 422E, 432E… End edge 420…Second Drain Layer 421…Second Body Section 422…Second Extension 422P, 432P... Lifting Zone 430…Third drain layer 431…Third Body Section 432…Third Extension F2…length L1, L2, L3… length R1…area Distances T1, T2, T3… Detailed Implementation

[0010] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact," or it may mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0011] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "under," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientations shown in the diagram, these spatially related terms are also used to describe the possible orientations of the semiconductor element during use and operation. As the orientation of the semiconductor element varies (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0012] Although this invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0013] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0014] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other elements or connection means.

[0015] In this invention, "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element. The group III element can be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element can be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Further, "group III-V semiconductor" can include: aluminum nitride (AlN), gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), gallium indium nitride (GaInN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (AlInAs), gallium indium arsenide (GaInAs), analogues thereof, or combinations of the above compounds, but is not limited thereto. In addition, depending on the requirements, III-V semiconductors may also include dopants to become III-V semiconductors with a specific conductivity type, such as N-type or P-type III-V semiconductors.

[0016] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.

[0017] This invention relates to a semiconductor device that exhibits good high-voltage performance and is suitable for use in the design of high electron mobility transistors (HEMTs).

[0018] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, as shown below. Figure 1 As shown, according to an embodiment of the present invention, a semiconductor device 10, such as a high electron mobility transistor, includes a substrate 101, and an optional buffer layer 102, a semiconductor channel layer 103, a semiconductor barrier layer 104, and a semiconductor capping layer 105 are sequentially disposed on the substrate 101. For ease of description, the substrate 101, buffer layer 102, semiconductor channel layer 103, and semiconductor barrier layer 104 can also be collectively referred to as semiconductor layer 110, and depending on different requirements, semiconductor layer 110 may also include non-semiconductor layers, such as metal layers or insulating layers. A gate electrode 200 can be disposed on the semiconductor barrier layer 104, a source electrode 300 can be disposed on one side of the gate electrode 200, and a drain stack layer 400 is disposed on the other side of the gate electrode 200, such that the source electrode 300 and the drain stack layer 400 are located on different sides of the gate electrode 200. The drain stack layer 400 may include a first drain layer 410, a second drain layer 420, and a third drain layer 430 stacked sequentially from bottom to top.

[0019] According to one embodiment of the present invention, substrate 101 may comprise a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, an aluminum nitride substrate, a sapphire substrate, a combination thereof, or similar materials, but the embodiments of the present invention are not limited thereto. According to one embodiment of the present invention, substrate 101 may also comprise a semiconductor-on-insulator (SOI) substrate, which is formed by depositing a semiconductor material on an insulating layer. According to one embodiment of the present invention, substrate 101 may be a composite substrate comprising a core substrate and a cladding layer, such as a QST (Qromis Substrate Technology) substrate, and the back side of the core substrate may be exposed from the cladding layer. The core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire, or silicon. The cladding layer may be a composite material layer comprising an insulating material layer and a semiconductor material layer, wherein the insulating material layer may be a single layer or multiple layers of silicon oxide, silicon nitride, or silicon oxynitride, and the semiconductor material layer may be silicon or polycrystalline silicon. Since the thermal conductivity of QST substrate is more than 100 times that of silicon substrate, QST substrate can provide excellent heat dissipation capabilities.

[0020] According to one embodiment of the present invention, the buffer layer 102 can be used to reduce the degree of stress or lattice mismatch existing between the substrate 101 and the semiconductor channel layer 103. According to one embodiment of the present invention, the buffer layer 102 may include a plurality of sub-semiconductors, and its overall resistance value is higher than that of other layers on the substrate 101. Specifically, the proportion of certain elements in the buffer layer 102, such as metal elements, gradually changes from the substrate 101 towards the semiconductor channel layer 103.

[0021] According to one embodiment of the present invention, the material of the semiconductor channel layer 103 may comprise one or more group III-V semiconductor materials, such as group III nitrides. According to one embodiment of the present invention, the material of the semiconductor channel layer 103 may be, for example, AlN (aluminum nitride), AlGaN (aluminum gallium nitride), AlInN (indium aluminum nitride), InGaAlN (indium gallium aluminum nitride), similar materials, or combinations thereof, but the embodiments of the present invention are not limited thereto. Furthermore, the semiconductor channel layer 103 may be doped or undoped.

[0022] According to one embodiment of the present invention, the material of the semiconductor barrier layer 104 may comprise a group III-V semiconductor material, such as a group III nitride. For example, the semiconductor barrier layer 104 may comprise AlN, AlGaN, AlInN, InGaAlN, similar materials, or combinations thereof, but the embodiments of the present invention are not limited thereto. The semiconductor barrier layer 104 may comprise a single-layer or multi-layer structure, and the semiconductor barrier layer 104 may be doped or undoped.

[0023] According to one embodiment of the present invention, the semiconductor element 10 may further include a semiconductor capping layer 105 disposed on the semiconductor barrier layer 104. See also Figure 1 Because of the discontinuous bandgap between the semiconductor channel layer 103 and the semiconductor barrier layer 104, by stacking the semiconductor channel layer 103 and the semiconductor barrier layer 104 together, electrons are concentrated at the heterojunction between the semiconductor channel layer 103 and the semiconductor barrier layer 104 due to the piezoelectric effect, thus generating a thin layer with high electron mobility, namely a two-dimensional electron gas (2DEG) region 112a. In contrast, the region covered by the semiconductor capping layer 105 does not form a two-dimensional electron gas and can therefore be considered as a two-dimensional electron gas cutoff region 112b. The semiconductor capping layer 105 can be one or more doped III-V semiconductor layers, such as a p-type III-V semiconductor layer. For the p-type III-V semiconductor layer, the dopant can be C, Fe, Mg, or Zn; and according to an embodiment of the present invention, the semiconductor capping layer 105 can be a p-type GaN layer.

[0024] According to one embodiment of the present invention, the gate electrode 200 may be a single-layer or multi-layer structure, which may be disposed on the semiconductor capping layer 105 and electrically connected to the underlying semiconductor capping layer 105, such as a Schottky contact. The composition of the gate electrode 200 may be, for example, TiN, W, Pt, Ni, Ti, Al, Au, Mo, their stacked layers, or alloys thereof, but is not limited thereto.

[0025] According to one embodiment of the present invention, the source electrode 300 may include at least one source layer, such as multiple source layers stacked along the Z direction, such as a first source layer 310, a second source layer 320, and a third source layer 330. The composition of each of the first source layer 310, the second source layer 320, and the third source layer 330 may include a conductive metal, such as W, Pt, Ni, Ti, Al, Au, Mo, or an alloy of the above metals, and each layer may include a stacked layer of the above metals or alloys, but the embodiments of the present invention are not limited thereto. Figure 1 As shown, the first source layer 310, the second source layer 320, and the third source layer 330 in the source electrode 300 extend toward the drain stack layer 400 in the same direction (e.g., the X direction). According to one embodiment of the present invention, at least one source layer in the source electrode 300 may cover and extend over the gate electrode 200 to prevent electric field concentration at the bottom tip of the gate electrode 200.

[0026] According to one embodiment of the present invention, the composition of the first drain layer 410, the second drain layer 420 and the third drain layer 430 may each include a conductive metal, such as W, Pt, Ni, Ti, Al, Au, Mo, their stacked layers or alloys thereof, but the embodiments of the present invention are not limited thereto.

[0027] According to one embodiment of the present invention, an optional passivation layer 106 may be provided on the semiconductor layer 110, covering the semiconductor barrier layer 104. The passivation layer 106 can be used to eliminate or reduce surface defects present on the top surface of the semiconductor barrier layer 104 and the side surface of the semiconductor capping layer 105, thereby improving the electrical performance of the semiconductor device 10. According to one embodiment of the present invention, the passivation layer 106 may contain any suitable dielectric material, such as Si3N4 (silicon nitride), SiON (silicon oxynitride), AlN (aluminum nitride), Al2O3 (aluminum oxide), SiO2 (silicon oxide), similar materials, or combinations thereof, but the embodiments of the present invention are not limited thereto.

[0028] Figure 2 As illustrated in an embodiment of the present invention Figure 1 A magnified view of the local region R1. (See image below.) Figure 2 As shown, according to an embodiment of the present invention, multiple dielectric layers can be disposed on the semiconductor barrier layer 104. For example, the bottom dielectric layer 150, the first interlayer dielectric layer 151, the second interlayer dielectric layer 152, the third interlayer dielectric layer 153, and the fourth interlayer dielectric layer 154 can be stacked sequentially on the semiconductor barrier layer 104 from bottom to top. The material of each dielectric layer can be selected from Si3N4, AlN, Al2O3, SiO2, SiON, or combinations thereof, but the embodiments of the present invention are not limited thereto.

[0029] The drain opening 140 may be disposed at least in the bottom dielectric layer 150, for example, in the bottom dielectric layer 150 and the first interlayer dielectric layer 151, and may be used to accommodate a portion of the drain stack layer 400, such that the drain stack layer 400 penetrates the drain opening 140 and is electrically connected to the underlying semiconductor channel layer 103.

[0030] The first drain layer 410, the second drain layer 420, and the third drain layer 430 of the drain stack layer 400 each have a body portion and an extension portion. Specifically, the first drain layer 410 includes a first body portion 411 and a first extension portion 412. The top surface 411T of the first body portion 411 is located in the drain opening 140, while the first extension portion 412 forwardly covers the sidewall of the drain opening 140 and a portion of the first interlayer dielectric layer 151, such that the bottom surface 412B of the first extension portion 412 can be higher than the top surface 411T of the first body portion 411. The second drain layer 420 is disposed on the first drain layer 410 and includes a second body portion 421 and a second extension portion 422. The bottom surface of the second body portion 422 is located in the drain opening 140. The third drain layer 430 is disposed on the second drain layer 420 and includes a third body portion 431 and a third extension portion 432.

[0031] See also Figure 2 According to one embodiment of the present invention, a first interlayer dielectric layer 151 is located between a first extension 412 and a bottom dielectric layer 150, a second interlayer dielectric layer 152 is located between a second extension 422 and a first extension 412, and a third interlayer dielectric layer 153 is located between a third extension 432 and a second extension 422. According to one embodiment of the present invention, while referring to… Figure 1 and Figure 2 The first interlayer dielectric layer 151 covers the gate electrode 200 and the bottom dielectric layer 150, and isolates the gate electrode 200 and the source electrode 300. The second interlayer dielectric layer 152 extends into the drain opening 140 and is located above the first body portion 411, covering the top surface 411T of the first body portion 411, so that the first extension portion 412 and the second extension portion 422 are longitudinally separated from each other. Similarly, the third interlayer dielectric layer 153 extends above the second body portion 421 and directly contacts the top surface 421T of the second body portion 421. According to an embodiment of the present invention, the materials of the first interlayer dielectric layer 151, the second interlayer dielectric layer 152, and the third interlayer dielectric layer 153 may be selected from Si3N4, AlN, Al2O3, SiO2, SON, or combinations thereof, but the embodiments of the present invention are not limited thereto. According to one embodiment of the present invention, the dielectric layer described above can be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, spin coating, similar deposition processes, or combinations thereof, but the embodiments of the present invention are not limited thereto.

[0032] According to one embodiment of the present invention, the second interlayer dielectric layer 152 may cover the first extension 412, such that the surface of the second interlayer dielectric layer 152 may include at least one protruding profile (or raised region 152P), and the raised region 152P is located directly above the first extension 412. The second extension 422 covers and extends beyond the second interlayer dielectric layer 152, such that the length L2 of the second drain layer 420 in the X direction may be greater than the length L1 of the first drain layer 410 in the X direction, and the second extension 422 extends beyond the end edge 412E of the first extension 412. According to one embodiment of the present invention, the second extension 422 may have a protruding profile (or raised region 422P), and the raised region 422P is located directly above the first extension 412. The raised region 422P includes an arc-shaped top surface, such that the apex of the raised region 422P of the second extension 422 is higher than the top surface 421T of the second body portion, or further, the apex of the raised region 152P of the second interlayer dielectric layer 152 is higher than the bottom surface 422B of the second extension 422. According to an embodiment of the present invention, the bottom surface 422B of the second extension 422 may also be equal to or lower than the top surface 421T of the second body portion.

[0033] According to one embodiment of the present invention, both the second extension 422 and the first extension 412 can serve as field plates for the semiconductor element 10. (See also...) Figure 1 and Figure 2 Regarding the second extension 422, considering its influence on the extension of the source electrode 300 and the electric field in the drift region when it acts as a field plate, its length F2 in the X direction must have an appropriate length, for example, it can be the distance L0 between the drain stack layer 400 and the gate electrode 200 (refer to...). Figure 1 5%-30%. Distance L0 can also be considered as the length of the drift region of semiconductor element 10.

[0034] By extending the second extension 422 beyond the end edge 412E of the first extension 412, the electric field peak near the top of the raised region 422P of the second drain layer 420 can be effectively reduced to improve the withstand voltage capability of the semiconductor device 10 during chip testing. In addition, the second drain layer 420 can have a flatter surface morphology, which can effectively reduce structural defects such as voids in the interlayer dielectric layer stacked on it, and further improve the ability of the semiconductor device 10 to withstand high voltage.

[0035] See also Figure 2 According to one embodiment of the present invention, the third extension 432 of the third drain layer 430 may cover a portion of the second extension 422 of the second drain layer 420. Therefore, the length L3 of the third drain layer in the X direction will be less than the length L2 of the second drain layer in the X direction, and the third extension 432 may be laterally separated from the first interlayer dielectric layer 151.

[0036] Furthermore, according to an embodiment of the present invention, the semiconductor element 10 may further include a fourth interlayer dielectric layer 154 covering and directly contacting the third drain layer 430 and the third interlayer dielectric layer 153, wherein above the drain stack layer 400, there is a vertical distance T1 between the highest point 154T of the top surface and the lowest point 154B of the bottom surface of the fourth interlayer dielectric layer 154, and the magnitude of the distance T1 can be used as a basis for judging the flatness of the fourth interlayer dielectric layer 154.

[0037] By retracting the end edge 432E of the third extension 432 from the end edge 422E of the second extension 422, the electric field peak near the top of the third drain layer 430 can be effectively reduced to improve the withstand voltage capability of the semiconductor device 10 during chip testing. In addition, the third drain layer 430 can have a flatter surface morphology, which can effectively reduce structural defects such as voids in the interlayer dielectric layer stacked on it, and further improve the ability of the semiconductor device 10 to withstand high voltage.

[0038] Figure 3 As illustrated in another embodiment of the present invention Figure 1 A magnified view of a local region R1. According to an embodiment of the present invention, with... Figure 2 Similar to the embodiments, the difference between the two embodiments is that the third extension 432 of the third drain layer 430 can cover and extend over the second extension 412 of the second drain layer 420, such that the length L3 of the third drain layer 430 in the X direction is greater than the length L2 of the second drain layer 420 in the X direction, and the end edge 432E of the third extension 432 extends over the end edge 422E of the second extension 422. According to one embodiment of the present invention, the third extension 432 covering the third interlayer dielectric layer 153 can form at least one protruding profile (or raised region 432P) above the second extension 422, and the raised region 432P forms a top surface including at least one arcuate shape. Since the top surface of the raised region 422P of the second extension 422 is located directly above the first extension 412, the top surface of the raised region 432P of the third extension 432 can also be located directly above the first extension 412. Additionally, above the drain stack layer 400, there is a vertical distance T2 between the highest point 154T on the top surface and the lowest point 154B on the bottom surface of the fourth interlayer dielectric layer 154.

[0039] By extending the third extension 432 beyond the end edge 422E of the second extension 422, the electric field peak near the top of the raised region 432P of the third drain layer 430 can be effectively reduced to improve the withstand voltage capability of the semiconductor device 10 during chip testing. In addition, the third drain layer 430 can have a flatter surface morphology, which can effectively reduce structural defects such as voids in the interlayer dielectric layer stacked on it, and further improve the ability of the semiconductor device 10 to withstand high voltage.

[0040] See Figure 4 It is illustrated according to another embodiment of the present invention. Figure 1 A magnified view of the local region R1. Figure 4 The illustrated embodiments and Figure 2 The embodiments are similar, the difference being that the length L2 of the second drain layer 420 in the X direction is similar to the length L1 of the first drain layer 410 in the X direction. Therefore, its second extension 422 only partially covers the first extension 412, and the end edge 422E of the second extension 422 is located above the first extension 412 without extending beyond it. Similarly, the length of the third drain layer 430 in the X direction is similar to that of the second drain layer 420, so that the end edge 432E of the third extension 432 is also located above the first extension 412 without extending beyond it. That is, the end edges 412E, 422E, and 432E of each drain layer are not staggered. This configuration causes the fourth interlayer dielectric layer 154 to form a steeply sloping surface when deposited at the end of the third extension 432, with the vertical distance T3 between the highest point 154T on its top surface and the bottom surface 154B corresponding to the sum of the lengths of the end edges 422E of the second extension 422 and the third extension 432 in the Z direction. In this invention... Figure 2 or Figure 3 In the embodiments described, because the ends of each drain layer are staggered, the fourth interlayer dielectric layer 154 has a relatively flat surface morphology; however, Figure 4 In the illustrated embodiment, the end edges of each drain layer are not staggered, making the distance T3 significantly greater than the distances T1 and T2. Therefore, compared to the aforementioned... Figure 2 or Figure 3 The embodiment shown, Figure 4 In addition to being less effective at reducing the electric field peak near the top of the third drain layer 430, the embodiment shown also has a long steep-dip surface morphology at the end edge 432E of the third drain layer 430, which can easily cause structural defects, such as voids, in the dielectric layer stacked on the third drain layer 430, which is not conducive to the high voltage withstand performance of the semiconductor device 10 during chip testing.

[0041] See Figure 5 It is illustrated according to an embodiment of the present invention. Figure 1 A magnified view of the local region R1. (See image below.) Figure 5 As shown, the interlayer metal dielectric layer 160 on the drain stack layer 400 has gaps S located at the ends of the third extension 432 and the third body 431, and extends upward in a generally oblique direction (e.g., the XZ direction). Each gap S may be discontinuous or continuous in the interlayer metal dielectric layer 160. This is in contrast to the case where the end edges 422E of the second drain layer 420 and the third drain layer 430 are not staggered ( Figure 4 As shown), by offsetting the end edges 422E of the second drain layer 420 and the third drain layer 430, even the fourth interlayer dielectric layer 154 located at the end edge 432E of the third drain layer 430 still has a steeply sloping surface morphology (e.g., as shown). Figure 2 , Figure 3 , Figure 5 (As shown), but its steep drop distance is relatively short, so even if a gap S exists, the maximum size (e.g., length) of the gap S will not be too large, for example, it can be less than 5 nanometers, or there may not even be any gap. Therefore, the withstand voltage capability of the semiconductor device 10 during chip testing can be improved.

[0042] To enable those skilled in the art to implement the invention, the method for manufacturing the semiconductor element of the present invention is further described in detail below.

[0043] Figures 6 to 10 These are schematic cross-sectional views illustrating various stages of semiconductor device manufacturing, based on some embodiments. See also... Figure 6 According to an embodiment of the present invention, a buffer layer 102, a semiconductor channel layer 103, a semiconductor barrier layer 104 (the substrate 101, buffer layer 102, semiconductor channel layer 103, and semiconductor barrier layer 104 can be collectively referred to as semiconductor layer 110), a passivation layer 106, and a bottom dielectric layer 150 may be sequentially disposed on a substrate 101 in the semiconductor device 10. A semiconductor capping layer 105 may be disposed above the semiconductor barrier layer 104 to deplete the two-dimensional electron gas below the gate electrode 200, thereby achieving a normally-off state of the semiconductor device. A gate opening 120 may be provided in the bottom dielectric layer 150 to expose the underlying semiconductor capping layer 105. The stacked layers on the substrate 101 can be formed by any suitable means, such as molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable means.

[0044] Next, see still Figure 6 A gate metal layer (not shown) can be formed on the top surface of the bottom dielectric layer 150 and within the gate opening 120 via a suitable deposition process. For example, it can be a composite conductive layer including a Schottky contact metal. The thickness of the gate metal layer can be from 500 angstroms to 2000 angstroms, but is not limited thereto. Next, a patterning process is performed on the gate metal layer to form the gate electrode 200.

[0045] See next Figure 7 According to one embodiment of the present invention, after completing Figure 6 After the process, a first interlayer dielectric layer 151 can be formed in the oriented direction on the semiconductor layer 110 and the gate electrode 200, and then a source opening 130 and a drain opening 140 are etched on the first interlayer dielectric layer 151. The first interlayer dielectric layer 151 can be formed by a suitable deposition process, such as chemical vapor deposition, spin coating, similar deposition processes or combinations thereof, but the embodiments of the present invention are not limited thereto.

[0046] See next Figure 8 According to one embodiment of the present invention, after completing Figure 7 After the process, a first conductive material layer (not shown) can be formed on the semiconductor layer 110, and then a patterning process is performed on the first conductive material layer to simultaneously form a first source layer 310 and a first drain layer 410 that are separated from each other, so as to avoid a short circuit caused by the first source layer 310 being electrically connected to the first drain layer 410. The first conductive material layer can be formed by a deposition process, and its composition can include conductive metals, such as W, Pt, Ni, Ti, Al, Au, Mo, their stacked layers, or alloys thereof, but the embodiments of the present invention are not limited thereto. The first source layer 310 is formed in the source opening 130, and the first drain layer 410 is formed in the drain opening 140. The first source layer 310 can extend outward from the source opening 130 and extend from one side of the gate electrode 200 to the other side of the gate electrode 200.

[0047] See still Figure 8 According to one embodiment of the present invention, a second interlayer dielectric layer 152 may be formed on the first source layer 310 and the first drain layer 410. The second interlayer dielectric layer 152 may be formed by a deposition process, and the material and formation method of the second interlayer dielectric layer 152 may be the same as those of the first dielectric layer 151. According to one embodiment of the present invention, the second interlayer dielectric layer 152 may then be patterned to re-form the source opening 130 and the drain opening 140, which respectively expose the first source layer 310 and the first drain layer 410.

[0048] See next Figure 9According to one embodiment of the present invention, a second conductive material layer (not shown) may be formed on the second interlayer dielectric layer 152, and then the second conductive material layer may be patterned to simultaneously form a second source layer 320 and a second drain layer 420 that are separated from each other. The second conductive material layer may be formed by a deposition process, and the material and formation method of the second conductive material layer may be the same as those of the aforementioned first conductive material layer. According to one embodiment of the present invention, the second source layer 320 and the second drain layer 420 are electrically connected to the first source layer 310 and the first drain layer 410 via source opening 130 and drain opening 140, respectively.

[0049] See still Figure 9 According to one embodiment of the present invention, a third interlayer dielectric layer 153 may be formed on the second source layer 320, the second interlayer dielectric layer 152, and the second drain layer 420. The third interlayer dielectric layer 153 may be formed by a deposition process, and the material and formation method of the third interlayer dielectric layer 153 may be the same as those of the aforementioned first interlayer dielectric layer 151. According to one embodiment of the present invention, the third interlayer dielectric layer 153 may then be patterned to re-form the source opening 130 and the drain opening 140, which respectively expose the second source layer 320 and the second drain layer 420.

[0050] See next Figure 10 According to one embodiment of the present invention, a third conductive material layer (not shown) may be formed on the third interlayer dielectric layer 153, and then the third conductive material layer 153 may be patterned to simultaneously form a third source layer 330 and a third drain layer 430 that are separated from each other. The third conductive material layer may be formed by a deposition process, and the material and formation method of the third conductive material layer may be the same as those of the aforementioned first conductive material layer. The third source layer 330 and the third drain layer 430 are electrically connected to the second source layer 320 and the second drain layer 410 via source opening 130 and drain opening 140, respectively.

[0051] See still Figure 10 According to one embodiment of the present invention, a fourth interlayer dielectric layer 154 can be formed on the third source layer 330 and the third drain layer 430. The fourth interlayer dielectric layer 154 can be formed by a deposition process, and the material and formation method of the fourth interlayer dielectric layer 154 can be the same as those of the aforementioned first interlayer dielectric layer 151. According to one embodiment of the present invention, the fourth interlayer dielectric layer 154 can be formed oriented on the third source layer 330 and the third drain layer 430. Subsequently, an interlayer metal dielectric layer 160 can be formed on the fourth interlayer dielectric layer 154 to obtain a similar... Figure 1The structure shown in the embodiment. Because the end edges of the third drain layer 430 and the second drain layer 420 are staggered, when the deposition process is performed to form the fourth interlayer dielectric layer 154 and the interlayer metal dielectric layer 160, the third interlayer dielectric layer 154 and the interlayer metal dielectric layer 160 can completely cover the region of the end edge of the third drain layer 430 without creating any voids in the third interlayer dielectric layer 154 and the interlayer metal dielectric layer 160, or even if there are voids, their maximum size can still be less than 5 nanometers. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A semiconductor element, characterized in that, include: One base; A semiconductor channel layer and a semiconductor barrier layer are disposed on the substrate; A gate electrode is disposed on the semiconductor barrier layer; A first interlayer dielectric layer is disposed on the semiconductor barrier layer and the gate electrode; A source electrode is disposed on one side of the gate electrode; as well as A drain stack layer is disposed on the other side of the gate electrode and laterally separated from the gate electrode. The drain stack layer includes: A first drain layer includes a first body portion and a first extension portion, the first extension portion covering the first interlayer dielectric layer, and the bottom surface of the first extension portion being higher than the top surface of the first body portion. A second drain layer is disposed on the first drain layer and includes a second body portion and a second extension portion, the second extension portion covering the first extension portion, wherein, in a first direction, the length of the second drain layer is greater than the length of the first drain layer, and the top surface of the second extension portion is higher than the top surface of the second body portion; and A third drain layer is disposed on the second drain layer and includes a third body portion and a third extension portion.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes a drain opening disposed in the first interlayer dielectric layer, and the first body portion is located within the drain opening.

3. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the second extension includes a circular arc top surface.

4. The semiconductor device as described in claim 3, characterized in that, The arc-shaped top surface is located directly above the first extension.

5. The semiconductor device as claimed in claim 1, characterized in that, The second extension extends beyond one end edge of the first extension.

6. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second interlayer dielectric layer is disposed between the first extension and the second extension, and covers the top surface of the first body portion.

7. The semiconductor device as claimed in claim 6, characterized in that, A portion of the second interlayer dielectric layer is located within the drain opening.

8. The semiconductor device as claimed in claim 6, characterized in that, The second interlayer dielectric layer includes a raised region, and the apex of the raised region is higher than the bottom surface of the second extension.

9. The semiconductor device as claimed in claim 1, characterized in that, In the first direction, the length of the third drain layer is less than the length of the first drain layer, and the third extension is laterally separated from the first interlayer dielectric layer.

10. The semiconductor device as claimed in claim 1, characterized in that, In the first direction, the length of the third drain layer is greater than the length of the second drain layer, and the third extension covers and extends over the second extension.

11. The semiconductor device as claimed in claim 10, characterized in that, The third extension includes an arcuate top surface, which is located directly above the first extension.

12. The semiconductor device as claimed in claim 1, characterized in that, In the first direction, the length of the second extension is 5%-30% of the distance between the drain structure and the gate electrode.

13. The semiconductor device as claimed in claim 1, characterized in that, It further includes an interlayer metal dielectric layer disposed on the third drain layer, wherein the interlayer metal dielectric layer contains at least one void, and in a cross-sectional view, the maximum length of the at least one void is less than 5 nm.

14. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, which comprises, from bottom to top, a substrate, a semiconductor channel layer and a semiconductor barrier layer; A gate electrode is formed on the bottom dielectric layer; A first interlayer dielectric layer is formed to cover the gate electrode; A source electrode is formed on one side of the gate electrode; A first drain layer is formed on the other side of the gate electrode, wherein the first drain layer includes a first body portion and a first extension portion, and the first extension portion covers a portion of the first interlayer dielectric layer; and A second drain layer is formed on the first drain layer, wherein the second drain layer includes a second body portion and a second extension portion, and the second extension portion covers the second interlayer dielectric layer, wherein, in a first direction, the length of the second drain layer is greater than the length of the first drain layer, and the top surface of the second extension portion is higher than the top surface of the second body portion.

15. The method for manufacturing a semiconductor device as described in claim 14, characterized in that, After the formation of the second drain layer, the following is further included: A third interlayer dielectric layer is formed, covering the second extension and the second interlayer dielectric layer; and A third drain layer is formed on the second drain layer, wherein the third drain layer includes a third body portion and a third extension portion.

16. The method for manufacturing a semiconductor device as described in claim 14, characterized in that, Before forming the gate electrode, the process further includes: A bottom dielectric layer is formed on the semiconductor barrier layer, wherein the bottom dielectric layer includes a gate opening and the gate electrode is located within the gate opening.

17. The method for manufacturing a semiconductor device as described in claim 14, characterized in that, In the first direction, the length of the third drain layer is less than or equal to the length of the second drain layer, and the third extension covers a portion of the second extension.

18. The method for manufacturing a semiconductor device as described in claim 14, characterized in that, In the first direction, the length of the third drain layer is greater than the length of the second drain layer, and the third extension covers and extends beyond one end edge of the second extension.

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