Semiconductor layout pattern and manufacturing method thereof

Abstract

A semiconductor layout pattern and a method of fabricating the same are disclosed, where the semiconductor layout pattern includes a substrate having two content addressable memory (CAM) cells arranged on both sides of an axis of symmetry, and a first matching line (ML) conductive layer and a second matching line conductive layer on the substrate, where when viewed from a top view, the first matching line conductive layer and the second matching line conductive layer are electrically connected to each other, and the first matching line conductive layer and the second matching line conductive layer are electrically connected to each other. The first matching line conductive layer and the second matching line conductive layer are overlapped with a symmetry axis between the two content addressable memory units and are arranged along the direction of the symmetry axis.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a layout pattern of a Content Addressable Memory (CAM) and a method for manufacturing the same. Background Technology

[0002] Generally, when performing digital data operations, the amount of data to be processed is enormous, and the stored data in some applications (such as network routers) needs to be updated dynamically in large quantities and cannot be pre-sorted, making real-time data query processing difficult. To effectively speed up data retrieval for this large amount of randomly stored data, Content Addressable Memory (CAM) is used to solve various search problems. Content Addressable Memory (also known as associative memory) acts like a giant lookuptable, finding the address of a matching keyword based on the input keyword. This is achieved through a special hardware architecture design of the CAM, allowing the searched keyword to be compared simultaneously with the data stored in the CAM, and outputting the address of the data matching the input keyword. The data associated with the keyword can then be found using the address found by the CAM.

[0003] Content-addressable memory (CAM) can include binary CAM (BCAM) and tertiary CAM (TCAM). In BCAM, each bit has two states, 0 or 1, while in TCAM, each bit has three states: 0, 1, and a "don't care" state. This third state characteristic of TCAM enables it to perform both exact match searches and fuzzy match searches. Summary of the Invention

[0004] The present invention provides a semiconductor layout pattern comprising a substrate on which two Content Addressable Memory (CAM) cells are arranged on opposite sides of an axis of symmetry, and a first matching line (ML) conductive layer and a second matching line conductive layer are located on the substrate. In a top view, the first matching line conductive layer and the second matching line conductive layer overlap with the axis of symmetry between the two CAM cells and are arranged along the direction of the axis of symmetry.

[0005] The present invention also provides a method for fabricating a semiconductor layout pattern, comprising providing a substrate on which two Content Addressable Memory (CAM) cells are formed, arranged on both sides of an axis of symmetry, and forming a first matching line (ML) conductive layer and a second matching line conductive layer on the substrate, wherein, from a top view, the first matching line conductive layer and the second matching line conductive layer overlap with the axis of symmetry between the two CAM cells and are arranged along the direction of the axis of symmetry.

[0006] The present invention is characterized by providing a layout pattern for a ten-transistor unit and a corresponding circuit diagram. In another embodiment of the invention, the conductive layers connecting the matching lines in each region are aligned in the same direction to reduce the number of wire structures passing through each region, thereby allowing the regions to be arranged more closely to reduce the component area. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the circuit pattern of two adjacently arranged ten transistor units in the first embodiment of the present invention;

[0008] Figure 2 This is a schematic diagram of the layout pattern of two adjacent ten transistor units in the first embodiment of the present invention;

[0009] Figure 3 This is a top view schematic diagram of a first embodiment of the present invention, showing multiple regions containing ten transistor units and wires connecting the matching lines.

[0010] Figure 4 This is a schematic diagram of the circuit pattern of two adjacently arranged ten transistor units in the second embodiment of the present invention;

[0011] Figure 5 , Figure 6 and Figure 7 This is a schematic diagram of the layout pattern of two adjacent ten transistor units in the second embodiment of the present invention;

[0012] Figure 8 This is a top view schematic diagram of a second embodiment of the present invention, showing multiple regions containing ten transistor units and wires connecting the matching lines.

[0013] Symbol Explanation

[0014] 1: Ten transistor units (content-addressable memory)

[0015] 2: Ten transistor units (content-addressable memory)

[0016] 3: Ten transistor units (content-addressable memory)

[0017] 4: Ten transistor units (content-addressable memory)

[0018] 6T-SRAM: Six-transistor static random access memory

[0019] BL: Bitline

[0020] BLB: Position Line

[0021] E1: Boundary line (axis of symmetry)

[0022] F: Fin-like structure

[0023] G: Gate structure

[0024] INV1: First Inverter

[0025] INV2: Second Inverter

[0026] L1: Conductor Structure

[0027] L2: Conductor Structure

[0028] L3: Conductor Structure

[0029] M1: First metal layer

[0030] M2: Second metal layer

[0031] MD: Conductive layer

[0032] MD1: Conductive layer (first matching line conductive layer)

[0033] MD2: Conductive layer (matching line conductive layer)

[0034] MD3: Conductive layer (matching line conductive layer)

[0035] MD4: Conductive layer (second matching line conductive layer)

[0036] MD5: Conductive layer (bit line conductive layer)

[0037] MD6: Conductive layer (Vcc voltage source conductive layer)

[0038] MD7: Conductive layer (Vss voltage source conductive layer)

[0039] MD8: Conductive layer (first Vss voltage source conductive layer)

[0040] MD9: Conductive layer (second Vss voltage source conductive layer)

[0041] MD10: Conductive layer (Vcc voltage source conductive layer)

[0042] MD11: Conductive layer (bit line conductive layer)

[0043] MD12: Conductive layer (third Vss voltage source conductive layer)

[0044] ML: Matching line

[0045] MP: Conductive layer

[0046] N1: Storage node

[0047] N2: Storage Node

[0048] PU1: First pull-up transistor

[0049] PU2: Second pull-up transistor

[0050] PD1: First pull-down transistor

[0051] PD2: Second pull-down transistor

[0052] PG1: First transmission gate transistor

[0053] PG2: Second transmission gate transistor

[0054] R1, R2, R3, R4, R5, R6: Regions

[0055] SL1: Search Line

[0056] SL2: Search Line

[0057] SL1B: Search Line

[0058] SL2B: Search Line

[0059] T1: First transistor

[0060] T2: Second transistor

[0061] T3: Third transistor

[0062] T4: Fourth transistor

[0063] V0: Contact via

[0064] V1: First through hole

[0065] Vcc: Voltage source

[0066] Vss: Voltage source

[0067] WL1: Wordline

[0068] WL2: Wordline Detailed Implementation

[0069] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0070] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0071] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or to convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0072] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0073] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0074] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0075] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0076] Please refer to Figure 1 , Figure 1 The diagram illustrates a circuit pattern of two adjacently arranged ten transistor units in a first embodiment of the present invention. Please refer to [reference needed]. Figure 1 , Figure 1 The memory comprises adjacent regions R1 and R2. Region R1, located in the upper half, contains a ten-transistor unit 1, and region R2, located in the lower half, contains a ten-transistor unit 2. In this embodiment, the ten-transistor unit 1 or 2 can be applied to a content-addressable memory (CAM) cell. In subsequent steps, the ten-transistor unit 1 or 2 can be configured as a two-state content-addressable memory (BCAM) or a three-state content-addressable memory (TCAM) as needed. The following paragraphs primarily describe the ten-transistor unit 1; most components of the ten-transistor unit 2 are the same as those of the ten-transistor unit 1 and will not be repeated.

[0077] like Figure 1As shown, the ten-transistor unit 1 consists of a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, two series-connected first transistors T1 and T2, and two series-connected third transistors T3 and T4. The first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter INV1, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter INV2. The first inverter INV1 and the second inverter INV2 constitute a latch circuit, allowing data to be latched onto storage nodes N1 and N2.

[0078] In this embodiment, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 together constitute a six-transistor static random access memory (6T-SRAM). Additionally, the first pull-up transistor PU1 and the second pull-up transistor PU2 serve as active loads; they can also be replaced by ordinary resistors as pull-up elements, in which case it becomes a four-transistor static random access memory (4T-SRAM). Furthermore, in this embodiment, one source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc (not shown), and one source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss (not shown).

[0079] Generally speaking, the first pull-up transistor PU1 and the second pull-up transistor PU2 of a 6T-SRAM memory cell are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors.

[0080] At memory node N1, the gates G of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drains D of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first transmission gate transistor PG1 are electrically connected, respectively. Similarly, at memory node N2, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, and the second transmission gate transistor PG2 are also electrically connected, respectively. The gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are coupled to the word line WL1, and the sources of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are coupled to the corresponding bit lines BL and BLB, respectively.

[0081] like Figure 1 As shown, in this embodiment, the gate of the first transistor T1 is connected to the storage node N2 of the 6T-SRAM, meaning the gate of the first transistor T1 is connected to the gates of the first pull-up transistor PU1 and the first pull-down transistor PD1. The drain of the first transistor T1 is connected to a voltage source (e.g., a voltage source Vss). Furthermore, the second transistor T2 is connected in series with the first transistor T1, meaning the drain of the second transistor T2 is connected to the source of the first transistor T1. Additionally, the gate of the second transistor T2 is connected to a search line SL1, and the source of the second transistor T2 is connected to a match line ML. On the other hand, the connection methods of the third transistor T3 and the fourth transistor T4 are similar and symmetrical to those of the first transistor T1 and the second transistor T2, respectively. The gate of the third transistor T3 is connected to the storage node N1 of the 6T-SRAM, meaning the gate of the third transistor T3 is connected to the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2. The drain of the third transistor T3 is connected to a voltage source (e.g., a voltage source Vss). Furthermore, the fourth transistor T4 is connected in series with the third transistor T3, meaning the drain of the fourth transistor T4 is connected to the source of the third transistor T3. Additionally, the gate of the fourth transistor T4 is connected to the search line SL1B, and the source of the fourth transistor T4 is connected to the matching line ML.

[0082] The 6T-SRAM described above can be used as a signal storage unit in a tri-state content-addressable memory (TPM). The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4, which are connected to the 6T-SRAM, are used as the comparison logic circuit for the TPM. In other words, a TPM in this embodiment is composed of one 6T-SRAM and four other transistors.

[0083] In practice, the matching line ML can be pre-charged to a high potential. Then, search lines SL1 and SL1B can be supplied with either a high or low potential to turn on or off the second transistor T2 and the fourth transistor T4. This allows the signals from search lines SL1 and SL1B to be compared with the signals previously stored in the 6T-SRAM. For example, a high potential can be defined as signal 1, and a low potential as signal 0. Depending on the application, the signals of search lines SL1 and SL1B can be set to (0, 1), (1, 0), or (0, 0). Signals (0, 1) or (1, 0) are compared with the signals stored in memory nodes N1 and N2 in the 6T-SRAM. If the comparison matches, the electrical signal of the matching line ML remains high; otherwise, if the comparison does not match, the electrical signal of the matching line ML drops from high to low. Additionally, signal (0, 0) represents a "don't care" state, allowing for fuzzy comparison. In summary, the ten-transistor unit 1 described in this invention can be used as a two-state content-addressable memory (BCAM) or a three-state content-addressable memory (TCAM) according to usage requirements, both of which fall within the scope of this invention. Other related technologies concerning the principles and logic comparison methods of content-addressable memory are existing technologies in this field and will not be elaborated upon in this paragraph.

[0084] Figure 2 The diagram illustrates the layout pattern of two adjacent ten-transistor units in a first embodiment of the present invention. For example... Figure 2 As shown, in order to form ten transistor units in each region, multiple fin structures F, multiple gate structures G (e.g., polysilicon gates, but not limited thereto), and multiple conductive layers are formed on the substrate 10. Figure 2 In this design, the conductive layer overlapping with the gate structure G is defined as MP, while the conductive layer not overlapping with the gate structure G is defined as MD. The conductive layers MP and MD can be made of the same material, such as metals like tungsten, cobalt, copper, aluminum, gold, or silver, but are not limited to these. Both the conductive layers MP and MD function as connecting elements. Therefore, in some embodiments, the conductive layers MP and MD can be considered as a single layer structure.

[0085] Alternatively, the fin structure F can be replaced by a diffusion region; however, the fin structure F will be referred to as such hereinafter. The gate structure G spans the fin structure F and is combined to form the aforementioned transistors, including a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first transmission gate transistor PG1, a second transmission gate transistor PG2, a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Each transistor can be electrically connected to various signal sources, such as bit lines BL / BLB, word lines WL1 / WL2, search lines SL1 / SL1B / SL2 / SL2B, matching line ML, voltage source Vcc, and voltage source Vss, through subsequently formed metal wires or contact structures. For clarity, the accompanying drawings are provided. Figure 2 In the layout diagrams of various embodiments of the present invention, the names of transistors or connected signal sources are directly marked at the corresponding positions in the layout diagram to indicate that a specific transistor is formed at that position, or that the position is connected to a specific signal source.

[0086] When two or more ten transistor units 1 are arranged adjacently, refer to Figure 1 and Figure 2 As shown. Figure 1 The lower half of the package contains a region R2 containing a ten-transistor unit 2, which has a circuit pattern that is substantially symmetrical to that of the aforementioned ten-transistor unit 1. The difference is that the second transistor T2 in the ten-transistor unit 2 is connected to the search line SL2, while the fourth transistor T4 in the ten-transistor unit 2 is connected to the search line SL2B, and the gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 in the ten-transistor unit 2 are respectively coupled to the word line WL2. Apart from the above components, the remaining components of the ten-transistor unit 2 are arranged symmetrically with the components of the ten-transistor unit 1 along the matching line ML. For the sake of simplicity, the components of these symmetrical ten-transistor units 2 will not be described again.

[0087] It is worth noting that, in the first embodiment of the present invention, as Figure 1 and Figure 2 As shown, ten transistor units 1 and 2 are connected to the same matching line ML. Therefore, if the conductive layer MD connecting the matching line ML can be placed between region R1 and region R2 in the layout pattern, ten transistor units 1 and 2 can share the conductive layer MD connecting the matching line ML, which is helpful for the layout and configuration of the components.

[0088] However, the applicant found that the layout pattern of the first embodiment of the present invention still has room for improvement. More specifically, from Figure 2As shown in the layout diagram, only a portion of the conductive layer MD connecting the matching lines ML is located on the boundary line E1 between region R1 and region R2, while the conductive layer MD of the other connecting matching lines ML is not located on the boundary line between region R1 and region R2. Specifically, Figure 2 The conductive layer connecting the matching line ML and located on the boundary line E1 between region R1 and region R2 is defined as MD1. Two other conductive layers are further defined as MD2 and MD3. Conductive layer MD2 is located at the upper boundary of region R1, while conductive layer MD3 is located at the lower boundary of region R2.

[0089] from Figure 1 From the circuit diagram, conductive layers MD1, MD2, and MD3 are all connected to the same signal. Therefore, in subsequent steps, additional wires need to be formed to interconnect conductive layers MD1, MD2, and MD3. However, this configuration will occupy more component area and is not conducive to component miniaturization. (See also...) Figure 3 , Figure 3 A top view schematic diagram illustrating a plurality of regions containing ten transistor units and connecting wires according to a first embodiment of the present invention is shown. Figure 3 As shown, the substrate includes regions R1, R2, R3, R4, R5, and R6, with regions R1 and R2 arranged adjacent to each other. The conductors connecting the matching line ML are defined as conductor structures L1, L2, and L3, respectively. Regions R1 and R2 each contain three conductor structures L1 extending laterally, and these three conductor structures L1 are electrically connected to… Figure 2 The conductive layers MD1, MD2, and MD3 are electrically connected to the matching line ML. That is, the three conductor structures L1 pass through the upper boundary of region R1, the boundary between region R1 and region R2, and the lower boundary of region R2, respectively. Regions R1 and R2 described here are the same as those mentioned above. Figure 2 The diagram contains a region containing ten transistor units. To simplify the illustration, only the region and the wiring structure are shown here. Similarly, the remaining regions R3, R4, R5, R6 and the wiring structures L2 and L3 are similar to the regions R1, R2 and the wiring structure L1 described above, so they will not be repeated here.

[0090] From Figure 3 It becomes clearer that when multiple regions containing ten transistor cells are arranged adjacent to each other, the layout pattern is constrained by the position of the wire structures, preventing the regions from being closely aligned. For example, for regions R1 and R2, since their upper and lower boundaries each contain a wire structure L1, while the ten transistor cells in region R4 are connected to another matching line (corresponding to wire structure L2), regions R1 and R4 cannot share the same wire structure. For example, in... Figure 3 In this design, the upper boundary of region R1 contains a conductor structure L1, and the lower boundary of region R4 contains another conductor structure L2. Therefore, a certain gap needs to be maintained between the upper boundary of region R1 and the lower boundary of region R4 to accommodate the two conductor structures L1 and L2 respectively. This configuration results in large gaps between the regions, which is detrimental to component miniaturization.

[0091] To address the aforementioned issues, in another embodiment of the present invention, a modified version of the first embodiment is proposed, providing an alternative layout pattern for ten transistors and a corresponding circuit diagram. In another embodiment of the present invention, the conductive layers MD connecting the matching lines ML in each region are aligned along the same direction to reduce the number of wire structures passing through each region, thereby allowing the regions to be arranged more closely to reduce component area. See the following paragraphs for details.

[0092] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0093] Please refer to Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 , Figure 4 The circuit diagram of two adjacently arranged ten transistor units in the second embodiment of the present invention is shown. Figure 5 , Figure 6 and Figure 7 The diagram illustrates the layout pattern of two adjacent ten-transistor units in the second embodiment of the present invention. Figure 8 The illustration shows a top view of multiple regions containing ten transistor units and connecting wires according to a second embodiment of the present invention. In the first embodiment described above, the reason for the large number of wire structures passing through each region is mainly because the conductive layers MD1, MD2, and MD3, distributed within each region and connecting each matching line, are not aligned in the same direction. In other words, in Figure 2 The conductive layer MD1 is located on the boundary line E1 between region R1 and region R2, but the conductive layers MD2 and MD3 are not located on the boundary line E1 between region R1 and region R2. Therefore, in the second embodiment of the present invention, as... Figure 5As shown, an adjusted layout pattern for ten-transistor units 3 and 4 is provided. The main difference from the aforementioned ten-transistor units 1 and 2 is that, in this embodiment, within regions R1 and R2, all conductive layers MD connecting the matching lines ML are located on the boundary line E1 of regions R1 and R2. In other words, for region R1, except for the boundary line E1 (the lower boundary of region R1), the other three boundaries (… Figure 5 The left, top, and right boundaries of region R1 do not overlap with the conductive layer MD connecting the matching line ML. For region R2, except for boundary line E1 (the top boundary of region R2), the other three boundaries ( Figure 5 The left, lower, and right boundaries of region R2 do not overlap with the conductive layer MD connecting the matching line ML. More specifically, in this embodiment, the conductive layer connecting the matching line ML and the source of the second transistor T2 is defined as MD1, and the conductive layer connecting the matching line ML and the source of the fourth transistor T4 is defined as MD4. Both conductive layers MD1 and MD4 are located on the boundary line E1 between regions R1 and R2 and are aligned with each other in the X direction. Except for the boundary line E1, the other three boundaries of regions R1 and R2 do not contain the conductive layer MD connecting the matching line ML.

[0094] Figure 5 It contains multiple contact vias, which are defined as V0. The main function of these contact vias is to connect components in different layers, such as electrically connecting the subsequently formed first metal layer M1, first via V1, and second metal layer M2. Unlike the conductive layers MP and MD mentioned above, contact vias V0 and first via V1 are typically used to connect components in different layers in the vertical direction (Z direction), while conductive layers MP, MD, first metal layer M1, and second metal layer M2 are used to connect components in the planar direction (XY plane).

[0095] Because the layout pattern has been adjusted in this embodiment, the corresponding circuit diagram has also been adjusted. Please refer to... Figure 4 The main difference between this embodiment and the first embodiment described above lies in the change in the circuit connection between the third transistor T4 and the fourth transistor T4 to the 6T-SRAM. More specifically, in this embodiment, the gate of the fourth transistor T4 is connected to the storage node N1 of the 6T-SRAM, that is, the gate of the fourth transistor T4 is connected to the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2. Additionally, the gate of the third transistor T3 is connected to the search line SL1B. Apart from this, the remaining circuit connections are largely the same as described above. Figure 1As shown, this includes a third transistor T3 whose drain is connected to a voltage source (e.g., a voltage source Vss), a fourth transistor T4 connected in series with the third transistor T3, and a fourth transistor T4 whose source is connected to a matching line ML. Other parts not mentioned can be referred to in the first embodiment described above and related... Figure 1 The content will not be repeated here.

[0096] Please continue to refer to the following: Figure 6 and Figure 7 The first metal layer M1, the first via V1, and the second metal layer M2 are then formed. This connects the components to different signal sources, such as bit lines BL / BLB, word lines WL1 / WL2, search lines SL1 / SL1B / SL2 / SL2B, matching line ML, voltage source Vcc, voltage source Vss, etc. For clarity, the accompanying drawings are provided. Figures 6-7 In the layout diagrams of various embodiments of the present invention, the names of transistors or the names of connected signal sources are directly marked at the corresponding positions in the layout diagrams to indicate that a specific transistor is formed at that position, or that the position is connected to a specific signal source.

[0097] It is worth noting that in this embodiment, the layout pattern of the ten transistor units is adjusted so that all conductive layers connecting the matching lines ML (i.e., conductive layers MD1 and MD4) are located on the boundary line E1 between region R1 and region R2, while the number of conductive layers connecting the matching lines ML is also reduced. For example, in Figure 2 Regions R1 and R2 together contain three conductive layers MD1, MD2, and MD3 that connect the matching lines ML, but Figure 5 In the embodiment, regions R1 and R2 together contain two conductive layers MD1 and MD4 that connect matching lines ML.

[0098] Therefore, as Figure 7 As shown, after forming the second metal layer M2, the second metal layer M2 contains multiple metal lines parallel to each other along the X direction. Only one of these metal lines is needed to electrically connect the conductive layers MD1 and MD4 in region R1 and region R2. Here, the second metal layer of the electrical connection matching line ML is defined as the conductor structure L1, wherein the conductor structure passes through the boundary line between region R1 and region R2, and Figure 7 The wire structure L1 and Figure 8 The wire structure L1 is the same.

[0099] To make it clearer, Figure 8 The main components shown are the conductor structures L1, L2, and L3, and regions R1 to R6; other components are omitted. Figure 8As shown, when forming conductor structures L1, L2, and L3 to connect the conductive layers, it can be seen that the number of conductor structures passing through each region and connecting the matching line ML will also be reduced. For example, only one conductor structure L1 is needed to pass through region R1 and region R2 to connect the conductive layers MD1 and MD4 located in region R1 and region R2. The same applies to other regions.

[0100] Therefore, as Figure 8 As shown, taking regions R1 and R4 as examples, the upper boundary of region R1 does not contain any wire structures, and the lower boundary of the corresponding region R4 also does not contain any wire structures. Therefore, no space needs to be reserved between regions R1 and R4 to accommodate wire structures. In this embodiment, regions R1 and R4 can be arranged closely together (directly adjacent). Compared to the above... Figure 3 The embodiment shown can reduce the total area of ​​the components.

[0101] Based on the above description and accompanying drawings, this invention provides a semiconductor layout pattern, please refer to... Figures 4-8 It includes a substrate 10, on which two Content Addressable Memory (CAM) cells 3 and 4 are arranged on both sides of a symmetry axis (boundary line E1), and a first matching line conductive layer. Figure 5 The conductive layer MD1 and a second matching line conductive layer (in the middle) Figure 5 The conductive layer MD4 is located on the substrate, wherein, from a top view, the first matching line conductive layer MD1 and the second matching line conductive layer MD4 overlap with the axis of symmetry between the two content-addressable memory cells and are arranged along the direction of the axis of symmetry. In other words, the first matching line conductive layer MD1 and the second matching line conductive layer MD4 overlap with the boundary line E1 and are arranged along the direction of the boundary line E1.

[0102] In some embodiments of the present invention, each content-addressable memory cell includes four sides, one of which is a symmetry axis (boundary line E1), and the other three sides besides the symmetry axis are defined as outer boundaries, and the first matching line conductive layer MD1 and the second matching line conductive layer MD4 do not overlap with the three outer boundaries.

[0103] In some embodiments of the present invention, each content-addressable memory cell includes ten transistor layout patterns, and each ten-transistor layout pattern includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2), a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter, and a first transistor T1 and a second transistor T2 connected in series, wherein the gate structure of the first transistor T1 is connected to the gate structure of the first pull-down transistor (PD1), and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure of the fourth transistor T4 is connected to the gate structure of the second pull-down transistor (PD2).

[0104] In some embodiments of the present invention, a gate of the second transistor T2 and a gate of the third transistor T3 are respectively connected to a search line SL1 and a search line SL1B.

[0105] In some embodiments of the present invention, one source of the second transistor T2 and one source of the fourth transistor T4 are connected to a matching line ML.

[0106] In some embodiments of the present invention, a drain of the first transistor T1 and a drain of the third transistor T3 are connected to a voltage source (Vss).

[0107] In some embodiments of the present invention, a first matching line conductive layer is sequentially included on the axis of symmetry E1 between two content-addressable memory cells, viewed from a top view, along a horizontal direction. Figure 5 The conductive layer MD1 and the first line conductive layer (in the middle) Figure 5 The conductive layer MD5 in the middle), and the conductive layer of the Vcc voltage source ( Figure 5 The conductive layer MD6 in the middle), and the Vss voltage source conductive layer ( Figure 5 The conductive layer MD7 in the middle), and the second matching line conductive layer ( Figure 5 (The conductive layer MD4 in the middle).

[0108] In some embodiments of the present invention, a second metal layer M2 is further included, wherein the second metal layer includes a first portion (i.e. Figure 7 The conductor structure L1 connecting conductive layer MD1 and conductive layer MD4 has a first part that is a long strip pattern extending in the horizontal direction, and the first part is electrically connected to the first matching line conductive layer MD1 and the second matching line conductive layer MD4.

[0109] In some embodiments of the present invention, one of the two content-addressable memory cells includes an upper boundary, wherein along a horizontal direction, the upper boundary of the content-addressable memory cell sequentially includes a first Vss voltage source conductive layer. Figure 5 The conductive layer MD8 in the middle), and the second Vss voltage source conductive layer ( Figure 5 The conductive layer MD9 in the middle), and the conductive layer of the Vcc voltage source ( Figure 5 The conductive layer MD10 in the middle), the first line conductive layer ( Figure 5 The conductive layer MD11 in the middle), and a third Vss voltage source conductive layer ( Figure 5 The conductive layer MD12 in the middle.

[0110] In some embodiments of the present invention, the second metal layer M2 includes a second portion (see reference) Figure 5 and Figure 7 The second metal layer M2 located at the upper boundary has a conductor structure L4. The second part is a strip-shaped pattern extending horizontally and overlapping with the upper boundary. The second part is electrically connected to the first Vss voltage source conductive layer MD8, the second Vss voltage source conductive layer MD9 and the third Vss voltage source conductive layer MD12.

[0111] This invention also provides a method for fabricating a semiconductor layout pattern; please refer to [reference needed]. Figures 4-8 It includes providing a substrate 10, on which two content addressable memory (CAM) cells 3 and 4 are formed, arranged on both sides of a symmetry axis (boundary line E1), and a first matching line conductive layer is formed. Figure 5 MD1 in the middle) and a second matching line conductive layer ( Figure 5 MD4 is located on the substrate, wherein, from a top view, the first matching line conductive layer MD1 and the second matching line conductive layer MD4 overlap with the axis of symmetry between the two content-addressable memory cells and are arranged along the direction of the axis of symmetry. In other words, the first matching line conductive layer MD1 and the second matching line conductive layer MD4 overlap with the boundary line E1 and are arranged along the direction of the boundary line E1.

[0112] The present invention is characterized by providing a layout pattern for a ten-transistor unit and a corresponding circuit diagram. In another embodiment of the invention, the conductive layers connecting the matching lines in each region are aligned in the same direction to reduce the number of wire structures passing through each region, thereby allowing the regions to be arranged more closely to reduce the component area.

[0113] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor layout pattern, comprising: A substrate, on which two Content Addressable Memory (CAM) cells are arranged on opposite sides of an axis of symmetry; and A first matching line (ML) conductive layer and a second matching line conductive layer are located on the substrate, wherein, in a top view, the first matching line conductive layer and the second matching line conductive layer overlap with the axis of symmetry between the two content addressable memory cells and are arranged along the direction of the axis of symmetry.

2. The semiconductor layout pattern as claimed in claim 1, wherein each content-addressable memory cell includes four sides, one of which is the axis of symmetry, the other three sides besides the axis of symmetry are defined as outer boundaries, and the first matching line conductive layer and the second matching line conductive layer do not overlap with the three outer boundaries.

3. The semiconductor layout pattern of claim 1, wherein each content-addressable memory cell comprises ten transistor layout patterns, and each ten-transistor layout pattern comprises: The first pull-up transistor (PU1) and the first pull-down transistor (PD1) together form the first inverter (INV1); The second pull-up transistor (PU2) and the second pull-down transistor (PD2) together form the second inverter (INV2); The first transmission gate transistor (PG1) and the second transmission gate transistor (PG2) are connected to the first inverter and the second inverter; and A first transistor and a second transistor connected in series, wherein the gate structure of the first transistor is connected to the gate structure of the first pull-down transistor (PD1); and A third transistor and a fourth transistor are connected in series, wherein the gate structure of the fourth transistor is connected to the gate structure of the second pull-down transistor (PD2).

4. The semiconductor layout pattern as claimed in claim 3, wherein the gate of the second transistor and the gate of the third transistor are respectively connected to search line SL1 and another search line SL1B.

5. The semiconductor layout pattern of claim 3, wherein the source of the second transistor and the source of the fourth transistor are connected to a matching line (ML).

6. The semiconductor layout pattern of claim 3, wherein the drain of the first transistor and the drain of the third transistor are connected to a voltage source (Vss).

7. The semiconductor layout pattern of claim 1, wherein, viewed from the top view, along the horizontal direction, the first matching line conductive layer, the bit line conductive layer, the Vcc voltage source conductive layer, the Vss voltage source conductive layer, and the second matching line conductive layer are sequentially included on the axis of symmetry between the two content addressable memory cells.

8. The semiconductor layout pattern of claim 1, further comprising a second metal layer, wherein the second metal layer includes a first portion, the first portion being an elongated strip pattern extending in a horizontal direction, and the first portion being electrically connected to the first matching line conductive layer and the second matching line conductive layer.

9. The semiconductor layout pattern of claim 8, wherein one of the two content addressable memory cells includes an upper boundary, wherein along the horizontal direction, the upper boundary of the content addressable memory cell sequentially includes a first Vss voltage source conductive layer, a second Vss voltage source conductive layer, a Vcc voltage source conductive layer, a bit line conductive layer, and a third Vss voltage source conductive layer.

10. The semiconductor layout pattern of claim 9, wherein the second metal layer includes a second portion, the second portion being an elongated pattern extending in a horizontal direction and overlapping the upper boundary, wherein the second portion is electrically connected to the first Vss voltage source conductive layer, the second Vss voltage source conductive layer and the third Vss voltage source conductive layer.

11. A method for fabricating a semiconductor layout pattern, comprising: Provide a substrate on which two Content Addressable Memory (CAM) cells are formed, arranged on opposite sides of an axis of symmetry; and A first matching line (ML) conductive layer and a second matching line conductive layer are formed on the substrate, wherein, from a top view, the first matching line conductive layer and the second matching line conductive layer overlap with the axis of symmetry between the two content addressable memory cells and are arranged along the direction of the axis of symmetry.

12. The method for fabricating a semiconductor layout pattern as described in claim 11, wherein each content-addressable memory cell includes four sides, one of which is the axis of symmetry, the other three sides besides the axis of symmetry are defined as outer boundaries, and the first matching line conductive layer and the second matching line conductive layer do not overlap with the three outer boundaries.

13. The method for fabricating a semiconductor layout pattern as described in claim 11, wherein each content-addressable memory cell comprises ten transistor layout patterns, and each ten-transistor layout pattern comprises: The first pull-up transistor (PU1) and the first pull-down transistor (PD1) together form the first inverter (INV1); The second pull-up transistor (PU2) and the second pull-down transistor (PD2) together form the second inverter (INV2); The first transmission gate transistor (PG1) and the second transmission gate transistor (PG2) are connected to the first inverter and the second inverter; and A first transistor and a second transistor connected in series, wherein the gate structure of the first transistor is connected to the gate structure of the first pull-down transistor (PD1); and A third transistor and a fourth transistor are connected in series, wherein the gate structure of the fourth transistor is connected to the gate structure of the second pull-down transistor (PD2).

14. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the gate of the second transistor and the gate of the third transistor are respectively connected to search line SL1 and another search line SL1B.

15. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the source of the second transistor and the source of the fourth transistor are connected to a matching line (ML).

16. The method for fabricating a semiconductor layout pattern as described in claim 11, wherein the drain of the first transistor and the drain of the third transistor are connected to a voltage source (Vss).

17. The method for fabricating a semiconductor layout pattern as claimed in claim 11, wherein, viewed from the top view, along the horizontal direction, the first matching line conductive layer, the bit line conductive layer, the Vcc voltage source conductive layer, the Vss voltage source conductive layer, and the second matching line conductive layer are sequentially included on the axis of symmetry between the two content addressable memory cells.

18. The method for fabricating a semiconductor layout pattern as claimed in claim 11, further comprising forming a second metal layer, wherein the second metal layer includes a first portion, the first portion being an elongated pattern extending in a horizontal direction, and the first portion being electrically connected to the first matching line conductive layer and the second matching line conductive layer.

19. The method for fabricating a semiconductor layout pattern as claimed in claim 18, wherein one of the two content addressable memory cells includes an upper boundary, wherein along the horizontal direction, the upper boundary of the content addressable memory cell sequentially includes a first Vss voltage source conductive layer, a second Vss voltage source conductive layer, a Vcc voltage source conductive layer, a bit line conductive layer, and a third Vss voltage source conductive layer.

20. The method for fabricating a semiconductor layout pattern as claimed in claim 19, wherein the second metal layer includes a second portion, the second portion being an elongated pattern extending in a horizontal direction and overlapping the upper boundary, wherein the second portion is electrically connected to the first Vss voltage source conductive layer, the second Vss voltage source conductive layer, and the third Vss voltage source conductive layer.

Images