Self-error-correction erasable NVM (Non-Volatile Memory) storage method based on data detection and erasable NVM storage system
By employing a data-based self-correction method and redundant address management, the problem of data errors in erasable NVM memory under aging and interference is solved, achieving real-time error correction, extended lifespan, and reduced cost, making it suitable for high-reliability applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN LIAN MICROELECTRONICS CO LTD
- Filing Date
- 2026-02-02
- Publication Date
- 2026-05-15
AI Technical Summary
Existing erasable NVM memories suffer from data read/write errors due to physical aging, voltage fluctuations, and external interference during long-term use. Traditional external error correction solutions cannot fundamentally solve the problem of memory cell aging, increasing system complexity and cost.
A self-correction method based on data detection is adopted. Through the collaborative work of the CPU and coprocessor module, data errors are detected and corrected in real time. Redundant address space is used for dynamic management to avoid repeated errors at the same location. The built-in error correction mechanism simplifies system design.
It achieves real-time error correction capabilities, extends memory lifespan, reduces system costs, and improves data integrity and reliability, making it suitable for high-reliability scenarios such as industrial control and automotive electronics.
Smart Images
Figure CN122044488A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor storage technology, and specifically to a self-correcting, erasable NVM storage method and an erasable NVM storage system based on data detection. Background Technology
[0002] Existing erasable and rewritable NVM (Non-Volatile Memory) may experience data read / write errors during long-term use due to factors such as physical aging, voltage fluctuations, or external interference. Specifically, physical aging mainly stems from charge leakage, oxide layer damage, or the accumulation of tunneling effects in floating-gate transistors, leading to threshold voltage drift in memory cells and subsequently causing data misreads or writes. Voltage fluctuations may introduce timing deviations or logic level instability during read / write operations, resulting in compromised data integrity.
[0003] External interference such as electromagnetic radiation and sudden temperature changes can further exacerbate the degradation of the electrical characteristics of storage cells. Traditional solutions typically rely on technologies such as external error correction codes (ECC) or redundant arrays (RAID). While these methods can achieve a certain degree of error detection and recovery through data redundancy and verification mechanisms, they have significant limitations: for example, ECC requires additional decoding circuitry and algorithm logic, increasing system hardware complexity and design costs; RAID requires multiple chips to work together, which not only consumes more physical space and energy but may also affect system real-time performance due to the synchronization delay of redundant data. More importantly, these external solutions can only passively respond to errors that have already occurred and cannot fundamentally solve the aging problem of the storage cells themselves—that is, they cannot reverse charge leakage or repair oxide layer damage, causing the memory to fail due to physical degradation after multiple erase and write cycles.
[0004] Therefore, there is an urgent need for an erasable NVM memory with built-in self-correction function. Summary of the Invention
[0005] To address the problems existing in the prior art, this invention provides a self-correcting, erasable, and writable NVM storage system based on data detection. This system reduces the risk of stored data being unmodifiable and improves the overall effective lifespan of the chip.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The erasable and rewritable NVM self-correction method based on data detection includes the following steps: (1) The CPU accesses the erasable NVM storage module through the coprocessor module; (2) The erasable NVM storage module reads the data at the address allocated by the CPU and feeds the data back to the CPU through the coprocessing module; (3) The CPU controls the coprocessor module to detect the data read from the erasable NVM storage module; (4) If the detected data is correct, continue executing the program; if the detected data is incorrect, enter the data correction mode to correct the erroneous data. (5) After the data correction is completed, the coprocessing module executes steps (2) to (3) again to detect the data that has been corrected in the erasable NVM storage module; (6) If the detection data still contains errors, the coprocessor module will feed back the error data to the CPU, and the CPU will determine that "the chip is completely faulty" and stop executing the program; If the detection data does not contain errors, the coprocessor module will feed back the corrected data to the CPU. (7) The CPU obtains the redundant address space of the erasable NVM storage module and writes the corrected data after error correction; (8) After the data is written, the CPU reads the newly written address data again and compares the read data with the written data. If they match, the data writing is confirmed to be successful. (9) The CPU marks the mapping relationship between the old and new addresses, and jumps to the new data address when the program executes the erroneous data again.
[0007] Further, in step (7), the way the CPU obtains the redundant address space of the erasable NVM storage module is: the CPU marks the current erroneous data address and controls the coprocessor to read the redundant space of the erasable NVM storage module; If the erasable NVM storage module has no redundant space, the CPU will indicate "the chip is at risk of damage"; if the erasable NVM storage module has redundant space, the coprocessor will transmit the redundant space address data of the erasable NVM storage module to the CPU; the CPU will then place the corrected data into the new address.
[0008] Furthermore, the coprocessor module reads the redundant space of the erasable NVM storage module from low to high address; the coprocessor module transmits address data of the smallest redundant space address of the erasable NVM storage module that is empty to the CPU.
[0009] Further, in step (9), the step of the CPU marking the mapping relationship between the old and new addresses includes: During the execution of the CPU monitoring program, when the program encounters erroneous data in the erasable NVM storage module, the CPU calculates the difference between the new address and the original address, and adds the difference between the new address and the original address to the data at the address location according to different addressing modes; if the original address fails, the program executes normally according to the new address; the process of the CPU marking the mapping relationship between the old and new addresses can be implemented by embedding a BootLoader program.
[0010] Furthermore, the addressing mode includes ECC error correction mode and BCH encoding mode.
[0011] Furthermore, in step (3), the data read by the erasable NVM storage module is Bitcell data.
[0012] An erasable NVM storage system using the data detection-based erasable NVM self-correction method described above includes a CPU, a coprocessor module, and an erasable NVM storage module. The CPU controls the coprocessor module to communicate with the erasable NVM storage module, enabling read, write, and erase operations on the erasable NVM storage module. The coprocessor module detects whether the data read from and written to the erasable NVM is erroneous, corrects erroneous data, allocates the correct address space for the correct erasable NVM data based on the erroneous data, and cooperates with the CPU to write the correct data into the new address of the erasable NVM.
[0013] Furthermore, the coprocessing module includes: a data verification module 1, a data verification module 2, a data error correction circuit, an erasable NVM address space reallocation module, an erasable NVM address error marking module, and an erasable NVM erasure control module; the erasable NVM storage module includes an erasable NVM external circuit, a program address storage space, and a redundant address storage space.
[0014] Furthermore, the data verification module 1 is used to detect the data read from the erasable NVM storage module; the data verification module 2 is used to detect the data in the erasable NVM storage module that has completed error correction.
[0015] Furthermore, the data error correction circuit is an ECC error correction circuit.
[0016] Technical effects achieved by using the technical solution of this invention: (1) Real-time error correction capability: Real-time detection and correction of errors during data reading and writing without external intervention.
[0017] (2) Dynamic redundancy management: By address marking and redundancy space allocation, the vicious cycle caused by repeated errors at the same location is avoided.
[0018] (3) Extend service life: Reduce the risk of data loss due to storage unit failure and significantly improve the overall life of erasable NVM.
[0019] (4) Reduce system cost: The built-in error correction mechanism does not require additional hardware support, simplifying system design and reducing costs.
[0020] (5) High reliability: The multi-level error correction process ensures data integrity and is suitable for scenarios with extremely high reliability requirements, such as industrial control and automotive electronics. Attached Figure Description
[0021] Figure 1 A schematic diagram of the erasable NVM self-correction method based on data detection provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an erasable NVM storage system provided in an embodiment of the present invention. Detailed Implementation
[0022] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.
[0023] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.
[0024] like Figure 1 As shown, when the CPU reads data from the erasable NVM storage module through the coprocessor module, the first data read is the data stored inside the bitcell of the erasable NVM. Therefore, we determine whether the data in the bitcell is correct according to the ECC verification method.
[0025] If an error is detected, it indicates that the write data of the erasable NVM memory module may be corrupted due to damage to the code point storage location. Therefore, the error correction circuit is activated. Here, we are using an ECC error correction circuit, which can detect 1 bit data errors and correct them to correct data.
[0026] After the error correction is completed, the output of the corrected error correction circuit is checked again to determine whether the error correction result is correct. If the data error correction result is detected as incorrect again, it means that there are more than two data error points at the same address in the bitcell of the erasable NVM memory module, which exceeds the error correction limit of the data error correction circuit. At this time, the coprocessor module feeds back the error information to the CPU, and the CPU reports "chip damaged".
[0027] If the data correction result is correct, it means that there is only one location point of data error in the Bitcell of the erasable NVM storage module at the same address. The coprocessor module will send the corrected data to the CPU completely.
[0028] After receiving the correct error-correcting data, the CPU first determines whether the data read error was caused by a bitcell error. Specifically, this is done by rewriting the error-correcting data at the current address. The CPU performs a write instruction on the erasable NVM memory module, rewriting the error-correcting data back into the erasable NVM. After the write instruction cycle is complete, the CPU reads the data at the current address again. If the data detection module 1 indicates that the data is correct, it means that the previous data write error was likely caused by accidental factors such as voltage instability or chip impact, and the bitcell of the erasable NVM is undamaged, so no further processing is needed. If the data detection module 1 indicates that the data read error was caused by a bitcell error in the erasable NVM. To prevent another bitcell failure at that address from causing two error points that prevent the error-correcting circuit from recovering the data and rendering the chip unusable, the CPU checks the dedicated redundancy space counter of the erasable NVM to determine if there are any free addresses in the redundancy space.
[0029] The CPU checks the dedicated counter for the redundant space of the erasable NVM. If the data of the dedicated counter for the redundant space of the erasable NVM is Hff, the CPU indicates that the chip may be damaged in the future. If it is not HFF, the CPU rewrites the error correction data into the detected free address space and records the current address space. Because the data of the erasable NVM is written to a new address space, it is necessary to automatically recalibrate the relationship between the data in the new address space and the original instructions. Therefore, we have the CPU automatically record the mapping label between the original address of the data and the new redundant address. When the program later executes to the address space of the erasable NVM that has an access error, the "label" automatically guides the program to jump to execute the data in the new address space.
[0030] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.
[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A self-correcting method for erasable and rewritable NVM based on data detection, characterized in that, Includes the following steps: (1) The CPU accesses the erasable NVM memory module through the coprocessor module; (2) The erasable NVM memory module reads the data under the address allocated by the CPU and feeds the data back to the CPU through the coprocessor module; (3) The CPU controls the coprocessor module to detect the data read by the erasable NVM memory module; (4) If the detected data is not erroneous, the program continues to be executed; if the detected data is erroneous, the data correction mode is entered to correct the erroneous data; (5) After the data correction is completed, the coprocessor module executes steps (2) to (3) again to detect the data that has been corrected in the erasable NVM memory module; (6) If the detected data is still erroneous, the coprocessor module feeds the erroneous data back to the CPU, the CPU judges that "the chip is completely erroneous" and stops executing the program; if the detected data is not erroneous, the coprocessor module feeds the corrected data back to the CPU; (7) The CPU obtains the redundant address space of the erasable NVM memory module and writes the corrected data after error correction; (8) After the data is written, the CPU reads the newly written address data again and compares the read data with the written data. If they match, the data writing is confirmed to be successful. (9) The CPU marks the mapping relationship between the old and new addresses, and jumps to the new data address when the program executes the erroneous data again.
2. The erasable NVM self-correction method based on data detection according to claim 1, characterized in that, In step (7), the CPU obtains the redundant address space of the erasable NVM storage module by marking the current erroneous data address and controlling the coprocessor to read the redundant space of the erasable NVM storage module. If the erasable NVM storage module has no redundant space, the CPU will prompt "the chip is at risk of damage"; if the erasable NVM storage module has redundant space, the coprocessor will transmit the redundant space address data of the erasable NVM storage module to the CPU; the CPU will then put the corrected data into the new address.
3. The erasable NVM self-correction method based on data detection according to claim 2, characterized in that, The coprocessor module reads the redundant space of the erasable NVM storage module from low to high address; the coprocessor module transmits the address data of the smallest redundant space of the erasable NVM storage module that is empty to the CPU.
4. The erasable NVM self-correction method based on data detection according to claim 1, characterized in that, In step (9), the step of the CPU marking the mapping relationship between the old and new addresses includes: During the execution of the CPU monitoring program, when the program encounters erroneous data in the erasable NVM storage module, the CPU calculates the difference between the new address and the original address, and adds the difference between the new address and the original address to the data at the address location according to different addressing modes; if the original address fails, the program executes normally according to the new address; the process of the CPU marking the mapping relationship between the old and new addresses can be implemented by embedding a BootLoader program.
5. The erasable NVM self-correction method based on data detection according to claim 4, characterized in that, The addressing modes include ECC error correction mode and BCH encoding mode.
6. The erasable NVM self-correction method based on data detection according to claim 1, characterized in that, In step (3), the data read by the erasable NVM storage module is Bitcell data.
7. A rewritable NVM storage system using the data detection-based rewritable NVM self-correction method as described in any one of claims 1 to 6, characterized in that, It includes a CPU, a coprocessor module, and an erasable NVM storage module.
8. The erasable and rewritable NVM storage system according to claim 7, characterized in that, The coprocessor module includes: a data verification module 1, a data verification module 2, a data error correction circuit, an erasable NVM address space reallocation module, an erasable NVM address error marking module, and an erasable NVM erasure control module; the erasable NVM storage module includes an erasable NVM external circuit, a program address storage space, and a redundant address storage space.
9. The erasable and rewritable NVM storage system according to claim 8, characterized in that, The data verification module 1 is used to detect the data read from the erasable NVM storage module; the data verification module 2 is used to detect the data in the erasable NVM storage module that has completed error correction.
10. The erasable and rewritable NVM storage system according to claim 8, characterized in that, The data error correction circuit is an ECC error correction circuit.