Circuit board defect detection method and device, computer equipment and storage medium

Abstract

The invention relates to a circuit board defect detection method and device, computer equipment and a storage medium. The method comprises the following steps: respectively carrying out positioning and defect identification on a target circuit board to obtain a structure type to which each positioning area belongs and a defect type to which each defect area belongs; for each structure type, constructing a hierarchical spatial index corresponding to the structure type according to the spatial coordinates of all the positioning areas under the structure type; according to association rules of defect types and structure types, determining at least one target structure type associated with each defect region; searching in a hierarchical spatial index corresponding to the at least one target structure type according to the position information of the defect area to obtain an adjacent positioning area meeting a preset distance condition with the defect area; and according to the distance between the defect area and the adjacent positioning area, determining quantitative information of the distance between the defect area and the adjacent normal element. By adopting the method, the defect distance detection efficiency in multiple positioning scenes can be improved.

Description

Technical Field

[0001] This application relates to the field of defect detection technology, and in particular to a method, apparatus, computer equipment, and storage medium for detecting defects in circuit boards. Background Technology

[0002] With the continuous evolution of semiconductor packaging technology and high-density interconnect (HDI) circuit board manufacturing processes, the size of components on circuit boards is becoming increasingly smaller, the wiring spacing is constantly decreasing, and structures such as aluminum wires (conductors), independent chips, and multi-chip modules are becoming highly dense in space.

[0003] In related technologies, in high-density circuit boards with a large number of components (such as tens of thousands of aluminum wires), the common approach to defect detection is to calculate the distance between each defect and all similar components. This approach is computationally complex, time-consuming, and difficult to meet the cycle time requirements of online real-time detection, resulting in low engineering practicality.

[0004] Therefore, a more efficient defect distance detection solution is needed in multi-location scenarios. Summary of the Invention

[0005] Therefore, it is necessary to provide a circuit board defect detection method, apparatus, computer equipment, computer-readable storage medium, and computer program product to address the above-mentioned technical problems, which can improve the efficiency of defect distance detection in multi-positioning scenarios.

[0006] In a first aspect, embodiments of this application provide a method for detecting defects in a circuit board, including:

[0007] The target circuit board is located and defect identified separately to obtain multiple location areas and the structural type of each location area, as well as at least one defect area and the defect type of each defect area; wherein, the location area represents the preset component structure on the circuit board.

[0008] For each structure type, a hierarchical spatial index is constructed based on the spatial coordinates of all positioning regions under the structure type. In the hierarchical spatial index, multiple nodes are connected hierarchically, and the spatial range represented by a node is the union of the spatial ranges represented by the lower-level child nodes of the current node.

[0009] For each defect area, based on the association rules between defect type and structure type, at least one target structure type associated with the defect area is determined;

[0010] Based on the location information of the defect area, a search is performed in the hierarchical spatial index corresponding to at least one target structure type to obtain the neighboring positioning area that meets the preset distance condition with respect to the defect area.

[0011] Based on the distance between the defective area and the adjacent positioning area, the distance quantification information between the defective area and its adjacent normal components is determined; the distance quantification information is used to assess the degree of impact of the defective area on the performance of the target circuit board.

[0012] Secondly, embodiments of this application provide a circuit board defect detection device, comprising:

[0013] The identification module is used to locate and identify defects in the target circuit board, and obtain multiple positioning areas and the structural type of each positioning area, as well as at least one defect area and the defect type of each defect area; wherein, the positioning area represents the preset component structure on the circuit board.

[0014] The construction module is used to build a hierarchical spatial index for each structure type based on the spatial coordinates of all positioning regions under the structure type. In the hierarchical spatial index, multiple nodes are connected hierarchically, and the spatial range represented by a node is the union of the spatial ranges represented by the lower-level child nodes of the current node.

[0015] The determination module is used to determine at least one target structure type associated with each defect area based on the association rules between defect type and structure type.

[0016] The search module is used to search in the hierarchical spatial index corresponding to at least one target structure type according to the location information of the defect area, and obtain the neighboring positioning area that meets the preset distance condition with the defect area.

[0017] The quantization module is used to determine the distance quantization information between the defective area and its neighboring normal components based on the distance between the defective area and the adjacent positioning area; the distance quantization information is used to evaluate the degree of impact of the defective area on the performance of the target circuit board.

[0018] Thirdly, embodiments of this application provide a computer device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the circuit board defect detection method described above.

[0019] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the circuit board defect detection method described above.

[0020] Fifthly, embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the circuit board defect detection method described above.

[0021] The aforementioned circuit board defect detection method, apparatus, computer equipment, computer-readable storage medium, and computer program product, by constructing a hierarchical spatial index for each structural type, organize massive positioning regions into a tree structure according to spatial relationships. This reduces the computational complexity of proximity search from traversal to logarithmic level, thereby improving the search efficiency for defect distances in high-density (e.g., multi-positioning region) circuit boards. Furthermore, this application pre-determines the target structural type that the defect needs to be associated with through association rules, avoiding meaningless searches in irrelevant component types, further enhancing the focus and overall efficiency of the analysis. Attached Figure Description

[0022] Figure 1 This application provides an illustration of the application environment for a circuit board defect detection method according to an embodiment of the present application.

[0023] Figure 2 A schematic flowchart illustrating a circuit board defect detection method provided in an embodiment of this application;

[0024] Figure 3 A structural block diagram of a circuit board defect detection device provided in an embodiment of this application;

[0025] Figure 4 An internal structural diagram of a computer device provided in an embodiment of this application;

[0026] Figure 5 This is an internal structural diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0028] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms used in this application include and have, and any variations thereof, are intended to cover non-exclusive inclusion. The term "multiple" in this application refers to two or more. The terms used in this application and / or refer to one of the embodiments, or any combination of multiple embodiments.

[0029] The circuit board defect detection method provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a communication network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or located in the cloud or on other network servers. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, drones, low-altitude aircraft, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. Server 104 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0030] like Figure 2 As shown, this application embodiment provides a circuit board defect detection method, which is applied to... Figure 1 Taking server 104 as an example, the following steps are included:

[0031] Step 202: Locate and identify defects in the target circuit board to obtain multiple location areas and the structural type of each location area, as well as at least one defect area and the defect type of each defect area; wherein, the location area represents the preset component structure on the circuit board.

[0032] The target circuit board can be a printed circuit board (PCB) or integrated circuit board to be inspected for defects. The identification process can be based on the analysis of high-resolution images of the target circuit board (such as RGB or grayscale images acquired by a linear or area array camera). Specifically, the identification process can be implemented using a trained deep neural network model (e.g., a semantic segmentation model based on architectures such as U-Net or Mask R-CNN). This deep neural network model takes the circuit board image as input and outputs a probability distribution map of each pixel belonging to different categories (including multiple preset structural types and defect types).

[0033] Structure type refers to a predefined, normal category of components or structures on a circuit board; for example, structure types may include: aluminum wire areas (characterizing wires or bonding wires on a circuit), isolated chip areas (characterizing isolated, well-packaged integrated circuit chips), and non-isolated chip areas (characterizing closely adjacent chip areas in a multi-chip module, whose outlines may be connected or very close together). These categories are predefined based on circuit board design and manufacturing knowledge. Defect type refers to a category of anomalies or malfunctions that may occur on a circuit board. For example, defect types may include: solder joint anomalies (such as cold solder joints, bridging), contaminated pads, surface scratches (such as physical scratches, missing material), and contaminated chips.

[0034] The output of the deep neural network model, after post-processing (such as thresholding and connected component analysis), yields a series of discrete region contours. Each contour is labeled with its category (structure type or defect type) and accompanied by its location information (e.g., coordinates of the contour polygon vertices, coordinates of the minimum bounding rectangle, coordinates of the region centroid, etc.). This results in a set of localized regions for all normal component structures, each with its structure type label and spatial coordinates, and a set of defective regions for all abnormal regions, each with its defect type label and location information.

[0035] Step 204: For each structure type, construct a hierarchical spatial index corresponding to the structure type based on the spatial coordinates of all positioning areas under the structure type; where multiple nodes in the hierarchical spatial index are connected hierarchically, and the spatial range represented by a node is the union of the spatial ranges represented by the lower-level child nodes of the current node.

[0036] Considering the potentially enormous number of similar components (such as aluminum wires) on a circuit board, the traditional method of calculating distances by traversing each defect area sequentially (time complexity O(N)) is inefficient in real-time detection scenarios if it is necessary to quickly find the neighboring normal components of the same type for each defect area. Therefore, in this embodiment, a separate spatial index is constructed for each structural type, thereby transforming the linear search into a logarithmic tree search. Specifically, the hierarchical spatial index is a tree-like data structure that presents a multi-level (multi-layer) organizational form, where higher-level nodes summarize and aggregate the spatial range of lower-level nodes. This structure differs from simple linear lists or flat groupings, establishing a spatial navigation path from macro to micro through tree-like connections (such as parent-child node relationships). The hierarchical spatial index is used to organize and quickly retrieve geometric objects (i.e., positioning areas) on a two-dimensional plane. Each node (leaf node or non-leaf node) is associated with a defined spatial range (which can be represented by a minimum bounding rectangle).

[0037] A concrete and mature implementation is the R-tree or its variants (such as the R* tree). Taking the R-tree as an example, the construction process can include: First, obtaining the minimum bounding rectangle of all location regions under this type. Then, using a spatial partitioning algorithm (e.g., the R-tree batch loading algorithm STR, or a kd-tree-based partitioning algorithm), these rectangles are grouped. Each group forms an intermediate node, which records a merged rectangle that completely contains the rectangles of all its child nodes. This grouping operation is performed recursively until each leaf node contains only the rectangle of one original location region. The resulting tree structure has its root node's merged rectangle covering all elements of this type, intermediate nodes representing spatial subsets of different granularities, and leaf nodes corresponding to specific individual elements. Thus, the spatial extent represented by any non-leaf node is the union of the spatial extents of all its child nodes. This structure provides the foundation for subsequent regional queries and distance pruning.

[0038] In this embodiment, a hierarchical spatial index is constructed separately for each structural type, thereby efficiently organizing all discrete positioning regions under that type according to their spatial relationships. This eliminates the need to traverse all components of that type when searching for components adjacent to a specific location (such as a defect area) (time complexity O(N), where N is the number of components). Using the hierarchical index, starting from the root node (covering the entire area), the spatial range information recorded by the node can be used to quickly eliminate entire branches that are clearly not spatially adjacent, rapidly converging the search range to a few leaf nodes that may contain the target, thus achieving an efficient search of O(log N). The merged rectangle of the node records facilitates the rapid calculation of spatial relationships (such as the minimum possible distance), which is the basis for efficient pruning. Furthermore, since indexes with different parameters or depths can be constructed for different types of components (such as a large number of aluminum wires and a small number of chips), the utilization of circuit board defect detection resources is more rational.

[0039] Step 206: For each defect area, determine at least one target structure type associated with the defect area based on the association rules between defect type and structure type.

[0040] In particular, the impact of different defects on circuit board performance may depend on the proximity of the specific defect to a specific type of normal component structure, rather than its proximity to all components. For example, the danger of an abnormal solder joint defect depends mainly on whether it is too close to the aluminum wire area (which may lead to a short circuit or open circuit); while the impact of a chip contamination defect needs to be assessed on how close it is to the active surface of an isolated chip area or a non-isolated chip area.

[0041] Therefore, in this embodiment, a set of association rules is predefined, which takes the form that if the defect type is A, then its associated target structure type is B and / or C. Specifically, a list of target structure types can be maintained for each defect type. When processing a specific defect area, based on its identified defect type, this list is queried to determine which structure types' spatial indices need to be searched for proximity.

[0042] Step 208: Based on the location information of the defect area, search in the hierarchical spatial index corresponding to at least one target structure type to obtain the neighboring positioning area that meets the preset distance condition with respect to the defect area.

[0043] The location information of the defect area can be the minimum bounding rectangle of the defect area, or a more precise outline polygon. For each target structure type (e.g., aluminum wire), a search is performed in the corresponding hierarchical spatial index (e.g., aluminum wire index tree). The search algorithm is a tree traversal algorithm based on distance pruning. Specifically, pruning refers to the key technique of identifying and discarding as many subtrees as possible that are unlikely to contain the final answer as early as possible during tree traversal, avoiding unnecessary precise calculations of all nodes within them, thereby improving search efficiency.

[0044] It should be noted that the pruning operation is performed in this embodiment because the lower bound information of the spatial range provided by the merged rectangles stored in the non-leaf nodes of the hierarchical spatial index. That is, for any non-leaf node, its merged rectangle M contains the spatial range of all descendant nodes (i.e., the actual positioning areas) under that node. Therefore, the distance from the queried geometry Q (defect area) to any actual positioning area under that node must be greater than or equal to the minimum possible distance from Q to the merged rectangle M. That is: Distance(Q, any_child_in_node) >= MinPossibleDistance(Q, M).

[0045] Specifically, during the search process, the currently found best distance `best_dist` (initially infinity) and its corresponding best candidate region can be maintained. When visiting a non-leaf node, although it's not immediately known which region under its child nodes is closest to Q, the minimum possible distance `d_min` from Q to the merged rectangle M of that node can be calculated. This is a conservative estimate, and the computational cost is much less than traversing all child nodes. If `d_min >= best_dist`, it means that even in the optimal case of this node (i.e., there exists a region under it that happens to be located at the point in M ​​closest to Q), the distance from that region to Q will not be better than the currently known best result `best_dist`. Therefore, the entire branch under this node can be safely skipped (pruned) without further exploration. Conversely, if `d_min < best_dist`, it indicates that there may be a location region under this node that is closer than the current best region, and it is necessary to continue traversing its child nodes for investigation.

[0046] In circuit board inspection scenarios, the number of similar components (such as aluminum wires) can reach tens of thousands. Pruning avoids the need for precise distance calculations with the vast majority of components that are spatially far from defects. The search process changes from comparing all components one by one to making precise comparisons with only a few spatially adjacent candidate components, reducing computational complexity from linear to logarithmic levels. This is crucial for automated optical inspection systems that require real-time or near-real-time processing of high-resolution circuit board images.

[0047] The specific retrieval process can be as follows: using the outline of the defective region as the query geometry, starting from the root node of the index tree.

[0048] When traversing to a non-leaf node, calculate the minimum possible distance between the query geometry and the merged rectangle recorded by that node (i.e., the closest distance the two geometries can reach in space). If this minimum possible distance is greater than or equal to (i.e., not less than) the currently known candidate closest distance (initially set to infinity or a large threshold), it can be concluded that none of the child nodes under this node (i.e., all elements within this spatial subset) can be closer than the current candidate. Therefore, traversing this branch can be stopped, achieving pruning and significantly reducing the amount of computation. If the minimum possible distance is less than the current candidate value, it is necessary to continue traversing its child nodes.

[0049] Correspondingly, when traversing to a leaf node, the leaf node corresponds to a specific positioning region. At this point, it is necessary to accurately calculate the geometric distance (e.g., the shortest Euclidean distance between polygons) between the contour of the defect region and the contour of the positioning region. If this distance is less than the currently recorded nearest candidate distance value, then the candidate value is updated to this smaller distance, and the positioning region corresponding to the current leaf node is recorded as the current nearest candidate positioning region.

[0050] By combining depth-first traversal with pruning, the algorithm can quickly eliminate a large number of irrelevant regions and ultimately efficiently find the nearest or nearest neighboring regions that truly meet the requirements of the defective region.

[0051] Step 210: Determine the distance quantification information between the defective area and its neighboring normal components based on the distance between the defective area and the adjacent positioning area; the distance quantification information is used to assess the degree of impact of the defective area on the performance of the target circuit board.

[0052] Considering that one or more neighboring locations may be found for each target structure type, these search results are combined to generate a final distance quantification. For simple associations (such as defects associated with only one target type), the distance quantification can be directly the shortest distance from the defect area to the nearest component of that type. For cases involving associations with multiple target types (such as scattered defects associated with independent and non-independent chips), more complex logic is required. For example, the shortest distance to both types of chips can be calculated separately, then compared and judged: if the distance to the non-independent chip is closer, it may mean that the defect is located in a densely populated chip area, and the scope of influence may be more complex; if the distance to the independent chip is closer, the distance itself can directly reflect the proximity of the defect to the chip package.

[0053] The final distance quantification information can be a specific distance value or a typed distance description (e.g., 0.1mm from the nearest aluminum wire, or attached to a non-independent chip cluster). This information provides crucial input for downstream decision-making logic. For example, the decision-making system can set rules: when the distance between a solder joint anomaly and the aluminum wire is less than 10 micrometers, it is judged as a high-risk defect; when chip contamination directly intersects the chip outline (distance is 0), it is judged as a defect requiring re-inspection. By quantifying the spatial relationship between defects and related normal components, the assessment of their impact on electrical performance, heat dissipation performance, or long-term reliability will be more accurate and objective.

[0054] In summary, the embodiments of this application establish a hierarchical spatial index (such as an R-tree) for each structural type, organizing discrete and massive components into a tree structure according to their spatial location. Based on the index, subtree branches far from the defect in the entire space can be eliminated in the early stage of traversal, making the search range converge exponentially. This makes it efficient and feasible to perform nearest neighbor search in large-scale circuit board images, and can significantly shorten the processing time without sacrificing detection accuracy, meeting the requirements of industrial production lines for high throughput and real-time response.

[0055] In some embodiments, the hierarchical spatial index includes a multi-level tree index; for each structure type, a hierarchical spatial index corresponding to the structure type is constructed based on the spatial coordinates of all positioning regions under the structure type, including:

[0056] For each structure type, the relative positional relationships of all positioning areas under the structure type are determined based on the spatial coordinates of all positioning areas under the structure type; the relative positional relationships include inclusion relationships and adjacency relationships.

[0057] For all positioning regions under the structure type, determine the minimum bounding rectangle of the outline of each positioning region;

[0058] Using the minimum bounding rectangle as the basic unit, a multi-level tree index is constructed based on the relative positional relationship between multiple minimum bounding rectangles; wherein, the spatial range represented by the non-leaf node in the multi-level tree index is the merged rectangle of the minimum bounding rectangles corresponding to all child nodes of the current non-leaf node.

[0059] To accurately and efficiently construct hierarchical spatial indexes for each structural type, for each structural type (e.g., aluminum wire region), the spatial relationships between all pairwise positioning regions within it need to be analyzed. Containment relationship refers to the fact that the outline (or its smallest bounding rectangle) of one positioning region is completely located inside the outline (or rectangle) of another positioning region. Containment relationship is used to determine potential parent-child node levels when constructing a tree index. Adjacency relationship refers to two positioning regions being spatially adjacent, with their outlines or smallest bounding rectangles being less than a certain threshold in distance, or directly intersecting or tangent. Adjacency relationship is the basis for grouping during index construction, because grouping spatially adjacent elements in the same group (i.e., under the same parent node) ensures that the merged rectangles corresponding to that parent node are as compact as possible, thus achieving better pruning results in future searches.

[0060] The relative positional relationships can be determined by calculating the distance between the polygonal outlines of the regions, or more efficiently, by calculating the distance or overlapping area between their minimum bounding rectangles. To simplify calculations and improve the efficiency of index building and querying, in this embodiment, the complex polygonal outline of each location region is approximated by its minimum bounding rectangle. The minimum bounding rectangle is the smallest rectangle that completely encloses the region's outline and whose edges are parallel to the coordinate axes. It can be defined using the coordinates (x_min, y_min, x_max, y_max) of its lower left and upper right corners. It is understood that calculating the spatial relationships (containment, intersection, distance) between rectangles is much simpler and faster than that of polygons, thus laying the foundation for the efficient calculation of the minimum possible distance in subsequent large-scale index building and searching.

[0061] A large number of discrete minimum bounding rectangles belonging to the same structural type are organized into a multi-level tree index, where spatial proximity (i.e., adjacency relationship) between rectangles is used as the primary grouping criterion. The algorithm attempts to group several rectangles that are close together to form a group and creates a parent node (non-leaf node) for this group. This parent node does not store specific component information, but rather stores a new merged rectangle that can completely contain all its child rectangles.

[0062] It should be noted that the grouping process described above is recursive. All original rectangles are considered leaf nodes. Using a spatial partitioning algorithm (such as the "Sort-Tile-Recursive" method in R-tree construction), these leaf nodes are grouped to generate the first level of non-leaf nodes. Then, these first-level non-leaf nodes (each with a merged rectangle) are treated as new objects, and the grouping continues to generate higher-level non-leaf nodes. This process is repeated recursively until all nodes can be contained within a single root node.

[0063] In a multi-level tree index, a leaf node corresponds to the original location region (represented by its smallest bounding rectangle). Non-leaf nodes do not correspond to actual elements; their role is organization and indexing. Their stored merged rectangle is the spatial union of the rectangles of all their child nodes. Higher-level nodes (such as the root node) have merged rectangles covering large areas, while lower-level nodes cover smaller areas. This hierarchical structure allows for rapid, coarse-to-fine location of the target region during a search.

[0064] The multi-level tree-structured index built through the above steps compresses the spatial information of massive components into a hierarchical data structure. Therefore, during a search, when calculating the distance between the queried defect region and the merged rectangle of a non-leaf node, this distance is actually the lower bound of the distance from the defect region to any actual component region under that node. This provides the foundation for subsequent efficient pruning operations, ensuring that potential nearest neighbors are not missed when excluding irrelevant branches, thus improving speed while maintaining the accuracy of search results.

[0065] In some embodiments, based on the location information of the defect area, searches are performed in the hierarchical spatial index corresponding to at least one target structure type to obtain neighboring positioning areas that meet a preset distance condition with respect to the defect area, including:

[0066] Using the outline of the defective area as the query range, the system traverses from the root node of the multi-level tree index until it reaches the leaf node, and determines the candidate location areas obtained by the traversal as the neighboring location areas that meet the preset distance from the defective area.

[0067] Specifically, when traversing to a leaf node, the geometric distance between the defect area and the location area corresponding to the current leaf node is calculated. If the geometric distance is less than a preset distance threshold, the preset distance threshold is updated to the geometric distance, and the location area corresponding to the current leaf node is determined as a candidate location area. When traversing to a non-leaf node, the minimum possible distance between the query range and the merged rectangle represented by the non-leaf node is calculated. If the minimum possible distance is less than a preset distance threshold, the child nodes of the current non-leaf node are traversed. If the minimum possible distance is not less than the preset distance threshold, the traversal of all child nodes of the current non-leaf node is stopped.

[0068] In order to perform accurate spatial relationship calculations, the precise outline polygon of the defect area can be defined as the query range Q of this search, thereby ensuring the accuracy of the final distance calculation.

[0069] First, set an initial nearest neighbor distance threshold. This threshold can be initialized in several ways: set to infinity (inf), indicating that no candidates have been found; or set to a preset maximum effective search distance. For example, in circuit board inspection, components farther than 1mm can be considered negligible in their impact on the defect, so the initial threshold can be set to 1.0mm. This method can preemptively prune more distant branches. Alternatively, a reasonable initial value can be dynamically set based on historical data or defect type. Simultaneously, initialize a candidate location region variable to record the region of the currently found normal component closest to the defect.

[0070] The search process can adopt the depth-first search (DFS) strategy, starting from the root node of the index tree and recursively visiting each node. Among them, when visiting each node, different logics are executed according to its type (leaf node or non-leaf node). When traversing to the non-leaf node Node_NL, calculate the minimum possible distance between the query range Q (defect contour) and the merged rectangle M stored in this non-leaf node. Among them, d_min is the theoretical lower bound of the closest distance that the two geometries of Q and M can reach in space. Specifically, the distance between the minimum bounding rectangle B_Q of Q and M can be calculated first. If B_Q and M intersect, then d_min = 0; otherwise, d_min is the closest distance from the four sides of B_Q to the four sides of M. Since M contains all the descendant leaf nodes under Node_NL (i.e., the actual component areas), d_min is大概率 greater than or equal to a conservative lower bound of the distance of any actual component under the subtree of Node_NL. That is, Distance(Q, any_leaf_in_Node_NL) >= d_min. Compare the calculated d_min with the currently maintained distance threshold D_thresh. If d_min >= D_thresh, it indicates that even if there is an ideal component (exactly located at the point closest to Q in M) under the subtree of Node_NL, its distance to the defect is unlikely to be better than the current best candidate (or the preset valid range). Therefore, it is unlikely that the entire subtree of Node_NL contains a better solution. At this time, pruning is performed, that is, stop traversing all the child nodes of Node_NL.

[0071] If d_min < D_thresh, it indicates that there may be a component closer than the current best candidate (or there is a component within the valid range) under the subtree of Node_NL. Therefore, recursively traverse each child node of Node_NL (these child nodes may be non-leaf nodes at a lower level or leaf nodes).

[0072] When traversing to the leaf node Node_L, calculate the geometric distance between the query range Q (defect contour) and the exact contour of this positioning area. Compare the calculated d_exact with the current D_thresh. If d_exact < D_thresh: A closer (or within the valid range) candidate component is found, and the following updates are performed: Update the distance threshold: D_thresh = d_exact. This makes the subsequent pruning conditions more stringent and helps to further accelerate the search. And update the candidate positioning area: Record the positioning area corresponding to the current leaf node Node_L as the new candidate positioning area (i.e., the current adjacent positioning area).

[0073] The traversal continues until the entire tree structure starting from the root node has been visited, or until a large number of branches are skipped due to pruning. After the traversal, the last updated candidate location region is the location region found in the index tree of the target structure type that is closest to the defective region. If D_thresh is initialized to a finite value (such as a preset maximum search distance), and the final D_thresh is still the initial value, it means that no candidate was found within the valid range, and the result can be recorded as none.

[0074] The search mechanism described in this application combines the hierarchical nature of tree structures with the pruning principle of spatial distance. By pre-judging the d_min of non-leaf nodes, it can eliminate a large number of completely irrelevant subtrees in a large-scale index tree very early, thereby traversing all leaf nodes and reducing the average search complexity from O(N) to O(logN). This is crucial for handling tens of thousands of components on a circuit board. Since d_min is a lower bound of the actual distance, pruning based on d_min>=D_thresh is safe and will never mistakenly prune branches that may contain nearest neighbors, ensuring the accuracy of the search results.

[0075] In some embodiments, normal components of the preset category include aluminum wires, stand-alone chips, and non-stand-alone chips; the defect types to which the defect area belongs include solder joint abnormalities, solder pad contamination, burrs, and chip contamination.

[0076] The association rules between defect type and structure type include: if the defect type is solder joint abnormality or pad contamination, the structure type is aluminum line area; if the defect type is scattered damage or chip contamination, the structure type is independent chip area and non-independent chip area.

[0077] In the field of circuit board inspection, components with different geometries and functions exhibit varying failure modes and are affected by defects. Therefore, in this application embodiment, the component structures of circuit boards are classified into the following three structural types based on electrical function, spatial form, and defect detection requirements:

[0078] Aluminum wires are used to characterize metal conductors, bonding wires, or conductive traces on circuit boards. Aluminum wires typically have a long, winding geometry and are responsible for transmitting signals and electricity. Aluminum wires require extremely high integrity in their electrical connections; any nearby anomalies (such as excess solder or conductive contaminants) can lead to short circuits, open circuits, or signal crosstalk.

[0079] A standalone chip is used to characterize an integrated circuit chip that is fully packaged and spatially isolated from other chips. The outline of a standalone chip is typically a regular rectangle, and it is the core functional unit of the circuit board. During testing, attention must be paid to the integrity of its surface and edges.

[0080] Non-independent chips are used to characterize chip regions in multi-chip modules, chip stacks, or chip arrays with extremely small spacing, where the chip outlines are adjacent or nearly connected. In an image, a non-independent chip may appear as an aggregate of multiple chip outlines. Its key characteristic is the extremely small gaps between the chips; any defects located in these gaps (such as contaminants or scratches) can affect multiple chips or cause heat dissipation problems.

[0081] Accordingly, the embodiments of this application focus on the following common defects that have a significant impact on the reliability of circuit boards:

[0082] Solder joint abnormalities include cold solder joints (insufficient solder), bridging (excessive solder causing unwanted connections), and poor solder ball shape. These defects directly affect the reliability of electrical connections.

[0083] Dirty solder pads refer to the presence of foreign matter, oxidation, or contamination on the surface of solder pads, which may affect soldering quality or cause corrosion.

[0084] Scattered damage refers to physical damage such as scratches, dents, missing materials, and cracks. These defects can damage the insulation layer, affect mechanical strength, or become corrosion initiation points.

[0085] Chip contamination refers to the presence of contaminants such as dust, fibers, and gel on the surface or edges of a chip, which may affect heat dissipation, cause electromigration, or lead to other reliability issues.

[0086] Based on the physical characteristics of the aforementioned components and defects, embodiments of this application define the following core association rules to guide the focus of defect analysis to the most relevant class or several classes of normal components:

[0087] Rule 1: If the defect type is solder joint abnormality or solder pad contamination, the target structure type is aluminum wire.

[0088] Given that the core function of solder joints and pads is to achieve a reliable electrical connection between aluminum wires (conductors) and chip pins or other components, the main risk of defects at solder joints / pads lies in affecting the conductivity of the connected aluminum wires. For example, bridging defects can cause short circuits in adjacent aluminum wires; poor solder joints can cause broken aluminum wires. The most direct quantitative indicator for assessing the severity of such defects is measuring the distance between the defective area and the adjacent aluminum wires. The closer the distance, the higher the risk of short circuits or open circuits. Associating these defects with other structural types (such as chips) is not very meaningful for risk assessment.

[0089] Rule 2: If the defect type is scattered damage or chip contamination, then the target structure type is independent chip or non-independent chip.

[0090] Considering that the hazards of surface scratches (scratches, dents) mainly lie in the potential damage to the chip itself (such as silicon wafer cracks) or the destruction of the protective layer on the chip surface, it is necessary to assess the proximity of the surface scratch to the chip. Especially for non-independent chips, if the surface scratch is located in a narrow gap between densely packed chips, its hazard may be amplified (for example, a scratch may affect two chips simultaneously).

[0091] For chip contamination: contaminants directly affect the function of the substrate they adhere to. Therefore, it is necessary to determine whether the contaminant is attached to the chip (high risk) or only falls on an empty substrate (low risk). By associating with both individual and non-independent chips, the search algorithm will accurately find the distance between the defect and the nearest chip outline. If the distance is zero (i.e., they intersect), it can be identified as adhesive contamination; if there is a certain distance, its proximity can be quantified.

[0092] Specifically, the above rules can be implemented in the form of lookup tables, configuration, or hard-coded logic. Once a defective region is identified and its defect type (e.g., "solder joint anomaly") is determined, the target structure type requiring subsequent proximity search (in this example, "aluminum wire") is identified based on the aforementioned association rules. Then, the system performs the efficient search steps described above only on the hierarchical spatial index of "aluminum wire," calculating the distance from the defect to the nearest aluminum wire, without performing meaningless searches in the index of "chip."

[0093] The specific categories and association rules defined in this application's embodiments eliminate the need for blindly calculating the distance between defects and all types of components. Instead, targeted searches are performed based on the nature of the defects, avoiding a large amount of unnecessary calculations and further optimizing the overall processing time. For other types of circuit boards (such as flexible boards and power modules) or newly added defect types, those skilled in the art can follow the same "defect-component association" principle to define new structural types and association rules, giving this application's embodiments good adaptability and scalability.

[0094] In some embodiments, when the defect type is scratches or chip contamination, distance quantification information between the defect region and its neighboring normal components is determined based on the distance between the defect region and the adjacent positioning region, including:

[0095] Calculate the first shortest distance from the defect region to the candidate region retrieved from the independent chip data structure, and the second shortest distance to the candidate region retrieved from the non-independent chip data structure, respectively.

[0096] If the second shortest distance is less than the first shortest distance, then distance quantization information indicating the defect region's attachment to the non-independent chip is generated; or,

[0097] If the second shortest distance is greater than or equal to the first shortest distance, then distance quantification information is generated, which uses the first distance to characterize the proximity of the defect region to the independent chip.

[0098] In cases where a defect is associated with multiple target structure types (such as "independent chip regions" and "non-independent chip regions"), in order to synthesize the search results from different indexes and generate a more physically meaningful and engineering-judgment-valued quantitative description, in this embodiment of the application, for defect regions identified as "scattered damage" or "chip contamination," their proximity to both types of chip regions needs to be considered simultaneously. Specifically, the following parallel operations are performed:

[0099] Using the defective region as the query scope in the independent chip region index, an efficient nearest neighbor search with pruning is performed in a pre-built hierarchical spatial index of "independent chip regions" (such as an R-tree). The search ultimately outputs a candidate location region (i.e., the independent chip region closest to the defect) and the precise geometric distance between them, which is denoted as the first shortest distance D_indep.

[0100] Simultaneously, using the same defect area as the query range, the same nearest neighbor search algorithm is executed in the pre-built "non-independent chip region" hierarchical spatial index. This search outputs another candidate location region (i.e., the non-independent chip region closest to the defect) and the precise geometric distance between the two, which is denoted as the second shortest distance D_nondep.

[0101] After obtaining D_indep and D_nondep, compare the values ​​of D_indep and D_nondep.

[0102] If D_nondep < D_indep, it indicates that the defect area is closer to a certain "non-independent chip area" than to other "independent chip areas." Considering that in circuit board layouts, "non-independent chip areas" typically represent densely packed chip areas or complex modules, a defect (especially "scratches" or "chip contaminants") closest to such an area may actually be located in a shared gap between multiple densely packed chips, or it may be attached to one chip but identified as part of a "non-independent chip area" because its outline is connected to the outline of neighboring chips in the image. Therefore, the generated distance quantification information goes beyond simple distance values, adding morphological correlation descriptions. For example, the generated quantification information could be: "Defect (ID: XXX) is attached to / adjacent to a non-independent chip area, at a distance of D_nondep micrometers from its outline." This description clearly indicates to inspection personnel or downstream systems that the defect involves a densely packed chip area and may require special attention regarding its potential impact on multiple chips or the risk of blocking narrow heat dissipation channels.

[0103] Correspondingly, if D_nondep >= D_indep, it means that the distance from the defect region to the nearest "isolated chip region" is less than or equal to the distance to other "non-isolated chip regions". The most common case is that D_indep is significantly less than D_nondep, indicating that the defect is clearly close to an isolated chip. This defect mainly poses a risk to a single, isolated chip. Therefore, the distance quantification information generated in this case uses D_indep as the core metric. For example: "Defect (ID:123) is D_indep micrometers away from the nearest isolated chip region". If D_indep is zero, it can be clearly stated as "The defect is attached to the surface of an isolated chip". Thus, the threat level of a defect to a specific chip is clearly quantified through distance quantification information.

[0104] This application's embodiments transform simple distance values ​​into quantitative information that includes spatial context (whether it is in a chip-dense area), which greatly enhances the readability and engineering guidance of automatic detection reports.

[0105] In some embodiments, the target circuit board is located and defects are identified to obtain multiple location areas and the structural type of each location area, as well as at least one defect area and the defect type of each defect area, including:

[0106] A segmentation model based on a deep neural network is used to perform pixel-level semantic segmentation on the image of the target circuit board, and the probability distribution of each pixel in the image belonging to different component categories or defect types is obtained.

[0107] Based on the probability distribution, generate region contour information corresponding to aluminum wires, independent chips, non-independent chips, and different defect types;

[0108] Before constructing a multi-level tree index based on the relative positions of multiple minimum bounding rectangles, using the minimum bounding rectangle as the basic unit, the method also includes:

[0109] Area filtering is performed on the location area and the defect area respectively, and areas with an area smaller than the corresponding type area threshold are removed.

[0110] To achieve accurate identification of complex components and minute defects in circuit board images, this application employs a semantic segmentation model based on deep neural networks as a technique for identifying structural types and localization regions. The semantic segmentation model can be trained on a large number of labeled circuit board images to learn the visual features of different components and defects.

[0111] The input to the semantic segmentation model includes a high-resolution optical image (such as an RGB three-channel image) of the target circuit board.

[0112] The semantic segmentation model outputs a probability distribution map of the same size as the input image. For each pixel location (i, j) in the image, the model outputs a probability vector, where each dimension represents the probability that the pixel belongs to a predefined category. These categories include normal component structure types (aluminum wire area, standalone chip area, non-standalone chip area) and defect types (solder joint abnormality, pad contamination, surface defects, chip contamination, etc.).

[0113] Semantic segmentation models can employ encoder-decoder network architectures, such as U-Net and DeepLabv3+. The encoder (e.g., ResNet, MobileNet) is responsible for extracting multi-level features, while the decoder is responsible for upsampling the feature maps to the original image size and performing pixel-level classification.

[0114] Compared to traditional methods based on thresholding, edge detection, or template matching, the deep neural network model used in this application embodiment is more robust to changes in illumination, background noise, and the diversity of component shapes, and can achieve higher recognition accuracy, especially for small defects with low contrast and irregular shapes.

[0115] After obtaining the pixel-level probability distribution map, for each pixel, the category corresponding to the maximum value in its probability vector is selected as the predicted category of that pixel, thus generating a category label map. The category label map is analyzed, and spatially adjacent pixels (e.g., using 8-neighborhood connections) with the same category label are grouped together to form connected components. Each connected component corresponds to a candidate "location region" or "defect region". Finally, for each connected component, a contour tracing algorithm (such as the Suzuki-Abe algorithm) is used to extract its precise polygonal contour, thereby obtaining a preliminary set of contour information for aluminum wire regions, independent chip regions, non-independent chip regions, and various defect regions.

[0116] Specifically, after obtaining preliminary region contour information and before constructing the spatial index, this application introduces an important filtering step to eliminate the interference of noise and invalid regions on subsequent processing. During image acquisition, noise points or minute artifacts may be introduced, which may be misidentified by the model as extremely small regions. The model may produce low-confidence fragmented predictions for objects with blurred boundaries or extremely small dimensions, forming isolated regions with very small areas. Circuit boards may contain extremely small, non-functional process features (such as minute surface textures) that do not belong to the "components" or "defects" that require attention. If these small areas are allowed to enter subsequent processes without processing, they will pollute the spatial index, increase the number of index nodes, reduce search efficiency, and even lead to incorrect proximity relationships due to abnormal positions. Furthermore, as defect areas, they will generate numerous false alarms, reducing the practicality of the detection system.

[0117] One or more area filtering thresholds (Area_Threshold_Type) can be set for each structure type and each defect type. These thresholds can be determined based on prior knowledge (such as the design size of the smallest component, the minimum acceptable defect size) or statistical analysis of the training dataset. For example, the minimum area threshold for "aluminum wire" might be set to 50 pixels, and the threshold for "scattered damage" defects might be set to 10 pixels.

[0118] For each location region and defect region, calculate its contour area (in pixels or actual physical size). If the area of ​​the region is less than the preset area threshold corresponding to its type, the region is considered invalid noise or an object of no interest and is removed from the region set for subsequent processing.

[0119] This application employs deep neural network semantic segmentation to achieve pixel-level accurate parsing of complex circuit board images, providing reliable input for subsequent spatial relationship analysis. Through area filtering, a simple yet effective preprocessing technique, the set of location and defect regions is significantly purified.

[0120] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all the various non-contradictory solutions formed by the combinations are within the scope of protection of the embodiments of this application.

[0121] Based on the same inventive concept, this application also provides a circuit board defect detection device. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more circuit board defect detection device embodiments provided below can be found in the limitations of the circuit board defect detection method above, and will not be repeated here.

[0122] like Figure 3 As shown, this application embodiment provides a circuit board defect detection device 300, including:

[0123] The identification module 302 is used to locate and identify defects in the target circuit board, and obtain multiple positioning areas and the structural type of each positioning area, as well as at least one defect area and the defect type of each defect area; wherein, the positioning area represents the preset component structure on the circuit board.

[0124] Module 304 is used to construct a hierarchical spatial index for each structure type based on the spatial coordinates of all positioning regions under the structure type. In the hierarchical spatial index, multiple nodes are connected hierarchically, and the spatial range represented by a node is the union of the spatial ranges represented by the lower-level child nodes of the current node.

[0125] The determination module 306 is used to determine at least one target structure type associated with each defect area based on the association rules between defect type and structure type.

[0126] Search module 308 is used to search in the hierarchical spatial index corresponding to at least one target structure type according to the location information of the defect area, and obtain the neighboring positioning area that meets the preset distance condition with the defect area.

[0127] The quantization module 310 is used to determine the distance quantization information between the defective area and its neighboring normal components based on the distance between the defective area and the adjacent positioning area; the distance quantization information is used to evaluate the degree of impact of the defective area on the performance of the target circuit board.

[0128] In some embodiments, the hierarchical spatial index includes a multi-level tree index; regarding the construction of the hierarchical spatial index corresponding to each structure type based on the spatial coordinates of all positioning regions under the structure type, the construction module 304 is specifically used for:

[0129] For each structure type, the relative positional relationships of all positioning areas under the structure type are determined based on the spatial coordinates of all positioning areas under the structure type; the relative positional relationships include inclusion relationships and adjacency relationships.

[0130] For all positioning regions under the structure type, determine the minimum bounding rectangle of the outline of each positioning region;

[0131] Using the minimum bounding rectangle as the basic unit, a multi-level tree index is constructed based on the relative positional relationship between multiple minimum bounding rectangles; wherein, the spatial range represented by the non-leaf node in the multi-level tree index is the merged rectangle of the minimum bounding rectangles corresponding to all child nodes of the current non-leaf node.

[0132] In some embodiments, in order to obtain neighboring locations that satisfy a preset distance condition from the defect area by searching in the hierarchical spatial index corresponding to at least one target structure type based on the location information of the defect area, the search module 308 is specifically used for:

[0133] Using the outline of the defective area as the query range, the system traverses from the root node of the multi-level tree index until it reaches the leaf node, and determines the candidate location areas obtained by the traversal as the neighboring location areas that meet the preset distance from the defective area.

[0134] Specifically, when traversing to a leaf node, the geometric distance between the defect area and the location area corresponding to the current leaf node is calculated. If the geometric distance is less than a preset distance threshold, the preset distance threshold is updated to the geometric distance, and the location area corresponding to the current leaf node is determined as a candidate location area. When traversing to a non-leaf node, the minimum possible distance between the query range and the merged rectangle represented by the non-leaf node is calculated. If the minimum possible distance is less than a preset distance threshold, the child nodes of the current non-leaf node are traversed. If the minimum possible distance is not less than the preset distance threshold, the traversal of all child nodes of the current non-leaf node is stopped.

[0135] In some embodiments, normal components of the preset category include aluminum wires, stand-alone chips, and non-stand-alone chips; the defect types to which the defect area belongs include solder joint abnormalities, solder pad contamination, burrs, and chip contamination.

[0136] The association rules between defect type and structure type include: if the defect type is solder joint abnormality or pad contamination, the structure type is aluminum line area; if the defect type is scattered damage or chip contamination, the structure type is independent chip area and non-independent chip area.

[0137] In some embodiments, when the defect type is a scratch or chip contamination, the quantization module 310 is specifically used to determine the distance quantization information between the defect region and its neighboring normal components based on the distance between the defect region and the adjacent positioning region.

[0138] Calculate the first shortest distance from the defect region to the candidate region retrieved from the independent chip region data structure, and the second shortest distance to the candidate region retrieved from the non-independent chip region data structure, respectively.

[0139] If the second shortest distance is less than the first shortest distance, then distance quantization information indicating the defect region's attachment to the non-independent chip is generated; or,

[0140] If the second shortest distance is greater than or equal to the first shortest distance, then distance quantification information is generated, which uses the first distance to characterize the proximity of the defect region to the independent chip.

[0141] In some embodiments, in locating and identifying defects in the target circuit board to obtain multiple location areas and the structural type of each location area, and at least one defect area and the defect type of each defect area, the identification module 302 is specifically used for:

[0142] A segmentation model based on a deep neural network is used to perform pixel-level semantic segmentation on the image of the target circuit board, and the probability distribution of each pixel in the image belonging to different component categories or defect types is obtained.

[0143] Based on the probability distribution, the region contour information corresponding to aluminum wires, independent chips, non-independent chips, and different defect types is generated.

[0144] Each module in the aforementioned circuit board defect detection device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0145] In some embodiments, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements the steps in the aforementioned circuit board defect detection method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0146] Those skilled in the art will understand that Figure 4 The structures shown are merely block diagrams of some structures related to the embodiments of this application and do not constitute a limitation on the computer devices on which the embodiments of this application are applied. Specific computer devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0147] In some embodiments, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps included in any of the aforementioned circuit board defect detection method embodiments.

[0148] In some embodiments, such as Figure 5 As shown, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps included in any of the aforementioned circuit board defect detection method embodiments.

[0149] In some embodiments, a computer program product is provided, which includes a computer program that, when executed by a processor, implements the steps included in any of the aforementioned circuit board defect detection method embodiments.

[0150] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0151] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided by this invention may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided by this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0152] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above embodiments merely illustrate several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the embodiments of this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the appended claims.

Claims

1. A method for detecting defects in a circuit board, characterized in that, include: The target circuit board is located and defect identified to obtain multiple location areas and the structural type of each location area, as well as at least one defect area and the defect type of each defect area; wherein, the location area represents a preset component structure on the circuit board. For each structure type, a hierarchical spatial index is constructed based on the spatial coordinates of all the positioning regions under the structure type; wherein, multiple nodes in the hierarchical spatial index are connected hierarchically, and the spatial range represented by a node is the union of the spatial ranges represented by the lower-level child nodes of the current node; For each of the defect regions, at least one target structure type associated with the defect region is determined according to the association rules between defect type and structure type; Based on the location information of the defect area, a search is performed in the hierarchical spatial index corresponding to at least one target structure type to obtain a neighboring location area that meets the preset distance condition with the defect area. Based on the distance between the defective region and the adjacent positioning region, distance quantification information between the defective region and its adjacent normal components is determined; the distance quantification information is used to assess the degree of impact of the defective region on the performance of the target circuit board.

2. The method according to claim 1, characterized in that, The hierarchical spatial index includes a multi-level tree index; the construction of the hierarchical spatial index corresponding to each structure type, based on the spatial coordinates of all the positioning regions under that structure type, includes: For each structure type, the relative positional relationship of all the positioning areas under the structure type is determined based on the spatial coordinates of all the positioning areas under the structure type; the relative positional relationship includes inclusion relationship and adjacency relationship; For all positioning regions under the aforementioned structure type, determine the minimum bounding rectangle of the outline of each positioning region; Using the minimum bounding rectangle as the basic unit, the multi-level tree index is constructed based on the relative positional relationship between multiple minimum bounding rectangles; wherein, the spatial range represented by the non-leaf nodes in the multi-level tree index is the merged rectangle of the minimum bounding rectangles corresponding to all child nodes of the current non-leaf node.

3. The method according to claim 2, characterized in that, The step of searching in the hierarchical spatial index corresponding to the at least one target structure type according to the location information of the defect area to obtain the neighboring positioning area that meets the preset distance condition with respect to the defect area includes: Using the outline of the defective region as the query range, the multi-level tree index is traversed from the root node until the leaf node is reached. The candidate positioning regions obtained by the traversal are determined as the neighboring positioning regions that meet the preset distance with the defective region. Specifically, when traversing to a leaf node, the geometric distance between the defective region and the positioning region corresponding to the current leaf node is calculated; if the geometric distance is less than a preset distance threshold, the preset distance threshold is updated to the geometric distance, and the positioning region corresponding to the current leaf node is determined as the candidate positioning region; when traversing to a non-leaf node, the minimum possible distance between the query range and the merged rectangle represented by the non-leaf node is calculated; if the minimum possible distance is less than the preset distance threshold, the child nodes of the current non-leaf node are traversed; if the minimum possible distance is not less than the preset distance threshold, the traversal of all child nodes of the current non-leaf node is stopped.

4. The method according to claim 2, characterized in that, The preset categories of normal components include aluminum wires, independent chips, and non-independent chips; The defect types to which the defect area belongs include solder joint abnormalities, solder pad contamination, chip damage, and chip contamination. The association rules between defect type and structure type include: if the defect type is solder joint abnormality or solder pad contamination, then the structure type is aluminum wire area; If the defect type is a scratch or chip contamination, then the structure type is an independent chip area and a non-independent chip area.

5. The method according to claim 4, characterized in that, When the defect type is scratches or chip contamination, the step of determining the distance quantification information between the defect area and its neighboring normal components based on the distance between the defect area and the adjacent positioning area includes: Calculate the first shortest distance from the defect region to the candidate region retrieved from the independent chip region data structure, and the second shortest distance to the candidate region retrieved from the non-independent chip region data structure, respectively. If the second shortest distance is less than the first shortest distance, then distance quantization information indicating that the defect region is attached to a non-independent chip is generated; or, If the second shortest distance is greater than or equal to the first shortest distance, then distance quantification information is generated, which uses the first distance to characterize the proximity of the defective region to the independent chip.

6. The method according to claim 4, characterized in that, The step of locating and identifying defects in the target circuit board to obtain multiple location areas and the structural type of each location area, as well as at least one defect area and the defect type of each defect area, includes: A segmentation model based on a deep neural network is used to perform pixel-level semantic segmentation on the image of the target circuit board, and the probability distribution of each pixel in the image belonging to different component categories or defect types is obtained. Based on the probability distribution, generate the contour information of the aluminum wire, the independent chip, the non-independent chip, and the regions corresponding to different defect types; Before constructing the multi-level tree index based on the relative positional relationships between multiple minimum bounding rectangles using the minimum bounding rectangle as the basic unit, the method further includes: The location area and the defect area are filtered by area respectively to remove areas whose area is smaller than the corresponding type area threshold.

7. A circuit board defect detection device, characterized in that, include: The identification module is used to locate and identify defects in the target circuit board, thereby obtaining multiple positioning areas and the structural type to which each positioning area belongs, as well as at least one defect area and the defect type to which each defect area belongs; wherein, the positioning area represents a preset component structure on the circuit board. A construction module is used to construct a hierarchical spatial index corresponding to each structure type based on the spatial coordinates of all the positioning regions under the structure type; wherein, multiple nodes in the hierarchical spatial index are connected hierarchically, and the spatial range represented by a node is the union of the spatial ranges represented by the lower-level child nodes of the current node; The determination module is used to determine at least one target structure type associated with each defect region based on the association rules between defect type and structure type. The search module is used to search in the hierarchical spatial index corresponding to the at least one target structure type according to the location information of the defect area, and obtain the neighboring positioning area that meets the preset distance condition with the defect area. A quantization module is used to determine distance quantization information between the defective region and its neighboring normal components based on the distance between the defective region and the adjacent positioning region; the distance quantization information is used to evaluate the degree of impact of the defective region on the performance of the target circuit board.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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