Packaging structure and manufacturing method thereof

Abstract

The invention provides a packaging structure and a manufacturing method thereof. Specifically, on the basis of a substrate on which a first chip is packaged, an uncured viscous dielectric layer is adopted to bond a second chip and stack the chips layer by layer, and the stacked chips are fanned out and conducted to the substrate in the stacking process, so that an ultrathin chip substrate is replaced and solder ball welding is avoided in such a manner, and the cost is reduced. The manufacturing difficulty and the thickness of the whole product are reduced, and the electrical performance is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and in particular to a packaging structure and its fabrication method. Background Technology

[0002] Fan-out packaging technology uses a "mold encapsulation + redistribution layer (RDL)" to replace the traditional substrate, effectively improving power efficiency and thermal management performance. Integrated fan-out packaging (InFO-POP) offers high precision and speed, while fan-out panel-level packaging (FO-PLP) offers large size and low cost. These two technologies complement each other, supporting the thin, light, and heterogeneous integration requirements of mobile phones, smart wearables, automobiles, and high-performance computing (HPC). Both InFO-POP and FO-PLP require ultra-thin Dynamic Random Access Memory (DRAM) packaging substrates. However, ultra-thin DRAM packaging substrates are difficult to manufacture and have low yield rates. Furthermore, the connection between the upper and lower substrates via solder balls makes it difficult to reduce thickness, and the impedance inconsistency between the copper traces and solder balls is detrimental to signal integrity. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is to provide an encapsulation structure and a method for manufacturing the same.

[0004] In view of the above objectives, firstly, this disclosure provides a method for manufacturing an encapsulation structure, comprising: (a) A substrate is provided; the substrate includes a first outer circuit layer and a first chip embedded in the substrate; the first outer circuit layer is electrically connected to the first chip; (b) Laminating an uncured, adhesive first dielectric layer onto the first outer circuit layer; (c) Attach a second chip to the surface of the first dielectric layer; (d) Press the second chip into the first dielectric layer and expose the terminals of the second chip; (e) A second dielectric layer is laminated onto the surfaces of the first dielectric layer and the second chip, and the first dielectric layer and the second dielectric layer are cured. (f) A first circuit layer is formed on the second dielectric layer to conduct the terminals connecting the first outer circuit layer and the second chip; (g) Press an uncured, adhesive third dielectric layer onto the surface of the first circuit layer; (h) Attach a third chip to the surface of the third dielectric layer; (i) Press the third chip into the third dielectric layer and expose the terminals of the third chip; (j) A fourth dielectric layer is laminated onto the surfaces of the third dielectric layer and the third chip, and the third dielectric layer and the fourth dielectric layer are cured. (k) A second circuit layer is formed on the fourth dielectric layer to conduct the terminals connecting the first circuit layer and the third chip.

[0005] In some embodiments, step (d) and / or step (i) employ vacuum hot pressing technology.

[0006] In some embodiments, the first dielectric layer and the second dielectric layer are made of the same or different materials; and / or The third dielectric layer and the fourth dielectric layer may be made of the same or different materials.

[0007] In some embodiments, step (f) includes: (f1) A first blind via and a second blind via are formed in the first dielectric layer and the second dielectric layer; wherein the first blind via exposes the first outer circuit layer; and the second blind via exposes the terminals of the second chip; (f2) A first seed layer is formed on the first blind via, the second blind via, and the second dielectric layer; (f3) Electroplating and pattern transfer are performed on the first seed layer to form the first circuit layer.

[0008] In some embodiments, the materials of the first dielectric layer and the third dielectric layer are each independently selected from at least one of BT resin, semi-cured prepreg, ABF film, and epoxy resin.

[0009] In some embodiments, step (k) includes: (k1) A third blind via and a fourth blind via are formed in the third dielectric layer and the fourth dielectric layer; wherein the third blind via exposes the first circuit layer; and the fourth blind via exposes the terminals of the third chip; (k2) A second seed layer is formed on the third blind hole, the fourth blind hole and the fourth dielectric layer; (k3) Electroplating and pattern transfer are performed on the second seed layer to form the second circuit layer.

[0010] In some embodiments, the second chip and the third chip are memory chips.

[0011] Secondly, this disclosure provides a packaging structure, including a substrate, a first dielectric layer, a second dielectric layer, a second chip, a first circuit layer, a third dielectric layer, a fourth dielectric layer, a third chip, and a second circuit layer; wherein, the substrate includes a first outer circuit layer and a first chip; the first chip is embedded in the substrate and is electrically connected to the first outer circuit layer; the first dielectric layer and the second dielectric layer are disposed on the first outer circuit layer, and the second chip is embedded in the first dielectric layer and the second dielectric layer; the first circuit layer is disposed on the second dielectric layer; the first circuit layer is electrically connected to the terminals of the second chip and the first outer circuit layer; the third dielectric layer and the fourth dielectric layer are disposed on the first circuit layer, and the third chip is embedded in the third dielectric layer and the fourth dielectric layer; the second circuit layer is disposed on the fourth dielectric layer; the second circuit layer is electrically connected to the terminals of the third chip and the first circuit layer.

[0012] In some embodiments, the second chip and the third chip are memory chips.

[0013] In some embodiments, the first dielectric layer and the second dielectric layer are made of the same or different materials; and / or The third dielectric layer and the fourth dielectric layer may be made of the same or different materials.

[0014] As can be seen from the above, the packaging structure and manufacturing method provided in this disclosure use an uncured, adhesive dielectric layer to bond memory chips to a substrate on which the first chip has already been packaged, and stack memory chips layer by layer. During the stacking process, the memory chips are fanned out to conduct to the substrate. This method replaces the ultra-thin memory chip substrate and avoids the use of solder balls, which not only reduces the manufacturing difficulty and the overall product thickness, but also improves the electrical performance. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figures 1(a) to 1(m) show cross-sectional schematic diagrams of the intermediate structures of each step in a method for manufacturing an encapsulation structure according to an embodiment of the present disclosure; Figure 2 This diagram illustrates a packaging structure provided in an embodiment of the present disclosure. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. In the accompanying drawings, for better understanding and ease of description, the thickness and shape of some layers and regions may be exaggerated.

[0019] In related technologies, FO-PLP packaging involves soldering two separately packaged DRAM packaging substrates and a fan-out packaging substrate stacked on top of each other using solder balls. InFO-POP packaging also requires soldering the DRAM packaging substrate using solder balls. In other words, regardless of the packaging method, the technical problems described in the background art exist.

[0020] In view of this, the present disclosure provides a packaging structure and manufacturing method thereof, on the basis of a substrate that has already packaged the first chip, using an uncured adhesive dielectric layer to bond DRAM chips and stacking DRAM chips layer by layer, and fanning out the DRAM chips to conduct to the substrate during the stacking process, thereby replacing the ultra-thin DRAM substrate and avoiding the use of solder ball soldering, which not only reduces the manufacturing difficulty and the overall product thickness, but also improves the electrical performance.

[0021] In a first aspect, embodiments of this disclosure provide a method for manufacturing an encapsulation structure. Figures 1(a) to 1(m) show cross-sectional schematic diagrams of intermediate structures in each step of the method for manufacturing an encapsulation structure provided by embodiments of this disclosure. As shown in Figures 1(a) to 1(m), the manufacturing method includes: First, a substrate 100 is provided—step (a), as shown in Figure 1(a).

[0022] In some embodiments, the substrate 100 includes a first outer circuit layer 102 and a first chip 101 embedded in the substrate 100; the first outer circuit layer 102 is electrically connected to the first chip 101.

[0023] Optionally, the substrate 100 may further include a second outer circuit layer 103. The first outer circuit layer 102 and the second outer circuit layer 103 are electrically connected by interlayer metal pillars. Here, the first outer circuit layer 102 and the second outer circuit layer 103 are located on opposite sides of the substrate 100.

[0024] For example, the first chip 101 may be a power amplifier (PA) or a system chip, and this disclosure does not limit it.

[0025] It should be noted that the terminals of the first outer circuit layer 102 and the first chip 101 face opposite sides of the substrate 100. The first outer circuit layer 102 can be connected to the second outer circuit layer 103 through interlayer metal pillars, and the terminals of the first chip 101 can be connected through the second outer circuit layer 103.

[0026] Next, an uncured, sticky first dielectric layer 201 is laminated onto the first outer circuit layer 102—step (b), as shown in Figure 1(b).

[0027] Optionally, the material of the first dielectric layer 201 is selected from at least one of BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto build-up) film, and epoxy resin. It should be understood that the material of the first dielectric layer 201 is tacky when uncured and at room temperature (e.g., 25°C).

[0028] It should be noted that the first dielectric layer 201 can also be disposed on the second circuit layer 103, and this disclosure does not limit this.

[0029] Then, the second chip 301 is attached to the surface of the first dielectric layer 201—step (c), as shown in Figure 1(c).

[0030] Here, the second chip 301 is of a different type than the first chip 101. For example, the second chip 301 may be a memory chip, such as a dynamic random access memory.

[0031] Next, the second chip 301 is pressed into the first dielectric layer 201—step (d), as shown in Figure 1(d).

[0032] In some embodiments, step (d) employs vacuum hot pressing technology.

[0033] Then, the second dielectric layer 202 is pressed onto the surface of the first dielectric layer 201 and the second chip 301, and the first dielectric layer 201 and the second dielectric layer 202 are cured—step (e), as shown in FIG1 (e).

[0034] Optionally, the materials of the first dielectric layer 201 and the second dielectric layer 202 may be the same or different, and this disclosure does not limit this.

[0035] For example, the first dielectric layer 201 is made of epoxy resin, and the second dielectric layer 201 is made of ABF. Or, for example, both the first dielectric layer 201 and the second dielectric layer 201 are made of epoxy resin.

[0036] Next, a first circuit layer 401 is formed on the second dielectric layer 202 to conduct the terminals of the first outer circuit layer 102 and the second chip 301—step (f), as shown in Figures 1(f) to 1(g).

[0037] In some embodiments, step (f) includes: (f1) As shown in Figure 1(f), a first blind via 203 and a second blind via 204 are formed in the first dielectric layer 201 and the second dielectric layer 202; wherein, the first blind via 203 exposes the first outer circuit layer 102; and the second blind via 204 exposes the terminals of the second chip 301. Optionally, the first blind hole 203 and the second blind hole 204 can be prepared by laser drilling.

[0038] (f2) A first seed layer is formed on the first blind hole 203, the second blind hole 204, and the second dielectric layer 202; Here, the first seed layer is prepared by chemical plating or sputtering, and the first seed layer may include titanium, copper, titanium-tungsten alloy or a combination thereof; preferably, the first seed layer is prepared by sputtering titanium and copper.

[0039] (f3) As shown in Figure 1(g), the first line layer 401 is formed by electroplating and pattern transfer on the first seed layer.

[0040] Then, an uncured, viscous third dielectric layer 501 is pressed onto the surface of the first circuit layer 401—step (g), as shown in Figure 1 (h).

[0041] Optionally, the material of the third dielectric layer 501 is selected from at least one of BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto build-up) film, and epoxy resin. It should be understood that the material of the third dielectric layer 501 is tacky when uncured and at room temperature (e.g., 25°C).

[0042] Next, a third chip 601 is attached to the surface of the third dielectric layer 501—step (h), as shown in Figure 1(i).

[0043] In some embodiments, the third chip 601 is of a different type than the first chip 101. For example, the third chip 601 may be a memory chip, such as a dynamic random access memory (DRAM). It can be seen that the first chip 101 is of a different type than the second chip 301 and the third chip 601.

[0044] Then, the third chip 601 is pressed into the third dielectric layer 501—step (i), as shown in Figure 1(j).

[0045] Optionally, step (i) employs vacuum hot pressing technology.

[0046] Next, a fourth dielectric layer 502 is laminated onto the surfaces of the third dielectric layer 501 and the third chip 601, and the third dielectric layer 501 and the fourth dielectric layer 502 are cured—step (j), as shown in Figure 1 (k).

[0047] Here, similar to the first dielectric layer 201 and the second dielectric layer 202, the materials of the third dielectric layer 501 and the fourth dielectric layer 502 may be the same or different, and this disclosure does not limit this.

[0048] Finally, a second circuit layer 701 is formed on the fourth dielectric layer 502 to conduct the terminals connecting the first circuit layer 401 and the third chip 601—step (k), as shown in Figures 1(l) to 1(m).

[0049] In some embodiments, step (k) includes: (k1) As shown in Figure 1(l), a third blind via 503 and a fourth blind via 504 are formed in the third dielectric layer 501 and the fourth dielectric layer 502; wherein, the third blind via 503 exposes the first circuit layer 401; and the fourth blind via 504 exposes the terminals of the third chip 601. (k2) A second seed layer is formed on the third blind hole 503, the fourth blind hole 504 and the fourth dielectric layer 502; (k3) As shown in Figure 1 (m), the second line layer 701 is formed by electroplating and pattern transfer on the second seed layer.

[0050] Therefore, the packaging structure fabrication method provided in this disclosure eliminates the need for ultra-thin DEAM substrates and solder balls, reducing fabrication difficulty and cost. It also helps reduce the overall thickness of the packaging structure and decreases its size. Furthermore, the connection between multiple circuit layers does not require solder balls, resulting in similar impedance between the layers, which is beneficial for signal transmission and thus improves electrical performance.

[0051] Based on the same inventive concept, corresponding to any of the above-described embodiments, this disclosure also provides a packaging structure.

[0052] refer to Figure 2 The packaging structure includes: a substrate, a first dielectric layer 201, a second dielectric layer 202, a second chip 301, a first circuit layer 401, a third dielectric layer 501, a fourth dielectric layer 502, a third chip 601, and a second circuit layer 701; wherein, the substrate includes a first outer circuit layer 102 and a first chip 101; the first chip 101 is embedded in the substrate and is electrically connected to the first outer circuit layer 102; the first outer circuit layer 102 is provided with a first dielectric layer 201 and a second dielectric layer 202, and the second chip 301 is embedded in the first dielectric layer 201 and the second dielectric layer 202; the third chip 601 is embedded in the first dielectric layer 201 and the second dielectric layer 202; the fourth dielectric layer 501, a fifth dielectric layer 501, a sixth dielectric layer 601, and a seventh circuit layer 701; the fifth dielectric layer 601, a sixth dielectric layer 701, a seventh dielectric layer 701, a saturated layer 601, a saturated layer 701, a first dielectric layer 401, a third dielectric layer 501, a fourth dielectric layer 502, a fifth chip 601, a sixth dielectric layer 701, a saturated layer 601, a saturated layer 701, a saturated layer 601, a saturated layer 701, a saturated layer 601, a saturated layer 701, a saturated layer 701, a third dielectric layer 601, a saturated layer 701, a saturated layer 701, a saturated layer 701, a saturated layer 701, a saturated layer 801, a saturated layer 901, a saturated layer 101, a A first circuit layer 401 is disposed on the second dielectric layer 202; the first circuit layer 401 is electrically connected to the terminals of the second chip 301 and the first outer circuit layer 102; a third dielectric layer 501 and a fourth dielectric layer 502 are disposed on the first circuit layer 401, and the third chip 601 is embedded in the third dielectric layer 501 and the fourth dielectric layer 502; a second circuit layer 701 is disposed on the fourth dielectric layer 502; the second circuit layer 701 is electrically connected to the terminals of the third chip 601 and the first circuit layer 401; wherein, the type of the first chip 101 is different from the types of the second chip 301 and the third chip 601.

[0053] Optionally, the substrate further includes a second outer circuit layer 103, which is disposed on the side of the first chip 101 away from the first outer circuit layer 102.

[0054] In some embodiments, the second chip 301 and the third chip 601 are memory chips.

[0055] In some embodiments, the first dielectric layer 201 and the second dielectric layer 202 may be made of the same or different materials.

[0056] In some embodiments, the third dielectric layer 501 and the fourth dielectric layer 502 may be made of the same or different materials.

[0057] The packaging structure of the above embodiments is obtained by the corresponding manufacturing method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0058] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0059] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing an encapsulation structure, characterized in that, include: (a) A substrate is provided; the substrate includes a first outer circuit layer and a first chip embedded in the substrate; The first outer circuit layer is electrically connected to the first chip; (b) Laminating an uncured, adhesive first dielectric layer onto the first outer circuit layer; (c) Attach a second chip to the surface of the first dielectric layer; (d) Press the second chip into the first dielectric layer and expose the terminals of the second chip; (e) A second dielectric layer is laminated onto the surfaces of the first dielectric layer and the second chip, and the first dielectric layer and the second dielectric layer are cured. (f) A first circuit layer is formed on the second dielectric layer to conduct the terminals connecting the first outer circuit layer and the second chip; (g) Press an uncured, adhesive third dielectric layer onto the surface of the first circuit layer; (h) Attach a third chip to the surface of the third dielectric layer; (i) Press the third chip into the third dielectric layer and expose the terminals of the third chip; (j) A fourth dielectric layer is laminated onto the surfaces of the third dielectric layer and the third chip, and the third dielectric layer and the fourth dielectric layer are cured. (k) A second circuit layer is formed on the fourth dielectric layer to conduct the terminals connecting the first circuit layer and the third chip.

2. The manufacturing method according to claim 1, characterized in that, Step (d) and / or step (i) employ vacuum hot pressing technology.

3. The manufacturing method according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer may be made of the same or different materials; and / or The third dielectric layer and the fourth dielectric layer may be made of the same or different materials.

4. The manufacturing method according to claim 1, characterized in that, Step (f) includes: (f1) A first blind via and a second blind via are formed in the first dielectric layer and the second dielectric layer; wherein the first blind via exposes the first outer circuit layer; and the second blind via exposes the terminals of the second chip; (f2) A first seed layer is formed on the first blind via, the second blind via, and the second dielectric layer; (f3) Electroplating and pattern transfer are performed on the first seed layer to form the first circuit layer.

5. The manufacturing method according to claim 1, characterized in that, The materials of the first dielectric layer and the third dielectric layer are each independently selected from at least one of BT resin, semi-cured prepreg, ABF film, and epoxy resin.

6. The manufacturing method according to claim 1, characterized in that, Step (k) includes: (k1) A third blind via and a fourth blind via are formed in the third dielectric layer and the fourth dielectric layer; wherein the third blind via exposes the first circuit layer; and the fourth blind via exposes the terminals of the third chip; (k2) A second seed layer is formed on the third blind hole, the fourth blind hole and the fourth dielectric layer; (k3) Electroplating and pattern transfer are performed on the second seed layer to form the second circuit layer.

7. The manufacturing method according to claim 1, characterized in that, The second chip and the third chip are memory chips.

8. A packaging structure, characterized in that, The system includes a substrate, a first dielectric layer, a second dielectric layer, a second chip, a first circuit layer, a third dielectric layer, a fourth dielectric layer, a third chip, and a second circuit layer. The substrate includes a first outer circuit layer and a first chip. The first chip is embedded within the substrate and is electrically connected to the first outer circuit layer. The first outer circuit layer has the first dielectric layer and the second dielectric layer disposed thereon, and the second chip is embedded within the first dielectric layer and the second dielectric layer. The second dielectric layer has the first circuit layer disposed thereon. The first circuit layer is electrically connected to a terminal of the second chip and the first outer circuit layer. The first circuit layer has the third dielectric layer and the fourth dielectric layer disposed thereon, and the third chip is embedded within the third dielectric layer and the fourth dielectric layer. The fourth dielectric layer has the second circuit layer disposed thereon. The second circuit layer is electrically connected to a terminal of the third chip and the first circuit layer.

9. The packaging structure according to claim 8, characterized in that, The second chip and the third chip are memory chips.

10. The packaging structure according to claim 8, characterized in that, The first dielectric layer and the second dielectric layer may be made of the same or different materials; and / or The third dielectric layer and the fourth dielectric layer may be made of the same or different materials.

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