Register low-power-consumption management method and device for chip and chip

Abstract

The invention relates to the technical field of register configuration, and discloses a register low-power-consumption management method for a chip, the chip comprises a programmable flash memory module, a power-down domain register and an RAM module, and written module data of the programmable flash memory module is a loop data structure at least comprising a module configuration address; the method comprises the steps that when a chip enters a low-power-consumption field storage scene, hardware reads a module configuration address written into module data and reads module configuration data from power-down domain register hardware corresponding to the module configuration address; the module configuration address and the module configuration data are sequentially written into the RAM module; when the chip enters a low-power-consumption field recovery scene, hardware reads module configuration addresses and module configuration data which are sequentially adjacent to physical addresses in the RAM module; the write-in module configures data to the first target register module. According to the method, the availability of the power-down domain register after low-power-consumption wakeup can be ensured. The invention further discloses a register low-power-consumption management device for the chip and the chip.

Description

Technical Field

[0001] This application relates to the field of register configuration technology, such as a register low-power management method and apparatus for chips, and chips. Background Technology

[0002] Currently, when a chip enters low-power mode, some modules undergo power-down processing to reduce power consumption. The register configuration values ​​of these modules are reset to their reset values ​​upon power loss. When the chip exits low-power mode, software reconfiguration of the register modules is required to restore functionality as before the power loss. Because the register configurations of these modules may have timing requirements, the RETEN register method cannot be used for low-power context recovery.

[0003] To achieve low-power field recovery, a software solution is employed. Before the chip enters low-power mode, the software determines the configuration address and stores the configuration data of the register module corresponding to the configuration address in the RAM (Random Access Memory) module. After the chip exits low-power mode, the software reads the configuration data from the RAM module and configures it in the corresponding register module in one go. If the register module configuration has timing requirements, a delay can be set in software to meet the actual register configuration needs.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: The software solutions employed in these technologies rely on the CPU (Central Processing Unit) for execution. When the chip wakes up from low power, it needs to perform urgent / critical tasks such as interrupts or wake-up events, making it impossible to restore the functionality of the power-down module immediately, resulting in the module being unavailable during this period.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a register low-power management method, apparatus, and chip for chips, thereby eliminating the strong dependence on software under low-power management and ensuring the availability of power-down domain registers after low-power wake-up.

[0008] In some embodiments, the chip includes a programmable flash memory module, a power-down domain register, and a RAM module. The module data to be written to the programmable flash memory module is a circular data structure containing at least a module configuration address. The power-down domain register includes at least one register module. The low-power management method includes: when the chip enters a low-power field-saving scenario, the hardware reads the module configuration address from the module data to be written and reads the module configuration data from the power-down domain register corresponding to the module configuration address; sequentially writes the module configuration address and the module configuration data to the random access memory (RAM) module; when the chip enters a low-power field-recovery scenario, the hardware reads the module configuration addresses and module configuration data that are sequentially adjacent in physical address in the RAM module; and writes the module configuration data to a first target register module; wherein, the first target register module is the register module in the power-down domain register corresponding to the module configuration address.

[0009] In some embodiments, the cyclic data structure further includes a module configuration interval; the low-power management method further includes: when the chip enters a low-power field-saving scenario, the hardware reads the module configuration address written into the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address, and then reads the module configuration interval from the programmable flash memory module that is in the same cyclic data structure as the module configuration address; after sequentially writing the module configuration address and module configuration data to the RAM module, and after waiting for the module configuration interval, the hardware again reads the module configuration address of the next cyclic data structure in the programmable flash memory module and reads the module configuration data; and then sequentially writes the module configuration address and module configuration data of the next cyclic data structure to the RAM module.

[0010] In some embodiments, the low-power management method further includes: when the chip enters a low-power field saving scenario, writing the module configuration address and module configuration data to the RAM module in sequence, and writing the module configuration interval to the RAM module before waiting for the module configuration interval.

[0011] In some embodiments, the chip further includes a PMU module; hardware reading of module configuration addresses and module configuration data that are sequentially adjacent in physical address in RAM module includes: hardware reading of module configuration addresses and module configuration data that are sequentially adjacent in physical address in RAM module through PMU module.

[0012] In some embodiments, the cyclic data structure further includes a module configuration interval, which is first written to the programmable flash memory module by the chip during wafer testing; the low-power management method further includes: when the chip enters a low-power field recovery scenario, while the hardware reads the module configuration addresses and module configuration data that are sequentially adjacent to the physical addresses in the RAM module, the hardware reads the module configuration interval that is adjacent to the physical address of the module configuration data in the RAM module; after writing the module configuration data to the first target register module, after waiting for the module configuration interval, the hardware reads the module configuration addresses, module configuration data, and module configuration interval that are sequentially adjacent to the physical addresses in the RAM module again; based on the module configuration address read again, the second target register module in the power domain register is determined; and the module configuration data that is adjacent to the physical address of the module configuration address read again is written to the second target register module.

[0013] In some embodiments, the circular data structure further includes a terminator; the low-power management method further includes: after writing the module configuration address and module configuration data to the RAM module in sequence, and when the terminator is read from the hardware in the written module data, the low-power field saving of the register is completed.

[0014] In some embodiments, the low-power management method further includes: when the chip enters a low-power field recovery scenario, after writing module configuration data to the first target register module, and after the end symbol is read from the written module data, completing the low-power field recovery of the register.

[0015] In some embodiments, the low-power management device includes a processor and a memory storing program instructions, the processor being configured to execute, when running the program instructions, a register low-power management method for a chip as described above.

[0016] In some embodiments, the chip includes: a chip body including a RAM module and a power-down domain register, the power-down domain register including at least one register module; a programmable flash memory module on which module data is written as a circular data structure containing at least a module configuration address; and a register low-power management device for the chip as described above, mounted on the chip body.

[0017] In some embodiments, it further includes: a PMU module, installed on the chip body, electrically connected to the register low-power management device for the chip, and configured to perform low-power field recovery.

[0018] The register low-power management method, apparatus, and chip for chips provided in this disclosure can achieve the following technical effects: When the chip enters a low-power field saving scenario, the chip uses hardware to move the register module address (i.e., module configuration address) and register configuration data (module configuration data) from the power-down register to the RAM module for storage. Data stored in the RAM module is not lost during low-power field saving. When the chip enters a low-power field recovery scenario, the chip uses hardware to obtain the register module address to lock the register module, and moves the register configuration data from the RAM module and inserts it into the locked register module, thus restoring the register module to its state before low-power field saving. In summary, this application implements low-power field saving and low-power field recovery of registers through hardware, eliminating the strong dependence on software under low-power management. This allows the chip to immediately restore the functionality of the power-down register after low-power wake-up, ensuring the availability of the power-down register after low-power wake-up.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the hardware structure of the chip provided in the embodiments of this disclosure; Figure 2(a) is a schematic diagram of module data being written into a programmable flash memory module provided in an embodiment of this disclosure; Figure 2(b) is a schematic diagram of module data being written into another programmable flash memory module provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a register low-power management method for a chip provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another register low-power management method for a chip provided in this disclosure embodiment; Figure 5 This is a schematic diagram of another register low-power management method for a chip provided in this disclosure embodiment; Figure 6 This is a schematic diagram of another register low-power management method for a chip provided in this disclosure embodiment; Figure 7 This is a schematic diagram of another register low-power management method for a chip provided in this disclosure embodiment; Figure 8(a) is a schematic diagram of the application of the chip in a low-power field storage scenario provided in the embodiments of this disclosure; Figure 8(b) is a schematic diagram illustrating the application of the chip in a low-power field recovery scenario provided in this embodiment of the present disclosure; Figure 9(a) is a schematic diagram of the hardware state machine provided in an embodiment of this disclosure; Figure 9(b) is a schematic diagram of the software state machine process in the related technology; Figure 10 This is a schematic diagram of a register low-power management device for a chip provided in an embodiment of this disclosure. Detailed Implementation

[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] Unless otherwise stated, the term "multiple" means two or more.

[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0027] Combination Figure 1 As shown, this embodiment of the present disclosure provides a chip 10, including a programmable flash memory module 101, a power-down domain register 102, and a RAM module 103.

[0028] The write-to-module data of the programmable flash memory module 101 is a circular data structure containing at least the module configuration address. As shown in Figure 2(a), the programmable flash memory module 101 is a Flash module, and the write-to-module data of the Flash module is a circular data structure containing at least module configuration address 1#, module configuration address 2#, and module configuration address 3#. The module configuration address is used to indicate the register module for low-power field saving timing and / or low-power field recovery. The module configuration address is first written to the programmable flash memory module during chip probing (wafer testing). It should be noted that after the module configuration address is first written, it can be flexibly configured according to the register configuration requirements of the power-down domain register. Flexible configuration includes, but is not limited to, modifying, adding, and reducing the module configuration address. Here, after the chip is fabricated, the registers that need to save the field can be adjusted by modifying the write-to-module data in the programmable flash memory module, providing high configuration flexibility. This not only improves the efficiency of low-power field recovery but also reduces software complexity and improves the overall chip performance.

[0029] RAM module 103 enables the RETEN function in low-power field save scenario. RAM module 103 is configured to store data read by programmable flash memory module 101 from storage chip 10 in low-power field save / low-power field restore scenario.

[0030] Optionally, the power-down domain register 102 includes at least one register module. Here, the register module included in the power-down domain register 102 is a module belonging to the power-down domain. The register module's configuration is lost after the chip enters a low-power field save scenario. After the chip enters a low-power field restore scenario, the register module's configuration is restored to its default configuration.

[0031] Combination Figure 3 As shown, this disclosure provides a register low-power management method for a chip, including: S01, when the chip enters a low-power field save scenario, the chip hardware reads the module configuration address written to the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address.

[0032] S02, the chip sequentially writes the module configuration address and module configuration data to the RAM module.

[0033] In this step, the chip sequentially writes the module configuration address and module configuration data to the RAM module, including: the chip writing the module configuration address to the RAM module; and after writing the module configuration address to the RAM module, writing the module configuration data to the RAM module.

[0034] S03, when the chip enters a low-power field recovery scenario, the chip hardware reads the module configuration addresses and module configuration data that are sequentially adjacent in the physical address in the RAM module.

[0035] S04, the chip writes module configuration data to the first target register module. The first target register module is the register module in the power-down domain register corresponding to the module configuration address.

[0036] The low-power register management method for chips provided in this disclosure involves the following steps when the chip enters a low-power field saving scenario: The chip hardware reads the module configuration address from the programmable flash memory module where module data has been written, and reads the module configuration data from its corresponding power-down domain register. Then, it sequentially writes the module configuration address and module configuration data to the RAM module. This hardware-based transfer of the register module address (i.e., module configuration address) and register configuration data (module configuration data) from the power-down domain register to the RAM module for storage. Since the RAM module is configured in a RETEN state during the low-power field saving scenario, the data stored in the RAM module during this scenario is not lost. When the chip enters a low-power field recovery scenario, the chip hardware reads the sequentially adjacent module configuration addresses and module configuration data from the RAM module, writes the module configuration data to the first target register module, and obtains the register module address to lock the register module. It also moves the register configuration data from the RAM module and inserts it into the locked register module, restoring the register module to its state before the low-power field saving.

[0037] In summary, the embodiments of this disclosure implement low-power field saving and low-power field recovery of registers through hardware, eliminating the strong dependence on software under low-power management, so that the chip can restore the function of the power-down register as soon as possible after waking up from low power, ensuring the availability of the power-down register after waking up from low power.

[0038] It should be noted that, in addition to the hardware reading of the module configuration address from the written module data and the module configuration data from the corresponding power-down register when the chip enters a low-power field saving scenario, and then writing the module configuration address and module configuration data sequentially to the RAM module, the chip can also, during the idle period after initial power-on, read the module configuration address from the written module data and the module configuration data from the corresponding power-down register, and then write the module configuration address and module configuration data sequentially to the RAM module. This way, the low-power field saving process does not go through the programmable flash memory module, which helps improve the efficiency of low-power field saving.

[0039] Optionally, the cyclic data structure also includes a module configuration interval. The module configuration interval is used to construct the low-power field-saving timing and / or low-power field-recovery timing. The module configuration interval is first written to the programmable flash memory module during chip CP (Construction Processing). It should be noted that after the module configuration interval is first written, it can be flexibly configured according to the register configuration requirements of the power-down domain registers. This flexible configuration includes, but is not limited to, modifying the module configuration interval. Here, after chip fabrication, the registers that need to save the field and the configuration timing can be adjusted by modifying the written module data in the programmable flash memory module, providing high configuration flexibility. This not only improves the efficiency of low-power field recovery but also reduces software complexity and improves the overall chip performance.

[0040] In some optional embodiments, as shown in FIG2(b), the programmable flash memory module 101 is a Flash module, and the module data written to the Flash module is a cyclic data structure that includes at least module configuration address 1# and module configuration interval 1#, module configuration address 2# and module configuration interval 2#, and module configuration address 3# and module configuration interval 3#.

[0041] Combination Figure 4 As shown in the embodiments of this disclosure, a low-power register management method for a chip is also provided, including: S11, when the chip enters a low-power field save scenario, the hardware reads the module configuration address written to the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address.

[0042] S12, the chip reads the module configuration interval from the programmable flash memory module hardware, which is in the same circular data structure as the module configuration address.

[0043] S13, the chip sequentially writes the module configuration address and module configuration data to the RAM module.

[0044] S14, after waiting for the module configuration interval, the chip again reads the module configuration address of the next cycle data structure in the programmable flash memory module and reads the module configuration data.

[0045] S15, the chip sequentially writes the module configuration address and module configuration data of the next cycle data structure to the RAM module.

[0046] The low-power register management method for chips provided in this disclosure involves the chip, when entering a low-power field saving scenario, moving the register module addresses and register configuration data in the power-down registers to the RAM module for storage one by one according to the module configuration intervals read from the same cyclic data structure. Data stored in the RAM module is not lost during the low-power field saving scenario. When entering a low-power field recovery scenario, the chip, through hardware, moves the read register module addresses and register configuration data from the RAM module one by one according to the module configuration intervals and inserts them into the register modules in the power-down registers, restoring the register modules to their state before low-power field saving. Thus, this disclosure implements low-power field saving and low-power field recovery of registers through hardware, eliminating the strong dependence on software under low-power management and ensuring the availability of the power-down registers after low-power wake-up. Furthermore, this disclosure can also implement low-power field recovery of register configuration data according to the timing requirements of low-power register management. While ensuring the availability of the power-down registers after low-power wake-up, it also satisfies the timing requirements of register configuration through hardware, which helps improve the reliability of low-power wake-up of the power-down registers.

[0047] Optionally, the register low-power management method for the chip further includes: when the chip enters a low-power field saving scenario, after the chip sequentially writes the module configuration address and module configuration data to the RAM module, and before the chip waits for the module configuration interval, writing the module configuration interval to the RAM module.

[0048] Thus, the embodiments of this disclosure can also realize the low-power field recovery of register configuration data in accordance with the timing requirements of register low-power management during the register low-power field recovery phase, so as to take into account both the availability after the low-power wake-up of the power-down domain register and the timing requirements of register low-power management.

[0049] Optionally, combined Figure 1 As shown, chip 10 also includes a PMU (Power Management Unit) module 104. The PMU module 104 is used for low-power management of the register module.

[0050] In some optional embodiments, when chip 10 enters a low-power field saving scenario, the CPU stops running; at the same time, PMU module 104 executes a hardware state machine; wherein, executing the hardware state machine includes sequentially executing low-power field saving and partial / all register module power-down, entering low power, exiting low power, partial / all register module power-on, low-power field restoration, and CPU startup.

[0051] Figure 9(b) is a schematic diagram of the software state machine flow in the related technology. Figure 9(a) is a schematic diagram of the hardware state machine flow. Combining Figures 9(a) and 9(b), in the hardware state machine flow, low-power context recovery occurs earlier than CPU startup. In the software state machine flow, low-power context recovery occurs later than CPU startup. This shows that the hardware-based low-power context recovery occurs earlier than the software-based low-power context recovery, effectively shortening the time for register low-power context recovery.

[0052] The chip hardware reads the module configuration addresses and module configuration data from the RAM module, which are sequentially adjacent in physical address, including: The chip reads the module configuration addresses and module configuration data that are sequentially adjacent to each other in the RAM module through the PMU module hardware.

[0053] Thus, in this embodiment of the present disclosure, the chip can read the module configuration address and module configuration data that are sequentially adjacent to the physical address in the RAM module through its configured PMU module, so as to move the data in the RAM module out and configure it into the register module in the power-down domain register, so that the register module is restored to the register state before low-power field saving.

[0054] Combination Figure 5 As shown in the embodiments of this disclosure, a low-power register management method for a chip is also provided, including: S21, when the chip enters a low-power field save scenario, the chip hardware reads the module configuration address written into the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address.

[0055] S22, the chip sequentially writes the module configuration address and module configuration data to the RAM module.

[0056] S23, when the chip enters a low-power field recovery scenario, the chip hardware reads the module configuration addresses and module configuration data that are sequentially adjacent to the physical addresses in the RAM module, and the hardware reads the module configuration interval that is adjacent to the physical address of the module configuration data in the RAM module.

[0057] S24, the chip writes module configuration data to the first target register module. The first target register module is the register module in the power-down domain register corresponding to the module configuration address.

[0058] S25, after waiting for the module configuration interval, the chip again reads the module configuration addresses, module configuration data, and module configuration intervals that are sequentially adjacent to the physical addresses in the RAM module.

[0059] S26, the chip determines the second target register module in the power domain register based on the module configuration address read again.

[0060] S27, the chip writes module configuration data adjacent to the physical address of the module configuration address that is read again to the second target register module.

[0061] The low-power register management method for chips provided in this disclosure involves the chip, when entering a low-power field saving scenario, reading the sequentially adjacent module configuration addresses, configuration data, and configuration intervals from the RAM module via hardware. The register module addresses and configuration data in the power-down register are then moved to the RAM module for storage according to the configuration intervals. Data stored in the RAM module is not lost during the low-power field saving scenario. When the chip enters a low-power field recovery scenario, the chip, via hardware, moves the read register module addresses and configuration data from the RAM module one by one according to the configuration intervals and inserts them into the register modules in the power-down register, restoring the register modules to their state before the low-power field saving. Thus, this disclosure implements low-power field saving and low-power field recovery of registers via hardware, ensuring the availability of the power-down registers after low-power wake-up. Meanwhile, the embodiments of this disclosure can also realize low-power field saving and low-power field recovery of register module address and register configuration data in accordance with the timing requirements of register low-power management. While ensuring the availability of the low-power wake-up of the power-down domain register, it also meets the timing of register configuration through hardware, which is conducive to improving the reliability of the low-power wake-up of the power-down domain register.

[0062] Optionally, the circular data structure also includes a terminator. The terminator indicates that the written module data is the last data, and the terminator is data in a custom format. The custom format can be flexibly set according to the register configuration requirements of the register module. As an example, the terminator is 0x5a5a5a5a. Furthermore, the terminator is initially written to the programmable flash module by the chip CP. After the terminator is initially written, it can be flexibly configured according to the register configuration requirements of the register module. Here, flexible configuration includes, but is not limited to, modifying the terminator format or deleting the terminator. In some optional embodiments, referring to Figure 2(b), the programmable flash module 101 is a Flash module, and the module data written to the Flash module is a circular data structure that includes at least module configuration address 1# and module configuration interval 1#, module configuration address 2# and module configuration interval 2#, module configuration address 3# and module configuration interval 3#, and a terminator.

[0063] Combination Figure 6 As shown in the embodiments of this disclosure, a low-power register management method for a chip is also provided, including: S31, when the chip enters a low-power field save scenario, the chip hardware reads the module configuration address written to the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address.

[0064] S32, the chip sequentially writes the module configuration address and module configuration data to the RAM module.

[0065] S33, when the end symbol is read from the data to be written to the module by the hardware, the chip writes the end symbol to the RAM module to complete the low-power field saving of the register.

[0066] S34, when the chip enters a low-power field recovery scenario, the chip hardware reads the module configuration addresses and module configuration data that are sequentially adjacent in physical address in the RAM module.

[0067] S35, the chip writes module configuration data to the first target register module. The first target register module is the register module in the power-down domain register corresponding to the module configuration address.

[0068] The low-power register management method for chips provided in this disclosure involves the following steps when the chip enters a low-power field saving scenario: The chip hardware reads the module configuration address from the programmable flash memory module containing the written module data and reads the module configuration data from its corresponding power-down domain register. Then, it sequentially writes the module configuration address and module configuration data to the RAM module, thereby moving the register module address and register configuration data from the power-down domain register to the RAM module for storage via hardware. When the chip reads an end-of-file marker from the written module data, it indicates that the end of the written module data has been read. At this point, the end-of-file marker is written to the RAM module to complete the low-power field saving of the register. Data stored in the RAM module is not lost during the low-power field saving scenario. When the chip enters a low-power field recovery scenario, the chip hardware reads the sequentially adjacent module configuration addresses and module configuration data from the RAM module, writes the module configuration data to the first target register module, and obtains the register module address to lock the register module via hardware. It also moves the register configuration data from the RAM module and inserts it into the locked register module, restoring the register module to its state before the low-power field saving. Thus, this embodiment of the disclosure implements low-power state saving and low-power state restoration of registers through hardware, ensuring the availability of power-down domain registers after low-power wake-up. Simultaneously, this embodiment of the disclosure can also complete low-power state saving and low-power state restoration of register module addresses and register configuration data according to the timing requirements and end markers of register low-power management. While ensuring the availability of power-down domain registers after low-power wake-up, it also satisfies the timing requirements of register configuration through hardware, which helps improve the reliability of low-power wake-up of power-down domain registers.

[0069] Combination Figure 7 As shown in the embodiments of this disclosure, a low-power register management method for a chip is also provided, including: S41, when the chip enters a low-power field save scenario, the chip hardware reads the module configuration address written into the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address.

[0070] S42, the chip sequentially writes the module configuration address and module configuration data to the RAM module.

[0071] S43, if the end character is read from the hardware in the data to be written to the module, the chip writes the end character to the RAM module to complete the low-power field saving of the register.

[0072] S44, when the chip enters a low-power field recovery scenario, the chip hardware reads the module configuration addresses and module configuration data that are sequentially adjacent in physical address in the RAM module.

[0073] S45, the chip writes module configuration data to the first target register module. The first target register module is the register module in the power-down domain register corresponding to the module configuration address.

[0074] S46, when the end-of-phase character is read from the hardware in the data written to the module, the chip performs a low-power field recovery of the registers.

[0075] The low-power register management method for chips provided in this disclosure involves the following steps: When the chip enters a low-power field-saving scenario, the chip hardware reads the module configuration address from the programmable flash memory module containing the written module data and reads the module configuration data from its corresponding power-down domain register. Then, it sequentially writes the module configuration address and module configuration data to the RAM module, thereby moving the register module address and register configuration data from the power-down domain register to the RAM module for storage via hardware. Data stored in the RAM module is not lost during the low-power field-saving scenario. When the chip enters a low-power field-recovery scenario, the chip hardware reads the sequentially adjacent module configuration addresses and module configuration data from the RAM module and writes the module configuration data to the first target register module. This allows the chip hardware to obtain the register module address to lock the register module and to move the register configuration data from the RAM module and insert it into the locked register module, restoring the register module to its state before the low-power field-saving. Thus, this disclosure implements low-power field-saving and low-power field-recovery of registers via hardware, ensuring the availability of the power-down domain register after low-power wake-up. Meanwhile, the embodiments of this disclosure can also complete the low-power field saving and low-power field restoration of register module address and register configuration data according to the timing requirements and end marker of register low-power management. While ensuring the availability of the low-power wake-up of the power-down domain register, it also meets the timing of register configuration through hardware, which is conducive to improving the reliability of the low-power wake-up of the power-down domain register.

[0076] In practical applications, as shown in Figure 8(a), the power-down domain register includes register module A, register module B, and register module C. When the chip enters a low-power state and saves its state, the configuration of each register module in the power-down domain register is lost. However, when the chip exits low power (i.e., enters a low-power state recovery state), each register module in the power-down domain register is restored to its default configuration.

[0077] Before the chip enters low-power field saving, the chip configures the power-down registers via software as follows: register module A (address 0x40001000) is configured with register module data 0xA, register module B (address 0x40002000) is configured with register module data 0xB, and register module C (address 0x40003000) is configured with register module data 0xC. Furthermore, the register configuration requirements for the power-down registers include configuring register module A first, waiting 10 system clock cycles before configuring register module B, and then waiting another 10 system clock cycles before configuring register module C.

[0078] Register low-power management methods for chips include register low-power context saving and register low-power context restoration procedures.

[0079] The specific steps for the low-power register context saving process are as follows: S101: Software configuration enables low power consumption, CPU stops running. PMU module state machine begins transitioning.

[0080] S102: When the PMU module jumps to the low-power field save state, the PMU low-power field save function is started.

[0081] S103: The PMU module first reads the first module configuration address 0x40001000 from the Flash module's address 0x14000000, and then writes it to the RAM module's address 0x20000000.

[0082] The PMU module then reads the data (0xA) corresponding to address 0x40001000 and writes 0xA to address 0x20000004 of the RAM module.

[0083] The address 0x14000000 of the Flash module and the address 0x20000000 of the RAM module are both set by the chip's hardware circuitry.

[0084] S104: The PMU module then reads the module configuration interval from address 0x14000004 of the Flash module and writes it to address 0x20000008 of the RAM module.

[0085] At this point, the low-power field saving of register module A is complete.

[0086] The PMU module continues to perform low-power field saving of register module B and register module C in the manner described above.

[0087] S105: The PMU module reads address 0x14000018 of the Flash module, obtains the end character, and writes it to address 0x20000024 of the RAM module to complete the low-power field saving of the power-down domain register.

[0088] The specific steps for the register low-power context recovery process are as follows: S201: The PMU module reads the module configuration address 0x40001000, module configuration data 0xA, and module configuration interval from the RAM module's addresses 0x20000000 to 0x20000008 in one go, and writes them into the register module A corresponding to the addresses 0xA to 0x40001000.

[0089] S202: The PMU module reads the module configuration address 0x40002000, module configuration data 0xB, and module configuration interval from addresses 0x2000000C to 0x20000014 of the RAM module in one go, and writes them into register module B corresponding to addresses 0xB to 0x40002000.

[0090] S203: The PMU module reads the module configuration address 0x40003000, module configuration data 0xC, and module configuration interval from the RAM module's addresses 0x20000018 to 0x20000020 in one go, and writes them into the register module B corresponding to the addresses 0xC to 0x40003000.

[0091] S204: After the PMU module reads the end symbol from the RAM module, it completes the low-power field recovery of the power-down domain register.

[0092] Combination Figure 10 As shown, this disclosure provides a register low-power management device 70 for a chip, including a processor 700 and a memory 701. Optionally, the device 70 may further include a communication interface 702 and a bus 703. The processor 700, communication interface 702, and memory 701 can communicate with each other via the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call logical instructions in the memory 701 to execute the register low-power management method for the chip described in the above embodiment.

[0093] Furthermore, the logic instructions in the aforementioned memory 101 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0094] The memory 101, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 100 executes functional applications and data processing by running the program instructions / modules stored in the memory 101, thereby implementing the register low-power management method for the chip in the above embodiments.

[0095] The memory 101 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 101 may include high-speed random access memory and may also include non-volatile memory.

[0096] This disclosure provides a chip, including a chip body, a programmable flash memory module, and a register low-power management device 70 for the chip as described above. The chip body includes a RAM module and a power-down domain register, the power-down domain register including at least one register module. The programmable flash memory module is written with module data in a circular data structure containing at least a module configuration address. The register low-power management device 70 for the chip is mounted on the chip body. The mounting relationship described herein is not limited to placement within the chip body, but also includes mounting connections with other components of the chip, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the register low-power management device 70 for the chip can be adapted to feasible chip bodies to achieve other feasible embodiments.

[0097] Optionally, the chip also includes a PMU module. The PMU module, mounted on the chip body, is electrically connected to the register low-power management device used by the chip and is configured to perform low-power field recovery.

[0098] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the aforementioned register low-power management method for a chip.

[0099] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0100] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0101] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A low-power register management method for a chip, characterized in that, The chip includes a programmable flash memory module, a power-down register, and a random access memory (RAM) module. The data written to the programmable flash memory module is a circular data structure containing at least the module configuration address. The power-down register includes at least one register module. Low-power management methods include: When the chip enters a low-power field save scenario, the hardware reads the module configuration address written into the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address. Write the module configuration address and module configuration data to the RAM module sequentially; When the chip enters a low-power field recovery scenario, the hardware reads the module configuration addresses and module configuration data that are sequentially adjacent in physical address in the RAM module; Write the module configuration data to the first target register module; wherein, the first target register module is the register module in the power-down domain register that corresponds to the module configuration address.

2. The register low-power management method according to claim 1, characterized in that, The circular data structure also includes module configuration intervals; low-power management methods also include: When the chip enters a low-power field save scenario, the hardware reads the module configuration address written to the module data and reads the module configuration data from the power-down domain register corresponding to the module configuration address. Then, the hardware reads the module configuration interval from the programmable flash memory module which is in the same cyclic data structure as the module configuration address. After writing the module configuration address and module configuration data to the RAM module in sequence, and after waiting for the module configuration interval, the module configuration address of the next cycle data structure in the programmable flash memory module is read again by hardware and the module configuration data is read. The module configuration address and module configuration data of the next loop data structure are written to the RAM module in sequence.

3. The register low-power management method according to claim 2, characterized in that, Low-power management methods also include: When the chip enters a low-power field save scenario, after writing the module configuration address and module configuration data to the RAM module in sequence, and before waiting for the module configuration interval, the module configuration interval is written to the RAM module.

4. The register low-power management method according to claim 1, characterized in that, The chip also includes a power management unit (PMU) module; The hardware reads the module configuration addresses and module configuration data from the RAM module, which are sequentially adjacent in physical address, including: The PMU module reads the module configuration addresses and module configuration data from the RAM module, which are located at consecutive physical addresses.

5. The register low-power management method according to claim 1, characterized in that, The cyclic data structure also includes a module configuration interval, which is first written to the programmable flash memory module during wafer testing; low-power management methods also include: When the chip enters a low-power field recovery scenario, the hardware reads the module configuration addresses and module configuration data that are sequentially adjacent to the physical addresses in the RAM module, while simultaneously reading the module configuration interval that is adjacent to the physical address of the module configuration data in the RAM module. After writing the module configuration data to the first target register module, and after waiting for the module configuration interval, the hardware reads the module configuration addresses, module configuration data, and module configuration intervals that are sequentially adjacent to the physical addresses in the RAM module. Based on the module configuration address read again, the second target register module in the power domain register is determined; Write the module configuration data, which is adjacent to the physical address of the module configuration address that is read again, to the second target register module.

6. The register low-power management method according to any one of claims 1 to 5, characterized in that, Looping data structures also include terminators; low-power management methods also include: After writing the module configuration address and module configuration data to the RAM module in sequence, the register is saved in a low-power state when the end symbol is read from the data written to the module.

7. The register low-power management method according to claim 6, characterized in that, Low-power management methods also include: When the chip enters a low-power field recovery scenario, after writing the module configuration data to the first target register module, and after the end symbol is read from the data written to the module, the low-power field recovery of the register is completed.

8. A register-based low-power management device for a chip, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform, when executing the program instructions, the register low-power management method for a chip as described in any one of claims 1 to 7.

9. A chip, characterized in that, include: The chip body includes a random access memory (RAM) module and a power-down domain register, wherein the power-down domain register includes at least one register module. A programmable flash memory module, wherein the data written to the module is a circular data structure containing at least the module configuration address; The register low-power management device for a chip as described in claim 8 is installed on the chip body.

10. The chip according to claim 9, characterized in that, Also includes: The power management unit (PMU) module is installed on the chip body and electrically connected to the register low-power management device for the chip, and is configured to perform low-power field recovery.

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