ZUFS memory system, operation method and system thereof and storage medium

Abstract

The embodiment of the invention provides a ZUFS memory system, an operation method and system of the ZUFS memory system and a storage medium, and the ZUFS memory system comprises a memory device; the memory controller is coupled with the memory device, the memory controller is configured to control the memory device to carry out partitioned storage according to regions, and storage spaces of the regions are configured to support sequential writing; wherein the memory controller is configured with a first interface used for being coupled with a host and receives a first command from the host through the first interface, the first command comprises specified mode information, and the specified mode information indicates a storage mode of a to-be-created area; the memory controller is further configured to: determine whether an available storage space of the memory device satisfies a creation condition according to the specified mode information; and in response to the fact that the available storage space meets the creation condition, creating a region with a storage mode according to the first command.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a ZUFS memory system, its operation method, system, and storage medium. Background Technology

[0002] A memory system may include one or more memories for storing data. The memory system may be a memory system that supports Region Namespaces (ZNS). Improving the management of multiple regions within a Region Namespace (ZNS) is one of the key technical problems that urgently needs to be solved in this field at present. Summary of the Invention

[0003] This disclosure provides a memory system, its operation method, system, and storage medium.

[0004] In a first aspect, embodiments of this disclosure provide a Region Universal Flash Memory (ZUFS) system, including: a memory device; and a memory controller coupled to the memory device, the memory controller being configured to control the memory device to perform partitioned storage by region, wherein the storage space of the region is configured to support sequential writes; wherein the memory controller is configured with a first interface for coupling with a host, and receives a first command from the host through the first interface, the first command including specified mode information, the specified mode information indicating the storage mode of the region to be created; the memory controller is further configured to: determine whether the available storage space of the memory device meets the creation conditions according to the specified mode information; and in response to the available storage space meeting the creation conditions, create a region with a storage mode according to the first command.

[0005] In the above scheme, the memory controller is configured to set the status of the created region to open and send a creation success message to the host through the first interface.

[0006] In the above scheme, the memory controller is configured to send a creation failure message to the host through the first interface in response to the fact that the available storage space does not meet the creation conditions.

[0007] In the above scheme, the creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

[0008] In the above scheme, the memory controller is further configured to: receive a region write request and write data through a first interface, and write the write data into the created region according to the region write request.

[0009] In the above scheme, the storage modes include a first storage mode and a second storage mode. Each storage unit corresponding to the storage space of the region configured as the first storage mode can be written with N bits of data; each storage unit corresponding to the storage space of the region configured as the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

[0010] In the above scheme, the memory controller is further configured to: receive a region write request and write data through a first interface; if the write data is hot data, the storage mode is a first storage mode; if the write data is non-hot data, the storage mode is a second storage mode; and write the write data into the region created according to the first command according to the region write request.

[0011] In the above scheme, the first command includes an open region command, and the specified mode information occupies seven bits in the open region command.

[0012] In the above scheme, the region refers to the region in the Region Namespace (ZNS).

[0013] Secondly, embodiments of this disclosure provide a system, including: a ZUFS memory system and a host; wherein the memory system includes: a memory device and a memory controller coupled to the memory device, the memory controller being configured to control the memory device to perform partitioned storage by region, wherein the storage space of the region is configured to support sequential writes; the host includes a host controller and a second interface, the host controller being configured to generate a first command and send the first command to the memory controller through the second interface, the first command including specified mode information, the specified mode information being used to indicate the storage mode of the region to be created; and the memory controller being configured with a first interface for coupling to the second interface, and receiving the first command from the host through the first interface; determining whether the available storage space of the memory device meets the creation conditions according to the specified mode information; and in response to the available storage space meeting the creation conditions, creating a region with a storage mode according to the first command.

[0014] In the above scheme, the memory controller is configured to set the status of the created region to open and send a creation success message to the host through the first interface.

[0015] In the above scheme, the memory controller is configured to send a creation failure message to the host through the first interface in response to the fact that the available storage space does not meet the creation conditions.

[0016] In the above scheme, the creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

[0017] In the above scheme, the storage modes include a first storage mode and a second storage mode. Each storage unit corresponding to the storage space of the region configured as the first storage mode can be written with N bits of data; each storage unit corresponding to the storage space of the region configured as the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

[0018] In the above scheme, the host controller is configured to generate a corresponding first command based on the hot or cold attribute of the written data; if the written data is hot data, the storage mode in the first command is the first storage mode, and if the written data is non-hot data, the storage mode in the first command is the second storage mode.

[0019] In the above scheme, the host controller is configured to generate a region write request corresponding to the write data, and send the write data and the region write request to the memory controller through the second interface; the memory controller is further configured to receive the region write request and the write data through the first interface, and write the write data into the region created according to the first command according to the region write request.

[0020] In the above scheme, the first command includes an open region command, and the specified mode information occupies seven bits in the open region command.

[0021] In the above scheme, the region refers to the region in the Region Namespace (ZNS).

[0022] Thirdly, embodiments of this disclosure provide an operation method for a ZUFS memory system. The memory system includes a memory device and a memory controller coupled to the memory device. The memory controller is configured with a first interface for coupling with a host. The method includes: receiving a first command through the first interface, the first command including specified mode information, the specified mode information being used to indicate the storage mode of a region to be created; the region corresponding to the storage space of the memory device, the storage space of the region being configured to support sequential writing; determining whether the available storage space of the memory device meets the creation conditions based on the specified mode information; and, in response to the available storage space meeting the creation conditions, creating a region with a storage mode according to the first command.

[0023] The above scheme also includes: setting the status of the created area to open and sending a creation success message to the host through the first interface.

[0024] The above scheme further includes: in response to the fact that the available storage space does not meet the creation conditions, sending a creation failure message to the host through the first interface.

[0025] In the above scheme, the creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

[0026] In the above scheme, the storage modes include a first storage mode and a second storage mode. Each storage unit corresponding to the storage space of the region configured as the first storage mode can be written with N bits of data; each storage unit corresponding to the storage space of the region configured as the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

[0027] The above scheme further includes: receiving a region write request and write data through a first interface; if the write data is hot data, the storage mode is a first storage mode; if the write data is non-hot data, the storage mode is a second storage mode; and writing the write data into the region created according to the first command according to the region write request.

[0028] In the above scheme, the first command includes an open region command, and the specified mode information occupies seven bits in the open region command.

[0029] In the above scheme, the region refers to the region in the Region Namespace (ZNS).

[0030] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program, which, when executed, implements the method as described in any of the third aspects.

[0031] This disclosure provides a ZUFS memory system, its operation method, system, and storage medium. The ZUFS memory system includes: a memory device; and a memory controller coupled to the memory device. The memory controller is configured to control the memory device to perform partitioned storage by region, wherein the storage space of each region is configured to support sequential writes. The memory controller is configured with a first interface for coupling with a host and receives a first command from the host through the first interface. The first command includes specified mode information, which indicates the storage mode of the region to be created. The memory controller is further configured to: determine whether the available storage space of the memory device meets the creation conditions based on the specified mode information; and, in response to the available storage space meeting the creation conditions, create a region with a storage mode according to the first command. In this disclosure, the creation of a region with a storage mode can be achieved based on the specified mode information in the first command. That is, the creation of a region with a storage mode can be achieved by transmitting only one command between the host and the memory system. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0033] Figure 2AThis is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0034] Figure 2B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0035] Figure 3A This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0036] Figure 3B This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0037] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND memory strings according to an embodiment of the present disclosure;

[0038] Figure 5A This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0039] Figure 5B A schematic diagram of a memory controller provided according to an embodiment of this disclosure;

[0040] Figure 6 A schematic diagram of the structure of the open region command in ZBC provided in an embodiment of this disclosure;

[0041] Figure 7 A schematic diagram of the interaction process between a ZUFS memory system and a host provided in an embodiment of this disclosure. Figure 1 ;

[0042] Figure 8 A schematic diagram of the interaction process between the ZUFS storage system and the host provided in one embodiment of this disclosure;

[0043] Figure 9 This is a flowchart illustrating the operation method of a ZUFS memory system provided in an embodiment of this disclosure. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0051] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory devices. For ease of understanding, a three-dimensional NAND type memory device will be used as an example for explanation.

[0052] Figure 1 This is a block diagram of an exemplary system 100 having a memory device according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104. The host 108 includes a host controller and a second interface for coupling with the memory controller 106; that is, the second interface may also be an interface for communication between the host and the memory controller.

[0053] In some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0054] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), and Firewire. These interfaces can also be referred to as first interfaces (or front-end interfaces). Here, the first interface is the interface coupled to the aforementioned second interface of the host. In some embodiments, the memory controller 106 interacts with the memory device 104 via multiple configured channels for command / data exchange. These channels are also referred to as back-end interfaces.

[0055] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0056] Figure 3A This is a schematic diagram of the structure of a memory cell array in a three-dimensional NAND type memory device according to an embodiment of the present disclosure, as shown below. Figure 3A As shown, the memory cell array of a three-dimensional NAND flash memory device consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each pair of memory cell rows is separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory strings. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks, and the multiple second gate isolation structures and the up-select gate isolation structure can divide the memory blocks into sub-blocks. Figure 3A The storage block shown contains 6 sub-blocks. In practical applications, the number of sub-blocks in a storage block is not limited to this.

[0057] It should be noted that, Figure 3AThe number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0058] Figure 3B This is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to an embodiment of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0059] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0060] like Figure 3BAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0061] like Figure 3B As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0062] Figure 4 This is a schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 according to an embodiment of this disclosure. Figure 4As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0063] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0064] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0065] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0066] Return to reference Figure 3B The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Figure 5A This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure. The peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include... Figure 5A Additional peripheral circuitry not shown.

[0067] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301. That is, interface 516 here is the interface coupled to the back-end interface of the aforementioned memory controller; that is, interface 516 can also be the interface for communication between the memory device and the memory controller.

[0068] In some implementations, the page buffer / sensor amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cells 306 of the memory cell array 301. In another example, the page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cells 306 coupled to selected word lines 318. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0069] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0070] Figure 5B This is a schematic diagram of a memory controller 106 provided according to an embodiment of the present disclosure. The memory controller 106 may include one or more processors 522 and a memory module, the memory module including a cache 524. The memory controller 106 may also include an interface (I / F) 528 (i.e., a first interface) coupled to a host 108 and an interface (I / F) 530 (i.e., a back-end interface) coupled to a memory device 104. Here, the first interface is the interface coupled to the aforementioned second interface of the host. The processor 522 may include an arithmetic logic unit (ALU) for performing arithmetic and logical operations. The interface 528 may receive instructions and data from the host 108 and buffer the instructions and data to the processor 522 and the cache 524, respectively. The interface 530 may transmit control signals and data from the processor 522 and the cache 524 to the memory device 104, respectively.

[0071] This disclosure provides a Region Universal Flash Memory (ZUFS) system. The specific structure and composition of the memory system can be found in the foregoing. Figure 1 , Figure 2A , Figure 2BThe relevant structure and composition of the memory system 102 are described below for brevity. The ZUFS memory system includes: a memory device; and a memory controller coupled to the memory device, configured to control the memory device to partition storage by region, wherein the storage space of the region is configured to support sequential writes; wherein the memory controller is configured with a first interface for coupling with a host, and receives a first command from the host through the first interface, the first command including specified mode information indicating the storage mode of the region to be created; the memory controller is further configured to: determine whether the available storage space of the memory device meets the creation conditions based on the specified mode information; and, in response to the available storage space meeting the creation conditions, create a region with a storage mode according to the first command.

[0072] In some implementations, the aforementioned Figure 1 , Figure 2A , Figure 2B The storage system 102 is a storage system conforming to the Zoned Universal Flash Storage (ZUFS) standard, and is simply referred to as the ZUFS storage system. The communication interface (e.g., the first interface and the second interface) between the ZUFS storage system and the host can perform communication according to the specifications described in the UFS specification of the JEDEC standard.

[0073] In some implementations, a region is a region within a zone namespace (ZNS). A ZNS comprises multiple zones. A zone is a fixed-size sub-region within a ZNS, and each zone has a logical block address (LBA) range. The number of LBAs corresponding to each zone can be the same. In some implementations, each of the multiple zones in a ZNS can have the same configuration. Typically, in a ZNS, an external device (e.g., a host) provides the logical block address definitions to the memory system. For example, the host may indicate an LBA range corresponding to a first zone, an LBA range corresponding to a second zone, and so on. The ZUFS memory system then maps each zone in the ZNS to a physical block in the memory device. For example, the ZUFS memory system may map the LBA corresponding to a first zone to a first physical block, the LBA corresponding to a second zone to a second physical block, and so on.

[0074] In some implementations, the storage capacity of a single region is less than the storage capacity corresponding to a physical block of the memory device. Here, storage capacity may refer to how much storage space the memory device provides.

[0075] In some implementations, the Region Namespace (ZNS) can have a preset or adjustable storage capacity. A ZUFS memory system supporting ZNS can establish multiple regions, allowing the memory controller to partition the memory device by region. For example, host-transmitted data can be stored in regions, and the ZUFS memory system can allocate at least one storage block or a portion of a storage block to each region. The ZUFS memory system can then sequentially store host-transmitted data in the regions specified by the corresponding LBAs.

[0076] In some implementations, the storage capacity of the region is close to the storage capacity corresponding to the erase block. In one specific example, the storage capacity of the region is the same as the storage capacity corresponding to the erase block, or the storage capacity of the region is an integer multiple of the storage capacity corresponding to the erase block, or the storage capacity corresponding to the erase block is an integer multiple of the storage capacity of the region. Since garbage collection moves from the memory device to the host, if the storage capacity of the region is an integer multiple of the storage capacity corresponding to the erase block, write amplification caused by garbage collection on the memory device side can be eliminated. If the storage capacity corresponding to the erase block is an integer multiple of the storage capacity of the region, the memory device still needs to perform garbage collection.

[0077] In ZUFS memory systems that support Region Namespaces (ZNS), regions in a ZNS only support sequential writes and not random writes, while regions in a ZNS can support both random and sequential reads.

[0078] In some implementations, the creation condition includes that the available storage space in the memory device is greater than the storage space occupied by the region to be created. In other words, the available storage space in the memory device must meet the requirements for region creation.

[0079] In some implementations, the first command may be used to instruct the creation of multiple regions having a storage pattern indicated by specified pattern information, such that the creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the multiple regions to be created.

[0080] In this embodiment of the disclosure, a region with a storage mode indicated by specified mode information can be created by means of a first command.

[0081] In some implementations, the memory controller is configured to send a creation failure message (open zone fail) to the host via a first interface in response to the availability of storage space not meeting the creation conditions.

[0082] In some implementations, after receiving creation failure information via the second interface, the host may send a second command to the memory controller. This second command instructs the memory controller to configure at least one non-full region in the memory device to the storage mode indicated by the specified mode information. Here, the second command can be a Reset Write Pointer Command in ZBC.

[0083] In some implementations, the second command includes an identifier for a specified region and mode switching information for that region; the memory controller is configured to switch the storage mode of the specified region to the storage mode indicated in the mode switching information based on the mode switching information. Thus, the memory controller can switch the storage mode of the specified region to the storage mode indicated by the mode switching information based on the second command.

[0084] In some implementations, the storage modes include a first storage mode and a second storage mode. Each storage cell corresponding to the storage space of the region configured in the first storage mode can be written with N bits of data; each storage cell corresponding to the storage space of the region configured in the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

[0085] In some implementations, the memory controller determines the storage mode of the region to be created as a first storage mode or a second storage mode based on specified mode information. Specifically, when the specified mode information indicates that the storage mode of the region to be created is the first storage mode, the memory controller creates a region with the first storage mode according to a first command; when the specified mode information indicates that the storage mode of the region to be created is the second storage mode, the memory controller creates a region with the second storage mode according to the first command.

[0086] As described above, in NAND flash memory devices, memory cells can be classified into single-level cell (SLC) and multi-level cell (MLC) based on their storage density. Correspondingly, the first storage mode can be a single-level cell (SLC) storage mode, i.e., N=1, and the second storage mode can be a multi-level cell (MLC) storage mode, i.e., M is an integer greater than 1. The storage density of the first storage mode is less than that of the second storage mode, i.e., N is less than M. The multi-level cell (MLC) storage mode can be at least one of two-level cell (BLC), three-level cell (TLC), and four-level cell (QLC) storage modes. When M=2, the second storage mode is a two-level cell storage mode; when M=3, the second storage mode is a TLC storage mode; and when M=4, the second storage mode is a QLC storage mode.

[0087] In one specific example, the first command can be used to create a region with SLC storage mode. In another specific example, the first command can be used to create a region with MLC storage mode.

[0088] In some implementations, in addition to the region namespace (ZNS), the ZUFS memory system may also include one or more conventional namespaces (CNS).

[0089] In some implementations, the first command includes Zoned Block Commands (ZBCs). For example, the first command can be a command in the ZBC used to configure a zone. In a specific example, the first command can be an Open Zone Command in the ZBC. Here, the first command is a command that conforms to the Zoned UFS (Zoned Universal Flash Storage) protocol format.

[0090] Figure 6 This is a schematic diagram illustrating the structure of an open region command in ZBC according to an embodiment of this disclosure. (Refer to...) Figure 6 Open zone commands can include fields such as Operation Code, Service Action, Zone ID, Zone Count, Control bytes, and Reserved. The various fields and information included in open zone commands can be understood by referring to the ZBC specification. Figure 6 In the example, ZONEID is the identifier of the region to be created, and ZONE TYPE is the specified mode information.

[0091] In some implementations, the memory controller is configured to create and open regions in response to an open region command. Opening a region means setting the state of the created region to an open state.

[0092] In some implementations, the memory controller is configured to reset the state of a specified region to an empty state according to a reset write pointer command. Since the reset write pointer command can reset the write pointer to its initial value, that is, the starting LBA of the region pointed to by the write pointer, the state of the specified region can be reset to an empty state by using the reset write pointer command.

[0093] In some implementations, the state of a region includes Empty, Open, and Full. In the Empty state, there is no valid data in the region, and its write pointer is set to the starting LBA (WP = 0). After the region switches from Empty to Open, data can be written to the region. In the Open state, the region may or may not have valid data; its write pointer points to a position between the end of the starting and last LBAs (WP > 0), and the corresponding storage space can receive write data via write commands. Additionally, the host can reset a region to clear or erase valid data stored in it, resetting the region to Empty. Once the corresponding storage space is full, the region switches to Full. In Full, the corresponding storage space is full and cannot be opened to receive write data. The write pointer then points to the LBA of the next region. If all regions in the ZNS are full, the write pointer points to the end of the last LBA of the region (WP = ZCAP). Here, ZCAP is the capacity of the region.

[0094] In some implementations, the Open Zone command can trigger a zone transition from an empty state to an open state. In any case, the Reset Write Pointer command can be used to transition a zone to an empty state. In some embodiments, the zone state also includes a Closed state, which can be triggered by the Close Zone Command to transition a zone from an open state to a closed state. In the Closed state, if the write pointer points to the beginning LBA of the zone, the zone state transitions to an empty state. The write pointer pointing to the end of the last LBA of the zone triggers a transition to a full state, and the Finish Zone Command can also trigger a transition to a full state.

[0095] In some implementations, when an open region command triggers the transition of a region from an empty state to an open state, the memory controller can determine whether the region requested by the open region command is openable. For example, the memory controller can determine whether the requested region is available to be opened. Specifically, if the state machine variable is set to FAILURE, the requested region cannot be opened, meaning the memory controller does not perform the open region operation. In this case, the memory controller can send information that the requested region cannot be opened or a creation failure message to the host. If the state machine variable is set to SUCCESS, the requested region can be opened, meaning the memory controller can perform the open region operation. In this case, the memory controller sends information that the requested region can be opened or a creation success message to the host. Here, a state machine variable set to SUCCESS indicates that there are sufficient open region resources available, i.e., there are regions that can be opened; a state machine variable set to FAILURE indicates that there are insufficient available open region resources, i.e., there are no regions that can be opened.

[0096] In some implementations, the specified mode information is included in unused reserved fields within open area commands based on existing ZBC specifications. In a specific example, refer to... Figure 6 The specified mode information (ZONE TYPE) occupies bits 1 through 8 of the 15th byte in the open zone command.

[0097] In a specific example, when the specified mode information is 01h, it indicates that the storage mode indicated by the specified mode information is SLC storage mode; when the specified mode information is 02h, it indicates that the storage mode indicated by the specified mode information is MLC storage mode.

[0098] In other implementations, the first storage mode can be SLC storage mode, and the second storage mode can be MLC storage mode. The second storage mode can specifically include TLC storage mode and QLC storage mode. In a specific example, when the specified mode information is 00h, it indicates that the storage mode indicated by the specified mode information is SLC storage mode; when the specified mode information is 01h, it indicates that the storage mode indicated by the specified mode information is TLC storage mode; and when the specified mode information is 02h, it indicates that the storage mode indicated by the specified mode information is QLC storage mode.

[0099] In some implementations, mode switching information may be included in an unused reserved field of the reset write pointer command based on the existing ZBC specification. In some implementations, the mode switching information occupies a two-bit field in the reset write pointer command. In one specific example, the mode switching information occupies the first and second bits of the fourteenth byte of the reset write pointer command.

[0100] In a specific example, mode switching information can be used to indicate the storage mode of a specified area. When the mode switching information is 01h, it indicates that the storage mode of the specified area is the first storage mode; when the mode response information is 02h, it indicates that the storage mode of the specified area is the second storage mode.

[0101] In a specific example, a mode switching information of 00h indicates that the storage mode of the specified area is not switched. It should be noted that when the ALL bit in the reset write pointer command is 1, the mode switching information in the reset write pointer command is ignored.

[0102] In a specific example, when the mode switching information is 01h, if the current storage mode of the specified region is the first storage mode, which is the same as the storage mode indicated in the mode switching information, then the storage mode of the specified region is not switched; if the current storage mode of the specified region is the second storage mode, which is different from the storage mode indicated in the mode switching information, then the specified region is switched from the second storage mode to the first storage mode. When the mode switching information is 02h, if the current storage mode of the specified region is the second storage mode, which is the same as the storage mode indicated in the mode switching information, then the storage mode of the specified region is not switched; if the current storage mode of the specified region is the first storage mode, which is different from the storage mode indicated in the mode switching information, then the specified region is switched from the first storage mode to the second storage mode.

[0103] In some implementations, the memory controller is configured to set the state of the created zone to open and send a creation success message (open zone success) to the host via a first interface.

[0104] In some implementations, the memory controller is further configured to receive a region write request and write data through the first interface, and write the write data to the created region according to the region write request. As mentioned above, if the available storage space does not meet the creation conditions, the host will send a second command to the memory controller after receiving the creation failure information, so that the memory controller can configure at least one region in the memory device that is not full to the storage mode indicated by the mode switching information according to the second command. Thus, before the host issues the region write request and write data, there is a region in the memory device that can be written with data.

[0105] In some implementations, the memory controller is further configured to: receive a region write request and write data through a first interface; if the write data is hot data, specify the storage mode indicated by the mode information as a first storage mode; if the write data is non-hot data, specify the storage mode indicated by the mode information as a second storage mode; and write the write data into the region created according to the first command according to the region write request.

[0106] In some implementations, if the storage space does not meet the creation conditions, and the memory controller cannot create a region with the storage mode indicated by the specified mode information according to the first command, then write data to the region configured according to the second command according to the region write request.

[0107] Here, non-hot data refers to data accessed less frequently than the memory device's set reference value, and its predetermined storage duration is relatively long; hot data refers to data accessed more frequently than the memory device's set reference value, and its predetermined storage duration is relatively short. Non-hot data includes cold data and warm data. Warm data has a higher access frequency than cold data, but a lower access frequency than hot data. Therefore, areas with the first storage mode can be used to store hot data with a shorter predetermined storage duration, and areas with the second storage mode can be used to store non-hot data with a longer predetermined storage duration. In this way, the host can create or configure areas with corresponding storage modes based on the hot / cold attributes of the data being written, thereby improving the write and read speeds of hot data.

[0108] In this embodiment, on the host side: by adding specified mode information to the open region command, the specified mode information can be set according to actual needs, thereby controlling the storage mode of the region to be created. Correspondingly, on the ZUFS memory system side: a region with the storage mode indicated by the specified mode information can be created based on the specified mode information in the open region command. In this embodiment, the creation of a region with a specified storage mode can be achieved using existing ZBC commands.

[0109] In this embodiment, on the host side: by adding mode switching information to the reset write pointer command, the mode switching information can be set according to actual needs, thereby controlling the storage mode of a specified area. Correspondingly, on the ZUFS memory system side: based on the mode switching information in the reset write pointer command, the storage mode of the specified area can be switched to the storage mode indicated in the mode switching information. In this embodiment, the switching of the specified area between the first storage mode and the second storage mode can be achieved using existing ZBC commands.

[0110] In this embodiment of the disclosure, when writing data, regions of a first storage mode can be selectively created or configured for hot data and regions of a second storage mode can be created or configured for non-hot data based on the hot / cold properties of the data being written. This can improve the writing and reading speeds of hot data.

[0111] This disclosure provides a system, the specific structure and composition of which can be referred to the foregoing. Figure 1 The relevant structure and components are not detailed here for the sake of brevity. Figure 7 A schematic diagram of the interaction process between a ZUFS memory system and a host provided in an embodiment of this disclosure. Figure 1 , combined Figure 7 and Figure 1 The system's workflow is described. It should be understood that not all steps may be required during the interaction between the ZUFS storage system and the host. Figure 7 The operational steps shown may not be exhaustive, and other operational steps may be performed before, after, or between any of the operational steps shown. Furthermore, some operational steps in the operational steps may be performed simultaneously, or in conjunction with... Figure 7 The different execution sequences are shown in the diagram. The system includes: a ZUFS memory system and a host; wherein, the ZUFS memory system includes: a memory device and a memory controller coupled to the memory device, the memory controller being configured to control the memory device to partition storage by region, wherein the storage space of the region is configured to support sequential writes; the host includes a host controller and a second interface for coupling with the memory controller, wherein at step 701: the host controller is configured to generate a first command; at step 702: the first command is sent to the memory controller through the second interface, the first command including specified mode information, the specified mode information indicating the storage mode of the region to be created; and the memory controller is configured with a first interface for coupling with the second interface, the memory controller receiving the first command from the host through the first interface; at step 703: whether the available storage space of the memory device meets the creation conditions according to the specified mode information; in response to the available storage space meeting the creation conditions, a region having the storage mode indicated by the specified mode information is created according to the first command.

[0112] In some implementations, a region is a region within a Region Namespace (ZNS). The storage capacity of each region is less than the storage capacity corresponding to a physical block of the memory device. Here, storage capacity may refer to how much storage space the memory device provides. The Region Namespace (ZNS) may have a preset or adjustable storage capacity. A ZUFS memory system supporting Region Namespaces (ZNS) can establish multiple regions, allowing the memory controller to control the memory device to partition storage by region. For example, host-transmitted data can be stored in regions, and the ZUFS memory system can allocate at least one storage block or a portion of a storage block to each region. The ZUFS memory system can sequentially store host-transmitted data in regions specified by the corresponding LBAs. In a memory system supporting Region Namespaces (ZNS), regions within the ZNS only support sequential writes and not random writes, while regions within the ZNS can support both random and sequential reads.

[0113] In some implementations, the first command includes an open region command. The specified mode information occupies a seven-bit field in the open region command. In a specific example, the specified mode information occupies bits one through eight of the fifteenth byte in the open region command. The open region command can be referred to the foregoing. Figure 6 This will be understood and will not be elaborated upon here. The specified mode information is used to indicate the storage mode of the region to be created.

[0114] In some implementations, the storage mode includes a first storage mode and a second storage mode. The first storage mode can be a single-level cell (SLC) storage mode, and the second storage mode can be a multi-level cell (MLC) storage mode. In a specific example, when the specified mode information is 01h, it indicates that the storage mode is an SLC storage mode; when the specified mode information is 02h, it indicates that the storage mode is an MLC storage mode.

[0115] In other implementations, the storage mode includes a first storage mode and a second storage mode. The first storage mode can be an SLC storage mode, and the second storage mode can be an MLC storage mode, which can further include a TLC storage mode and a QLC storage mode. In a specific example, when the specified mode information is 00h, the storage mode is represented as an SLC storage mode; when the specified mode information is 01h, the storage mode of the represented region is a TLC storage mode; and when the specified mode information is 02h, the storage mode of the represented region is a QLC storage mode.

[0116] In some implementations, at step 704: the memory controller is configured to: set the state of the created region to open and send a creation success message to the host via the first interface.

[0117] In some implementations, the creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

[0118] In some implementations, at step 701: the host controller is configured to generate a corresponding first command based on the hot / cold attribute of the written data; if the written data is hot data, the storage mode in the first command is the first storage mode, and if the written data is non-hot data, the storage mode in the first command is the second storage mode.

[0119] Specifically, if the data to be written is hot data, the storage mode in the first command indicates that the storage mode of the region to be created is the first storage mode. In this case, the memory controller responds to the availability of storage space satisfying the creation conditions and creates a region with the first storage mode according to the first command. If the data to be written is non-hot data, the storage mode in the first command indicates that the storage mode of the region to be created is the second storage mode. In this case, the memory controller responds to the availability of storage space satisfying the creation conditions and creates a region with the second storage mode according to the first command.

[0120] In some implementations, at step 705: the host controller is configured to generate a region write request corresponding to the write data, and send the write data and the region write request to the memory controller via a second interface.

[0121] In some implementations, at step 706: a region write request and write data are received through a first interface, and the write data is written into the region created according to the first command according to the region write request.

[0122] Specifically, if the data to be written is hot data, the memory controller writes the data to a region with a first storage mode created according to the first command based on the region write request; if the data to be written is non-hot data, the memory controller writes the data to a region with a second storage mode created according to the first command based on the region write request.

[0123] Figure 8 This is a schematic diagram of the interaction process between the ZUFS storage system and the host provided in one embodiment of the present disclosure. It should be understood that the above... Figure 7 and Figure 8 The illustrated ZUFS storage system may not require all steps to be performed during its interaction with the host, and Figure 7 and Figure 8 The operational steps shown may not be exhaustive, and other operational steps may be performed before, after, or between any of the operational steps shown. Furthermore, some operational steps in the operational steps may be performed simultaneously, or in conjunction with... Figure 7 and Figure 8 The different orders of execution are shown in the diagram. (Combined) Figure 7 , Figure 8 and Figure 1 Describe the system's workflow. (Refer to...) Figure 8 The system includes a ZUFS storage system and a host. The ZUFS storage system includes a storage device and a storage controller coupled to the storage device. The storage controller is configured to control the storage device to perform partitioned storage by region, wherein the storage space of each region is configured to support sequential writes. The host includes a host controller and a second interface coupled to the storage controller. At step 801: the host controller is configured to generate a first command. At step 802: the first command is sent to the storage controller via the second interface. The first command includes specified mode information indicating the storage mode of the region to be created. The storage controller is configured with a first interface coupled to the second interface, through which it receives the first command from the host. At step 803: the storage controller is configured to determine whether the available storage space of the storage device meets the creation conditions based on the specified mode information. At step 804: the storage controller is configured to send creation failure information to the host via the first interface in response to the available storage space not meeting the creation conditions.

[0124] In some implementations, the creation condition includes that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

[0125] In some implementations, at step 805: the host controller is configured to generate a second command; at step 806: the second command is sent to the memory controller via a second interface; the second command includes an identifier of a specified region and mode switching information for the specified region; step 807 specifically includes: the memory controller is configured to switch the storage mode of the specified region to the storage mode indicated in the mode switching information according to the mode switching information.

[0126] Specifically, if the data to be written is hot data, the mode switching information in the second command is used to indicate that the storage mode of the specified area is switched to the first storage mode. At this time, the memory controller configures the storage mode of the specified area to the first storage mode according to the second command. If the data to be written is non-hot data, the mode switching information in the second command is used to indicate that the storage mode of the specified area is switched to the second storage mode. At this time, the memory controller configures the storage mode of the specified area to the second storage mode according to the second command.

[0127] In some implementations, at step 808: the host controller is configured to generate a region write request corresponding to the write data, and send the write data and the region write request to the memory controller via a second interface.

[0128] In some implementations, at step 809: a region write request and write data are received through a first interface, and the write data is written to the region configured according to the second command according to the region write request.

[0129] Specifically, if the data to be written is hot data, the memory controller writes the data to a region with a first storage mode configured according to the second command according to the region write request; if the data to be written is non-hot data, the memory controller writes the data to a region with a second storage mode configured according to the second command according to the region write request.

[0130] As mentioned earlier, if the available storage space does not meet the creation conditions, the host will send a second command to the memory controller after receiving the creation failure information. This allows the memory controller to configure at least one non-full region in the memory device into storage mode according to the second command. Therefore, before the host issues a region write request and writes data, there is a region in the memory device that can be written to.

[0131] In some implementations, the host controller can issue control commands to the memory controller, which then controls the memory device to perform programming, erasing, reading, and other operations based on the control commands. These other operations may include at least one of garbage collection, wear leveling, read recycling, and bad block management.

[0132] In some implementations, the host controller can send a command to the memory controller to perform garbage collection on a specified region. Upon receiving the command, the memory controller performs garbage collection operations and related operations on the storage space corresponding to the specified region. These related operations may include wear leveling operations, read-and-reclaim operations, etc.

[0133] In some implementations, a garbage collection operation initiated by the host controller may include a series of operations, such as an operation to store valid data from a specified region to another region, and an operation to reset the specified region. In this case, the operations performed by the memory controller on the storage space corresponding to the specified region after receiving the command may include: read operations and programming operations for storing valid data from the specified region to another region, and may include an erase operation for resetting the specified region.

[0134] In some implementations, because the storage space of a region is configured to support sequential writes, data can be written sequentially to regions in the ZNS. Therefore, during garbage collection, garbage collection can begin with the first region in the ZNS, followed by the second region, and so on. It should be noted that the region being garbage collected must contain invalid data and be in a closed state.

[0135] The description of the above system embodiments is similar to that of the ZUFS memory system embodiments described above, and has similar beneficial effects. For technical details not disclosed in the system embodiments of this disclosure, please refer to the description of the ZUFS memory system embodiments of this disclosure for understanding.

[0136] Figure 9 This is a flowchart illustrating an operation method of a ZUFS memory system according to an embodiment of this disclosure. The specific structure and composition of the ZUFS memory system can be found in the foregoing. Figure 1 , Figure 2A , Figure 2B The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here. It should be understood that... Figure 9 The operational steps shown may not be exhaustive, and other operational steps may be performed before, after, or between any of the operational steps shown. Furthermore, some operational steps in the operational steps may be performed simultaneously, or in conjunction with... Figure 9 The different execution orders are shown in the diagram. (See reference.) Figure 9 In step 901: A first command is received through a first interface. The first command includes specified mode information, which indicates the storage mode of the region to be created. The region corresponds to the storage space of the memory device, and the storage space of the region is configured to support sequential writing. In step 902: It is determined whether the available storage space of the memory device meets the creation conditions based on the specified mode information. In response to the availability of storage space meeting the creation conditions, a region with the storage mode indicated by the specified mode information is created according to the first command.

[0137] In some implementations, the method further includes setting the state of the created area to open and sending a creation success message to the host via a first interface.

[0138] In some implementations, the method further includes: in response to the availability of storage space not meeting the creation conditions, sending a creation failure message to the host via a first interface.

[0139] In some implementations, the creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

[0140] In some implementations, the storage modes include a first storage mode and a second storage mode. Each storage cell corresponding to the storage space of the region configured in the first storage mode can be written with N bits of data; each storage cell corresponding to the storage space of the region configured in the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

[0141] In some implementations, the method further includes: receiving a region write request and write data through a first interface; if the write data is hot data, specifying the storage mode indicated by the mode information as a first storage mode; if the write data is non-hot data, specifying the storage mode indicated by the mode information as a second storage mode; and writing the write data into the region created according to the first command according to the region write request.

[0142] In some implementations, the first command includes an open region command, specifying that mode information occupies a seven-bit field in the open region command.

[0143] In some implementations, a region is a region within a region namespace (ZNS).

[0144] The description of the operation method embodiments of the ZUFS memory system above is similar to the description of the ZUFS memory system embodiments above, and has similar beneficial effects. For technical details not disclosed in the operation method embodiments of the ZUFS memory system of this disclosure, please refer to the description of the ZUFS memory system embodiments of this disclosure for understanding.

[0145] In this embodiment, on the host side: by adding specified mode information to the open region command, the specified mode information can be set according to actual needs, thereby controlling the storage mode of the region to be created. Correspondingly, on the ZUFS memory system side: a region with the storage mode indicated by the specified mode information can be created based on the specified mode information in the open region command. In this embodiment, the creation of a region with a specified storage mode can be achieved using existing ZBC commands.

[0146] In this embodiment, on the host side: by adding mode switching information to the reset write pointer command, the mode switching information can be set according to actual needs, thereby controlling the storage mode of a specified area. Correspondingly, on the ZUFS memory system side: based on the mode switching information in the reset write pointer command, the storage mode of the specified area can be switched to the storage mode indicated in the mode switching information. In this embodiment, the switching of the specified area between the first storage mode and the second storage mode can be achieved using existing ZBC commands.

[0147] In this embodiment of the disclosure, when writing data, regions of a first storage mode can be selectively created or configured for hot data and regions of a second storage mode can be created or configured for non-hot data based on the hot / cold properties of the data being written. This can improve the writing and reading speeds of hot data.

[0148] This disclosure also provides a computer-readable storage medium storing a computer program, which, when executed, implements the operation method of the memory system provided in this disclosure.

[0149] In some embodiments, the computer-readable storage medium may be a memory such as ferromagnetic random access memory (FRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); or it may be a device that includes one or any combination of the above-mentioned memories.

[0150] In some embodiments, a computer program may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0151] As an example, a computer program may, but does not necessarily, correspond to a file in a file system. It may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0152] As an example, a computer program may be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0153] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0154] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A Zone Universal Flash Memory (ZUFS) system, characterized in that, include: Memory devices; as well as A memory controller coupled to the memory device is configured to control the memory device to perform partitioned storage by region, wherein the storage space of the region is configured to support sequential writes; The memory controller is configured with a first interface for coupling with a host and receives a first command from the host through the first interface. The first command includes specified mode information, which indicates the storage mode of the region to be created. The memory controller is further configured to: determine whether the available storage space of the memory device meets the creation conditions based on the specified mode information; and, in response to the available storage space meeting the creation conditions, create a region having the storage mode according to the first command.

2. The ZUFS memory system according to claim 1, characterized in that, The memory controller is configured to: Set the created area to an open state and send a creation success message to the host through the first interface.

3. The ZUFS memory system according to claim 1, characterized in that, The memory controller is configured to: In response to the fact that the available storage space does not meet the creation conditions, a creation failure message is sent to the host through the first interface.

4. The ZUFS memory system according to claim 1, characterized in that, The creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

5. The ZUFS memory system according to claim 1, characterized in that, The memory controller is further configured to: receive a region write request and write data through the first interface, and write the write data into the created region according to the region write request.

6. The ZUFS memory system according to claim 1, characterized in that, The storage mode includes a first storage mode and a second storage mode, wherein each storage unit corresponding to the storage space of the region configured as the first storage mode can be written with N bits of data. Each storage cell corresponding to the storage space of the region configured in the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

7. The ZUFS memory system according to claim 6, characterized in that, The memory controller is further configured to: receive a region write request and write data through the first interface; if the write data is hot data, the storage mode is the first storage mode; if the write data is non-hot data, the storage mode is the second storage mode; and write the write data into the region created according to the first command according to the region write request.

8. The ZUFS memory system according to claim 1, characterized in that, The first command includes an open region command, and the specified mode information occupies a seven-bit field in the open region command.

9. The ZUFS memory system according to claim 1, wherein, The region is a region within a Region Namespace (ZNS).

10. A system, characterized in that, include: ZUFS storage system and host; among which... The memory system includes: a memory device and a memory controller coupled to the memory device, the memory controller being configured to control the memory device to perform partitioned storage by region, wherein the storage space of the region is configured to support sequential writes; The host includes a host controller and a second interface. The host controller is configured to generate the first command and send it to the memory controller via the second interface. The first command includes specified mode information, which indicates the storage mode of the region to be created. The memory controller is configured with a first interface for coupling with the second interface and receives a first command from the host through the first interface; determines whether the available storage space of the memory device meets the creation conditions based on the specified mode information; and creates a region with the storage mode according to the first command in response to the available storage space meeting the creation conditions.

11. The system according to claim 10, characterized in that, The memory controller is configured to: Set the created area to an open state and send a creation success message to the host through the first interface.

12. The system according to claim 10, characterized in that, The memory controller is configured to: In response to the fact that the available storage space does not meet the creation conditions, a creation failure message is sent to the host through the first interface.

13. The system according to claim 10, characterized in that, The creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

14. The system according to claim 10, characterized in that, The storage mode includes a first storage mode and a second storage mode, wherein each storage unit corresponding to the storage space of the region configured as the first storage mode can be written with N bits of data. Each storage cell corresponding to the storage space of the region configured in the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

15. The system according to claim 14, characterized in that, The host controller is configured as follows: The first command is generated based on the hot / cold attribute of the written data; if the written data is hot data, the storage mode in the first command is the first storage mode, and if the written data is non-hot data, the storage mode in the first command is the second storage mode.

16. The system according to claim 15, characterized in that, The host controller is configured to generate a region write request corresponding to the write data, and send the write data and the region write request to the memory controller through the second interface; The memory controller is further configured to: receive a region write request and write data through the first interface, and write the write data into the region created according to the first command according to the region write request.

17. The system according to claim 10, characterized in that, The first command includes an open partition command, and the specified mode information occupies a seven-bit field in the open partition command.

18. The system according to claim 10, characterized in that, The region is a region within a Region Namespace (ZNS).

19. A method for operating a ZUFS memory system, characterized in that, The ZUFS storage system includes a storage device and a storage controller coupled to the storage device, the storage controller being configured with a first interface for coupling with a host, the method comprising: A first command is received through the first interface. The first command includes specified mode information, which indicates the storage mode of the region to be created. The region corresponds to the storage space of the memory device, and the storage space of the region is configured to support sequential writing. Based on the specified mode information, determine whether the available storage space of the memory device meets the creation conditions; in response to the available storage space meeting the creation conditions, create a region with the storage mode according to the first command.

20. The operating method according to claim 19, characterized in that, The method further includes: Set the created area to an open state and send a creation success message to the host through the first interface.

21. The operating method according to claim 19, characterized in that, The method further includes: In response to the fact that the available storage space does not meet the creation conditions, a creation failure message is sent to the host through the first interface.

22. The operating method according to claim 19, characterized in that, The creation conditions include that the available storage space of the memory device is greater than the storage space occupied by the region to be created.

23. The operating method according to claim 19, characterized in that, The storage mode includes a first storage mode and a second storage mode, wherein each storage unit corresponding to the storage space of the region configured as the first storage mode can be written with N bits of data. Each storage cell corresponding to the storage space of the region configured in the second storage mode can be written with M bits of data, where M and N are integers greater than or equal to 1, and M is greater than N.

24. The operating method according to claim 23, characterized in that, The method further includes: The system receives a region write request and write data through the first interface. If the write data is hot data, the storage mode is the first storage mode; if the write data is non-hot data, the storage mode is the second storage mode. The system writes the write data into the region created according to the first command based on the region write request.

25. The operating method according to claim 19, characterized in that, The first command includes an open partition command, and the specified mode information occupies a seven-bit field in the open partition command.

26. The operating method according to claim 19, characterized in that, The region is a region within a Region Namespace (ZNS).

27. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the method as described in any one of claims 19 to 26.

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