Compression device, chip, computer equipment and compression method

Abstract

The invention discloses a compression device, a chip, computer equipment and a compression method, and relates to the field of chips. The compression device comprises an arithmetic unit, a statistical unit and a generation unit, the arithmetic unit is connected with the statistical unit, and the statistical unit is connected with the generation unit. The arithmetic unit is used for executing operation on at least two memory access addresses in the memory access request to obtain an operation result, the operation result is used for indicating the interval between every two memory access addresses executed in sequence in the at least two memory access addresses, and the at least two memory access addresses respectively correspond to one cache line of the memory; the statistical unit is used for counting the operation result to obtain a statistical result, and the statistical result is used for indicating the condition that every two adjacent intervals in the intervals are equal; and the generation unit is used for generating at least one equidistant compression request based on the statistical result and the memory access request, and the equidistant compression request is used for indicating to sequentially execute read-write operation on at least two cache lines of the memory.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a compression device, a chip, a computer device, and a compression method. Background Technology

[0002] In a multithreaded processor, each thread can perform read and write operations on memory, which can be sequential or discrete.

[0003] In related technologies, discrete read and write operations require sending memory access requests via the bus, on a cache line-by-cache basis. When the memory addresses accessed in discrete memory access requests are not in the same cache line, multiple memory access requests need to be sent via the bus to perform discrete read and write operations on the memory. For one of these multiple memory access requests, there may be a large number of memory addresses that do not need to be accessed.

[0004] However, the way related technologies send multiple memory access requests results in low bus utilization. Summary of the Invention

[0005] This application provides a compression device, a chip, a computer device, and a compression method. The technical solution is as follows:

[0006] On the one hand, a compression device is provided, the compression device comprising: an arithmetic unit, a statistical unit, and a generation unit, wherein the arithmetic unit is connected to the statistical unit, and the statistical unit is connected to the generation unit;

[0007] The arithmetic unit is used to perform operations on at least two memory access addresses in the memory access request to obtain an operation result. The operation result is used to indicate the interval between each pair of memory access addresses that are executed sequentially among the at least two memory access addresses. Each of the at least two memory access addresses corresponds to a cache line of the memory.

[0008] The statistical unit is used to calculate the calculation results and obtain statistical results, which are used to indicate the case where every two adjacent intervals are equal.

[0009] The generation unit is configured to generate at least one equidistant compression request based on the statistical results and the memory access request. The equidistant compression request is used to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0010] On the other hand, a compression method is provided. The compression device includes: an arithmetic unit, a statistical unit, and a generation unit, wherein the arithmetic unit is connected to the statistical unit, and the statistical unit is connected to the generation unit; the compression method applied to the compression device includes:

[0011] The arithmetic unit performs operations on at least two memory access addresses in the memory access request to obtain an operation result. The operation result is used to indicate the interval between each pair of memory access addresses that are executed sequentially among the at least two memory access addresses. Each of the at least two memory access addresses corresponds to a cache line of the memory.

[0012] The statistical unit calculates the calculation results to obtain statistical results, which are used to indicate the case where every two adjacent intervals are equal.

[0013] Based on the statistical results and the memory access request, the generation unit generates at least one equidistant compression request, which is used to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0014] In some embodiments, the generation unit further includes: a third generation unit, wherein the third generation unit is connected in parallel with the first generation unit and the second generation unit;

[0015] The compression method further includes:

[0016] When the number of target values ​​is greater than or equal to the second threshold, the third generation unit generates at least two cache line access requests corresponding to the access request, based on the cache lines corresponding to the at least two access addresses in the access request, in units of cache lines.

[0017] In some embodiments, the compression device further includes a multiplexer, wherein the first generation unit, the second generation unit, and the third generation unit are respectively connected to the multiplexer;

[0018] The compression method further includes:

[0019] The multiplexer sends the at least one equidistant compression request or the at least two cache line access requests to the bus to route the at least one equidistant compression request or the at least two cache line access requests to the memory via the bus, so as to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0020] In some embodiments, the statistical unit includes: a first target value detection unit and a target value quantity statistics unit. The arithmetic unit is connected to the first target value detection unit and is also connected to the target value quantity statistics unit. The first target value detection unit is connected to the generation unit, and the target value quantity statistics unit is connected to the multiplexer.

[0021] The statistical unit calculates the computation results to obtain statistical results, including:

[0022] The first target value detection unit detects the position of the first target value in the calculation result, and the position of the first target value is used to indicate the boundary point in the memory access request;

[0023] The target value counting unit counts the number of target values ​​in the calculation result.

[0024] In some embodiments, at least two memory addresses in the memory access request are N, and the arithmetic unit includes: N-1 subtractors and N-2 comparators; the i-th subtractor and the (i+1)-th adjacent subtractor in the N-1 subtractors are each connected to the i-th comparator in the N-2 comparators, where N is greater than or equal to 2, and i is greater than 0 and less than or equal to N-2;

[0025] The arithmetic unit performs operations on at least two memory access addresses in the memory access request to obtain the operation results, including:

[0026] The N-1 subtractors extract N memory access addresses from the memory access request, and sequentially perform a subtraction operation on every two memory access addresses among the N memory access addresses to obtain a subtraction result, which includes N-1 intervals.

[0027] The N-2 comparators sequentially perform comparison operations on every two adjacent intervals in the N-1 intervals to obtain comparison results; the operation result is obtained based on the comparison results.

[0028] In some embodiments, the N-2 comparators obtain the computation result based on the comparison result, including:

[0029] If the comparison result shows that two adjacent intervals are equal, the N-2 comparators determine that the operation result corresponding to the comparison result is the second value; otherwise, they determine that the operation result corresponding to the comparison result is the first value.

[0030] On the other hand, a chip is provided, the chip comprising: the compression device as described above.

[0031] On the other hand, a board is provided, the board including: the compression device as described above.

[0032] On the other hand, a processor is provided, the processor comprising: the compression device as described above.

[0033] On the other hand, a computer device is provided, the computer device comprising: a compression device as described above, or a chip as described above, or a board as described above.

[0034] On the other hand, a computer device is provided, the computer device comprising: a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the compression method as described above.

[0035] On the other hand, a computer-readable storage medium is provided that stores a computer program, which is loaded and executed by a processor to implement the compression method described above.

[0036] On the other hand, a computer program product is provided, the computer program product including computer instructions stored in a computer-readable storage medium, wherein a processor retrieves the computer instructions from the computer-readable storage medium, causing the processor to load and execute them to implement the compression method as described above.

[0037] The beneficial effects of the technical solutions provided in this application include at least the following:

[0038] A request compression device for equidistant memory access is provided. When at least two memory access addresses in a memory access request each correspond to a cache line in memory, the device identifies the interval between each pair of memory access addresses executed sequentially, thereby compressing the equidistant memory access request into at least one equidistant compressed request. Compared to existing methods that require sending at least two cache lines of memory access requests to the bus to execute the memory access request, fewer equidistant compressed requests are required, improving bus utilization and thus enhancing processor memory access performance. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a computer system provided in an exemplary embodiment of this application;

[0041] Figure 2 This is a schematic diagram of a discrete memory access request provided in an exemplary embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the related technology provided in an exemplary embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the processing of a compression apparatus provided in an exemplary embodiment of this application;

[0044] Figure 5 This is a schematic block diagram of a compression apparatus provided in an exemplary embodiment of this application;

[0045] Figure 6 This is a schematic block diagram of a compression apparatus provided in an exemplary embodiment of this application;

[0046] Figure 7 This is a schematic block diagram of a compression apparatus provided in an exemplary embodiment of this application;

[0047] Figure 8 This is a schematic block diagram of a compression apparatus provided in an exemplary embodiment of this application;

[0048] Figure 9 This is a schematic block diagram of a compression apparatus provided in an exemplary embodiment of this application;

[0049] Figure 10 This is a schematic diagram of the overall architecture of a compression device provided in an exemplary embodiment of this application;

[0050] Figure 11 This is a schematic diagram of equidistant memory access provided in an exemplary embodiment of this application;

[0051] Figure 12 This is a schematic diagram of the processing of a compression apparatus provided in an exemplary embodiment of this application;

[0052] Figure 13 This is a schematic diagram of equidistant memory access provided in an exemplary embodiment of this application;

[0053] Figure 14 This is a schematic diagram of the processing of a compression apparatus provided in an exemplary embodiment of this application;

[0054] Figure 15 This is a flowchart of a compression method provided in an exemplary embodiment of this application;

[0055] Figure 16 This is a schematic block diagram of a chip provided in an exemplary embodiment of this application;

[0056] Figure 17 This is a schematic block diagram of a board provided in an exemplary embodiment of this application;

[0057] Figure 18 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0058] Figure 19 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0059] Figure 20This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0060] Figure 21 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0061] Figure 22 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0063] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0064] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0065] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0066] It should be noted that this application may display a prompt interface, pop-up window, or output voice prompts before and during the collection of user-related data (e.g., instructions, operations, requests related to compression devices, computer equipment, chips, etc.). These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their relevant data is being collected. This ensures that the application only begins executing the steps related to acquiring user-related data after receiving confirmation from the user regarding the prompt interface or pop-up window; otherwise (i.e., without receiving confirmation from the user), the steps to acquire user-related data are terminated, meaning no user-related data is acquired. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of relevant user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0067] First, let me briefly introduce the terms used in the embodiments of this application.

[0068] Chip: Also known as an artificial intelligence (AI) chip, it includes a processor and memory. The processor is used to process data.

[0069] A cache line is the smallest unit of storage managed by the memory's cache. Each cache line contains data. In some embodiments, the data in the cache may be stored in a matrix format with N rows × M columns.

[0070] Figure 1 This is a schematic diagram of a computer system provided in an exemplary embodiment of this application. The computer system 100 can be implemented as a hardware architecture for a compression device, or as a system architecture for a compression method. The computer system 100 includes a terminal 120 and a server 140.

[0071] In some embodiments, terminal 120 includes the compression device of this embodiment, or terminal 120 includes a chip, and the chip includes the compression device of this embodiment. Terminal 120 may be an electronic device such as a mobile phone, tablet computer, vehicle terminal (vehicle system), wearable device, PC (Personal Computer), unmanned reservation terminal, etc., and this application embodiment does not limit it to this.

[0072] In some embodiments, server 140 includes the compression device of this embodiment, or server 140 includes a board that includes the compression device of this embodiment. Server 140 may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud servers, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Server 140 may be a backend server for terminal 120, used to provide backend services for the data operation and processing of terminal 120.

[0073] Cloud technology refers to a hosting technology that unifies hardware, software, and network resources within a wide area network (WAN) or local area network (LAN) to achieve data computing, storage, processing, and sharing. Based on the cloud computing business model, cloud technology encompasses network technology, information technology, integration technology, management platform technology, and application technology. It can form resource pools, providing flexible and convenient on-demand access. Cloud computing technology will become a crucial support. Backend services of technical network systems require substantial computing and storage resources, such as video websites, image websites, and many portal websites. With the rapid development and application of the internet industry, every item may have its own identification mark in the future, requiring transmission to backend systems for logical processing. Data at different levels will be processed separately, and various industry data will require robust system support, which can only be achieved through cloud computing.

[0074] Optionally, server 140 can also be implemented as a node in a blockchain system. Blockchain is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and cryptographic algorithms. Essentially, a blockchain is a decentralized database, a chain of data blocks linked using cryptographic methods. Each data block contains information about a batch of network transactions, used to verify the validity of the information (anti-counterfeiting) and generate the next block. A blockchain can include a blockchain underlying platform, a platform product service layer, and an application service layer.

[0075] The terminal 120 and the server 140 can communicate via a network, such as a wired or wireless network. In the compression method provided in this application, the execution entity for each step can be a compression device in a computer device, including the terminal 120 and / or the server 140.

[0076] In a multithreaded processor, each thread can perform read and write operations on memory. These operations can be sequential or discrete. Discrete read and write operations can be categorized as completely random or predictable. In related technologies, for discrete read and write operations, memory access requests are sent to memory in units of cache lines via the bus. When the memory addresses in discrete memory access requests are not in the same cache line, multiple memory access requests need to be sent from the processor to memory via the bus to perform discrete read and write operations. For one of these multiple memory access requests, there may be a large number of unnecessary memory addresses that are invalid for the processor. This method of sending multiple memory access requests results in low bus utilization and low processor memory access performance.

[0077] Figure 2 This is a schematic diagram of a discrete memory access request provided in an exemplary embodiment of this application. 'a' represents a vector, 'mem' represents memory, 'BASE' represents the starting address of the memory access, and 'STRIDE' represents the interval between memory access addresses. Data read from memory is written into vector 'a', and the length of the entire vector 'a' is 32.

[0078] As an example, Figure 3 This is a schematic diagram illustrating the processing of related technologies provided in an exemplary embodiment of this application. Assume the memory access addresses for the discrete memory access requests are 1 / 5 / 9 / 13, meaning that a column of data in a matrix needs to be accessed in memory. When sending memory access requests in units of cache lines, assuming the width of a cache line is 4, reading data from memory access addresses 1 / 5 / 9 / 13 requires sending 4 memory access requests.

[0079] The four memory access requests are as follows: Memory access request 0, used to access the first cache line, which corresponds to memory addresses 0-3 (req0:0-3); Memory access request 1, used to access the second cache line, which corresponds to memory addresses 4-7 (req1:4-7); Memory access request 2, used to access the third cache line, which corresponds to memory addresses 8-11 (req2:8-11); Memory access request 3, used to access the fourth cache line, which corresponds to memory addresses 12-15 (req3:12-15).

[0080] Within each of these four memory access requests, there may be a large number of unnecessary memory addresses that need to be accessed. Data at these unnecessary addresses is invalid for the processor. For example, for memory access request 0, the processor only needs to retrieve data from memory address 1, and does not need to retrieve data from memory addresses 0 / 2 / 3. That is, only access to memory address 1 is valid, and accesses to memory addresses 0 / 2 / 3 are invalid. For memory access request 1, the processor only needs to retrieve data from memory address 5, and does not need to retrieve data from memory addresses 0 / 2 / 3. That is, only access to memory address 5 is valid, and accesses to memory addresses 4 / 6 / 7 are invalid. For memory access request 2, the processor only needs to retrieve data from memory address 9, and does not need to retrieve data from memory addresses 8 / 10 / 11. That is, only access to memory address 9 is valid, and accesses to memory addresses 8 / 10 / 11 are invalid. For memory access request 3, the processor only needs to fetch data from memory address 13, and does not need to fetch data from memory addresses 12 / 14 / 15. That is, only the access to memory address 13 is valid, and the access to memory addresses 12 / 14 / 15 is invalid. This greatly wastes bus bandwidth and reduces bus utilization.

[0081] This application provides a request compression device suitable for equidistant memory access, in which hardware identifies the interval, or distance, between memory access addresses within a thread bundle. A thread bundle may include multiple threads, and each thread may include a discrete memory access request. Different memory access addresses in these discrete requests correspond to different cache lines in the memory. For discrete memory access requests with equidistant access, according to related technologies, multiple cache line access requests need to be sent. However, based on this application embodiment, these requests can be compressed into a single equidistant compressed request and sent to the bus. The bus routes the equidistant compressed request to the memory, which then decomposes the equidistant compressed request, sequentially obtains the required data, and packages this data back to the processor core.

[0082] As an example, Figure 4 This is a schematic diagram of the compression apparatus provided in an exemplary embodiment of this application. Assume the memory access addresses of the discrete memory access requests are 1 / 5 / 9 / 13, meaning that a column of data in a matrix in memory needs to be accessed, with a starting address of 1 and an equal interval of 4 between each memory access address. Then, based on the method of this embodiment, only one equal-interval compression request needs to be sent. This equal-interval compression request includes four fields: a starting address (start_addr) of 1, a width (size) of 1, a count of 4, and an interval (stride) of 4. The method of this embodiment can compress multiple memory access requests that would otherwise need to be sent into a single equal-interval compression request, improving bus utilization and thus enhancing the processor's memory access performance.

[0083] See below for detailed examples.

[0084] Figure 5 This is a schematic block diagram of a compression device 200 provided in an exemplary embodiment of this application. The compression device 200 includes: an arithmetic unit 10, a statistical unit 20, and a generation unit 30. The arithmetic unit 10 is connected to the statistical unit 20, and the statistical unit 20 is connected to the generation unit 30. Optionally, the connection can be a physical wiring connection or a communication connection.

[0085] Arithmetic unit 10 is used to perform operations on at least two memory access addresses in a memory access request and obtain an operation result. The operation result is used to indicate the interval between each pair of memory access addresses that are executed sequentially among the at least two memory access addresses. Each of the at least two memory access addresses corresponds to a cache line of memory.

[0086] A memory access request can also be called a memory access instruction. A memory access request is a discrete memory access request used to perform discrete read and write operations on memory. Optionally, a memory access request includes at least two memory access addresses (address, addr), each corresponding to a cache line in the memory. That is, the memory access request is used to request access to at least two cache lines in the memory; specifically, it can be used to request access to a memory access address for each of the at least two cache lines in the memory, to read data from that memory address. In some embodiments, the memory access request can be a vector memory access request (req_vector).

[0087] In some embodiments, memory access requests can be equally spaced discrete memory access requests. Equal spacing means that the interval between any two memory access addresses executed sequentially in a memory access request is equal. Equal spacing can also be called equally spaced. For example, if a memory access request is a discrete memory access request with memory access addresses 1 / 5 / 9 / 13, and the intervals between memory addresses 1 and 5, 5 and 9, and 9 and 13 are all 4, then this memory access request is an equally spaced discrete memory access request.

[0088] In other embodiments, memory access requests can also be partially equidistant discrete memory access requests. Partial equidistant means that a portion of the interval between any two memory access addresses executed sequentially in a memory access request is equal. For example, if the memory access requests are discrete, assuming the memory access addresses are 17 / 21 / 25 / 29 / 2 / 6 / 10 / 14, the intervals between memory addresses 17 and 21, 21 and 25, and 25 and 29 are all 4; the interval between memory address 29 and 2 is -27; and the intervals between memory addresses 2 and 6, 6 and 10, and 10 and 14 are all 4. Therefore, memory access addresses 17 / 21 / 25 / 29 are equidistant, and memory access addresses 2 / 6 / 10 / 14 are equidistant. This memory access request is a partially equidistant discrete memory access request.

[0089] In this embodiment, the arithmetic unit 10 determines the interval between each pair of memory access addresses executed sequentially in at least two memory access addresses within the memory access request. Optionally, it may further determine whether each pair of adjacent intervals is equal. It should also be noted that for two sequentially executed memory access addresses, the interval between these two memory access addresses refers to the address distance or address interval between the two memory access addresses, rather than the physical distance between their physical locations distributed in the chip. For example, the arithmetic unit 10 performs operations on at least two memory access addresses in the memory access request to obtain an operation result. The operation result is used to indicate the interval between each pair of sequentially executed memory access addresses within the at least two memory access addresses, where each of the at least two memory access addresses corresponds to a cache line in the memory. In some embodiments, the memory access request may be a vector memory access request (req_vector), and the operation result may also be represented by a vector.

[0090] In some embodiments, the result of the operation may include multiple numerical values. Optionally, the multiple numerical values ​​may be directly the intervals between every two memory accesses executed sequentially in at least two memory accesses, or they may be a first numerical value and / or a second numerical value. The first numerical value is used to indicate that two adjacent intervals are not equal in the intervals between every two memory accesses executed sequentially in at least two memory accesses. The second numerical value is used to indicate that two adjacent intervals are equal in the intervals between every two memory accesses executed sequentially in at least two memory accesses. In one example, the first numerical value may be 0, and the second numerical value may be 1.

[0091] The statistical unit 20 is used to calculate the results of the statistical operation and obtain statistical results. The statistical results are used to indicate the case where every two adjacent intervals are equal.

[0092] The calculation results are based on numerical representation, and the statistical results are obtained by statistically analyzing the numerical values ​​in the calculation results. The statistical unit 20 is used to statistically analyze the calculation results and obtain statistical results, which are used to indicate the cases where every two adjacent intervals are equal. Optionally, the statistical results are also used to indicate the cases where every two adjacent intervals are unequal. Since the intervals are calculated based on every two memory access addresses executed sequentially for memory access requests, two adjacent intervals involve the three memory access addresses executed sequentially for memory access requests. For example, if a memory access request includes four memory access addresses, the calculation results are used to indicate: the first interval between the first and second memory access addresses, the second interval between the second and third memory access addresses, and the third interval between the third and fourth memory access addresses. The statistical results are used to count the cases where the first and second adjacent intervals are equal or unequal, and the second and third adjacent intervals are equal or unequal.

[0093] Optionally, the statistical results include at least one of the following: the position and quantity of each value in the calculation result, the position of the memory access address corresponding to each value, and the position and quantity of identical values. In some embodiments, the statistical results can also be used to indicate the equidistant nature of the memory access request, or to indicate whether the memory access request is an equidistant discrete memory access request or a partially equidistant discrete memory access request. For example, when the statistical results indicate that every two adjacent intervals are equal, the memory access request is an equidistant discrete memory access request; when the statistical results indicate that some adjacent intervals are equal and some adjacent intervals are not equal, the memory access request is a partially equidistant discrete memory access request. The statistical results are also used to indicate the number and generation method of the required equidistant compressed requests. For example, when the statistical results indicate that every two adjacent intervals are equal, the memory access request can generate one equidistant compressed request; when the statistical results indicate that some adjacent intervals are equal and some adjacent intervals are not equal, the memory access request can generate two equidistant compressed requests.

[0094] The generation unit 30 is used to generate at least one equidistant compression request based on statistical results and memory access requests. The equidistant compression request is used to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0095] An equidistant compression request is generated based on statistical results and memory access requests, and is used to instruct read and write operations to be performed sequentially on at least two cache lines of memory. An equidistant compression request is characterized by equidistance, meaning that the interval between any two sequentially accessed memory addresses is equal; that is, for an equidistant compression request, the interval between any two sequentially accessed memory addresses is equal. Specifically, the generation unit 30 is used to generate at least one equidistant compression request based on statistical results and memory access requests, and the equidistant compression request is used to instruct read and write operations to be performed sequentially on at least two cache lines of memory.

[0096] In some embodiments, when the memory access request is an equally spaced discrete memory access request, there can be one equally spaced compression request; when the memory access request is a partially equally spaced discrete memory access request, there can be more than one equally spaced compression request, for example, two. The specific number of equally spaced compression requests needs to be determined based on the interval between every two memory access addresses executed sequentially in the memory access request, which can also be understood as being determined based on the calculation results and statistical results. The number of memory access addresses included in the equally spaced compression request also needs to be determined based on the calculation results and statistical results. This will be described in detail in the embodiments below.

[0097] In summary, the compression apparatus 200 provided in this application includes: an arithmetic unit 10, a statistical unit 20, and a generation unit 30. The arithmetic unit 10 is connected to the statistical unit 20, and the statistical unit 20 is connected to the generation unit 30. The arithmetic unit 10 performs calculations on at least two memory access addresses in a memory access request to obtain a calculation result. The calculation result indicates the interval between each pair of memory access addresses executed sequentially, and each of the at least two memory access addresses corresponds to a cache line in the memory. The statistical unit 20 performs statistical calculations on the calculation result to obtain a statistical result, which indicates the case where each pair of adjacent intervals is equal. The generation unit 30 generates at least one equidistant compression request based on the statistical result and the memory access request. The equidistant compression request indicates the sequential execution of read and write operations on at least two cache lines in the memory. Accordingly, a request compression device suitable for equidistant memory access is provided. When at least two memory access addresses in a memory access request each correspond to a cache line in the memory, the device identifies the interval between each pair of memory access addresses executed sequentially within the at least two memory access addresses, thereby compressing the equidistant memory access request into at least one equidistant compressed request. Compared to the prior art, which requires sending at least two cache line memory access requests to the bus to execute the memory access request, the number of equidistant compressed requests required is reduced, improving bus utilization and thus enhancing the processor's memory access performance.

[0098] In some embodiments, the result of the operation includes multiple numerical values. The target value is a value indicating that two adjacent intervals are not unequal within the intervals between each pair of memory accesses executed sequentially in at least two memory accesses; that is, the target value indicates that two adjacent intervals are not unequal within the intervals between each pair of memory accesses executed sequentially in at least two memory accesses. For example, the multiple numerical values ​​in the result of the operation include a first value and / or a second value. The first value indicates that two adjacent intervals are not unequal within the intervals between each pair of memory accesses executed sequentially in at least two memory accesses. The second value indicates that two adjacent intervals are equal within the intervals between each pair of memory accesses executed sequentially in at least two memory accesses. The target value is then the first value. In one example, the first value is 0.

[0099] Since the interval is calculated based on every two memory access addresses executed sequentially for each memory access request, two adjacent intervals involve three memory access addresses executed sequentially for each memory access request. Two adjacent intervals not being equal also indicates that among the three memory access addresses executed sequentially for each memory access request, there is an interval between two sequentially executed memory access addresses that is not equal to the interval between other sequentially executed memory access addresses.

[0100] For a memory access request, if the result of the memory access request does not include the target value, it means that the interval between every two memory access addresses executed sequentially in the memory access request is equal, and an equidistant compression request can be generated based on this memory access request. If the result of the memory access request includes at least one target value, it means that there is an interval between two memory access addresses executed sequentially in the memory access request that is not equal to the interval between other sequentially executed memory access addresses. This also indicates that the memory access request is a partially equidistant memory access request, and that it needs to generate two or more equidistant compression requests. In this case, the memory access request needs to be divided based on a boundary point (midx) to generate two or more equidistant compression requests, and this boundary point needs to be determined based on the location of the target value. It should also be noted that, in this embodiment, to ensure the benefits of equidistant compression, two equidistant compression requests are used as an example. In actual applications, the upper limit of the number of at least one equidistant compression request can be adjusted according to actual technical needs.

[0101] In some embodiments, the statistical results include: the position of the first target value in the target values ​​and the number of target values. The target value is used to indicate that two adjacent intervals are not equal. In one example, the target value is a first value, which is 0.

[0102] For example, the position of the first target value in the target values ​​is used to indicate the midpoint (midx) in the memory access request. The midpoint (midx) indicates from which position the memory access request is divided to obtain at least one equidistant compressed request. Alternatively, it can be understood as the dividing point between two equidistant compressed requests when the memory access request is divided into two equidistant compressed requests. The number of target values ​​indicates the specific number of at least one equidistant compressed requests that the memory access request needs to generate.

[0103] The generation unit 30 is used to determine the boundary point in the memory access request based on the position of the first target value in the target value; determine the number of at least one equidistant compression request based on the number of target values; and generate the number of equidistant compression requests based on the boundary point and the memory access request.

[0104] The target value indicates that in each of the two memory accesses executed sequentially within at least two memory access addresses, adjacent intervals are not equal. If the result of the memory access request does not include the target value, the memory access request is an equally spaced discrete memory access request. If the result of the memory access request includes the target value, the memory access request is a partially equally spaced discrete memory access request.

[0105] The midx delimiter indicates the position from which a memory access request is divided to obtain at least one equally spaced compaction request. Alternatively, it can be understood as the dividing point between two equally spaced compaction requests when a memory access request is divided into two equally spaced compaction requests. In some embodiments, the midx delimiter is associated with the position of the first target value among the target values.

[0106] For example, the first target value involves two intervals, which in turn involve three memory accesses executed sequentially within the memory access request. The demarcation point can be located between these three sequentially executed memory accesses. In one specific example, the demarcation point could be located between the last two of the three memory accesses. (See reference) Figure 14 The first target value refers to the first 0 in the comparison result, which corresponds to the third interval 4 and the fourth interval -27 in the subtraction result. The memory access addresses involved are specifically 25 / 29 / 2, so the dividing point is between 29 / 2.

[0107] Specifically, the generation unit 30 is configured to determine a boundary point in the memory access requests based on the position of the first target value; determine the number of at least one isometric compression requests based on the number of target values; and generate that number of isometric compression requests based on the boundary point and the memory access requests. In some embodiments, the target value is 0. Then the generation unit 30 is configured to determine a boundary point (midx) in the memory access requests based on the position of the first 0; determine the number of at least one isometric compression requests based on the number of 0s; and generate that number of isometric compression requests based on the boundary point and the memory access requests.

[0108] It should also be noted that determining the boundary point in the memory access request based on the position of the first target value is an optional step. Furthermore, determining the boundary point in the memory access request based on the position of the first target value, and determining the number of at least one equidistant compression request based on the number of target values, can be executed sequentially or simultaneously; there is no restriction on their execution order.

[0109] In this embodiment, the generation unit 30 can identify the equidistant nature of memory access requests based on statistical results, thereby determining the specific number of at least one equidistant compressed requests required for the memory access request and the boundary points within the memory access requests. This allows for the generation of a corresponding number of equidistant compressed requests, compressing the number of cache line memory access requests that would otherwise be required for the memory access request, resulting in fewer equidistant compressed requests. Furthermore, when the memory sequentially obtains the required data based on the equidistant compressed requests and packages this data to return to the processor core, this data is valid for the processor, further improving data processing efficiency.

[0110] The generation unit 30 is used to fill the field segments of the equidistant compression request based on the boundary point and at least two memory access addresses in the memory access request, and generate the number of equidistant compression requests; wherein the field segments of the equidistant compression request are used to indicate the content of the equidistant compression request.

[0111] Since equidistant compression requests are generated based on memory access requests, each equidistant compression request retains all or part of the memory access addresses from the memory access request. In some embodiments, multiple field segments are set for equidistant compression requests. After determining the number of equidistant compression requests and the boundary points in the memory access requests, the corresponding number of equidistant compression requests can be obtained by filling these field segments. The generation unit 30 is used to fill the field segments of the equidistant compression requests based on the boundary points and at least two memory access addresses in the memory access requests, thereby generating the specified number of equidistant compression requests.

[0112] The field segment of the equal-width compression request is used to indicate the content of the equal-width compression request. Specifically, the field segment of the equal-width compression request includes at least one of the following: start address (start_addr); width (size); count; stride.

[0113] Here, the starting address is the first memory access address in the equal-distance compression request, the width is the width of the memory access addresses in the equal-distance compression request, the number is the total number of memory access addresses in the equal-distance compression request, and the interval is the interval between every two memory access addresses executed sequentially in the equal-distance compression request.

[0114] For example, if the memory access request is a discrete memory access request, assuming the memory access addresses are 1 / 5 / 9 / 13, meaning it needs to access a column of data in a matrix in memory, starting at address 1, and the intervals between each memory access address are all 4 (equidistant), then an equidistant compressed request can be generated. This equidistant compressed request includes 4 domains: a start address (start_addr) of 1, a width (size) of 1, a count of 4, and an interval (stride) of 4.

[0115] In this embodiment, four field segments are set for the equidistant compression request. This allows for accurate representation of the equidistant compression request with as few field segments as possible, improving the accuracy and request generation efficiency. The generation unit 30 can fill these field segments with the delimiter and the specific memory access address in the memory access request to generate a corresponding number of equidistant compression requests. This reduces the number of cache line memory access requests that would otherwise be required for the memory access request, generating fewer equidistant compression requests, avoiding wasting bus transmission bandwidth, and improving bus utilization.

[0116] It should also be noted that the names, formats, contents, and orders of the various fields in the isometric compression request in this embodiment are only examples and not limitations. Based on the field settings of this isometric compression request, changes can be made to the names, formats, contents, and orders of the various fields, which are not restricted here.

[0117] The following embodiments illustrate specific types of generation unit 30 and their methods for generating isometric compression requests. In practical applications, one or more of these methods can be selected and used according to actual technical needs.

[0118] Figure 6 This is a schematic block diagram of a compression device 200 provided in an exemplary embodiment of this application.

[0119] In some embodiments, the generation unit 30 includes a first generation (one comp request gen) unit 31. The first generation unit 31 may also be referred to as an isometric compression request generation unit.

[0120] The first generation unit 31 is used to determine that the number of at least one isometric compression request is one when the number of target values ​​is a first threshold.

[0121] The first memory access address in the memory access request is used as the starting address, the width of the memory access addresses in the memory access request is used as the width, the total number of memory access addresses in the memory access request is used as the quantity, and the interval between any two memory access addresses executed sequentially in the memory access request is used as the interval. These are used to fill the field segment of the equidistant compression request to obtain an equidistant compression request.

[0122] The target value and the first threshold can be set according to actual needs. In some embodiments, the target value is 0 and the first threshold is 0. That is, the result of the memory access request does not include the target value, and the memory access request is an equally spaced discrete memory access request. Then, this memory access request can generate an equally spaced compressed request.

[0123] Specifically, the first generation unit 31 is used to determine that the number of at least one equal-width compression request is one, given that the number of target values ​​is a first threshold. The first threshold means that the number of zeros in the result is zero, or that the result contains no zeros, or that all values ​​in the result are 1s. For the equal-width compression request's field segment: start address (start_addr); width (size); number (count); stride. The first memory access address in the memory access request is used as the start address (start_addr), the width of the memory access addresses in the memory access request is used as the width (size), the total number of memory access addresses in the memory access request is used as the number (count), and the interval between any two sequentially executed memory access addresses in the memory access request is used as the stride. These values ​​are then used to fill the equal-width compression request's field segment, resulting in one equal-width compression request.

[0124] In this embodiment, when the memory access request is a discrete memory access request with equal intervals, it can be compressed into a single compressed request by the first generation unit 31, which reduces the number of cache line memory access requests that originally need to be sent and can improve the utilization of the bus.

[0125] In some embodiments, the generation unit 30 includes a second generation unit 32, which is connected in parallel with the first generation unit 31. The second generation unit 32 may also be referred to as two equidistant compression request generation units.

[0126] The second generation unit 32 is used to determine that the number of equal-distance compression requests is two when the number of target values ​​is greater than the first threshold and less than the second threshold.

[0127] Take the first memory access address in the memory access request before the delimiter as the starting address, take the width of the memory access address in the memory access request as the width, take half of the total number of memory access addresses in the memory access request as the quantity, and take the interval between any two memory access addresses executed sequentially before the delimiter in the memory access request as the interval. Fill the field segment of the equal-distance compression request to obtain the first equal-distance compression request in the two equal-distance compression requests.

[0128] Take the first memory access address after the delimiter in the memory access request as the starting address, take the width of the memory access addresses in the memory access request as the width, take half of the total number of memory access addresses in the memory access request as the quantity, and take the interval between any two memory access addresses executed sequentially after the delimiter in the memory access request as the interval. Fill the field segment of the equidistant compression request to obtain the second equidistant compression request of the two equidistant compression requests.

[0129] The target value, the first threshold, and the second threshold can be set according to actual needs. In some embodiments, the target value is 0, the first threshold is 0, and the second threshold is 3. That is, if the result of the memory access request includes the target value, and the target value is greater than 0 and less than 3, the memory access request is a partially equidistant discrete memory access request. Then, this memory access request can generate two equidistant compressed requests, each of which includes half of the memory addresses from at least two memory access addresses in the memory access request.

[0130] The second generation unit 32 is used to determine that the number of equal-distance compression requests is two when the number of target values ​​is greater than a first threshold and less than a second threshold. The number of target values ​​being greater than the first threshold and less than the second threshold means that the number of zeros in the calculation result is greater than 0 and less than 3, or it can be understood as the calculation result including zeros in addition to 1s, and the number of zeros being greater than 0 and less than 3.

[0131] For the field segment of the equidistant compression request: start address (start_addr); width (size); number (count); stride. The first memory access address in the memory access request before the boundary point (midx) is taken as the start address (start_addr), the width of the memory access addresses in the memory access request is taken as the width (size), half the total number of memory access addresses in the memory access request is taken as the number (count), and the interval between any two memory access addresses executed sequentially before the boundary point in the memory access request is taken as the stride. These are used to fill the field segment of the equidistant compression request, resulting in the first equidistant compression request of the two equidistant compression requests.

[0132] The first memory access address after the delimiter (midx) in the memory access request is taken as the starting address (start_addr), the width of the memory access addresses in the memory access request is taken as the width (size), half of the total number of memory access addresses in the memory access request is taken as the count (count), and the interval between any two memory access addresses executed sequentially after the delimiter in the memory access request is taken as the stride. These are used to fill the field segment of the equidistant compression request, resulting in the second equidistant compression request of the two equidistant compression requests.

[0133] In this embodiment, when the memory access request is a partially equidistant discrete memory access request, it can be compressed into two equidistant compressed requests by the second generation unit 32, which reduces the number of cache line memory access requests that originally need to be sent and can improve the utilization of the bus.

[0134] In some embodiments, the generation unit 30 further includes a third generation (normal request generation) unit 33, which is connected in parallel with the first generation unit 31 and the second generation unit 32. The third generation unit 33 may also be referred to as a normal memory access request generation unit, or a cache line memory access request generation unit.

[0135] The third generation unit 33 is used to generate at least two cache line access requests corresponding to the access request, based on the cache lines corresponding to at least two access addresses in the access request, in units of cache lines, when the number of target values ​​is greater than or equal to the second threshold.

[0136] The target value and the second threshold can be set according to actual needs. In some embodiments, the target value is 0 and the second threshold is 3. That is, if the result of the memory access request includes the target value and the target value is greater than 3, then the memory access request cannot be represented as two equally spaced compression requests. In this case, the benefit of using equally spaced compression is small, and the utilization of the bus is still not high. Therefore, a cache line memory access request is generated based on the cache line.

[0137] The third generation unit 33 is configured to, when the number of target values ​​is greater than or equal to the second threshold, generate at least two cache line access requests corresponding to the memory access request, based on the cache lines corresponding to at least two memory access addresses in the memory access request, on a cache line basis. Each of the at least two cache line access requests corresponds to a cache line in the memory, and each cache line access request is used to instruct a read / write operation to be performed on a cache line in the memory.

[0138] In this embodiment, when a memory access request cannot be represented as two equally spaced compressed requests, the third generation unit 33 can send the request in the original manner, which is based on cache lines, thus ensuring the accuracy of the sent cache line memory access requests.

[0139] Figure 7 This is a schematic block diagram of a compression device 200 provided in an exemplary embodiment of this application.

[0140] In some embodiments, after generating one or two isometric compression requests or at least two cache line access requests, they need to be selected and sent to memory via a bus. For example, the compression device 200 further includes a multiplexer (MUX) 40, with a first generation unit 31, a second generation unit 32, and a third generation unit 33 respectively connected to the multiplexer 40.

[0141] Multiplexer 40 is used to send at least one equidistant compression request or at least two cache line access requests to the bus to route at least one equidistant compression request or at least two cache line access requests to the memory via the bus to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0142] Specifically, the multiplexer 40 is used to send at least one equidistant compression request or at least two cache line access requests to the bus to route at least one equidistant compression request or at least two cache line access requests to the memory via the bus, so as to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0143] The memory is used to break down at least one equidistant compression request or at least two cache line access requests, execute each access address sequentially to obtain the accessed data, and pack the data and return it to the processor.

[0144] In this embodiment, the multiplexer 40 selects the equidistant compression request or the cache line access request and sends it to the memory via the bus, ensuring the accuracy of selection and transmission.

[0145] Figure 8 This is a schematic block diagram of a compression device 200 provided in an exemplary embodiment of this application.

[0146] In some embodiments, the statistics unit 20 includes: a first target value detection unit 21 and a target value count unit 22. In one example, the target value is 0, the first target value detection unit 21 can be specifically implemented as a first zero detect (fzd) unit 23, and the target value count unit 22 can be specifically implemented as a population count (ppc) unit 24.

[0147] The arithmetic unit 10 is connected to the first target value detection unit 21 and the target value quantity statistics unit 22. The first target value detection unit 21 is connected to the generation unit 30 and the target value quantity statistics unit 22 is connected to the multiplexer 40.

[0148] The first target value detection unit 21 is used to detect the position of the first target value in the calculation result. The position of the first target value is used to indicate the boundary point in the memory access request.

[0149] For example, the first target value detection unit 21 is used to detect the position of the first target value in the calculation result. Specifically, it can start from the leftmost part of the calculation result and detect the position of the first target value in the calculation result in a left-to-right order. Alternatively, it can be understood as starting from the least significant bit in the calculation result and detecting the position of the first target value in the calculation result in a low-to-high order. The position of the first target value is used to indicate the boundary point in the memory access request.

[0150] The target value count unit 22 is used to count the number of target values ​​in the calculation results.

[0151] For example, the target value count unit 22 is used to count the number of target values ​​in the calculation result. The number of target values ​​indicates the specific number of at least one isometric compression request.

[0152] In this embodiment, by using the target value in the statistical calculation results, relevant information can be provided for the generation method and number of isometric compression requests, thereby improving the accuracy of the generated at least one isometric compression request.

[0153] Figure 9 This is a schematic block diagram of a compression device 200 provided in an exemplary embodiment of this application.

[0154] In some embodiments, at least two memory addresses in a memory access request are N. The arithmetic unit 10 includes: N-1 subtraction subtractors 11 and N-2 comparators 12; the i-th subtractor 11 and the (i+1)-th subtractor 11 of the N-1 subtraction subtractors 11 are each connected to the i-th comparator 12 of the N-2 comparators 12, where N is greater than or equal to 2, and i is greater than 0 and less than or equal to N-2.

[0155] For example, suppose there are at least 8 memory access addresses in the memory access request. Then there are 7 subtractors 11 and 6 comparators 12. The first subtractor 11 and the second subtractor 11 are both connected to the first comparator 12, the second subtractor 11 and the third subtractor 11 are both connected to the second comparator, and so on. Specifically, the first subtractor 11 performs a subtraction operation on the first and second memory access addresses to obtain the first interval. The second subtractor 11 performs a subtraction operation on the second and third memory access addresses to obtain the second interval. The third subtractor 11 performs a subtraction operation on the third and fourth memory access addresses to obtain the third interval, and so on. The first comparator 12 is used to compare whether the first interval and the second interval are equal, the second comparator 12 is used to compare whether the second interval and the third interval are equal, and so on.

[0156] N-1 subtractors 11 are used to extract N memory access addresses from the memory access request, and perform subtraction operations on every two memory access addresses in sequence to obtain the subtraction result, which includes N-1 intervals.

[0157] Specifically, N-1 subtractors 11 are used to extract N memory access addresses from the memory access request, and sequentially perform a subtraction operation on every two memory access addresses among the N memory access addresses to obtain a subtraction result, which includes N-1 intervals. Specifically, the subtraction operation involves subtracting the previous memory access address from the later memory access address in every two sequentially executed memory access addresses.

[0158] For example, for the first subtractor 11 and the second subtractor 11 in N-1 subtractors 11, the first subtractor 11 is used to perform a subtraction operation on the first memory access address and the second memory access address, subtracting the first memory access address from the second memory access address to obtain the first interval. The second subtractor 11 is used to perform a subtraction operation on the second memory access address and the third memory access address, subtracting the second memory access address from the third memory access address to obtain the second interval, and so on.

[0159] N-2 comparators 12 are used to perform comparison operations on every two adjacent intervals in N-1 intervals in turn to obtain the comparison results; the operation results are obtained based on the comparison results.

[0160] Specifically, N-2 comparators 12 are used to sequentially perform comparison operations on every two adjacent intervals in the N-1 intervals to obtain a comparison result; the operation result is obtained based on the comparison result. The comparison result includes whether the two adjacent intervals are equal or unequal. For example, for the first comparator 12 in the N-2 comparators 12, the first comparator 12 is used to compare whether the first interval and the second interval are equal, and so on.

[0161] In some embodiments, different comparison results can be assigned different operation results to obtain the operation result.

[0162] N-2 comparators 12 are used to determine the operation result corresponding to the comparison result as the second value if the comparison result shows that two adjacent intervals are equal, otherwise, determine the operation result corresponding to the comparison result as the first value.

[0163] Specifically, N-2 comparators 12 are used to determine the operation result corresponding to the comparison result as the second value if two adjacent intervals are equal; otherwise, the operation result corresponding to the comparison result is determined as the first value. The operation result includes N-2 values. In one example, the first value is 0 and the second value is 1.

[0164] In this embodiment, the subtractor 11 can identify the interval between each pair of memory access addresses executed sequentially in at least two memory access addresses in a memory access request, and the comparator 12 can compare whether the intervals are equal to identify the equidistant nature of the memory access requests. By assigning values ​​when the intervals are equal and unequal respectively, the equidistant nature of the memory access requests can be accurately characterized, improving the accuracy of generating at least one equidistant compressed request in the future.

[0165] As an example, the compression device 200 provided in the embodiments of this application is described in detail below with reference to the schematic diagram.

[0166] 1. Product Realization

[0167] In the fields of chips, processors, high-performance processors, and high-performance AI processors, equidistant discrete access has a wide range of applications. For example, it is used in data-parallel computing and high-performance computing scenarios, such as image data processing, scientific computing, machine learning, and game data processing.

[0168] This application provides a request compression device suitable for equidistant access. For a discrete memory access request, multiple memory access requests that would normally be generated according to a cache line are compressed into at least one equidistant compressed request. This reduces the number of memory access requests that would normally need to be generated and sent via the bus, improving bus utilization and request generation efficiency. The device offers high performance and effectively enhances product competitiveness.

[0169] 2. Technical Implementation

[0170] Figure 10 This is a schematic diagram of the overall architecture of a compression device 200 provided in an exemplary embodiment of this application.

[0171] Taking a memory access request as a vector memory access request (req_vector) with a vector length of 8 as an example, the 8 memory access addresses (addr) in the vector memory access request (req_vector) are represented as: memory address 0 (addr[0]), memory address 1 (addr[1]), memory address 2 (addr[2]), memory address 3 (addr[3]), memory address 4 (addr[4]), memory address 5 (addr[5]), memory address 6 (addr[6]), and memory address 7 (addr[7]). Each of these 8 memory access addresses corresponds to a cache line in the memory. It should also be noted that the vector length can be arbitrarily extended according to actual technical needs, chip computing power, requirements, etc.

[0172] The compression device 200 includes: 7 subtractors 11, 6 comparators 12, a first zero detect (fzd) unit 23, a population count (ppc) unit 24, a first generation unit (one comp req gen) 31, a second generation unit (two comp req gen) 32, a third generation unit (normal req gen) 33, and a multiplexer (MUX) 40.

[0173] The first subtractor 11 and the second subtractor 11 are connected to the first comparator 12, the second subtractor 11 and the third subtractor 11 are connected to the second comparator 12, and so on. The six comparators 12 are respectively connected to the first zero detection unit 23 and the zero count unit 24. The first generation unit 31, the second generation unit 32, and the third generation unit 33 are connected in parallel, and are also respectively connected to the multiplexer 40. The first zero detection unit 23 is connected to the parallel first generation unit 31, the second generation unit 32, and the third generation unit 33, and the zero count unit 24 is connected to the multiplexer 40.

[0174] The vector memory access request input (req_vector_in) enters the compression device 200. Eight memory access addresses (addr) are extracted from the vector memory access request (req_vector). These eight memory access addresses (addr) are fed into seven subtractors 11 to perform a subtraction operation on each pair of memory access addresses (addr) in sequence, that is, to perform a subtraction operation between adjacent elements of these eight memory access addresses (addr). Among them, the first subtractor 11 is used to perform a subtraction operation on memory access address 0 (addr[0]) and memory access address 1 (addr[1]) to obtain the first interval; the second subtractor 11 is used to perform a subtraction operation on memory access address 1 (addr[1]) and memory access address 2 (addr[2]) to obtain the second interval, and so on, to obtain a total of seven intervals.

[0175] These seven intervals are fed into six comparators 12 to perform a comparison operation on every two adjacent intervals, i.e., comparing two adjacent subtraction results. Specifically, the first comparator 12 compares the first and second intervals; the second comparator 12 compares the second and third intervals, and so on, resulting in six comparison results. A value of 1 is assigned when the two intervals are equal, and a value of 0 is assigned when they are unequal. These comparison results are represented as a comparison result vector (cmp_vector) with a width of 6 bits. The first zero detection unit 23 detects the position of the first 0 in the comparison result vector to determine the boundary point (midx), and the zero count unit 24 counts the number of 0s in the comparison result vector.

[0176] Based on the number of 0s and 1s in the comparison result vector, there are three cases:

[0177] (1) If all values ​​in the comparison result vector are 1, it means that the intervals between the input memory access addresses are all equal, and they are compressed into an equal-distance compression request. The compression of the request is performed by the first generation unit 31.

[0178] (2) If the number of 0s in the comparison result vector is less than 3, it means that the interval between the input memory access addresses is partially equal, and it is compressed into two equal-interval compression requests. The compression of the requests is performed by the second generation unit 32.

[0179] (3) If the number of 0s in the comparison result vector is greater than or equal to 3, it means that the input memory access address cannot be represented as two equally spaced compression requests. At this time, the benefit of equally spaced compression is small. The third generation unit 33 performs the generation based on cache line requests to generate multiple cache line memory access requests.

[0180] Example 1: Figure 11This is a schematic diagram of equidistant memory access provided in an exemplary embodiment of this application. Figure 12 This is a schematic diagram of the processing of a compression device provided in an exemplary embodiment of this application.

[0181] refer to Figure 11 The eight memory addresses (addr) in the vector memory access request (req_vector) are represented as: memory address 0 (addr[0]), memory address 1 (addr[1]), memory address 2 (addr[2]), memory address 3 (addr[3]), memory address 4 (addr[4]), memory address 5 (addr[5]), memory address 6 (addr[6]), and memory address 7 (addr[7]). Among them, addr[0] = 1; addr[1] = 5; addr[2] = 9; addr[3] = 13; addr[4] = 17; addr[5] = 21; addr[6] = 25; and addr[7] = 29.

[0182] The vector memory access request needs to access a column of data in a matrix, starting at address 1, with all memory access addresses spaced equally. The first generation unit 31 performs compression of the request. (See reference) Figure 12 If the subtraction result is all 4 and the comparison result is all 1, it indicates that the vector memory access request is equidistant. Therefore, the equidistant compressed request generated by the first generation unit 31 includes four fields: a start address (start_addr) of 1, a width (size) equal to the width of each memory access address (1 byte), a count of 8, and a stride of 4, representing the interval between two adjacent memory access addresses. Accordingly, the multiple memory access requests that would normally be sent for a vector memory access request are compressed into a single equidistant compressed request.

[0183] Example 2: Figure 13 This is a schematic diagram of equidistant memory access provided in an exemplary embodiment of this application; Figure 14 This is a schematic diagram of the processing of a compression device provided in an exemplary embodiment of this application.

[0184] refer to Figure 13The eight memory addresses (addr) in the vector memory access request (req_vector) are represented as: memory address 0 (addr[0]), memory address 1 (addr[1]), memory address 2 (addr[2]), memory address 3 (addr[3]), memory address 4 (addr[4]), memory address 5 (addr[5]), memory address 6 (addr[6]), and memory address 7 (addr[7]). Among them, addr[0] = 17; addr[1] = 21; addr[2] = 25; addr[3] = 29; addr[4] = 2; addr[5] = 6; addr[6] = 10; and addr[7] = 14.

[0185] The vector memory access request needs to access a partially equidistant vector, starting at address 17. After the memory access address increments to 29, the memory access address starts incrementing from 2. This situation can be compressed into two equidistant compressed requests, and the second generation unit 32 performs the compression of the requests. (Reference) Figure 14 The subtraction result is 4 except for the third one which is -27. The comparison result is 1 except for the middle two which are 0. This means that the vector memory access request can be divided into two equally spaced compression requests. The first zero detection unit 23 finds the position of the first 0 in the comparison result vector to determine the dividing point (midx) between the two equally spaced compression requests. The dividing point (midx) is located between addr[3] = 29 and addr[4] = 2. Then the second generation unit 32 generates two equally spaced compression requests. The first equally spaced compression request includes 4 fields: the starting address (start_addr) is 17, the width (size) is the width of each memory access address, which is 1 byte, the count is 4, and the stride is 4, which is the interval between two adjacent memory access addresses before the dividing point (midx). The second equidistant compression request consists of four segments: a start address (start_addr) of 2, a width (size) equal to the width of each memory access address (1 byte), a count of 4, and a stride of 4, which is the interval between two adjacent memory access addresses after the midx delimiter. Therefore, the multiple memory access requests that would normally be sent in a vector memory access request are compressed into two equidistant compression requests.

[0186] In other cases, if it's impossible to compress the vector memory access request with fewer equidistant compression requests, the third generation unit 33 directly generates a cache line access request. The zero count unit 24 counts the number of 0s in the comparison result vector. If the number of 0s is 0, one equidistant compression request generated by the first generation unit 31 is selected; if the number of 0s is less than 3 and greater than 0, two equidistant compression requests generated by the second generation unit 32 are selected; otherwise, multiple cache line memory access requests generated by the third generation unit 33 are used. A multiplexer 40 selects among the three, and the selected request is sent to the bus as a vector memory access request output (mem_req_out) to be routed to the memory, indicating that read and write operations should be performed sequentially on at least two cache lines.

[0187] It should be noted that all the units, devices, queues, and connections involved in this overall architecture diagram can be implemented using various hardware such as corresponding components, connecting lines or connecting circuits, and logic circuits.

[0188] In summary, the embodiments of this application provide a request compression device suitable for equidistant memory access. The device identifies the equidistant nature of the vector memory access request (req_vector) by hardware, compresses it into at least one equidistant compressed request, and sends it to the memory via the bus, thereby improving bus utilization and achieving higher performance.

[0189] Figure 15 This is a flowchart of a compression method provided in an exemplary embodiment of this application. The method is executed by a compression device, which may be located in a chip, board, or computer device. The compression device includes: an arithmetic unit, a statistical unit, and a generation unit; the arithmetic unit is connected to the statistical unit, and the statistical unit is connected to the generation unit. The compression method applied to the compression device includes at least some of the steps 320, 340, and 360.

[0190] Step 320: The arithmetic unit performs operations on at least two memory access addresses in the memory access request and obtains the operation result. The operation result is used to indicate the interval between each pair of memory access addresses that are executed sequentially among the at least two memory access addresses. Each of the at least two memory access addresses corresponds to a cache line of the memory.

[0191] Step 340: The statistical unit performs statistical calculations to obtain statistical results, which are used to indicate the cases where every two adjacent intervals are equal.

[0192] Step 360: Based on the statistical results and memory access requests, the generation unit generates at least one equidistant compression request, which is used to indicate that read and write operations are performed sequentially on at least two cache lines of the memory.

[0193] In summary, the compression method provided in this application involves an arithmetic unit performing operations on at least two memory access addresses in a memory access request to obtain an operation result. This result indicates the interval between each pair of memory access addresses executed sequentially, with each of the at least two memory access addresses corresponding to a cache line in the memory. A statistical unit calculates the operation result to obtain a statistical result, indicating the case where each pair of adjacent intervals is equal. A generation unit generates at least one equidistant compression request based on the statistical result and the memory access request. This equidistant compression request indicates the sequential execution of read and write operations on at least two cache lines in the memory. Accordingly, a request compression apparatus and method suitable for equidistant memory access are provided. When at least two memory access addresses in a memory access request each correspond to a cache line in the memory, identifying the interval between each pair of memory access addresses executed sequentially can compress equidistant memory access requests into at least one equidistant compression request. Compared to existing technologies that require sending at least two cache line memory access requests to the bus to execute the memory access request, this method requires fewer equidistant compressed requests, improving bus utilization and thus enhancing the processor's memory access performance.

[0194] In some embodiments, the statistical results include: the position of the first target value in the target values, the number of target values, and the target values ​​used to indicate that two adjacent intervals are not equal; step 360 can be specifically implemented as step 362:

[0195] Step 362: The generation unit determines the boundary point in the memory access request based on the position of the first target value in the target value; determines the number of at least one equidistant compression request based on the number of target values; and generates that number of equidistant compression requests based on the boundary point and the memory access request.

[0196] It should also be noted that determining the boundary point in the memory access request based on the position of the first target value is an optional step. Furthermore, determining the boundary point in the memory access request based on the position of the first target value, and determining the number of at least one equidistant compression request based on the number of target values, can be executed sequentially or simultaneously; there is no restriction on their execution order.

[0197] In this embodiment, the generation unit can identify the equidistant nature of memory access requests based on statistical results, thereby determining the specific number of at least one equidistant compressed requests required for the memory access request and the boundary points within the memory access requests. This allows for the generation of a corresponding number of equidistant compressed requests, compressing the number of cache line access requests that would otherwise be required for the memory access request, resulting in fewer equidistant compressed requests. Furthermore, when the memory sequentially obtains the required data based on the equidistant compressed requests and packages this data to return to the processor core, this data is valid for the processor, further improving data processing efficiency.

[0198] In some embodiments, step 362, the generation unit generates the number of equidistant compression requests based on the boundary point and the memory access request, which can be specifically implemented as step 364:

[0199] Step 364: The generation unit fills the field segment of the equidistant compression request based on the boundary point and at least two memory access addresses in the memory access request, and generates the number of equidistant compression requests; wherein, the field segment of the equidistant compression request is used to indicate the content of the equidistant compression request.

[0200] A field segment of an equal-distance compression request includes at least one of the following: starting address; width; number; interval; wherein the starting address is the first memory access address in the equal-distance compression request, the width is the width of the memory access addresses in the equal-distance compression request, the number is the total number of memory access addresses in the equal-distance compression request, and the interval is the interval between every two memory access addresses executed sequentially in the equal-distance compression request.

[0201] In this embodiment, four field segments are set for the equidistant compression request. This allows for accurate representation of the equidistant compression request with as few field segments as possible, improving the accuracy and request generation efficiency. The generation unit can fill these field segments with the delimiter and the specific memory access address in the memory access request to generate a corresponding number of equidistant compression requests. This reduces the number of cache line memory access requests that would otherwise be required for the memory access request, generating fewer equidistant compression requests, avoiding wasting bus transmission bandwidth, and improving bus utilization.

[0202] In some embodiments, the generation unit includes: a first generation unit; step 364 is specifically implemented as step 3641:

[0203] Step 3641: When the number of target values ​​is a first threshold, the first generation unit determines that the number of at least one isometric compression request is one.

[0204] The first memory access address in the memory access request is used as the starting address, the width of the memory access addresses in the memory access request is used as the width, the total number of memory access addresses in the memory access request is used as the quantity, and the interval between any two memory access addresses executed sequentially in the memory access request is used as the interval. These are used to fill the field segment of the equidistant compression request to obtain an equidistant compression request.

[0205] In this embodiment, when the memory access request is a discrete memory access request with equal intervals, it can be compressed into a single compressed request with equal intervals by the first generation unit, which reduces the number of cache line memory access requests that originally need to be sent and can improve the utilization of the bus.

[0206] In some embodiments, the generating unit includes: a second generating unit, the second generating unit being connected in parallel with the first generating unit; step 364 is specifically implemented as step 3642:

[0207] Step 3642: If the number of target values ​​is greater than the first threshold and less than the second threshold, the second generation unit determines that the number of equal-distance compression requests is two.

[0208] Take the first memory access address in the memory access request before the delimiter as the starting address, take the width of the memory access address in the memory access request as the width, take half of the total number of memory access addresses in the memory access request as the quantity, and take the interval between any two memory access addresses executed sequentially before the delimiter in the memory access request as the interval. Fill the field segment of the equal-distance compression request to obtain the first equal-distance compression request in the two equal-distance compression requests.

[0209] Take the first memory access address after the delimiter in the memory access request as the starting address, take the width of the memory access addresses in the memory access request as the width, take half of the total number of memory access addresses in the memory access request as the quantity, and take the interval between any two memory access addresses executed sequentially after the delimiter in the memory access request as the interval. Fill the field segment of the equidistant compression request to obtain the second equidistant compression request of the two equidistant compression requests.

[0210] In this embodiment, when the memory access request is a partially equidistant discrete memory access request, it can be compressed into two equidistant compressed requests by the second generation unit, which reduces the number of cache line memory access requests that originally need to be sent and can improve the utilization of the bus.

[0211] In some embodiments, the generation unit further includes: a third generation unit, which is connected in parallel with the first generation unit and the second generation unit; the compression method further includes step 370:

[0212] Step 370: If the number of target values ​​is greater than or equal to the second threshold, the third generation unit generates at least two cache line access requests corresponding to the access requests, based on the cache lines corresponding to at least two access addresses in the access request, in units of cache lines.

[0213] In this embodiment, when a memory access request cannot be represented as two equally spaced compressed requests, the third generation unit can send the requests in the original manner, which is based on cache lines, thus ensuring the accuracy of the sent cache line memory access requests.

[0214] In some embodiments, the compression apparatus further includes a multiplexer, with the first generation unit, the second generation unit, and the third generation unit respectively connected to the multiplexer; after steps 360 and 370, the compression method further includes step 380:

[0215] In step 380, the multiplexer sends at least one equidistant compression request or at least two cache line access requests to the bus to route at least one equidistant compression request or at least two cache line access requests to the memory via the bus, so as to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

[0216] In this embodiment, a multiplexer is used to select either the equidistant compression request or the cache line access request, and the request is sent to the memory via the bus, ensuring the accuracy of selection and transmission.

[0217] In some embodiments, the statistical unit includes: a first target value detection unit, a target value quantity statistics unit, an arithmetic unit connected to the first target value detection unit, an arithmetic unit also connected to the target value quantity statistics unit, the first target value detection unit connected to the generation unit, and the target value quantity statistics unit connected to a multiplexer; step 340 is specifically implemented as steps 342 and 344:

[0218] Step 342: The target value quantity statistics unit counts the number of target values ​​in the calculation results;

[0219] Step 344: The first target value detection unit detects the position of the first target value in the calculation result. The position of the first target value is used to indicate the boundary point in the memory access request.

[0220] In this embodiment, by using the target value in the statistical calculation results, relevant information can be provided for the generation method and number of isometric compression requests, thereby improving the accuracy of the generated at least one isometric compression request.

[0221] In some embodiments, at least two memory addresses in the memory access request are N, and the arithmetic unit includes: N-1 subtractors and N-2 comparators; the i-th subtractor and the (i+1)-th adjacent subtractor in the N-1 subtractors are each connected to the i-th comparator in the N-2 comparators, where N is greater than or equal to 2, and i is greater than 0 and less than or equal to N-2; step 320 is specifically implemented as steps 322 and 324:

[0222] Step 322: N-1 subtractors extract N memory access addresses from the memory access request, and sequentially perform subtraction operations on every two memory access addresses among the N memory access addresses to obtain the subtraction result, which includes N-1 intervals.

[0223] Step 324: N-2 comparators sequentially perform comparison operations on two adjacent intervals in N-1 intervals to obtain the comparison results; the calculation result is obtained based on the comparison results.

[0224] In some embodiments, the N-2 comparators in step 324 obtain the operation result based on the comparison result, specifically implemented as step 3241:

[0225] Step 3241: If the comparison results of the N-2 comparators show that two adjacent intervals are equal, the operation result corresponding to the comparison result is determined to be the second value; otherwise, the operation result corresponding to the comparison result is determined to be the first value.

[0226] In this embodiment, a subtractor can identify the interval between each pair of memory access addresses executed sequentially in at least two memory access addresses within a memory access request. A comparator can compare whether the intervals are equal, thus identifying the equidistant nature of the memory access requests. By assigning values ​​separately when the intervals are equal and unequal, the equidistant nature of the memory access requests can be accurately characterized, improving the accuracy of generating at least one equidistant compressed request in the subsequent process.

[0227] It should also be noted that the description of the embodiments of the compression method can be found in the description of the embodiments of the compression device 200 provided in the above embodiments, and will not be repeated here.

[0228] This application provides a chip. Figure 16 This is a schematic block diagram of a chip provided in an exemplary embodiment of this application. Chip 500 includes the compression device 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a chip including programmable logic circuitry and / or program instructions, which, when run on a computer device, implements the compression method provided in the above method embodiment.

[0229] As an example, let's consider the application of chip 500 in image data processing. The image data that chip 500 needs to process is discrete in memory, not in the same cache line. Memory access requests are vector memory access requests (req_vector), where at least two memory access addresses in a vector memory access request each correspond to a cache line in memory. The compression device 200 in chip 500 identifies the interval between each two memory access addresses that are executed sequentially in the at least two memory access addresses, and compresses the vector memory access request into at least one equidistant compressed request. The at least one equidistant compressed request is routed to memory via a bus. The memory disassembles each equidistant compressed request of the at least one equidistant compressed request, obtains the accessed image data sequentially, packages all the image data, and returns it to the processor core so that chip 500 can obtain the image data required for processing.

[0230] This application provides a circuit board. Figure 17 This is a schematic block diagram of a board provided in an exemplary embodiment of this application. The board 600 includes the compression device 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a board that, when running on a computer device, is used to implement the compression method provided in the above method embodiment.

[0231] Specifically, a board, also known as a server board, is a type of printed circuit board (PCB). During manufacturing, it includes a connector that inserts into a slot on a server's motherboard to control hardware operations, such as monitors and data acquisition cards. After installing a driver or computer program on the board, it can perform its corresponding functions. This driver or computer program can be installed in the processor, which controls its execution, and in conjunction with the compression device 200, enables the board 600 to perform its functions.

[0232] This application provides a computer device. Figure 18 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 700 includes the compression device 200 provided in the above embodiment. Alternatively, an embodiment of this application provides a computer device. Figure 19 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 800 includes the chip 500 provided in the above embodiment, and the computer device 800 may optionally be implemented as a terminal. Alternatively, an embodiment of this application provides a computer device. Figure 20 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 900 includes the board 600 provided in the above embodiment, and the computer device 900 may be implemented as a server.

[0233] Optionally, embodiments of this application also provide a computer device, the computer device including: a processor and a memory, the memory storing a computer program; the processor is used to execute the computer program in the memory to implement the compression method provided in the above method embodiments.

[0234] Figure 21 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device is a server 1000. Typically, the server 1000 includes a processor 1001 and a memory 1002.

[0235] Processor 1001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a central processing unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1001 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0236] The memory 1002 may include one or more computer-readable storage media, which may be non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 are used to store at least one instruction, which is executed by the processor 1001 to implement the compression method provided in the method embodiments of this application.

[0237] In some embodiments, the server 1000 may optionally include an input interface 1003 and an output interface 1004. The processor 1001, memory 1002, and input interfaces 1003 and 1004 can be connected via a bus or signal lines. Various peripheral devices can be connected to the input interfaces 1003 and 1004 via a bus, signal lines, or a circuit board. The input interfaces 1003 and 1004 can be used to connect at least one input / output (I / O) related peripheral device to the processor 1001 and memory 1002. In some embodiments, the processor 1001, memory 1002, and input interfaces 1003 and 1004 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1001, memory 1002, and input interfaces 1003 and 1004 can be implemented on separate chips or circuit boards, and this application does not limit this.

[0238] Figure 22 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Optionally, the computer device 2000 is a terminal.

[0239] The computer device 2000 can be a portable mobile terminal, also referred to as a mobile terminal in this embodiment. Examples include smartphones, tablets, MP3 players (Moving Picture Experts Group Audio Layer III), and MP4 players (Moving Picture Experts Group Audio Layer IV). The computer device 2000 may also be referred to as user equipment, portable terminal, or other names.

[0240] Typically, a computer device 2000 includes a processor 2001 and a memory 2002.

[0241] Processor 2001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 2001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 2001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 2001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 2001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0242] The memory 2002 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 2002 may also include high-speed random access memory devices and non-volatile storage devices, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 2002 are used to store at least one instruction, which is executed by the processor 2001 to implement the compression method provided in the various method embodiments of this application.

[0243] In some embodiments, the computer device 2000 may optionally include a peripheral device interface 2003 and at least one peripheral device. Specifically, the peripheral device includes at least one of a radio frequency circuit 2004, a touch display screen 2005, a camera assembly 2006, an audio circuit 2007, and a power supply 2008. The computer device 2000 also includes one or more sensors 2009. The one or more sensors 2009 include, but are not limited to, an accelerometer 2010, a gyroscope 2011, a pressure sensor 2012, an optical sensor 2013, and a proximity sensor 2014.

[0244] Those skilled in the art will understand that Figure 16 The structure shown does not constitute a limitation on the chip. Figure 17 The structure shown does not constitute a limitation on the board. Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 The structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0245] This application provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the compression methods provided in the above-described method embodiments.

[0246] This application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the processor of the computer device to load and execute the compression method provided in the above-described method embodiments.

[0247] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0248] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0249] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0250] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A compression device, characterized in that, The compression device includes: an arithmetic unit, a statistical unit, and a generation unit, wherein the arithmetic unit is connected to the statistical unit, and the statistical unit is connected to the generation unit; The arithmetic unit is used to perform operations on at least two memory access addresses in the memory access request to obtain an operation result. The operation result is used to indicate the interval between each pair of memory access addresses that are executed sequentially among the at least two memory access addresses. Each of the at least two memory access addresses corresponds to a cache line of the memory. The statistical unit is used to calculate the calculation results and obtain statistical results, which are used to indicate the case where every two adjacent intervals are equal. The generation unit is configured to generate at least one equidistant compression request based on the statistical results and the memory access request. The equidistant compression request is used to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

2. The compression device according to claim 1, characterized in that, The statistical results include: the position of the first target value in the target values, and the number of target values, wherein the target values ​​are used to indicate that two adjacent intervals in the interval are not equal; The generation unit is configured to determine the boundary point in the memory access request based on the position of the first target value among the target values; determine the number of the at least one equidistant compression request based on the number of target values; and generate the number of equidistant compression requests based on the boundary point and the memory access request.

3. The compression device according to claim 2, characterized in that, The generation unit is used to fill the field segment of the equidistant compression request based on the boundary point and the at least two memory access addresses in the memory access request, and generate the number of equidistant compression requests. The field segment of the isometric compression request is used to indicate the content of the isometric compression request.

4. The compression device according to claim 3, characterized in that, The field segment of the equidistant compression request includes at least one of the following: starting address; width; number; interval; Wherein, the starting address is the first memory access address in the equal-distance compression request, the width is the width of the memory access addresses in the equal-distance compression request, the number is the total number of memory access addresses in the equal-distance compression request, and the interval is the interval between every two memory access addresses executed sequentially in the equal-distance compression request.

5. The compression device according to any one of claims 2 to 4, characterized in that, The generation unit includes: a first generation unit; The first generation unit is configured to determine that the number of the at least one isometric compression request is one when the number of the target values ​​is a first threshold. The first memory access address in the memory access request is taken as the starting address, the width of the memory access address in the memory access request is taken as the width, the total number of memory access addresses in the memory access request is taken as the number, and the interval between any two memory access addresses executed sequentially in the memory access request is taken as the interval. The field segment of the equidistant compression request is filled to obtain the equidistant compression request.

6. The compression device according to claim 5, characterized in that, The generation unit includes: a second generation unit, which is connected in parallel with the first generation unit; The second generation unit is configured to determine that the number of the equidistant compression requests is two when the number of the target values ​​is greater than the first threshold and less than the second threshold. The first memory access address in the memory access request before the demarcation point is taken as the starting address, the width of the memory access address in the memory access request is taken as the width, half of the total number of memory access addresses in the memory access request is taken as the quantity, and the interval between any two memory access addresses executed sequentially before the demarcation point in the memory access request is taken as the interval. The field segment of the equidistant compression request is filled to obtain the first equidistant compression request among the two equidistant compression requests. The first memory access address in the memory access request after the demarcation point is taken as the starting address, the width of the memory access address in the memory access request is taken as the width, half of the total number of memory access addresses in the memory access request is taken as the quantity, and the interval between any two memory access addresses executed sequentially after the demarcation point in the memory access request is taken as the interval. The field segment of the equidistant compression request is filled to obtain the second equidistant compression request of the two equidistant compression requests.

7. The compression device according to claim 6, characterized in that, The generation unit further includes: a third generation unit, which is connected in parallel with the first generation unit and the second generation unit; The third generation unit is used to generate at least two cache line access requests corresponding to the access request, based on the cache lines corresponding to the at least two access addresses in the access request, in units of cache lines, when the number of target values ​​is greater than or equal to the second threshold.

8. The compression device according to claim 7, characterized in that, The compression device further includes a multiplexer, wherein the first generation unit, the second generation unit, and the third generation unit are respectively connected to the multiplexer; The multiplexer is used to send the at least one equidistant compression request or the at least two cache line access requests to the bus, so as to route the at least one equidistant compression request or the at least two cache line access requests to the memory via the bus, so as to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

9. The compression device according to any one of claims 1 to 8, characterized in that, The statistical unit includes: a first target value detection unit and a target value quantity statistics unit. The arithmetic unit is connected to the first target value detection unit and is also connected to the target value quantity statistics unit. The first target value detection unit is connected to the generation unit, and the target value quantity statistics unit is connected to the multiplexer. The first target value detection unit is used to detect the position of the first target value in the calculation result, and the position of the first target value is used to indicate the boundary point in the memory access request; The target value quantity counting unit is used to count the number of target values ​​in the calculation result.

10. The compression device according to any one of claims 1 to 9, characterized in that, The memory access request contains at least two memory access addresses, which are N. The arithmetic unit includes: N-1 subtractors and N-2 comparators; the i-th subtractor and the (i+1)-th adjacent subtractor in the N-1 subtractors are each connected to the i-th comparator in the N-2 comparators, where N is greater than or equal to 2, and i is greater than 0 and less than or equal to N-2. The N-1 subtractors are used to extract the N memory access addresses in the memory access request, and sequentially perform a subtraction operation on every two memory access addresses among the N memory access addresses to obtain the subtraction result, which includes N-1 intervals. The N-2 comparators are used to sequentially perform comparison operations on every two adjacent intervals in the N-1 intervals to obtain comparison results; and to obtain the operation result based on the comparison results.

11. The compression device according to claim 10, characterized in that, The N-2 comparators are used to determine the operation result corresponding to the comparison result as a second value if the comparison result shows that two adjacent intervals are equal, otherwise, to determine the operation result corresponding to the comparison result as a first value.

12. A chip, characterized in that, The chip includes: a compression device as described in any one of claims 1 to 11.

13. A circuit board, characterized in that, The board includes: a compression device as described in any one of claims 1 to 11.

14. A computer device, characterized in that, The computer device includes: a compression device as described in any one of claims 1 to 11, or a chip as described in claim 12, or a board as described in claim 13.

15. A compression method, characterized in that, The compression device includes: an arithmetic unit, a statistical unit, and a generation unit; the arithmetic unit is connected to the statistical unit, and the statistical unit is connected to the generation unit; the compression method applied to the compression device includes: The arithmetic unit performs operations on at least two memory access addresses in the memory access request to obtain an operation result. The operation result is used to indicate the interval between each pair of memory access addresses that are executed sequentially among the at least two memory access addresses. Each of the at least two memory access addresses corresponds to a cache line of the memory. The statistical unit calculates the calculation results to obtain statistical results, which are used to indicate the case where every two adjacent intervals are equal. Based on the statistical results and the memory access request, the generation unit generates at least one equidistant compression request, which is used to instruct read and write operations to be performed sequentially on at least two cache lines of the memory.

16. The compression method according to claim 15, characterized in that, The statistical results include: the position of the first target value in the target values, and the number of target values, wherein the target values ​​are used to indicate that two adjacent intervals in the interval are not equal; Based on the statistical results and the memory access request, the generation unit generates at least one equidistant compression request, including: The generation unit determines the boundary point in the memory access request based on the position of the first target value among the target values; determines the number of the at least one equidistant compression request based on the number of target values; and generates the number of equidistant compression requests based on the boundary point and the memory access request.

17. The compression method according to claim 16, characterized in that, The generation unit generates the specified number of equidistant compression requests based on the boundary point and the memory access request, including: The generation unit fills the field segment of the equidistant compression request based on the boundary point and the at least two memory access addresses in the memory access request, and generates the number of the equidistant compression requests. The field segment of the isometric compression request is used to indicate the content of the isometric compression request.

18. The compression method according to claim 17, characterized in that, The field segment of the equidistant compression request includes at least one of the following: starting address; width; number; interval; Wherein, the starting address is the first memory access address in the equal-distance compression request, the width is the width of the memory access addresses in the equal-distance compression request, the number is the total number of memory access addresses in the equal-distance compression request, and the interval is the interval between every two memory access addresses executed sequentially in the equal-distance compression request.

19. The compression method according to any one of claims 15 to 18, characterized in that, The generation unit includes: a first generation unit; The generation unit, based on the boundary point and the at least two memory access addresses in the memory access request, fills the field segments of the equidistant compression request to generate the specified number of equidistant compression requests, including: When the number of target values ​​is a first threshold, the first generation unit determines that the number of the at least one isometric compression request is one. The first memory access address in the memory access request is taken as the starting address, the width of the memory access address in the memory access request is taken as the width, the total number of memory access addresses in the memory access request is taken as the number, and the interval between any two memory access addresses executed sequentially in the memory access request is taken as the interval. The field segment of the equidistant compression request is filled to obtain the equidistant compression request.

20. The compression method according to claim 19, characterized in that, The generation unit includes: a second generation unit, which is connected in parallel with the first generation unit; The generation unit, based on the boundary point and the at least two memory access addresses in the memory access request, fills the field segments of the equidistant compression request to generate the specified number of equidistant compression requests, including: If the number of target values ​​is greater than the first threshold and less than the second threshold, the second generation unit determines that the number of equidistant compression requests is two. The first memory access address in the memory access request before the demarcation point is taken as the starting address, the width of the memory access address in the memory access request is taken as the width, half of the total number of memory access addresses in the memory access request is taken as the quantity, and the interval between any two memory access addresses executed sequentially before the demarcation point in the memory access request is taken as the interval. The field segment of the equidistant compression request is filled to obtain the first equidistant compression request among the two equidistant compression requests. The first memory access address in the memory access request after the demarcation point is taken as the starting address, the width of the memory access address in the memory access request is taken as the width, half of the total number of memory access addresses in the memory access request is taken as the quantity, and the interval between any two memory access addresses executed sequentially after the demarcation point in the memory access request is taken as the interval. The field segment of the equidistant compression request is filled to obtain the second equidistant compression request of the two equidistant compression requests.

Images