Preparation method of flash memory device
By depositing a word line protective layer of a predetermined thickness on the polysilicon surface of the word line and performing chemical mechanical polishing, the problem of poor uniformity of word line protective layer thickness in NORD flash memory devices is solved, improving wafer yield and reliability while reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-05-19
AI Technical Summary
In the fabrication process of NORD flash memory devices, the poor uniformity of the word line protective layer thickness affects wafer yield and reliability.
A word line protective layer of a predetermined thickness is deposited on the surface of the word line polysilicon, so that the upper surface of the second dielectric layer is higher than the upper surface of the word line protective layer directly above the word line polysilicon. The word line protective layer directly above the second dielectric layer is removed by chemical mechanical polishing, avoiding polishing and re-etching of the word line polysilicon, thus forming a flush word line protective layer.
It improves the uniformity of word line protective layer thickness, increases wafer yield and reliability, and reduces manufacturing costs.
Smart Images
Figure CN122069722A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a flash memory device. Background Technology
[0002] In the conventional fabrication process of NORD flash memory devices, the word line protective layer on the polysilicon surface of the word line is usually made through steps such as (1) etching back the word line polysilicon of a certain thickness → (2) depositing the word line protective layer → (3) smoothing the word line protective layer using chemical mechanical polishing → (4) wet etching back the word line protective layer. However, the word line protective layer is affected by various processes such as etching process, CVD process, CMP (chemical mechanical polishing) process, and wet etching process, resulting in poor uniformity of the thickness of the word line protective layer. Among them, in the thin position of the word line protective layer, there will be defects such as exposure of the polysilicon of the word line and pitting. In addition, in the thick position of the word line protective layer, there will be excess material residue of the word line protective layer. The excess residue of the word line protective layer makes it difficult for subsequent metal silicides to be deposited on the word line surface, resulting in a larger contact resistance Rc of the word line, which affects the wafer yield and reliability. Summary of the Invention
[0003] This application provides a method for fabricating a flash memory device, which can solve the problem of poor uniformity of word line protective layer thickness in the fabrication process of traditional NORD flash memory devices, which affects wafer yield and reliability.
[0004] This application provides a method for fabricating a flash memory device, including: A substrate is provided on which stacked pad oxide layers, floating gate layers, first dielectric layers, control gates, and first sidewalls are formed. Trenches are formed in the first sidewalls, the control gate, the first dielectric layer, and the floating gate layer. Second sidewalls are formed on the sidewalls of the trenches. Word line polysilicon is also filled in the trenches. A second dielectric layer is formed on the control gate and outside the first sidewalls. The upper surface of the second dielectric layer is higher than the upper surface of the first sidewalls and also higher than the upper surface of the word line polysilicon. A word line protection layer is formed, which covers the second dielectric layer, the first sidewall, and the word line polysilicon, wherein, after the word line protection layer is formed, the upper surface of the second dielectric layer is higher than the upper surface of the word line protection layer directly above the word line polysilicon; Grinding removes the word line protective layer directly above the second dielectric layer; A third dielectric layer is formed, which covers the second dielectric layer and the word line protection layer; A gate oxide layer is formed, which covers the third dielectric layer; A gate material layer is formed, the gate material layer covering the gate oxide layer; Remove the gate material layer, the gate oxide layer, a portion of the thickness of the third dielectric layer, and a portion of the thickness of the second dielectric layer. At this time, the word line protection layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer is exposed. The remaining thickness of the third dielectric layer covers a portion of the surface of the word line protection layer, and the upper surface of the remaining thickness of the third dielectric layer is flush with the upper surface of the remaining thickness of the second dielectric layer. Remove a portion of the word line protection layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer, so that the upper surface of the word line protection layer on the first sidewall surface is flush with the upper surface of the word line protection layer directly above the word line polysilicon. Remove the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer.
[0005] Optionally, in the method for fabricating the flash memory device, the thickness of the word line protective layer is 500 angstroms to 700 angstroms.
[0006] Optionally, in the method for fabricating the flash memory device, a chemical mechanical polishing process is used to remove the word line protective layer directly above the second dielectric layer.
[0007] Optionally, in the method for fabricating the flash memory device, a wet etching process is used to etch away a portion of the word line protection layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer.
[0008] Optionally, in the method for fabricating the flash memory device, a wet etching process is used to etch away the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer.
[0009] Optionally, in the method for fabricating the flash memory device, a dry etching process is used to etch and remove the gate material layer, the gate oxide layer, a portion of the third dielectric layer, and a portion of the second dielectric layer.
[0010] Optionally, in the method for fabricating the flash memory device, the first dielectric layer includes: a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, wherein the first silicon oxide layer covers the floating gate layer, the first silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the first silicon nitride layer.
[0011] Optionally, in the method for fabricating the flash memory device, the material of the second dielectric layer is silicon nitride.
[0012] Optionally, in the method for fabricating the flash memory device, the first sidewall is made of silicon dioxide.
[0013] Optionally, in the method for fabricating the flash memory device, the word line protective layer is made of silicon dioxide.
[0014] The technical solution of this application has at least the following advantages: This application provides a method for fabricating a flash memory device. After forming word line polysilicon, a word line protective layer of a predetermined thickness is deposited on the surface of the word line polysilicon, the surface of the second dielectric layer, and the surface of the first sidewall. The upper surface of the second dielectric layer is higher than the upper surface of the word line protective layer directly above the word line polysilicon. Thus, in the subsequent polishing step, only the word line protective layer directly above the second dielectric layer needs to be polished and removed. The word line protective layer directly above the word line polysilicon is the final target thickness, so no further polishing and etch-back operations are required. This avoids the word line protective layer directly above the word line polysilicon being polished and etched back. This improves the thickness uniformity of the word line protective layer on the surface of the word line polysilicon, improves the film quality of the word line protective layer, and improves the wafer yield and reliability. At the same time, it saves at least two steps and reduces manufacturing costs. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention; Figures 2-9 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 100 - Substrate, 110 - Pad oxide layer, 120 - Floating gate layer, 130 - First dielectric layer, 140 - Control gate, 150 - Second dielectric layer, 151 - Second dielectric layer with remaining thickness, 160 - First sidewall, 170 - Second sidewall, 180 - Word line polysilicon, 190 - Word line protection layer, 200 - Third dielectric layer, 201 - Third dielectric layer with remaining thickness, 210 - Gate oxide layer, 220 - Gate material layer. Detailed Implementation
[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0021] This application provides a method for fabricating a flash memory device, referring to... Figure 1 The method for fabricating the flash memory device includes: First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of the semiconductor structure after the formation of word line polysilicon according to an embodiment of this application. A substrate 100 is provided, the substrate 100 at least includes a memory region. Stacked pad oxide layer 110, floating gate layer 120, first dielectric layer 130, control gate 140 and first sidewall 160 are formed on the substrate 100 of the memory region. Trenches are formed in the first sidewall 160, the control gate 140, the first dielectric layer 130 and the floating gate layer 120. Second sidewalls 170 are formed on the sidewalls of the trenches. Word line polysilicon 180 is also filled in the trenches. A second dielectric layer 150 is formed on the control gate 140 and outside the first sidewall 160. The upper surface of the second dielectric layer 150 is higher than the upper surface of the first sidewall 160 and the upper surface of the second dielectric layer 150 is also higher than the upper surface of the word line polysilicon 180.
[0022] In this embodiment, the upper surface of the first sidewall 160 is higher than the upper surface of the word line polysilicon 180.
[0023] Furthermore, the first dielectric layer 130 includes: a stacked first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, wherein the first silicon oxide layer covers the floating gate layer 120, the first silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the first silicon nitride layer.
[0024] In this embodiment, the first sidewall 160 is made of silicon dioxide.
[0025] Preferably, the second sidewall 170 includes a third silicon oxide layer, a second silicon nitride layer, and a fourth silicon oxide layer, wherein the third silicon oxide layer covers the sidewall of the trench, the second silicon nitride layer covers the third silicon oxide layer, and the fourth silicon oxide layer covers the second silicon nitride layer.
[0026] In this embodiment, the material of the second dielectric layer 150 is silicon nitride.
[0027] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the word line protection layer is formed according to an embodiment of this application. The word line protection layer 190 is formed, and the word line protection layer 190 covers the second dielectric layer 150, the first sidewall 160 and the word line polysilicon 180.
[0028] Specifically, after the word line protection layer 190 is formed, the upper surface of the word line protection layer 190 directly above the second dielectric layer 150 is higher than the upper surface of the word line protection layer 190 directly above the word line polysilicon 180.
[0029] Furthermore, the upper surface of the second dielectric layer 150 is higher than the upper surface of the word line protection layer 190 directly above the word line polysilicon 180.
[0030] Preferably, the material of the word line protective layer 190 is silicon dioxide.
[0031] Preferably, the protective layer 190 for the letter lines is formed using a high-temperature furnace tube oxidation process.
[0032] In this embodiment, the thickness of the word line protective layer 190 is 500 angstroms to 700 angstroms.
[0033] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the word line protection layer directly above the second dielectric layer is removed by grinding, according to an embodiment of this application. The word line protection layer 190 directly above the second dielectric layer 150 is removed by grinding.
[0034] Preferably, the word line protective layer 190 directly above / on the upper surface of the second dielectric layer 150 is removed by chemical mechanical polishing (CMP).
[0035] It is worth noting that, since the upper surface of the word line protective layer 190 deposited on the upper surface of the word line polysilicon 180 is lower than the upper surface of the second dielectric layer 150, the word line protective layer 190 on the upper surface of the word line polysilicon 180 will not be polished in this polishing process.
[0036] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the third dielectric layer according to an embodiment of this application. The third dielectric layer 200 is formed, which covers the second dielectric layer 150 and the word line protection layer 190.
[0037] In this embodiment, the third dielectric layer 200 is made of silicon nitride.
[0038] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the gate oxide layer and the gate material layer in an embodiment of this application. The gate oxide layer 210 is formed, and the gate oxide layer 210 covers the third dielectric layer 200.
[0039] Further, proceed to step S6: Continue to refer to Figure 6 A gate material layer 220 is formed, which covers the gate oxide layer 210.
[0040] The gate oxide layer 210 and the gate material layer 220 may be deposited simultaneously on the second dielectric layer 150 and the word line protection layer 190 in the memory region during the process of forming the gate structure of the peripheral logic region.
[0041] Next, proceed to step S7: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after removing the gate material layer, the gate oxide layer, a portion of the thickness of the third dielectric layer, and a portion of the thickness of the second dielectric layer according to an embodiment of this application. After removing the gate material layer 220, the gate oxide layer 210, the portion of the thickness of the third dielectric layer 200, and the portion of the thickness of the second dielectric layer 150, a word line protection layer 190 between the remaining thickness of the third dielectric layer 201 and the remaining thickness of the second dielectric layer 151 is exposed. The remaining thickness of the third dielectric layer 201 covers a portion of the surface of the word line protection layer 190, and the upper surface of the remaining thickness of the third dielectric layer 201 is flush with the upper surface of the remaining thickness of the second dielectric layer 151.
[0042] Preferably, a dry etching process is used to etch and remove the gate material layer 220, the gate oxide layer 210, a portion of the thickness of the third dielectric layer 200, and a portion of the thickness of the second dielectric layer 150.
[0043] Further, proceed to step S8: (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after removing a portion of the word line protection layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer according to an embodiment of this application. The portion of the word line protection layer 190 between the remaining thickness of the third dielectric layer 201 and the remaining thickness of the second dielectric layer 151 is removed so that the upper surface of the word line protection layer 190 on the surface of the first sidewall 160 is flush with the upper surface of the word line protection layer 190 directly above the word line polysilicon 180.
[0044] Preferably, a wet etching process is used to etch away a portion of the word line protection layer 190 between the remaining thickness of the third dielectric layer 201 and the remaining thickness of the second dielectric layer 151.
[0045] Finally, proceed to step S7: (Refer to...) Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after removing the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer according to an embodiment of this application, where the remaining thickness of the third dielectric layer 201 and the remaining thickness of the second dielectric layer 151 are removed.
[0046] Preferably, a wet etching process is used to etch away the remaining thickness of the third dielectric layer 201 and the remaining thickness of the second dielectric layer 151.
[0047] In this application, after forming the word line polysilicon, a word line protective layer of a predetermined thickness is deposited on the surface of the word line polysilicon, the surface of the second dielectric layer, and the surface of the first sidewall. This ensures that the upper surface of the second dielectric layer is higher than the upper surface of the word line protective layer directly above the word line polysilicon. Therefore, in the subsequent polishing step, only the word line protective layer directly above the second dielectric layer needs to be polished and removed. Since the word line protective layer directly above the word line polysilicon is the final target thickness, no further polishing or etching is required. This avoids the word line protective layer directly above the word line polysilicon being polished or etched back. This improves the thickness uniformity of the word line protective layer on the surface of the word line polysilicon, improves the film quality of the word line protective layer, and avoids defects such as exposure and pitting of the word line polysilicon at the bottom of areas where the word line protective layer is too thin. It also avoids the situation where an excessively thick word line protective layer makes it difficult for subsequent metal silicides to deposit on the word line surface, resulting in a large contact resistance Rc of the word line. This improves wafer yield and reliability, while also eliminating at least two steps and reducing manufacturing costs.
[0048] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided on which stacked pad oxide layers, floating gate layers, first dielectric layers, control gates, and first sidewalls are formed. Trenches are formed in the first sidewalls, the control gate, the first dielectric layer, and the floating gate layer. Second sidewalls are formed on the sidewalls of the trenches. Word line polysilicon is also filled in the trenches. A second dielectric layer is formed on the control gate and outside the first sidewalls. The upper surface of the second dielectric layer is higher than the upper surface of the first sidewalls and also higher than the upper surface of the word line polysilicon. A word line protection layer is formed, which covers the second dielectric layer, the first sidewall, and the word line polysilicon, wherein, after the word line protection layer is formed, the upper surface of the second dielectric layer is higher than the upper surface of the word line protection layer directly above the word line polysilicon; Grinding removes the word line protective layer directly above the second dielectric layer; A third dielectric layer is formed, which covers the second dielectric layer and the word line protection layer; A gate oxide layer is formed, which covers the third dielectric layer; A gate material layer is formed, the gate material layer covering the gate oxide layer; Remove the gate material layer, the gate oxide layer, a portion of the thickness of the third dielectric layer, and a portion of the thickness of the second dielectric layer. At this time, the word line protection layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer is exposed. The remaining thickness of the third dielectric layer covers a portion of the surface of the word line protection layer, and the upper surface of the remaining thickness of the third dielectric layer is flush with the upper surface of the remaining thickness of the second dielectric layer. Remove a portion of the word line protection layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer, so that the upper surface of the word line protection layer on the first sidewall surface is flush with the upper surface of the word line protection layer directly above the word line polysilicon. Remove the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer.
2. The method for fabricating a flash memory device according to claim 1, characterized in that, The thickness of the word line protective layer is 500 angstroms to 700 angstroms.
3. The method for fabricating a flash memory device according to claim 1, characterized in that, The protective layer for the letter lines directly above the second dielectric layer is removed by chemical mechanical polishing.
4. The method for fabricating a flash memory device according to claim 1, characterized in that, A wet etching process is used to etch away a portion of the word line protective layer between the remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer.
5. The method for fabricating a flash memory device according to claim 1, characterized in that, The remaining thickness of the third dielectric layer and the remaining thickness of the second dielectric layer are removed by wet etching.
6. The method for fabricating a flash memory device according to claim 1, characterized in that, The gate material layer, the gate oxide layer, a portion of the third dielectric layer, and a portion of the second dielectric layer are removed by a dry etching process.
7. The method for fabricating a flash memory device according to claim 1, characterized in that, The first dielectric layer includes: a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, wherein the first silicon oxide layer covers the floating gate layer, the first silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the first silicon nitride layer.
8. The method for fabricating a flash memory device according to claim 1, characterized in that, The material of the second dielectric layer is silicon nitride.
9. The method for fabricating a flash memory device according to claim 1, characterized in that, The first sidewall is made of silicon dioxide.
10. The method for fabricating a flash memory device according to claim 1, characterized in that, The material of the word line protective layer is silicon dioxide.