Memory preparation method and memory

Abstract

The invention discloses a preparation method of a memory and the memory, and the preparation method comprises the steps: forming a first-layer storage structure which comprises a first conductive wire, a first storage array, a second conductive wire and a patterned hard mask which are sequentially stacked; forming a first initial medium filling layer covering the first storage structure and filling gaps among the first storage units; performing back etching on the patterned hard mask and the first initial dielectric filling layer until the second conductive wire is exposed, forming a first dielectric filling layer between the adjacent first storage units, and exposing at least part of the side wall of the second conductive wire by the first dielectric filling layer; sequentially forming an anti-fluorine corrosion layer at least covering the side wall of the second conductive wire and an etching stop layer at least covering the first dielectric filling layer; and then, forming a second memory unit on the first memory unit, thereby improving the electrical performance and yield of the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a memory and the memory itself. Background Technology

[0002] Phase-change memories (PCMs) utilize the reversible phase transition between amorphous and crystalline states of materials to store information, offering advantages such as non-volatility, high speed, and rewritability. To improve storage density, a three-dimensional stacked structure, with multiple layers of PCM arrays stacked vertically, has become a mainstream approach. Common architectures for 3D phase-change random access memories (3D PCMs) can include single-layer memory cells, two-layer stacked memory cells, or more layers of stacked memory cells. Each memory cell layer is typically self-aligned and formed at the intersection of mutually perpendicular word lines (WLs) and bit lines (BLs).

[0003] However, the electrical performance and yield of multilayer stacked three-dimensional phase-change memory in related technologies still need to be further improved. Summary of the Invention

[0004] To address the problems of the prior art, this application provides a method for fabricating a memory and a memory itself. The technical solution is as follows: On the one hand, a method for fabricating a memory is provided, comprising: A first layer of storage structure is formed, comprising a first conductive line, a first storage array, a second conductive line, and a patterned hard mask stacked sequentially along a first direction. The first conductive line extends along a second direction, and the second conductive line extends along a third direction that intersects the second direction. The first direction is perpendicular to the second direction and the third direction. The first storage array comprises a plurality of first storage cells arranged in an array. A first initial medium filling layer is formed to cover the first layer of storage structure, and the first initial medium filling layer is located between the first storage cells; The patterned hard mask and the first initial dielectric fill layer are etched back until the second conductive line is exposed, and a first dielectric fill layer is formed between adjacent first memory cells, the first dielectric fill layer exposing at least a portion of the sidewall of the second conductive line; An anti-fluorine corrosion layer and an etching stop layer are formed sequentially, wherein the anti-fluorine corrosion layer at least covers the sidewall of the second conductive line, and the etching stop layer at least covers the first dielectric filling layer; After the fluorine corrosion resistant layer and the etching stop layer are formed, a second memory cell is formed on the first memory cell.

[0005] In some embodiments, the sequential formation of the fluorine corrosion resistant layer and the etching stop layer includes: A fluorine corrosion resistant layer is formed, which covers the top surface of the second conductive wire, the exposed sidewalls, and the surface of the first dielectric filling layer; An etching stop layer is formed on the fluorine corrosion resistant layer.

[0006] In some embodiments, the thickness of both the fluorine corrosion resistant layer and the etching stop layer ranges from 5 Å to 40 Å.

[0007] In some embodiments, the materials of the fluorine corrosion resistant layer and the etching stop layer include dielectric materials with a dielectric constant of less than 10.

[0008] In some embodiments, the fluorine corrosion resistant layer is silicon nitride, and the etching stop layer is aluminum oxide.

[0009] In some embodiments, forming a second memory cell on the first memory cell after forming the fluorine corrosion resistant layer and the etching stop layer includes: A second initial dielectric fill layer is formed on the etch stop layer to cover the first layer memory structure, and the second initial dielectric fill layer fills the gap between adjacent first memory cells; The second initial dielectric filling layer is planarized until the top surface of the second conductive line is exposed, and a second dielectric filling layer is formed between adjacent first memory cells; A second memory cell stack is formed, covering the top surface of the second conductive line and the second dielectric filling layer; The second memory cell stack is etched based on the etch stop layer to form a second memory cell on each of the first memory cells.

[0010] In some implementations, forming the first-layer storage structure includes: A first conductive material layer and a first memory cell stack located on the first conductive material layer are formed; The first memory cell stack and the first conductive material layer are respectively etched into a plurality of first memory cell strips and first conductive lines extending along the second direction; A second conductive material layer is formed on a plurality of the first memory cell strips, and a patterned hard mask is formed on the second conductive material layer, the patterned hard mask having a plurality of openings exposing the second conductive material layer; The first layer storage structure is obtained by passing through the second conductive material layer and the multiple first storage cell strips along the multiple openings.

[0011] In some implementations, the first storage unit and / or the second storage unit includes any one of phase-change memory, select-only memory, dynamic random access memory, and flash memory.

[0012] On one hand, a memory is provided, obtained using any of the memory fabrication methods described above, the memory comprising: A first conductive line, a first storage array, a second conductive line, and a second storage array are sequentially stacked along a first direction. The first conductive line extends along a second direction, and the second conductive line extends along a third direction that intersects the second direction. The first direction is perpendicular to the second direction and the third direction. The first storage array includes a plurality of first storage cells arranged in an array, and the second storage array includes a plurality of second storage cells arranged in an array. The first dielectric filling layer located between adjacent first memory cells has at least a portion of the second conductive line sidewalls not covered by the first dielectric filling layer; A fluorine corrosion resistant layer is located at least on the sidewall of the second conductive line that is not covered by the first dielectric filling layer; An etch stop layer is located at least on the surface of the first dielectric filling layer.

[0013] In some embodiments, the fluorine corrosion resistant layer is located on the top surface of the second conductive wire, the sidewall of the second conductive wire not covered by the first dielectric filling layer, and the surface of the first dielectric filling layer; The etching stop layer is located on the fluorine corrosion resistant layer.

[0014] In some embodiments, the fluorine corrosion resistant layer is silicon nitride, and the etching stop layer is aluminum oxide.

[0015] In this embodiment, the patterned hard mask and the first initial dielectric filling layer in the first layer of the memory structure are etched back until the second conductive line in the first layer of the memory structure is exposed. A first dielectric filling layer is formed between adjacent first memory cells. After the first dielectric filling layer exposes at least part of the sidewall of the second conductive line, an anti-fluorine corrosion layer and an etch stop layer are formed in sequence. The anti-fluorine corrosion layer covers at least the sidewall of the second conductive line, and the etch stop layer covers at least the first dielectric filling layer. Then, a second memory cell is formed on the first memory cell. The anti-fluorine corrosion layer is used to block the adverse effects of fluorine-containing byproducts attached to the sidewall of the second conductive line formed during the etch-back process on subsequent processes. At the same time, the etch stop layer is used to effectively prevent damage to the first dielectric filling layer and the first memory cell when the upper second memory cell is formed, thereby improving the electrical performance and yield of the multilayer stacked memory. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figures 1 to 5 This is a structural cross-sectional view of the fabrication process of a double-layer stacked three-dimensional phase-change memory provided in one embodiment; Figure 6 This is a schematic flowchart of a method for fabricating a memory according to an embodiment of this application; Figures 7 to 13c This is a structural cross-sectional view of the memory fabrication process provided in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0021] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0022] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0023] Before introducing the technical solutions of the embodiments of this application, the various directions that may be used in the following description are defined. The stacking direction of the memory is defined as the first direction (i.e., the Z direction). A second direction (i.e., the X direction) and a third direction (i.e., the Y direction) that intersect are defined in a plane perpendicular to the Z direction. In some embodiments, the X direction, Y direction, and Z direction may be mutually perpendicular.

[0024] A multilayer stacked memory may include, sequentially stacked along the Z-direction, lower-level conductive lines (e.g., bit lines), lower-level memory cells, intermediate conductive lines (e.g., word lines), upper-level memory cells, and upper-level conductive lines (e.g., bit lines). The lower-level conductive lines may extend in the X-direction and be spaced apart in the Y-direction, which intersects the X-direction. The intermediate conductive lines may extend in the Y-direction and be spaced apart in the X-direction. The upper-level conductive lines may extend in the X-direction and be spaced apart in the Y-direction. Lower-level memory cells may be arranged at the intersections of lower-level and intermediate conductive lines, and upper-level memory cells may be arranged at the intersections of intermediate and upper-level conductive lines.

[0025] In fabricating this multilayer stacked memory, the lower layer structure typically needs to be etched back to the intermediate conductive lines (such as word lines) before fabricating the upper layer memory cells to achieve subsequent connectivity between the upper and lower layers. However, due to the complexity of the film layer stacking, the etch-back process for the lower layer may directly or indirectly introduce structural defects. Furthermore, the formation of the upper layer memory cells often affects the lower layer structure, causing structural defects and thus impacting the final electrical performance and yield of the memory. Taking the fabrication process of a two-layer stacked three-dimensional phase-change memory as an example, combined with... Figures 1-5 This is to illustrate the structural defects introduced during the fabrication of multilayer stacked memory.

[0026] like Figure 1 The diagram shows the lower-layer phase-change memory structure formed during fabrication. This lower-layer phase-change memory structure includes a lower-layer bit line 110, a lower-layer phase-change memory array, a lower-layer word line 130, and a word line hard mask 140, which are sequentially stacked along the Z-direction. The lower-layer bit lines 110 extend along the X-direction and are spaced apart in the Y-direction, the lower-layer word lines 130 extend along the Y-direction and are spaced apart in the X-direction, and the lower-layer phase-change memory array 120 is disposed between the lower-layer bit lines 110 and the lower-layer word lines 130.

[0027] The lower-level phase-change memory array includes a plurality of lower-level phase-change memory cells 120 arranged in an array, each lower-level phase-change memory cell 120 being located at a crossroads of the lower-level bit line 110 and the lower-level word line 130. The word line hard mask 140 includes a hard mask pattern extending in the same direction as the lower-level word line 130, thereby defining the pattern of the lower-level word line 130.

[0028] like Figure 2 As shown, a covering is formed Figure 1 The lower initial dielectric filling layer 210 of the lower phase change memory structure shown is located between the lower phase change memory cells, thereby filling the gaps between the lower phase change memory cells 120.

[0029] Next, as Figure 3 As shown, the word line hard mask 140 and the lower initial dielectric filling layer 210 are etched back until the lower word line 130 is exposed, thereby removing the word line hard mask 140 and providing a process basis for subsequent interconnection between the upper and lower phase change memory cells. However, during the etch-back process to completely remove the word line hard mask 140, it was found that the top surface of the lower dielectric filling layer 310 formed between the lower phase change memory cells 120 by etching back the lower initial dielectric filling layer 210 was lower than the top surface of the lower word line 130. This resulted in a recess 301 in the lower dielectric filling layer 310 between adjacent lower phase change memory cells 120, thereby exposing part of the lower word line sidewall 302. Furthermore, fluorine-containing byproducts 303 (such as tungsten tetrafluoroethylene) were attached to the exposed lower word line sidewall 302. ).

[0030] Due to the presence of the aforementioned recess 301, a new dielectric filler layer needs to be formed to fill the recess 301 between adjacent lower phase change memory cells 120 before the upper phase change memory cell process can begin. During this process, it was discovered that fluorine-containing byproducts 303 adhering to the exposed portion of the lower word line sidewall 302 react chemically with moisture to generate HF, which in turn corrodes the refilled dielectric filler layer, causing voids to appear in the dielectric filler layer near this portion of the lower word line sidewall. Figure 4 As shown, void 401 is formed in the dielectric filling layer 410 near the lower letter line sidewall 302. The fluorine-containing byproduct is tungsten tetrafluoroethylene. For example, the chemical reaction formula for its reaction with water vapor is: The voids 401 in the dielectric filling layer 410 introduce structural defects into the final three-dimensional phase-change memory, which in turn adversely affects its electrical performance and yield.

[0031] Although the fluorine-containing byproduct 303 attached to the exposed lower word line sidewall 302 can be removed by enhanced back etching process cleaning to avoid subsequent dielectric filling layer corrosion, the corrosiveness of the cleaning solution itself will cause damage to the top of the lower word line (such as tungsten) and the film layers such as the lower dielectric filling layer and phase change material. This will still introduce structural defects into the final three-dimensional phase change memory, resulting in poor electrical performance and yield of the three-dimensional phase change memory.

[0032] After forming the dielectric filling layer 410, an upper phase-change memory cell can be formed on the lower phase-change memory cell 120. To ensure that the lower word line 130 can be fully opened while keeping leakage current at a low level, a certain amount of over-etching (OE) is usually required in the etching process to open the lower word line 130. However, the following two problems were further discovered during the over-etching process, which adversely affected the device performance: On the one hand, over-etching causes the underlying dielectric filling layer to sink again: such as Figure 5 As shown, upper phase-change memory cells 510 are formed on each lower phase-change memory cell 120. The lower dielectric filling layer 410 is etched again due to excessive etching, resulting in dishing. Furthermore, due to the high aspect ratio of the structure, controlling the etching uniformity (U%) is difficult, leading to excessively deep dishing in some areas. On the other hand, high aspect ratio structures are prone to void defects: such as… Figures 2-5As shown, during the fabrication of the lower dielectric filling layer 310, due to the high aspect ratio structure, voids 201 are introduced into the lower dielectric filling layer 310. When the aforementioned issues of depressions and voids coexist, the formation process of the upper phase change memory cell 510 will damage the lower phase change memory structure, resulting in structural defects in the final three-dimensional phase change memory, thereby reducing its electrical performance and production yield.

[0033] Therefore, embodiments of this application provide a method for fabricating a memory, such as... Figure 6 The diagram shown is a flowchart illustrating a method for fabricating a memory according to an embodiment of this application. The method includes: In step S601, a first layer of storage structure is formed, which includes a first conductive line, a first storage array, a second conductive line, and a patterned hard mask stacked sequentially along a first direction.

[0034] Wherein, the first conductive line extends along the second direction, the second conductive line extends along a third direction that intersects the second direction, and the first direction is perpendicular to the second direction and the third direction; the first storage array includes a plurality of first storage cells arranged in an array.

[0035] The patterned hard mask defines the pattern of the second conductive line, including hard mask strips located on the second conductive line.

[0036] In step S603, a first initial medium filling layer is formed to cover the first layer of storage structure, and the first initial medium filling layer is located between the first storage cells.

[0037] Specifically, the first initial medium filling layer fills the gaps between the first storage cells and overflows to cover the first storage structure.

[0038] In step S605, the patterned hard mask and the first initial dielectric filling layer are etched back until the second conductive line is exposed, and a first dielectric filling layer is formed between adjacent first memory cells, wherein the first dielectric filling layer exposes at least a portion of the sidewall of the second conductive line.

[0039] In step S607, an anti-fluorine corrosion layer and an etching stop layer are formed sequentially. The anti-fluorine corrosion layer at least covers the sidewall of the second conductive line, and the etching stop layer at least covers the first dielectric filling layer.

[0040] In step S609, after forming the fluorine corrosion resistant layer and the etching stop layer, a second memory cell is formed on the first memory cell.

[0041] In this embodiment, after the lower layer's etch-back process, an anti-fluorine corrosion layer and an etch stop layer are formed sequentially. The anti-fluorine corrosion layer covers at least a portion of the exposed second conductive line sidewalls, and the etch stop layer covers at least the first dielectric filling layer. This prevents the fluorine-containing byproducts formed during the etch-back process and attached to the second conductive line sidewalls from having an adverse effect on subsequent processes. At the same time, the etch stop layer effectively prevents damage to the lower layer structure during the formation of the upper second memory cell, thereby improving the electrical performance and yield of the multilayer stacked memory.

[0042] In some implementations, the first and / or second storage units in the embodiments of this application may include any one of phase-change memory units, select-only memory units, dynamic random access memory units, and flash memory units. For example, both the first and second storage units may be phase-change memory units, thus the memory in the embodiments of this application may include a three-dimensional phase-change memory.

[0043] The following example uses phase-change memory cells as both the first and second memory cells as an example. Figures 7 to 13c The method for fabricating the memory provided in the embodiments of this application will be described in detail, wherein, Figures 7 to 13c This is a cross-sectional view of the memory during its fabrication process.

[0044] like Figure 7 As shown, a first-layer storage structure 710 is formed, which includes a first conductive line 711, a first storage array, a second conductive line 713, and a patterned hard mask 714 stacked sequentially along the Z direction, i.e., the first direction.

[0045] The first conductive lines 711 extend along the X direction (i.e., the second direction) and are spaced apart from each other in the Y direction (i.e., the third direction). The second conductive lines 713 extend along the Y direction (i.e., the third direction) and are spaced apart from each other in the X direction (i.e., the second direction). The first memory array includes a plurality of first phase-change memory cells 712 arranged in an array along the X and Y directions. Each first phase-change memory cell 712 is located at each intersection of the first conductive lines 711 and the second conductive lines 713. The first conductive lines 711 are connected to the plurality of first phase-change memory cells 712 spaced apart along the X direction, and the second conductive lines 713 are connected to the plurality of first phase-change memory cells 712 spaced apart along the Y direction.

[0046] For example, the first conductive line 711 can be used as a bit line and the second conductive line 713 can be used as a word line. In a specific implementation, the second conductive line 713 can be used as a common word line for the first phase change memory cell 712 and the second phase change memory cells subsequently formed on the first phase change memory cell 712.

[0047] Each first phase-change memory cell 712 may include at least a phase-change memory layer, a gating layer, and multiple electrode layers stacked in the Z direction, for example, reference Figure 7 The system may include a first electrode layer 7121, a first gating layer 7122, a second electrode layer 7123, a first phase-change memory layer 7124, and a third electrode layer 7125 stacked sequentially along the Z direction. Each first phase-change memory cell 712 can store one or more data bits, and each first phase-change memory cell 712 can be written to or read from by changing the voltage applied to the corresponding gating layer. In practical applications, the phase-change memory cell connected to the selected word line and the selected bit line can be selected by activating the selected word line and the selected bit line.

[0048] In some examples, the first phase-change memory cell 712 may further include a resistance adjustment layer and an adhesion layer. The resistance adjustment layer is located between the conductive lines and the electrode layer, such as... Figure 7 As shown, the first phase change memory cell 712 may include a first resistance adjustment layer 7126a located between the first conductive line 711 and the first electrode layer 7121, and a second resistance adjustment layer 7126b located between the third electrode layer 7125 and the second conductive line 713. The resistance adjustment layer can be used to adjust the resistivity of the phase change memory cell, and the material of the resistance adjustment layer may include at least one of tungsten silicon nitride (WSiN), titanium silicon nitride (TiSiN), titanium nitride (TiN), or tungsten nitride (WN).

[0049] The adhesion layer is located between the phase change storage layer and the electrode layer, such as Figure 7 As shown, the first phase change memory cell 712 may include a first adhesion layer 7127a located between the second electrode layer 7123 and the first phase change memory layer 7124, and a second adhesion layer 7127b located between the first phase change memory layer 7124 and the third electrode layer 7125. The adhesion layers can be used to enhance the adhesion between the electrode layer in contact with the phase change memory layer and the phase change memory layer, reducing the probability of peeling between the electrode layer and the phase change memory layer in subsequent processes. Simultaneously, the adhesion layers can also be used to reduce material interdiffusion between the phase change memory layer and the electrode layer. The material of the adhesion layers may include silicon tungsten nitride (WSiN) and / or silicon titanium nitride (TiSiN).

[0050] The patterned hard mask 714 defines the pattern of the second conductive line 713, and further includes multiple hard mask strips extending in the same direction as the second conductive line 713, each hard mask strip covering the corresponding second conductive line 713. The material of the patterned hard mask 714 may include, but is not limited to, silicon nitride.

[0051] In some examples, the first layer of memory structure 710 may further include a sidewall protection layer 715 that covers the sidewalls of each first phase change memory cell 712, the sidewalls of the second conductive line 713, and the sidewalls of the patterned hard mask 714, for protecting the first phase change memory cells 701 in subsequent processes. The material of the sidewall protection layer 715 may include, but is not limited to, silicon nitride, silicon oxide, etc.

[0052] In some examples, such as Figure 7 As shown, the first storage layer 710 may further include an interface layer 716, which may be formed between the sidewall protective layer 715 and the first phase change storage cell 12. The material of the interface layer 716 may include at least one of titanium nitride, tantalum nitride, silicon nitride, and silicon oxynitride, and may be a single-layer thin film or a multi-layer thin film stacked structure. The interface layer 716 can prevent elements in the phase change storage layer from diffusing outward and prevent external elements from diffusing into the phase change storage layer.

[0053] The following is combined Figures 8a to 8c The formation of the first-level storage structure will be introduced.

[0054] like Figure 8a As shown, a first conductive material layer 810 and a first memory cell stack 820 located on the first conductive material layer 810 are formed.

[0055] The first conductive material layer 810 is used to form the first conductive line after being patterned, and the first memory cell stack 820 is used to form the first memory array after being patterned.

[0056] In practical applications, a substrate can be provided first, located below the process execution plane, to support the process. Exemplarily, the substrate can be a bulk semiconductor or a silicon on insulator (SOI) substrate, which can be doped (e.g., doped with p-type or n-type dopant) or undoped. The SOI substrate is a semiconductor material layer formed on an insulating layer, which can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, disposed on a silicon or glass substrate. In specific implementations, the semiconductor material of the substrate can include one or more of silicon, germanium, compound semiconductors, and alloy semiconductors. The compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor can be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium arsenide phosphide. The substrate can be formed with active or passive electronic components such as metal oxide semiconductor transistors, diodes, and resistors, and can also have device isolation structures, and can further form multilayer metal interconnect structures, etc.

[0057] The conductive material of the first conductive material layer 810 may include one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides. The first conductive material layer 810 may be deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0058] After forming the first conductive material layer 810, a first memory cell stack 820 is formed on the first conductive material layer 810. The first memory cell stack 820 may include a phase-change memory material layer, a gating material layer, and multiple electrode material layers stacked in the Z direction, for example, referring to... Figure 8a It may include a first electrode material layer 821, a first gate material layer 822, a second electrode material layer 823, a first phase change storage material layer 824 and a third electrode material layer 825 stacked sequentially along the Z direction.

[0059] In some examples, the first memory cell stack 820 may also include a resistance-regulating material layer and an adhesion material layer, such as Figure 8aAs shown, the resistance regulating material layer may include a first resistance regulating material layer 8261 formed between the first conductive material layer 810 and the first electrode material layer 821, and a second resistance regulating material layer 8262 formed on the third electrode material layer 825; the adhesive material layer may include a first adhesive material layer 8271 formed between the second electrode material layer 823 and the first phase change storage material layer 824, and a second adhesive material layer 8272 formed between the first phase change storage material layer 824 and the third electrode material layer 825.

[0060] The multiple electrode material layers can be formed of conductive materials, which may include, for example, metals, conductive metal nitrides, conductive metal oxides, or combinations thereof. The phase change storage material layer can be a chalcogenide, such as germanium. antimony Tellurium (Ge Sb Te, GST) material or indium antimony Tellurium (In) Sb Te, IST) materials, etc., specifically, for example, the material of the phase change memory material layer can be , , or And so on. The material of the gating material layer can include any suitable bidirectional threshold switch (OTS) material, such as... , , or wait.

[0061] To form the first memory cell stack 820, one or more thin film deposition processes can be used to successively deposit the layers of the first memory cell stack 820. For example, one or a combination of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) processes can be used.

[0062] Next, the first memory cell stack 820 and the first conductive material layer 810 are etched into a plurality of first memory cell strips and first conductive lines extending along the X direction.

[0063] Specifically, the first memory cell stack 820 and the first conductive material layer 810 can be sequentially etched along the Z direction, so that the first conductive material layer 810 is formed into a first conductive line 711 extending along the X direction and the first memory cell stack 820 is formed into a first memory cell strip extending along the X direction in the same etching step.

[0064] In practical applications, a photoresist mask layer can be formed on the first memory cell stack 820. The photoresist mask layer is patterned by exposure and development. Based on the patterned photoresist mask layer, the first memory cell stack 820 and the first conductive material layer 810 are etched. Through this etching, trenches can be formed that penetrate the first memory cell stack 820 and the first conductive material layer 810. The first memory cell strip and the first conductive line 711 are separated by two adjacent trenches.

[0065] Next, see Figure 8b A second conductive material layer 830 is formed on a plurality of first memory cell strips, and a patterned hard mask 840 is formed on the second conductive material layer 830, the patterned hard mask 840 having a plurality of openings 841 exposing the second conductive material layer 830.

[0066] The second conductive material layer 830 is used to form the second conductive lines after being patterned. The conductive material of the second conductive material layer 830 may include one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides. The second conductive material layer 830 may be deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0067] After forming the second conductive material layer 830, a patterned hard mask 840 is formed on the second conductive material layer 830. Specifically, a hard mask material layer can be formed on the second conductive material layer 830 first. Based on the preset pattern of the second conductive lines, a plurality of openings 841 exposing the second conductive material layer 830 are formed in the hard mask material layer. The plurality of openings 841 extend along the Y direction and are spaced apart along the X direction, thereby forming the hard mask material layer into a patterned hard mask 840.

[0068] For example, the material of the hard mask material layer can be a nitride material, such as silicon nitride.

[0069] In practical applications, before forming the second conductive material layer 830, the trenches between two adjacent first memory cell strips can be filled with a filler material, such as silicon oxide, using one or more thin-film deposition processes. Afterwards, a planarization process, such as Chemical Mechanical Polishing (CMP), can be used to make the upper surface of the filler material in the trench flush with the upper surface of the first memory cell strip, exposing the upper surface of the first memory cell strip. Then, the second conductive material layer 830 and a patterned hard mask 840 are formed on the first memory cell strips and the filler material.

[0070] Next, see Figure 8c The first layer of storage structure is obtained by passing through the second conductive material layer 830 and the multiple first storage cell strips along the multiple openings 841.

[0071] In some examples, the second conductive material layer 830 and multiple first memory cell strips can be etched along multiple openings 841 in the Z direction, with the etching stopping at the first conductive line 711. This allows the first memory cell strips to be formed into cylindrical first phase-change memory cells 712 perpendicular to the substrate surface, while maintaining the integrity of the first conductive line. The second conductive material layer 830 is formed into second conductive lines 713 extending along the Y direction. It is understood that by etching along the openings 841, trenches are formed in the first memory cell strips and the filling material, with the second conductive line 713 and the first phase-change memory cell 712 separated by adjacent trenches.

[0072] In other examples, the second conductive material layer 830 and the multiple first memory cell strips can be etched in the Z direction along multiple openings 841, and the etching stops on the second electrode material layer 823, thereby forming a first trench in the first memory cell strip that exposes the second electrode material layer 823 therein; then, an interface layer is formed on the sidewall of the first trench through the first trench, the interface layer covering the sidewall of the patterned mask, the sidewall of the second conductive line, and the sidewall of the portion of the first phase change memory cell exposed by the trench; after the interface layer is formed, the remaining first memory cell strips are etched in the Z direction, and the etching stops on the first conductive line 711, thereby extending the first trench toward the first conductive line 711 until the first conductive line 711 is exposed, forming a second trench through the first memory cell strip, the second trench causing the first memory cell strip to be formed into multiple spaced first phase change memory cells; then, a sidewall protection layer is formed on the sidewall of the second trench, thereby covering the interface layer and the sidewalls of the remaining layers of the first phase change memory cell, resulting in... Figure 7 The first-level storage structure 710 is shown.

[0073] After forming the first layer of storage structure 710, as Figure 9 As shown, a filling material is used to fill the gaps between adjacent first phase change memory cells 712 to form a first initial dielectric filling layer 910 covering the first layer memory structure 710. It can be understood that the first initial dielectric filling layer 910 fills the gaps between the first phase change memory cells 701 and covers the top surface of the patterned hard mask 714.

[0074] The material of the first initial dielectric filling layer 910 can be a dielectric material, such as an oxide material. In some examples, the dielectric material can be silicon oxide. The first initial dielectric filling layer 910 can be deposited using suitable material deposition processes such as chemical vapor deposition or high aspect ratio vapor deposition.

[0075] Next, see Figure 10 The patterned mask 714 and the first initial dielectric filling layer 910 are etched back until the top surface of the second conductive line 713 is exposed or to the desired depth, so that the patterned hard mask 714 on the first conductive line 713 is completely removed. At the same time, the first initial dielectric filling layer 910 is also etched back, thereby forming a first dielectric filling layer 1010 between adjacent first phase change memory cells 712. The first dielectric filling layer 1010 exposes at least a portion of the second conductive line sidewall 1020, and fluorine-containing byproducts 1030 may be attached to the exposed portion of the second conductive line sidewall 1020.

[0076] The back etching can be performed using either wet etching or dry etching processes.

[0077] In some examples, when the first-layer storage structure 710 includes an interface layer and a sidewall protection layer, such as... Figure 10 As shown, during the above-mentioned back etching process, the interface layer and the sidewall protective layer will also be partially etched away along with the back etching of the first initial dielectric filling layer 910.

[0078] Next, see Figure 11 A fluorine corrosion resistant layer 1110 and an etching stop layer 1120 are formed sequentially. The fluorine corrosion resistant layer 1110 can at least cover the exposed portion of the second conductive line sidewall 1020, and the etching stop layer 1120 can at least cover the surface of the first dielectric filling layer 1010.

[0079] Specifically, the fluorine corrosion-resistant layer 1110 has resistance to fluorine (F) corrosion. Covering the exposed portion of the second conductive wire sidewall 1020, it encapsulates the fluorine-containing byproducts 1030 adhering to this portion of the sidewall, preventing them from reacting with moisture to generate HF and causing corrosive damage to the structure in subsequent processes. Furthermore, the fluorine corrosion-resistant layer 1110 also prevents oxidation of the second conductive wire sidewall by subsequent dielectric layer deposition, acting as a sidewall barrier layer and improving the resistivity (Rs) of the second conductive wire. Simultaneously, this fluorine corrosion-resistant layer 1110 does not damage other film layers.

[0080] The etch stop layer 1120 has etch resistance, protecting the underlying first dielectric filling layer 1010 from etching in subsequent etching processes. Furthermore, the etch stop layer 1120 provides a sufficient process window for over-etching, thereby improving the uniformity of hole depth during subsequent upper-layer etching.

[0081] After the above-mentioned etching back, atomic layer deposition (ALD) or low-temperature CVD can be used to sequentially deposit an anti-fluorine corrosion layer 1110 and an etching stop layer 1120.

[0082] For example, the thickness of the fluorine corrosion resistant layer 1110 ranges from 5 Å to 40 Å, such as 5 Å, 10 Å, 15 Å, 20 Å, 25 Å, 30 Å, 35 Å, or 40 Å; the thickness of the etch stop layer 1120 ranges from 5 Å to 40 Å, such as 5 Å, 10 Å, 15 Å, 20 Å, 25 Å, 30 Å, 35 Å, or 40 Å. This allows the fluorine corrosion resistant layer to provide resistance to fluorine corrosion and prevent corrosion of the subsequent dielectric filling layer, and the etch stop layer to provide resistance to etching and protect the underlying first dielectric filling layer, while avoiding excessive thickness that could adversely affect the electrical performance of the device.

[0083] For example, the materials of the fluorine corrosion resistant layer 1110 and the etch stop layer 1120 include dielectric materials with a dielectric constant less than 10, thereby reducing the effects of parasitic capacitance. Preferably, the fluorine corrosion resistant layer 1110 is silicon nitride (…). The etching stop layer 1120 is aluminum oxide ( ).

[0084] In some embodiments, sequentially forming the fluorine corrosion resistant layer 1110 and the etching stop layer 1120 may include: forming the fluorine corrosion resistant layer 1110, which covers the top surface of the second conductive wire, the exposed sidewall, and the surface of the first dielectric filling layer; and forming the etching stop layer 1120 on the fluorine corrosion resistant layer 1110.

[0085] Specifically, such as Figure 11As shown, the fluorine corrosion resistant layer 1110 is formed not only on the exposed portion of the second conductive line sidewall 1020, but also on the top surface of the second conductive line 713 and the surface of the first dielectric filling layer 1010, thereby providing more effective fluorine corrosion resistant protection as a whole. An etching stop layer 1120 is formed on the fluorine corrosion resistant layer 1110 to cover its surface, allowing the etching stop layer 1120 to further protect the sidewall of the second conductive line 713. This prevents sputtering damage to the second conductive line 713 (such as tungsten word lines) during subsequent etching processes, and also avoids severe structural leakage caused by the formation of a large amount of conductive element-containing byproducts (such as tungsten).

[0086] For example, when the etching stop layer 1120 is formed on the fluorine corrosion resistant layer 1110, the total thickness of the film formed by the two does not exceed 40 Å, for example, it can be 10 Å, 20 Å, 30 Å, or 40 Å, so as to avoid excessive thickness from adversely affecting the electrical performance of the device.

[0087] Next, see Figure 12 After forming the fluorine corrosion resistant layer 1110 and the etching stop layer 1120, a second phase change memory cell 1210 is formed on the first phase change memory cell 712.

[0088] The second phase change memory unit 1210 may have the same structure as the first phase change memory unit 712, and may include at least a phase change memory layer, a gate layer and multiple electrode layers stacked in the Z direction. For example, it may include a fourth electrode layer 1211, a second gate layer 1212, a fifth electrode layer 1213, a second phase change memory layer 1214 and a sixth electrode layer 1215 stacked sequentially in the Z direction.

[0089] In some examples, the second phase-change memory cell 1210 may further include a resistance regulating layer and an adhesion layer. The resistance regulating layer is located between the conductive lines and the electrode layer, such as... Figure 12 As shown, the second phase change memory cell 1210 may include a third resistance adjustment layer 1216a located between the second conductive line 713 and the fourth electrode layer 1211. An adhesion layer is located between the phase change memory layer and the electrode layer, such as... Figure 12 As shown, the second phase change memory cell 1210 may include a third adhesion layer 1217a located between the fifth electrode layer 1213 and the second phase change memory layer 1214 and a fourth adhesion layer 1217b located between the second phase change memory layer 1214 and the sixth electrode layer 1215.

[0090] In some examples, the second phase-change memory cell 1210 and the first phase-change memory cell 712 may share the second conductive line 713 (e.g., a word line). In other examples, such as... Figure 12As shown, a third conductive line 1220 extending along the Y direction and spaced apart in the X direction is formed on the second conductive line 713. The second phase-change memory cell 1210 is formed on the third conductive line 1220, which can serve as a word line or bit line of the second phase-change memory cell 1210. It is understood that a fourth conductive line (not shown in the figure) can also be formed on the second phase-change memory cell 1210, which can serve as a word line or bit line of the second phase-change memory cell 1210.

[0091] The following is combined Figures 13a to 13c The formation of the second phase change memory cell 1210 on the first phase change memory cell 712 will be described in detail.

[0092] See Figure 13a A second initial dielectric filling layer 1310 is formed on the etch stop layer 1120 to cover the first layer memory structure. The second initial dielectric filling layer 1310 fills the gap between adjacent first phase change memory cells 712.

[0093] Specifically, the material of the second initial dielectric filling layer 1310 can be a dielectric material, such as an oxide material; in some examples, the dielectric material can be silicon oxide. The second initial dielectric filling layer 1310 can be deposited using one or a combination of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) processes.

[0094] Next, see Figure 13b The second initial dielectric filling layer 1310 is planarized using a planarization process such as chemical mechanical polishing (CMP) until the top surface of the second conductive line 713 is exposed. At the same time, a second dielectric filling layer 1320 is formed between adjacent first phase change memory cells 712. The top surface of the second dielectric filling layer 1320 is flush with the top surface of the second conductive line 713 to expose the top surface of the second conductive line 713.

[0095] Next, see Figure 13c This forms a second memory cell stack 1330 covering the top surface of the second conductive line 713 and the second dielectric filling layer 1320.

[0096] Specifically, the structure of the second memory cell stack 1330 can be the same as that of the first memory cell stack 820, and may include a phase change memory material layer, a gating material layer, and multiple electrode material layers stacked in the Z direction, for example, referring to... Figure 13cThe device may include a fourth electrode material layer 1331, a second gate material layer 1332, a fifth electrode material layer 1333, a second phase change storage material layer 1334, and a sixth electrode material layer 1335, sequentially stacked along the Z-direction. The multiple electrode material layers may be formed of conductive materials, such as metals, conductive metal nitrides, conductive metal oxides, or combinations thereof. The phase change storage material layer may be a chalcogenide, for example, germanium. antimony Tellurium (Ge Sb Te, GST) material or indium antimony Tellurium (In) Sb Te, IST) materials, etc., specifically, for example, the material of the phase change memory material layer can be , , or And so on. The material of the gating material layer can include any suitable bidirectional threshold switch (OTS) material, such as... , , or wait.

[0097] In some examples, before forming the second memory cell stack 1330, a third conductive material layer 1340 covering the top surface of the second conductive line 713 and the second dielectric filling layer 1320 may be formed first, and then the second memory cell stack 1330 is formed on the third conductive material layer 1340. The third conductive material layer 1340 can be used to pattern the third conductive line 1220. The conductive material of the third conductive material layer 1340 may include one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides.

[0098] In some examples, the second memory cell stack 1330 may also include a resistance-regulating material layer and an adhesion material layer, such as Figure 13c As shown, the resistance regulating material layer may include a third resistance regulating material layer 1336 formed between the third conductive material layer 1340 and the fourth electrode material layer 1331; the adhesive material layer may include a third adhesive material layer 1337a formed between the fifth electrode material layer 1333 and the second phase change storage material layer 1334, and a fourth adhesive material layer 1337b formed between the second phase change storage material layer 1334 and the sixth electrode material layer 1335.

[0099] In specific implementation, the second memory cell stack 1330 can be obtained by successively depositing each layer therein using one or more thin film deposition processes.

[0100] Next, the second memory cell stack 1330 is etched based on the etch stop layer 1120 to form a second phase change memory cell 1210 on each of the first phase change memory cells 712.

[0101] Specifically, the second memory cell stack 1330 is etched into a plurality of second memory cell strips extending along the Y direction, and the etching stops at the etch stop layer 1120. Then, the second memory cell strips are etched into a plurality of independent, cylindrical second phase-change memory cells 1210 perpendicular to the substrate surface. These plurality of second phase-change memory cells 1210 are arranged in an array and stacked with a plurality of first phase-change memory cells in the Z direction. It is understood that if the second memory cell stack 1330 is formed on the third conductive material layer 1340, then when the second memory cell stack 1330 is etched into a plurality of second memory cell strips extending along the Y direction and the etching stops at the etch stop layer 1120, the third conductive material layer 1340 is also etched into a plurality of third conductive lines extending along the Y direction.

[0102] In practical applications, a photoresist mask layer can be formed on the second memory cell stack 1330. This photoresist mask layer is patterned through exposure and development. Based on the patterned photoresist mask layer, the second memory cell stack 1330 is etched until the etch stop layer 1120 is exposed. This etching forms multiple trenches extending along the Y direction through the second memory cell stack 1330, with adjacent trenches separating second memory cell strips. It is understood that the trenches between adjacent second memory cell strips can then be filled with a filler material, such as a dielectric material like silicon oxide. Next, the second memory cell strips are etched according to the aforementioned steps for etching the first memory cell strip, thereby forming multiple spaced second phase-change memory cells 1210.

[0103] During the etching process of the second memory cell stack 1330, the etching stop layer 1120 can effectively protect the structure below it and prevent damage to the lower structure during the etching of the upper layer.

[0104] The above-described technical solution of this application embodiment forms a combined film structure by sequentially depositing an anti-fluorine corrosion layer (such as a silicon nitride layer) and an etching stop layer (such as an aluminum oxide layer). The combined film structure at least covers the exposed sidewalls of the second conductive line (such as a word line, tungsten) and at least covers the surface of the first dielectric filling layer. This effectively avoids structural defects caused during the fabrication process without causing significant changes to the main structure of the memory, thereby improving the electrical performance and yield of the three-dimensional memory.

[0105] This application also provides a memory fabricated based on any of the foregoing methods, which can be a two-layer stacked or multi-layer stacked three-dimensional phase-change memory. Specifically, the memory includes: A first conductive line, a first storage array, a second conductive line, and a second storage array are sequentially stacked along a first direction; the first conductive line extends along a second direction, and the second conductive line extends along a third direction that intersects the second direction; the first direction is perpendicular to the second direction and the third direction; the first storage array includes a plurality of first storage cells arranged in an array; and the second storage array includes a plurality of second storage cells arranged in an array. The first dielectric filling layer located between adjacent first memory cells has at least a portion of the second conductive line sidewalls not covered by the first dielectric filling layer; A fluorine corrosion resistant layer is located at least on the sidewall of the second conductive line that is not covered by the first dielectric filling layer; An etch stop layer is located at least on the surface of the first dielectric filling layer.

[0106] In some embodiments, the fluorine corrosion resistant layer is located on the top surface of the second conductive wire, the sidewall of the second conductive wire not covered by the first dielectric filling layer, and the surface of the first dielectric filling layer; the etching stop layer is located on the fluorine corrosion resistant layer.

[0107] In some embodiments, the thickness of both the fluorine corrosion resistant layer and the etching stop layer ranges from 5 Å to 40 Å.

[0108] In some embodiments, the materials of the fluorine corrosion resistant layer and the etching stop layer include dielectric materials with a dielectric constant of less than 10.

[0109] In some embodiments, the fluorine corrosion resistant layer is silicon nitride, and the etching stop layer is aluminum oxide.

[0110] It should be noted that the memory embodiments provided in this application and the memory preparation method embodiments belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0111] The foregoing has provided a detailed description of a method for preparing a memory and the memory itself, as provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating a memory, characterized in that, include: A first layer of storage structure is formed, comprising a first conductive line, a first storage array, a second conductive line, and a patterned hard mask stacked sequentially along a first direction. The first conductive line extends along a second direction, and the second conductive line extends along a third direction that intersects the second direction. The first direction is perpendicular to the second direction and the third direction. The first storage array comprises a plurality of first storage cells arranged in an array. A first initial medium filling layer is formed to cover the first layer of storage structure, and the first initial medium filling layer is located between the first storage cells; The patterned hard mask and the first initial dielectric fill layer are etched back until the second conductive line is exposed, and a first dielectric fill layer is formed between adjacent first memory cells, the first dielectric fill layer exposing at least a portion of the sidewall of the second conductive line; An anti-fluorine corrosion layer and an etching stop layer are formed sequentially, wherein the anti-fluorine corrosion layer at least covers the sidewall of the second conductive line, and the etching stop layer at least covers the first dielectric filling layer; After the fluorine corrosion resistant layer and the etching stop layer are formed, a second memory cell is formed on the first memory cell.

2. The method according to claim 1, characterized in that, The sequential formation of the anti-fluorine corrosion layer and the etching stop layer includes: A fluorine corrosion resistant layer is formed, which covers the top surface of the second conductive wire, the exposed sidewalls, and the surface of the first dielectric filling layer; An etching stop layer is formed on the fluorine corrosion resistant layer.

3. The method according to claim 1 or 2, characterized in that, The thickness of both the anti-fluorine corrosion layer and the etching stop layer ranges from 5 Å to 40 Å.

4. The method according to claim 3, characterized in that, The materials of the fluorine corrosion resistant layer and the etching stop layer include dielectric materials with a dielectric constant of less than 10.

5. The method according to claim 4, characterized in that, The anti-fluorine corrosion layer is silicon nitride, and the etching stop layer is aluminum oxide.

6. The method according to claim 2, characterized in that, The step of forming a second memory cell on the first memory cell after forming the fluorine corrosion resistant layer and the etching stop layer includes: A second initial dielectric fill layer is formed on the etch stop layer to cover the first layer memory structure, and the second initial dielectric fill layer fills the gap between adjacent first memory cells; The second initial dielectric filling layer is planarized until the top surface of the second conductive line is exposed, and a second dielectric filling layer is formed between adjacent first memory cells; A second memory cell stack is formed, covering the top surface of the second conductive line and the second dielectric filling layer; The second memory cell stack is etched based on the etch stop layer to form a second memory cell on each of the first memory cells.

7. The method according to claim 1, characterized in that, The formation of the first-layer storage structure includes: A first conductive material layer and a first memory cell stack located on the first conductive material layer are formed; The first memory cell stack and the first conductive material layer are respectively etched into a plurality of first memory cell strips and first conductive lines extending along the second direction; A second conductive material layer is formed on a plurality of the first memory cell strips, and a patterned hard mask is formed on the second conductive material layer, the patterned hard mask having a plurality of openings exposing the second conductive material layer; The first layer storage structure is obtained by passing through the second conductive material layer and the multiple first storage cell strips along the multiple openings.

8. The method according to claim 1, characterized in that, The first storage unit and / or the second storage unit includes any one of phase-change storage units, select-only storage units, dynamic random access storage units, and flash memory units.

9. A memory, characterized in that, The memory is obtained using the method for fabricating a memory as described in any one of claims 1 to 8; the memory comprises: A first conductive line, a first storage array, a second conductive line, and a second storage array are sequentially stacked along a first direction. The first conductive line extends along a second direction, and the second conductive line extends along a third direction that intersects the second direction. The first direction is perpendicular to the second direction and the third direction. The first storage array includes a plurality of first storage cells arranged in an array, and the second storage array includes a plurality of second storage cells arranged in an array. The first dielectric filling layer located between adjacent first memory cells has at least a portion of the second conductive line sidewalls not covered by the first dielectric filling layer; A fluorine corrosion resistant layer is located at least on the sidewall of the second conductive line that is not covered by the first dielectric filling layer; An etch stop layer is located at least on the surface of the first dielectric filling layer.

10. The memory according to claim 9, characterized in that, The anti-fluorine corrosion layer is silicon nitride, and the etching stop layer is aluminum oxide.

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