Semiconductor device

Abstract

A semiconductor device includes: a barrier layer on a channel layer and including a material having an energy band gap different from an energy band gap of the channel layer; the source electrode and the drain electrode are located on the channel layer; a gate electrode on the barrier layer and between the source electrode and the drain electrode; a gate semiconductor layer between the barrier layer and the gate electrode; a first field dispersion layer between the source electrode and the drain electrode and connected to the source electrode; a second field dispersion layer on the barrier layer and between the gate electrode and the drain electrode, and connected to the first field dispersion layer; and a third field dispersion layer on the barrier layer and between the second field dispersion layer and the drain electrode. An edge of the first field dispersion layer is aligned with an edge of the third field dispersion layer in a vertical direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Power semiconductor devices are semiconductor devices used to handle high voltages or high currents and perform functions such as power conversion and control in high-power systems or high-output electronic devices. Power semiconductor devices can be used in a wide range of fields, including transportation such as electric vehicles, railways, and electric trams; renewable energy systems such as solar and wind power generation; and mobile devices. Power semiconductor devices have the ability and robustness to handle high power, so they can handle large amounts of current and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can improve efficiency by minimizing power losses. Furthermore, power semiconductor devices can be stably driven even in high-temperature environments.

[0003] These power semiconductor devices can be categorized based on their materials, and examples include silicon carbide (SiC) power semiconductor devices and gallium nitride (GaN) power semiconductor devices. The high-temperature instability of silicon can be compensated for by using SiC or GaN instead of existing silicon (Si) in the fabrication of power semiconductor devices. SiC power semiconductor devices can withstand high temperatures and have low power losses, making them suitable for electric vehicles, renewable energy systems, and more. GaN power semiconductor devices may be more expensive, but they can be highly efficient in terms of speed and are suitable for high-speed charging of mobile devices. Summary of the Invention

[0004] One or more embodiments provide a semiconductor device with stable electrical characteristics and improved reliability.

[0005] According to one aspect of an embodiment, a semiconductor device includes: a channel layer; a barrier layer located on the channel layer, the barrier layer comprising a material having a band gap different from that of the channel layer; a source electrode located on the channel layer; a drain electrode located on the channel layer; a gate electrode located on the barrier layer and between the source electrode and the drain electrode; a gate semiconductor layer located between the barrier layer and the gate electrode; a first field dispersion layer located between the source electrode and the drain electrode, the first field dispersion layer being connected to the source electrode; a second field dispersion layer located on the barrier layer and between the gate electrode and the drain electrode, the second field dispersion layer being connected to the first field dispersion layer; and a third field dispersion layer located on the barrier layer and between the second field dispersion layer and the drain electrode. The edges of the first field dispersion layer and the third field dispersion layer are aligned in a vertical direction.

[0006] According to another aspect of an embodiment, a semiconductor device includes: a channel layer; a barrier layer located on the channel layer, the barrier layer comprising a material having a band gap different from that of the channel layer; a source electrode located on the channel layer; a drain electrode located on the channel layer; a gate electrode located on the barrier layer and between the source electrode and the drain electrode; a gate semiconductor layer located between the barrier layer and the gate electrode; a first field dispersion layer located between the source electrode and the drain electrode, the first field dispersion layer being connected to the source electrode; a second field dispersion layer located between the barrier layer and the first field dispersion layer and between the gate electrode and the drain electrode, the second field dispersion layer being connected to the first field dispersion layer; and a third field dispersion layer located between the barrier layer and the first field dispersion layer and between the second field dispersion layer and the drain electrode. A single third field dispersion layer extends from a first edge of the semiconductor device to a second edge of the semiconductor device. The distance between the drain electrode and the first field dispersion layer is equal to the distance between the drain electrode and the third field dispersion layer.

[0007] According to another aspect of the embodiments, a semiconductor device includes: a channel layer including gallium nitride; a barrier layer located on the channel layer and including aluminum gallium nitride; a source electrode located on the channel layer; a drain electrode located on the channel layer; a gate electrode located on the barrier layer and between the source electrode and the drain electrode; a gate semiconductor layer located between the barrier layer and the gate electrode, the gate semiconductor layer including gallium nitride doped with p-type impurities; a first protective layer located on the barrier layer, the first protective layer at least partially covering the gate electrode; a second protective layer located on the first protective layer; a first field dispersion layer located on the second protective layer, wherein the first field dispersion layer overlaps with the gate electrode in a vertical direction and is integrally formed with the source electrode; a second field dispersion layer located between the first protective layer and the second protective layer, wherein the second field dispersion layer overlaps with the first field dispersion layer in a vertical direction and includes titanium nitride; and a third field dispersion layer located between the first protective layer and the second protective layer and between the second field dispersion layer and the drain electrode, wherein the third field dispersion layer includes titanium nitride. The distance from the side surface of the gate electrode to the side surface of the first field dispersion layer is equal to the distance from the side surface of the gate electrode to the side surface of the third field dispersion layer.

[0008] According to one or more embodiments, the reliability of semiconductor devices can be improved. Attached Figure Description

[0009] The above and other aspects and features will be more readily understood from the following description of exemplary embodiments with reference to the accompanying drawings, in which: Figure 1 A top view of a semiconductor device according to an embodiment is shown.

[0010] Figure 2 and Figure 3 Each shows a path along according to some embodiments Figure 1 A cross-sectional view taken from line A-A'.

[0011] Figure 4 An example is shown. Figure 2 Top view of region S1.

[0012] Figures 5 to 9 It shows the relationship with Figure 1 The top view corresponding to region S1 in the figure shows a semiconductor device according to some embodiments.

[0013] Figure 10 It shows the relationship with Figure 1 The cross-sectional view corresponding to A-A' shows a semiconductor device according to some embodiments.

[0014] Figures 11 to 14 Each shows a top view of a semiconductor device according to some embodiments.

[0015] Figure 15 The following is shown according to the embodiment. Figure 14 The cross-sectional view taken by line B-B'. Detailed Implementation

[0016] In the following description, embodiments will be given more fully with reference to the accompanying drawings. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure.

[0017] For the sake of clarity in describing this disclosure, parts that are not relevant to the description may be omitted, and throughout this specification, the same reference numerals denote the same or similar parts.

[0018] Furthermore, for better understanding and ease of description, the dimensions and thicknesses of the constituent components shown in the accompanying drawings may be arbitrarily given. In the drawings, the thicknesses of layers, regions, films, panels, areas, etc., may be exaggerated for clarity. Therefore, the embodiments are not limited to the dimensions and thicknesses shown.

[0019] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be located directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in this specification, the terms "on" or "above" indicate being located above or below a portion of the object and do not necessarily indicate being located on the upper side of the portion of the object based on the direction of gravity.

[0020] Furthermore, unless explicitly stated otherwise, the word "including" and variations such as "including" or "comprising" will be understood to imply inclusion of the stated element, but not exclusion of any other element. When preceding a list of elements, expressions such as "at least one" modify the entire list of elements, not individual elements within the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0021] Furthermore, throughout this specification, the phrase "in a top view" refers to the view of a portion of the object from above, and the phrase "in a cross-sectional view" refers to the view of a section taken by vertically cutting the portion of the object from the side.

[0022] In the following text, reference will be made to Figures 1 to 4 A semiconductor device according to an embodiment is described.

[0023] Figure 1 A top view of a semiconductor device according to an embodiment is shown. Figure 2 and Figure 3 Each showed along Figure 1 A cross-sectional view taken from line A-A'. Figure 4 It shows Figure 2 Top view of region S1. Figure 2 The diagram illustrates the state in which the semiconductor device 100 according to an embodiment is in an off state, and... Figure 3 The semiconductor device 100 according to an embodiment is shown in the on state.

[0024] refer to Figures 1 to 4 The semiconductor device 100 according to the embodiment may include a channel layer 132, a barrier layer 136 on the channel layer 132, a gate electrode 155 on the barrier layer 136, a gate semiconductor layer 152 between the barrier layer 136 and the gate electrode 155, a source electrode 170 and a drain electrode 190 located on opposite sides of the gate electrode 155 and connected to the channel layer 132, a first field dispersion layer 210 located between the source electrode 170 and the drain electrode 190 and electrically connected to the source electrode 170, a second field dispersion layer 220 located between the gate electrode 155 and the drain electrode 190, and a third field dispersion layer 230 located between the second field dispersion layer 220 and the drain electrode 190.

[0025] The channel layer 132 is a layer that forms a channel between the source electrode 170 and the drain electrode 190, and a two-dimensional electron gas (2DEG) 134 may be located inside the channel layer 132. The two-dimensional electron gas 134 is a charge transport model used in solid-state physics, and refers to a group of electrons that can move freely in two dimensions (e.g., along the X and Y directions extending in the XY plane) but cannot move in another dimension (e.g., the Z direction) and are tightly bound within the two dimensions. In this respect, the two-dimensional electron gas 134 can exist in a two-dimensional paper-like form in three-dimensional space. This two-dimensional electron gas 134 can primarily occur in semiconductor heterojunction structures, and in the semiconductor device 100 according to the embodiment, it can occur at the interface between the channel layer 132 and the barrier layer 136. For example, the two-dimensional electron gas 134 can be generated in the portion of the channel layer 132 adjacent to the barrier layer 136.

[0026] The channel layer 132 may comprise one or more materials selected from group III-V materials, such as nitrides comprising aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The channel layer 132 may be formed as a single layer or multiple layers. The channel layer 132 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, and x+y≤1). For example, channel layer 132 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or combinations thereof. Channel layer 132 may be a doped layer or an undoped layer. The thickness of channel layer 132 may be approximately several hundred nanometers (nm) or less.

[0027] The channel layer 132 may be located on the substrate 110, and the seed layer 121 and the buffer layer 120 may be disposed between the substrate 110 and the channel layer 132. The substrate 110, seed layer 121, and buffer layer 120 are layers used to form the channel layer 132, and may be omitted in some cases. For example, when a substrate made of gallium nitride (GaN) is used as the channel layer 132, at least one of the substrate 110, seed layer 121, or buffer layer 120 may be omitted. Considering the relatively high cost of substrates made of gallium nitride (GaN), a substrate 110 made of silicon (Si) may be used to grow the channel layer 132 including gallium nitride (GaN). In this case, since the lattice structure of Si is different from that of gallium nitride (GaN), it may not be easy to grow the channel layer 132 directly on the substrate 110. Therefore, a seed layer 121 and a buffer layer 120 can be grown on the substrate 110 first, and then a channel layer 132 can be grown on the buffer layer 120. In addition, at least one of the substrate 110, the seed layer 121, or the buffer layer 120 can be removed during manufacturing and is not included in the final structure of the semiconductor device 100 after use in the manufacturing process.

[0028] Substrate 110 may include semiconductor materials. For example, substrate 110 may include sapphire, silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or combinations thereof. Substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of substrate 110 is not limited to these, and substrate 110 may include different materials. In some cases, substrate 110 may include an insulating material. For example, several layers including channel layer 132 may first be formed on the semiconductor substrate, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

[0029] The seed layer 121 can be directly disposed on the substrate 110. However, the embodiment is not limited to this, and another predetermined layer can be further disposed between the substrate 110 and the seed layer 121. The seed layer 121 is a layer that serves as a seed for growing the buffer layer 120, and can be made of a lattice structure that serves as a seed for the buffer layer 120. The buffer layer 120 can be directly disposed on the seed layer 121. However, the embodiment is not limited to this, and another predetermined layer can be further disposed between the seed layer 121 and the buffer layer 120. The seed layer 121 may include one or more materials selected from group III-V materials, for example, nitrides containing aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The seed layer 121 may be Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, and x+y≤1). For example, the seed layer 121 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or combinations thereof.

[0030] A buffer layer 120 may be disposed on the seed layer 121. The buffer layer 120 may be disposed between the seed layer 121 and the channel layer 132. The buffer layer 120 may be a layer used to mitigate the difference in lattice constant and coefficient of thermal expansion between the seed layer 121 and the channel layer 132, or to prevent leakage current from flowing through the channel layer 132. The buffer layer 120 may include one or more materials selected from group III-V materials, for example, nitrides comprising aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The buffer layer 120 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, and x+y≤1). For example, buffer layer 120 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or combinations thereof.

[0031] The buffer layer 120 of the semiconductor device 100 according to the embodiment may include a superlattice layer 124 located on a seed layer 121 and a high-resistivity layer 126 located on the superlattice layer 124. The superlattice layer 124 and the high-resistivity layer 126 may be sequentially located on the substrate 110.

[0032] A superlattice layer 124 may be located on the seed layer 121. The superlattice layer 124 may be directly located on the seed layer 121. However, the embodiments are not limited to this, and another predetermined layer may be further disposed between the seed layer 121 and the superlattice layer 124. The superlattice layer 124 may be a layer used to mitigate the difference in lattice constant and coefficient of thermal expansion between the substrate 110 and the channel layer 132, thereby mitigating the tensile and compressive stresses generated between the substrate 110 and the channel layer 132, and mitigating stress between the entire layers formed by growth in the final structure of the semiconductor device 100 according to the embodiment. The superlattice layer 124 may include one or more materials selected from group III-V materials, for example, nitrides comprising aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The superlattice layer 124 may be Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, and x+y≤1). For example, the superlattice layer 124 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or combinations thereof.

[0033] In an embodiment, the superlattice layer 124 may be formed from multiple alternating layers comprising different materials. For example, the superlattice layer 124 may have a structure in which layers made of AlGaN and layers made of AlN are repeatedly stacked. That is, AlGaN / AlN / AlGaN / AlGaN / AlN can be sequentially stacked to form a superlattice layer. The number of AlGaN and AlN layers constituting the superlattice layer 124 may vary, and the materials constituting the superlattice layer 124 may vary. As another example, the superlattice layer 124 may have a structure in which layers made of AlGaN and layers made of GaN are repeatedly stacked. That is, AlGaN / GaN / AlGaN / GaN / AlGaN / GaN can be sequentially stacked to form a superlattice layer. In embodiments, when the superlattice layer 124 comprises gallium nitride (GaN), indium nitride (InN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum nitride (AlN), aluminum indium gallium nitride (AlInGaN), or a combination thereof, the superlattice layer 124 may have n-type semiconductor characteristics in which the electron concentration is greater than the hole concentration, but the embodiments are not limited thereto.

[0034] A high-resistivity layer 126 may be located on the superlattice layer 124. The high-resistivity layer 126 may be directly located on the superlattice layer 124. However, the embodiments are not limited to this, and another predetermined layer may be further disposed between the superlattice layer 124 and the high-resistivity layer 126. The high-resistivity layer 126 may be located between the superlattice layer 124 and the channel layer 132. The high-resistivity layer 126 may be a layer that prevents degradation of the semiconductor device 100 according to the embodiment by preventing leakage current from flowing through the channel layer 132. The high-resistivity layer 126 may be made of a low-conductivity material to electrically insulate the substrate 110 and the channel layer 132. The high-resistivity layer may include one or more materials selected from group III-V materials, for example, nitrides comprising aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The high-resistivity layer 126 may be Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, and x+y≤1). For example, the high-resistivity layer 126 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or combinations thereof. The high-resistivity layer 126 may be formed as a single layer or multiple layers.

[0035] The semiconductor device 100 according to the embodiment may further include a barrier layer 136 located on the channel layer 132.

[0036] A barrier layer 136 may be disposed on the channel layer 132. The barrier layer 136 may be directly disposed on the channel layer 132. However, the embodiment is not limited to this, and another predetermined layer may be further disposed between the channel layer 132 and the barrier layer 136. The region of the channel layer 132 overlapping with the barrier layer 136 between the source electrode 170 and the drain electrode 190 may be a drift region DTR. The drift region DTR may be located between the source electrode 170 and the drain electrode 190. The drift region DTR may refer to the region to which charge carriers move when a potential difference occurs between the source electrode 170 and the drain electrode 190.

[0037] The semiconductor device 100 according to the embodiment may be controlled to be in an on or off state depending on whether a voltage is applied to the gate electrode 155 and / or the magnitude of the voltage applied to the gate electrode 155, and thus may enable or prevent the movement of charge carriers in the drift region DTR.

[0038] The barrier layer 136 may comprise one or more materials selected from group III-V materials, such as nitrides comprising aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The barrier layer 136 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, and x+y≤1). The barrier layer 136 may include gallium nitride (GaN), indium nitride (InN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum nitride (AlN), aluminum indium gallium nitride (AlInGaN), or combinations thereof. The band gap of the barrier layer 136 can be adjusted by controlling the composition ratio of Al and / or In. The barrier layer 136 may be doped with predetermined impurities. In this case, the impurities doped in the barrier layer 136 may be p-type impurities capable of providing holes. For example, the impurities doped in the barrier layer 136 may be magnesium (Mg). The threshold voltage, on-resistance, etc., of the semiconductor device 100 according to the embodiment can be controlled by increasing or decreasing the impurity doping concentration of the barrier layer 136.

[0039] The barrier layer 136 may comprise a semiconductor material having properties different from those of the channel layer 132. The barrier layer 136 may differ from the channel layer 132 in at least one of the following: polarization characteristics, band gap, or lattice constant. For example, the barrier layer 136 may comprise a material having a band gap different from that of the channel layer 132. In this case, the barrier layer 136 may have a higher band gap and a higher polarization than the channel layer 132. A two-dimensional electron gas 134 may be induced in the channel layer 132, which has a relatively low polarization, through the barrier layer 136. In this respect, the barrier layer 136 may also be referred to as a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gas 134 may be formed within a portion of the channel layer 132 located below the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 may have a very high electron mobility.

[0040] The barrier layer 136 can be formed as a single layer or multiple layers. When the barrier layer 136 is made of multiple layers, the material of each layer constituting the multiple layers can have a different band gap. In this case, the various layers constituting the barrier layer 136 can be arranged such that the band gap increases as the layer approaches the channel layer 132.

[0041] Gate electrode 155 may be located on barrier layer 136. Gate electrode 155 may overlap with some regions of barrier layer 136 in the third direction (Z direction). Gate electrode 155 may overlap with a portion of the drift region DTR of channel layer 132 in the third direction (Z direction). Gate electrode 155 may be located between source electrode 170 and drain electrode 190. Gate electrode 155 may be spaced apart from source electrode 170 and drain electrode 190. For example, gate electrode 155 may be positioned closer to source electrode 170 than drain electrode 190. That is, the spacing between gate electrode 155 and source electrode 170 may be smaller than the spacing between gate electrode 155 and drain electrode 190, but the embodiments are not limited thereto. In an embodiment, gate electrode 155 may overlap with the first field dispersion layer 210, which will be described later, in the third direction (Z direction), and may not overlap with the second field dispersion layer 220, which will be described later, and the third field dispersion layer 230, which will be described later, in the third direction (Z direction). Here, the third direction (Z direction) can indicate the thickness direction and vertical direction of the channel layer 132.

[0042] The gate electrode 155 may include a conductive material. For example, the gate electrode 155 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the gate electrode 155 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten. The gate electrode 155 may be formed as a single layer or multiple layers. It may also be composed of: (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but is not limited thereto.

[0043] In an embodiment, the semiconductor device may further include a hard mask layer located on the gate electrode 155. The hard mask layer may be a hard mask used during the patterning of the gate electrode material layer and / or the gate semiconductor layer in the process of forming the gate electrode 155. However, the hard mask layer may be removed depending on the etch conditions of the gate electrode material layer and / or the gate semiconductor layer during etching or the cleaning conditions after etching. For example, the hard mask layer may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0044] A gate semiconductor layer 152 may be located between a barrier layer 136 and a gate electrode 155. That is, the gate semiconductor layer 152 may be located on the barrier layer 136, and the gate electrode 155 may be located on the gate semiconductor layer 152. The gate electrode 155 may have a Schottky or ohmic contact with the gate semiconductor layer 152. The gate semiconductor layer 152 may overlap with the gate electrode 155 in the third direction (Z direction). In this case, the gate semiconductor layer 152 may completely overlap with the gate electrode 155 in the third direction (Z direction), and the upper surface of the gate semiconductor layer 152 may be completely covered by the gate electrode 155. That is, the gate semiconductor layer 152 may have a planar shape substantially the same as the planar shape of the gate electrode 155. However, the embodiments are not limited to this, and the gate electrode 155 may be positioned to cover at least a portion of the gate semiconductor layer 152. For example, a portion of the gate semiconductor layer 152 may not be covered by the gate electrode 155.

[0045] A gate semiconductor layer 152 may be disposed between the source electrode 170 and the drain electrode 190. The gate semiconductor layer 152 may be spaced apart from the source electrode 170 and the drain electrode 190. The gate semiconductor layer 152 may be positioned closer to the source electrode 170 than the drain electrode 190. That is, the spacing between the gate semiconductor layer 152 and the source electrode 170 may be smaller than the spacing between the gate semiconductor layer 152 and the drain electrode 190, but the embodiments are not limited to this.

[0046] In this embodiment, the gate semiconductor layer 152 may overlap with the gate electrode 155 in the third direction (Z direction). For example, the gate semiconductor layer 152 may completely overlap with the gate electrode 155 in the third direction (Z direction). For example, the side surface of the gate semiconductor layer 152 may be coplanar with the side surface of the gate electrode 155. However, the embodiment is not limited to this, and the gate semiconductor layer 152 may partially overlap with the gate electrode 155. For example, the side surface of the gate semiconductor layer 152 may be located between the side surfaces of the gate electrode 155.

[0047] The gate semiconductor layer 152 may comprise one or more materials selected from group III-V materials, such as nitrides comprising aluminum (Al), gallium (Ga), indium (In), boron (B), or combinations thereof. The gate semiconductor layer 152 may be Al x In y Ga 1-x- y N (0≤x≤1, 0≤y≤1, and x+y≤1). For example, the gate semiconductor layer 152 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), or combinations thereof. The gate semiconductor layer 152 may include a material having a band gap different from that of the barrier layer 136. For example, the gate semiconductor layer 152 may include GaN, and the barrier layer 136 may include AlGaN. The gate semiconductor layer 152 may be doped with predetermined impurities. In this case, the impurities doped in the gate semiconductor layer 152 may be p-type dopants capable of providing holes. For example, the gate semiconductor layer 152 may include GaN doped with p-type impurities. That is, the gate semiconductor layer 152 may be made of a p-GaN layer. The embodiments are not limited thereto, and the gate semiconductor layer 152 may be a p-AlGaN layer.

[0048] The depletion region DPR can be formed within the channel layer 132 via the gate semiconductor layer 152. The depletion region DPR can be located within the drift region DTR and can have a narrower width than the drift region DTR. Since the gate semiconductor layer 152, having a different band gap than the barrier layer 136, is disposed on the barrier layer 136, the band level of the portion of the barrier layer 136 overlapping with the gate semiconductor layer 152 can be increased. Therefore, the depletion region DPR can be formed in the region of the channel layer 132 overlapping with the gate semiconductor layer 152. The depletion region DPR can be a region where no two-dimensional electron gas 134 is formed in the channel path of the channel layer 132, or it can have a lower electron concentration than the remaining region. That is, the depletion region DPR can indicate the region where the flow of the two-dimensional electron gas 134 within the drift region DTR is interrupted. When the depletion region DPR appears, current no longer flows between the source electrode 170 and the drain electrode 190, and the channel path can be blocked. Therefore, the semiconductor device 100 according to the embodiment can have normally off characteristics.

[0049] In other words, the semiconductor device 100 according to the embodiment can be a normally-off high electron mobility transistor (HEMT). For example... Figure 2 As shown, in the normal state where no voltage is applied to the gate electrode 155, a depletion region DPR may exist, and the semiconductor device 100 according to the embodiment may be in a turn-off state. Figure 3 As shown, when a voltage higher than the threshold voltage is applied to the gate electrode 155, the depletion region DPR can disappear, and the two-dimensional electron gas 134 can remain connected within the drift region DTR without disconnecting. In this respect, the two-dimensional electron gas 134 can extend continuously from the source electrode 170 to the drain electrode 190. That is, the two-dimensional electron gas 134 can be formed throughout the entire channel path between the source electrode 170 and the drain electrode 190, and the semiconductor device 100 according to the embodiment can be in a conducting state. In summary, the semiconductor device 100 according to the embodiment can include semiconductor layers with different polarization characteristics, and the semiconductor layer with relatively large polarization can induce the two-dimensional electron gas 134 in another semiconductor layer heterogeneously bonded to it. This two-dimensional electron gas 134 can be used as a channel between the source electrode 170 and the drain electrode 190, and the continuity or interruption of the flow of this two-dimensional electron gas 134 can be controlled by applying a bias voltage to the gate electrode 155. When the gate is off, the flow of the two-dimensional electron gas 134 can be blocked, so current can not flow between the source electrode 170 and the drain electrode 190. As the two-dimensional electron gas 134 continues to flow when the gate is on, current can flow between the source electrode 170 and the drain electrode 190.

[0050] Although the semiconductor device 100 according to the embodiment has been described above as a normally-off high electron mobility transistor, the embodiment is not limited thereto. For example, the semiconductor device 100 according to the embodiment can be a normally-on high electron mobility transistor. In the case of a normally-on high electron mobility transistor, the gate semiconductor layer 152 can be omitted, and therefore the gate electrode 155 can be located directly on the barrier layer 136. That is, the gate electrode 155 can be in contact with the barrier layer 136. In this structure, the two-dimensional electron gas 134 can be used as a channel when no voltage is applied to the gate electrode 155, and current can flow between the source electrode 170 and the drain electrode 190. In addition, when a negative voltage is applied to the gate electrode 155, a depletion region DPR in which the flow of the two-dimensional electron gas 134 is interrupted can appear at the lower part of the gate electrode 155.

[0051] The seed layer 121, superlattice layer 124, high-resistivity layer 126, channel layer 132, barrier layer 136, and gate semiconductor layer 152 described above can be sequentially stacked on the substrate 110. In the semiconductor device 100 according to the embodiment, at least one of the seed layer 121, superlattice layer 124, high-resistivity layer 126, channel layer 132, barrier layer 136, or gate semiconductor layer 152 may be omitted. The seed layer 121, superlattice layer 124, high-resistivity layer 126, channel layer 132, barrier layer 136, and gate semiconductor layer 152 can be formed from the same base semiconductor material, and the material composition ratio of each layer can be different considering the function of each layer, the performance required by the semiconductor device 100, etc.

[0052] The semiconductor device 100 according to the embodiment may further include a protective layer 140 located on the barrier layer 136.

[0053] A protective layer 140 may be located on the barrier layer 136 and the gate electrode 155. The protective layer 140 may cover the upper and side surfaces of the gate electrode 155 and the side surface of the gate semiconductor layer 152. Therefore, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 may be protected by the protective layer 140. However, embodiments are not limited thereto, and the gate electrode 155 may extend through the protective layer 140 to connect to the gate semiconductor layer 152, and the protective layer 140 may not cover the upper surface of the gate electrode 155. Alternatively, the lower surface of the protective layer 140 may contact the gate semiconductor layer 152. The protective layer 140 may include an insulating material. For example, the protective layer 140 may include oxides such as silicon dioxide (SiO2) or aluminum oxide (Al2O3). As another example, the protective layer 140 may also include nitrides such as silicon nitride (SiN) or oxides such as silicon oxynitride (SiON).

[0054] The protective layer 140 of the semiconductor device 100 according to the embodiment may include a first protective layer 141 located on the barrier layer 136 and a second protective layer 142 located on the first protective layer 141.

[0055] A first protective layer 141 may be located on the barrier layer 136 and the gate electrode 155. The first protective layer 141 may cover the upper and side surfaces of the gate electrode 155 and the side surface of the gate semiconductor layer 152. The first protective layer 141 may be conformally located on the upper and side surfaces of the gate electrode 155 and the side surface of the gate semiconductor layer 152. The lower surface of the first protective layer 141 may contact the barrier layer 136 and the gate electrode 155. A second protective layer 142 may be located on the first protective layer 141. The second protective layer 142 may be conformally located on the first protective layer 141. The first protective layer 141 and the second protective layer 142 may comprise the same material or may comprise different materials.

[0056] exist Figures 2 to 4 In this embodiment, the protective layer 140 is depicted as comprising two layers, but the embodiments are not limited thereto. For example, the protective layer 140 may be formed to comprise a single layer or three or more layers.

[0057] The source electrode 170 and the drain electrode 190 are located on the channel layer 132. The source electrode 170 and the drain electrode 190 can be in direct contact with the channel layer 132 and can be electrically connected to the channel layer 132.

[0058] Source electrode 170 and drain electrode 190 may extend in a second direction (Y direction). Source electrode 170 and drain electrode 190 may be spaced apart from each other, and gate electrode 155 and gate semiconductor layer 152 may be disposed between source electrode 170 and drain electrode 190. Gate electrode 155 and gate semiconductor layer 152 may be spaced apart from source electrode 170 and drain electrode 190. For example, source electrode 170 may be electrically connected to channel layer 132 on a first side of gate electrode 155, and drain electrode 190 may be electrically connected to channel layer 132 on a second side of gate electrode 155. Source electrode 170 and drain electrode 190 may be located outside the drift region DTR of channel layer 132. The boundary between source electrode 170 and channel layer 132 may be a first edge of drift region DTR. Therefore, the boundary between drain electrode 190 and channel layer 132 may be a second edge of drift region DTR.

[0059] The source electrode 170 and drain electrode 190 can be located within a trench recessed into the upper surface of the channel layer 132. Specifically, trenches extending through the protective layer 140 and the barrier layer 136 and recessed into the upper surface of the channel layer 132 can be located on opposite sides of the gate electrode 155 and spaced apart from each other. The source electrode 170 and drain electrode 190 can be located in the trenches located on opposite sides of the gate electrode 155. The source electrode 170 and drain electrode 190 can be formed to fill the interior of the trench. Within the trench, the source electrode 170 and drain electrode 190 can contact the channel layer 132 and the barrier layer 136. The channel layer 132 can form the bottom surface and sidewalls of the trench, and the barrier layer 136 can form the sidewalls of the trench. Therefore, the source electrode 170 and drain electrode 190 can contact the upper surface and side surface of the channel layer 132. In addition, the source electrode 170 and drain electrode 190 can contact the side surface of the barrier layer 136. In other words, the source electrode 170 and the drain electrode 190 can cover the side surfaces of the channel layer 132 and the barrier layer 136. However, the embodiments are not limited to this, and the channel layer 132 may not be recessed, and the source electrode 170 and the drain electrode 190 may contact the channel layer 132.

[0060] In one embodiment, the upper surfaces of the source electrode 170 and the drain electrode 190 may protrude beyond the upper surface of the protective layer 140. The source electrode 170 and the drain electrode 190 may cover at least a portion of the side surface of the protective layer 140. However, the embodiment is not limited to this, and the source electrode 170 and the drain electrode 190 may cover at least a portion of the side surface of the protective layer 140, but may not cover the remaining portion of the side surface of the protective layer 140. In this case, the remaining portion of the protective layer 140 may be located on the upper surfaces of the source electrode 170 and the drain electrode 190.

[0061] The source electrode 170 and drain electrode 190 may include conductive materials. For example, the source electrode 170 and drain electrode 190 may include metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal oxides. For example, the source electrode 170 and drain electrode 190 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). The materials used may include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but the embodiments are not limited thereto. The source electrode 170 and drain electrode 190 may be formed as a single layer or multiple layers. The source electrode 170 and drain electrode 190 may be in ohmic contact with the channel layer 132. Compared to other regions, the regions within the channel layer 132 that are in contact with the source electrode 170 and drain electrode 190 may be doped at a relatively high concentration.

[0062] exist Figure 2 and Figure 3 In this embodiment, a semiconductor device 100 is shown including pairs of source electrodes 170 and drain electrodes 190, but the number of source electrodes 170 and drain electrodes 190 is not limited thereto. For example, the source electrodes 170 may include a plurality of source electrodes sequentially stacked in a third direction (Z direction) on a channel layer 132, and the drain electrodes 190 may include a plurality of drain electrodes sequentially stacked in a third direction (Z direction) on a channel layer 132. This will be referred to Figure 10 To be described later.

[0063] The first field dispersion layer 210 may be disposed between the source electrode 170 and the drain electrode 190. The first field dispersion layer 210 may be located on the barrier layer 136. The first field dispersion layer 210 may be located on the protective layer 140, which is located on the barrier layer 136. For example, the first field dispersion layer 210 may be located on the second protective layer 142. The first field dispersion layer 210 may overlap with the channel layer 132 in the third direction (Z direction). In an embodiment, the first field dispersion layer 210 may overlap with the gate electrode 155 and the gate semiconductor layer 152 in the third direction (Z direction), but the embodiment is not limited to this.

[0064] The first field dispersion layer 210 can be electrically connected to the source electrode 170. Additionally, the first field dispersion layer 210 can be electrically connected to the second field dispersion layer 220, which will be described later, via a first via CV1 extending through the second protective layer 142. The first field dispersion layer 210 can be positioned spaced apart from the third field dispersion layer 230, which will be described later. The first field dispersion layer 210 can also be non-electrically connected to (i.e., electrically isolated from) the third field dispersion layer 230.

[0065] The first field dispersion layer 210 may be located between the gate electrode 155 and the drain electrode 190. For example, the channel layer 132 may include a first region AR1 that overlaps with the first field dispersion layer 210 in a third direction (Z direction) between the gate electrode 155 and the drain electrode 190, and a second region AR2 that does not overlap with the first field dispersion layer 210 in the third direction (Z direction). The first field dispersion layer 210 may be located in the first region AR1 and may not be located in the second region AR2. The first field dispersion layer 210 may extend from a first side of the gate electrode 155 toward the drain electrode 190. Therefore, at least a portion of the channel layer 132 located between the gate electrode 155 and the drain electrode 190 may overlap with the first field dispersion layer 210 in the third direction (Z direction). Here, the third direction (Z direction) may indicate the thickness direction and vertical direction of the channel layer 132.

[0066] The first field dispersion layer 210 may include a side surface 210_S facing the drain electrode 190. The side surface 210_S of the first field dispersion layer 210 may face the drain electrode 190. The side surface 210_S of the first field dispersion layer 210 may correspond to the boundary between the first region AR1 and the second region AR2. In an embodiment, the side surface 210_S of the first field dispersion layer 210 may have a first surface roughness. The first surface roughness may be defined by unevenness, grooves, etc., present on the side surface 210_S of the first field dispersion layer 210. For example, the surface roughness may be large when the maximum length of the protrusion from the surface baseline, the length deviation of the protrusions present on the surface, etc., are large. In an embodiment, the first surface roughness of the side surface 210_S of the first field dispersion layer 210 may be attributed to the characteristics of the conductive material constituting the first field dispersion layer 210.

[0067] The first field dispersion layer 210 may include the same material as the source electrode 170. The first field dispersion layer 210 may include a conductive material. For example, the first field dispersion layer 210 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The first field dispersion layer 210 may be located in the same layer as at least a portion of the source electrode 170. For example, a portion of the source electrode 170 located on the second protective layer 142 may be located in the same layer as the first field dispersion layer 210. The first field dispersion layer 210 may be formed together with the source electrode 170 in the same process. The first field dispersion layer 210 may be integrally formed with the source electrode 170. However, the embodiments are not limited thereto, and the first field dispersion layer 210 may be located in a different layer than the source electrode 170 and may be formed in a different process.

[0068] The first field dispersion layer 210 can be used to disperse the electric field concentrated around the gate electrode 155. Specifically, in the gate-off state, the two-dimensional electron gas 134 can be located at a very high concentration in the portion of the channel layer 132 located between the gate electrode 155 and the source electrode 170, and in another portion of the channel layer 132 located between the gate electrode 155 and the drain electrode 190. In this case, the electric field can be concentrated on the gate electrode 155 or the gate semiconductor layer 152. The gate electrode 155 and the gate semiconductor layer 152 can be susceptible to the electric field, and when the electric field is concentrated, the leakage current can increase and the breakdown voltage of the semiconductor device 100 can decrease. According to an embodiment, the first field dispersion layer 210 of the semiconductor device 100 can be located in a first region AR1 of the channel layer 132, thereby dispersing the electric field concentrated around the gate electrode 155 or the gate semiconductor layer 152, thereby reducing the leakage current and increasing the breakdown voltage.

[0069] like Figure 4 As shown, the first field dispersion layer 210 of the semiconductor device 100 according to the embodiment may include a first portion 210_P1 to a third portion 210_P3.

[0070] The first portion 210_P1 may cover the gate electrode 155. For example, the first portion 210_P1 may be located on the second protective layer 142 and overlap with the gate electrode 155 and the gate semiconductor layer 152 in the third direction (Z direction). The second portion 210_P2 may extend from a first side of the first portion 210_P1 toward the drain electrode 190. The second portion 210_P2 may be located on the second protective layer 142 and may overlap with the second field dispersion layer 220 and the third field dispersion layer 230, which will be described later, in the third direction (Z direction). The second portion 210_P2 may not overlap with the gate electrode 155 and the gate semiconductor layer 152 in the third direction (Z direction) (i.e., it may be offset from the gate electrode 155 and the gate semiconductor layer 152). The second portion 210_P2 may include a side surface facing the drain electrode 190. In an embodiment, the first portion 210_P1 and the second portion 210_P2 may be integrally formed. Part 210_P1 and Part 210_P2 may contain the same material.

[0071] The third portion 210_P3 may be located within the first through-hole CV1, which extends through the second protective layer 142 to expose the second protective layer 142. The third portion 210_P3 may fill the first through-hole CV1. The third portion 210_P3 may overlap with the second field dispersion layer 220, which will be described later, in the third direction (Z direction). The first field dispersion layer 210 and the second field dispersion layer 220, which will be described later, may be electrically connected through the third portion 210_P3. In an embodiment, the third portion 210_P3 may be integrally formed with the first portion 210_P1 and the second portion 210_P2. The third portion 210_P3 may include the same material as the first portion 210_P1 and the second portion 210_P2. However, the embodiment is not limited thereto; the third portion 210_P3 may include a different material than the first portion 210_P1 and the second portion 210_P2, and may be formed separately in different processes.

[0072] In this embodiment, the number of first field dispersion layers 210 may vary. For example, the first field dispersion layer 210 may include a plurality of first field dispersion layers located on the second protective layer 142.

[0073] The second field dispersion layer 220 may be located between the source electrode 170 and the drain electrode 190. The second field dispersion layer 220 may also be located between the gate electrode 155 and the drain electrode 190. The second field dispersion layer 220 may be positioned to be spaced apart from the gate electrode 155 and the gate semiconductor layer 152 along a first direction (X direction). Therefore, the second field dispersion layer 220 may not overlap with the gate electrode 155 and the gate semiconductor layer 152 along a third direction (Z direction) (i.e., it may be offset from the gate electrode 155 and the gate semiconductor layer 152). Additionally, the second field dispersion layer 220 may be positioned to be spaced apart from the drain electrode 190 along the first direction (X direction). The second field dispersion layer 220 may be located in the first region AR1 of the channel layer 132. That is, the second field dispersion layer 220 may be located on the lower surface of the first field dispersion layer 210. The second field dispersion layer 220 may overlap with the first field dispersion layer 210 in the third direction (Z direction). For example, the second field dispersion layer 220 can completely overlap with the first field dispersion layer 210 in the third direction (Z direction).

[0074] The second field dispersion layer 220 may be located on the barrier layer 136. The second field dispersion layer 220 may also be located on the protective layer 140, which is located on the barrier layer 136. For example, the second field dispersion layer 220 may be located between the first protective layer 141 and the second protective layer 142. The second field dispersion layer 220 may be located between the first protective layer 141 and the first field dispersion layer 210. The thickness of the second field dispersion layer 220 along the third direction (Z direction) may be less than or equal to the second thickness TH2 of the first field dispersion layer 210 along the third direction (Z direction).

[0075] In this embodiment, the upper surface of the second field dispersion layer 220 may be located at a lower horizontal level than the upper surface of the gate electrode 155. That is, the upper surface of the second field dispersion layer 220 may be positioned closer to the upper surface of the channel layer 132 than the upper surface of the gate electrode 155. At least a portion of the second field dispersion layer 220 may overlap with the gate electrode 155 in the first direction (X direction), but the embodiment is not limited thereto.

[0076] In an embodiment, the lower surface of the second field dispersion layer 220 may be located at a higher horizontal level than the lower surface of the gate semiconductor layer 152. That is, the lower surface of the second field dispersion layer 220 may be positioned further away from the upper surface of the channel layer 132 than the lower surface of the gate semiconductor layer 152. This can be attributed to the process characteristics of forming the first protective layer 141 after patterning the gate semiconductor layer 152 and the gate electrode 155, and forming the second field dispersion layer 220 on the first protective layer 141 to be spaced apart from the gate electrode 155 and the gate semiconductor layer 152 along a first direction (X direction). In an embodiment, the upper surface of the second field dispersion layer 220 may be located at a higher horizontal level than the upper surface of the gate semiconductor layer 152. That is, the upper surface of the second field dispersion layer 220 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate semiconductor layer 152, but the embodiment is not limited to this.

[0077] In an embodiment, the second field dispersion layer 220 may be electrically connected to the first field dispersion layer 210. For example, the second field dispersion layer 220 may be electrically connected to the first field dispersion layer 210 through a first through-hole CV1 extending through the second protective layer 142, but the embodiment is not limited thereto.

[0078] The second field dispersion layer 220 may include a conductive material. The second field dispersion layer 220 may include a material different from that of the first field dispersion layer 210. For example, the second field dispersion layer 220 may include TiN. However, the embodiments are not limited thereto. As another example, the second field dispersion layer 220 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride.

[0079] The third field dispersion layer 230 may be located between the second field dispersion layer 220 and the drain electrode 190. The third field dispersion layer 230 may also be located between the gate electrode 155 and the drain electrode 190. The third field dispersion layer 230 may be positioned to be spaced apart from the gate electrode 155 and the gate semiconductor layer 152 along a first direction (X direction). Therefore, the third field dispersion layer 230 may not overlap with the gate electrode 155 and the gate semiconductor layer 152 along a third direction (Z direction) (i.e., it may be offset from the gate electrode 155 and the gate semiconductor layer 152). Additionally, the third field dispersion layer 230 may be positioned to be spaced apart from the second field dispersion layer 220 along the first direction (X direction). Furthermore, the third field dispersion layer 230 may be positioned to be spaced apart from the drain electrode 190 along the first direction (X direction). In an embodiment, the third field dispersion layer 230 may refer to a field dispersion layer located between the barrier layer 136 and the first field dispersion layer 210 and between the second field dispersion layer 220 and the drain electrode 190.

[0080] In an embodiment, a single third field dispersion layer 230 may be provided. The single third field dispersion layer 230 may extend along a second direction (Y direction) in a top view. The third field dispersion layer 230 may extend from a first edge of the semiconductor device to a second edge of the semiconductor device in the second direction (Y direction). The third field dispersion layer 230 may extend parallel to the second field dispersion layer 220, but the embodiment is not limited thereto. The single third field dispersion layer 230 may be located between the second field dispersion layer 220 and the drain electrode 190. However, the embodiment is not limited thereto, and multiple third field dispersion layers 230 may be arranged along the second direction (Y direction). Alternatively, the third field dispersion layer 230 may be arranged along a first direction (X direction).

[0081] The third field dispersion layer 230 may overlap with the first field dispersion layer 210 in the third direction (Z direction). For example, the third field dispersion layer 230 may completely overlap with the first field dispersion layer 210 in the third direction (Z direction). The third field dispersion layer 230 may be located on the lower surface of the first field dispersion layer 210. In an embodiment, the third field dispersion layer 230 may be located in the first region AR1 of the channel layer 132 and may not be located in the second region AR2. That is, the third field dispersion layer 230 may be located in the first region AR1 of the channel layer 132.

[0082] The third field dispersion layer 230 may include a side surface 230_S facing the drain electrode 190. The side surface 230_S of the third field dispersion layer 230 may face the side surface of the drain electrode 190. For example, as... Figure 4 As shown, when a single third field dispersion layer 230 is provided, the side surface 230_S of the third field dispersion layer 230 can be the edge of the third field dispersion layer 230. In the following text, the side surface 230_S of the third field dispersion layer 230 can refer to the edge of the individually provided third field dispersion layer 230.

[0083] In an embodiment, the side surface 230_S of the third field dispersion layer 230 may have a second surface roughness less than or equal to the first surface roughness. The second surface roughness may be defined by unevenness, grooves, etc., present on the side surface 230_S of the third field dispersion layer 230. For example, the surface roughness may be large when the maximum length of the protrusion from the surface baseline, the deviation of the length of the protrusion present on the surface, etc., are large. In an embodiment, the surface roughness of the side surface 230_S of the third field dispersion layer 230 may be less than the surface roughness of the side surface 210_S of the first field dispersion layer 210. For example, the side surface 230_S of the third field dispersion layer 230 may have a smaller area ratio of unevenness or grooves per unit area than the side surface 210_S of the first field dispersion layer 210. As another example, the side surface 230_S of the third field dispersion layer 230 may have a smaller maximum protrusion length of unevenness compared to the side surface 210_S of the first field dispersion layer 210. The second surface roughness of the side surface 230_S of the third field dispersion layer 230 can be attributed to the properties of the conductive material constituting the third field dispersion layer 230.

[0084] The edge of the third field dispersion layer 230 can be aligned with the edge of the first field dispersion layer 210. For example, when a single third field dispersion layer 230 is provided, the edge of the third field dispersion layer 230 can indicate the side surface 230_S of the third field dispersion layer 230. The side surface 230_S of the third field dispersion layer 230 can be aligned with the side surface 210_S of the first field dispersion layer 210 and the reference axis AX. In this document, the reference axis AX can indicate an axis extending from the side surface 210_S of the first field dispersion layer 210 along the third direction (Z direction) in a cross section formed along a first direction (X direction) and a third direction (Z direction).

[0085] Therefore, the distance from the side surface of the gate electrode 155 to the side surface 230_S of the third field dispersion layer 230 can be substantially equal to the distance from the side surface of the gate electrode 155 to the side surface 210_S of the first field dispersion layer 210. Furthermore, the distance between the drain electrode 190 and the third field dispersion layer 230 along the first direction (X direction) can be substantially equal to the distance between the drain electrode 190 and the first field dispersion layer 210 along the first direction (X direction).

[0086] In an embodiment, the distance between the third field dispersion layer 230 and the drain electrode 190 along the first direction (X direction) can be greater than or equal to the distance between the third field dispersion layer 230 and the gate electrode 155 along the first direction (X direction). In an embodiment, the distance between the side surface of the gate electrode 155 and the side surface 210_S of the first field dispersion layer 210 along the first direction (X direction) can be less than or equal to the distance between the side surface 230_S of the third field dispersion layer 230 and the side surface of the drain electrode 190 along the first direction (X direction). In this case, the first width W1 of the third field dispersion layer 230 along the first direction (X direction) can be from 180 nanometers (nm) to 350 nanometers (nm). Within this range, the third field dispersion layer 230 can be sufficiently spaced from the second field dispersion layer 220 and easily aligned with the side surface 210_S of the first field dispersion layer 210.

[0087] The third field dispersion layer 230 may be located in the same layer as the second field dispersion layer 220. For example, the third field dispersion layer 230 and the second field dispersion layer 220 may be located between the first protective layer 141 and the second protective layer 142. The third field dispersion layer 230 and the second field dispersion layer 220 may be located between the barrier layer 136 and the first field dispersion layer 210.

[0088] In this embodiment, the upper surface of the third field dispersion layer 230 may be located at a lower horizontal level than the upper surface of the gate electrode 155. That is, the upper surface of the third field dispersion layer 230 may be positioned closer to the upper surface of the channel layer 132 than the upper surface of the gate electrode 155. At least a portion of the third field dispersion layer 230 may overlap with the gate electrode 155 in the first direction (X direction), but the embodiment is not limited thereto.

[0089] In an embodiment, the lower surface of the third field dispersion layer 230 may be located at a higher horizontal level than the lower surface of the gate semiconductor layer 152. That is, the lower surface of the third field dispersion layer 230 may be positioned further away from the upper surface of the channel layer 132 than the lower surface of the gate semiconductor layer 152. This can be attributed to the process characteristics of forming the first protective layer 141 after patterning the gate semiconductor layer 152 and the gate electrode 155, and forming the third field dispersion layer 230 on the first protective layer 141 to be spaced apart from the gate electrode 155 and the gate semiconductor layer 152 along a first direction (X direction). In an embodiment, the upper surface of the third field dispersion layer 230 may be located at a higher horizontal level than the upper surface of the gate semiconductor layer 152. That is, the upper surface of the third field dispersion layer 230 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate semiconductor layer 152, but the embodiment is not limited to this. The thickness TH1 of the third field dispersion layer 230 along the third direction (Z direction) can be less than or equal to the second thickness TH2 of the first field dispersion layer 210 along the third direction (Z direction).

[0090] In this embodiment, the third field dispersion layer 230 may be floating. For example, the third field dispersion layer 230 may not be connected to ground or other voltage sources.

[0091] The third field dispersion layer 230 may include a conductive material. The third field dispersion layer 230 may include the same material as the second field dispersion layer 220. The third field dispersion layer 230 may include a material different from the material of the first field dispersion layer 210. For example, the third field dispersion layer 230 may include TiN. However, the embodiments are not limited thereto. As another example, the third field dispersion layer 230 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride.

[0092] When the side surface 210_S of the first field dispersion layer 210 of the semiconductor device 100 according to the embodiment has a first surface roughness, the electric field concentrated around the gate electrode 155 or the gate semiconductor layer 152 may not be effectively dispersed. Since the side surface 230_S of the third field dispersion layer 230 of the semiconductor device 100 according to the embodiment is aligned with the side surface 210_S of the first field dispersion layer 210, the electric field concentrated around the gate electrode 155 or the gate semiconductor layer 152 can be effectively dispersed, and the reliability of the semiconductor device 100 according to the embodiment can be improved.

[0093] In the following text, reference will be made to Figures 5 to 9 Describes a semiconductor device according to some embodiments.

[0094] Figures 5 to 9 It shows the relationship with Figure 1The top view corresponding to region S1 in the figure shows a semiconductor device according to some embodiments.

[0095] Figures 5 to 9 It shows that according to Figures 1 to 4 Examples of various modifications to the semiconductor device in the illustrated embodiment. Figures 5 to 9 The modification example shown is the same as Figures 1 to 4 The examples shown are essentially the same, so their descriptions will be omitted and the differences between them will be described primarily. Additionally, the same reference numerals are used for the same parts.

[0096] refer to Figure 5 Multiple third field dispersion layers 230 can be provided in a semiconductor device according to some embodiments. For example, the third field dispersion layer 230 may include a first patterned portion 231 located on a first side of the second field dispersion layer 220 and a second patterned portion 232 located between the second field dispersion layer 220 and the first patterned portion 231.

[0097] The first pattern portion 231 and the second pattern portion 232 may be spaced apart from each other along a first direction (X direction). The first pattern portion 231 and the second pattern portion 232 may overlap with the first field dispersion layer 210 in a third direction (Z direction). For example, the first pattern portion 231 and the second pattern portion 232 may completely overlap with the first field dispersion layer 210 in the third direction (Z direction). The first pattern portion 231 and the second pattern portion 232 may be located in the first region AR1 of the channel layer 132. Figure 2 )middle.

[0098] In some embodiments, since the third field dispersion layer 230 includes a plurality of patterned portions 231 and 232, the edge of the third field dispersion layer 230 can be defined as the side surface 231_S of the first patterned portion 231. For example, the edge of the third field dispersion layer 230 can indicate the side surface 231_S of the first patterned portion 231 facing the drain electrode 190.

[0099] In some embodiments, the side surface 231_S of the first patterned portion 231 may have a second surface roughness less than or equal to the first surface roughness. The side surface 231_S of the first patterned portion 231 may be aligned with the side surface 210_S of the first field dispersion layer 210. This description is consistent with... Figures 1 to 4 The description of the third field dispersion layer 230 in the illustrated embodiment is substantially the same and will therefore be omitted.

[0100] refer to Figure 6According to some embodiments, the second field dispersion layer 220 and the third field dispersion layer 230 of the semiconductor device may not overlap with the gate semiconductor layer 152 in the first direction (X direction). For example, the lower surfaces of the second field dispersion layer 220 and the third field dispersion layer 230 may be located at a higher horizontal level than the upper surface of the gate semiconductor layer 152. That is, the lower surfaces of the second field dispersion layer 220 and the third field dispersion layer 230 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate semiconductor layer 152. This is because the thickness of the first protective layer 141 along the third direction (Z direction) is greater than the thickness of the gate semiconductor layer 152 along the third direction (Z direction).

[0101] refer to Figure 7 and Figure 8 According to some embodiments, the semiconductor device may also include a third protective layer 143 located between the first protective layer 141 and the second protective layer 142.

[0102] The third protective layer 143 may be located on the first protective layer 141. The third protective layer 143 may include an insulating material. The third protective layer 143 may include the same material as the first protective layer 141 and the second protective layer 142, but the embodiments are not limited thereto. For example, the third protective layer 143 may include oxides such as silicon dioxide (SiO2) or aluminum oxide (Al2O3). As another example, the third protective layer 143 may also include nitrides such as silicon nitride (SiN) or oxides of oxynitride such as silicon oxynitride (SiON).

[0103] In some embodiments, the second field dispersion layer 220 and the third field dispersion layer 230 may be located in different layers.

[0104] For example, such as Figure 7 As shown, the second field dispersion layer 220 can be located between the first protective layer 141 and the third protective layer 143, and the third field dispersion layer 230 can be located between the third protective layer 143 and the second protective layer 142. Therefore, the lower surface of the third field dispersion layer 230 can be located at a higher horizontal level than the lower surface of the second field dispersion layer 220. The lower surface of the third field dispersion layer 230 can be positioned further away from the upper surface of the channel layer 132 than the lower surface of the second field dispersion layer 220. Additionally, the upper surface of the third field dispersion layer 230 can be located at a higher horizontal level than the upper surface of the second field dispersion layer 220. The upper surface of the third field dispersion layer 230 can be positioned further away from the upper surface of the channel layer 132 than the upper surface of the second field dispersion layer 220.

[0105] As another example, such as Figure 8As shown, the second field dispersion layer 220 can be located between the third protective layer 143 and the second protective layer 142, and the third field dispersion layer 230 can be located between the first protective layer 141 and the third protective layer 143. Therefore, the lower surface of the third field dispersion layer 230 can be located at a lower horizontal level than the lower surface of the second field dispersion layer 220. The lower surface of the third field dispersion layer 230 can be positioned closer to the upper surface of the channel layer 132 than the lower surface of the second field dispersion layer 220. Additionally, the upper surface of the third field dispersion layer 230 can be located at a lower horizontal level than the upper surface of the second field dispersion layer 220. The upper surface of the third field dispersion layer 230 can be positioned closer to the upper surface of the channel layer 132 than the upper surface of the second field dispersion layer 220.

[0106] exist Figure 7 and Figure 8 In this embodiment, the protective layer 140 is depicted as comprising three layers, but the embodiment is not limited thereto. For example, the protective layer 140 may be formed to comprise four or more layers.

[0107] refer to Figure 9 According to some embodiments, at least a portion of the third field dispersion layer 230 of the semiconductor device may not overlap with the first field dispersion layer 210 in the third field direction (Z direction) (i.e., it may be offset from the first field dispersion layer 210). In some embodiments, at least a portion of the third field dispersion layer 230 may overlap with the first field dispersion layer 210 in the third field direction (Z direction), and the remaining portion of the third field dispersion layer 230 may not overlap with the first field dispersion layer 210 in the third field direction (Z direction). The side surface 230_S of the third field dispersion layer 230 may protrude from the side surface 210_S of the first field dispersion layer 210 toward the drain electrode 190. That is, the side surface 230_S of the third field dispersion layer 230 may be positioned further away from the side surface of the gate electrode 155 than the side surface 210_S of the first field dispersion layer 210.

[0108] In the following text, reference will be made to Figure 10 Describes a semiconductor device according to some embodiments.

[0109] Figure 10 It shows the relationship with Figure 1 The cross-sectional view corresponding to line A-A' shows a semiconductor device according to some embodiments.

[0110] Figure 10 It shows that according to Figures 1 to 4 Examples of various modifications to the semiconductor device in the illustrated embodiment. Figure 10 and Figures 1 to 4 The embodiments shown are similar, therefore their descriptions will be omitted and the differences between them will be mainly described. Additionally, the same reference numerals are used for the same parts.

[0111] refer to Figure 10 According to some embodiments, the semiconductor device 100_1 may also include an upper protective layer 180 located on the protective layer 140.

[0112] The upper protective layer 180 may be located on the protective layer 140, the source electrode 170, and the drain electrode 190. The upper protective layer 180 may include an insulating material. The upper protective layer 180 may include the same material as the protective layer 140, but the embodiments are not limited thereto. For example, the upper protective layer 180 may include oxides such as silicon dioxide (SiO2) or aluminum oxide (Al2O3). As another example, the upper protective layer 180 may also include nitrides such as silicon nitride (SiN) or oxides of oxynitride such as silicon oxynitride (SiON).

[0113] According to some embodiments, a plurality of source electrodes 170 and a plurality of drain electrodes 190 may be provided for the semiconductor device 100_1.

[0114] For example, source electrode 170 may include a plurality of source electrodes 171 and 172 sequentially stacked in a third direction (Z direction) on channel layer 132, and drain electrode 190 may include a plurality of drain electrodes 191 and 192 sequentially stacked in a third direction (Z direction) on channel layer 132. First source electrode 171 and first drain electrode 191 may be electrically connected to channel layer 132 by extending through protective layer 140 and barrier layer 136. Second source electrode 172 may be electrically connected to first source electrode 171 by upper protective layer 180. Then, second drain electrode 192 may be electrically connected to first drain electrode 191 by extending through upper protective layer 180.

[0115] According to some embodiments, a first field dispersion layer 210_1 of the semiconductor device 100_1 may be located on the upper protective layer 180. The first field dispersion layer 210_1 may be integrally formed with the second source electrode 172. The first field dispersion layer 210_1 may comprise the same material as the second source electrode 172. The remainder of the description of the first field dispersion layer 210_1 is consistent with... Figures 1 to 4 The description of the first dispersion layer 210 is essentially the same, so it will be omitted.

[0116] In some embodiments, the second field dispersion layer 220 and the third field dispersion layer 230 may be located between the protective layer 140 and the upper protective layer 180. The second field dispersion layer 220 may be electrically connected to the first field dispersion layer 210_1 via a second through-hole CV2 extending through the upper protective layer 180. In some embodiments, the second field dispersion layer 220 may be located in the same layer as the third field dispersion layer 230. The lower surface of the second field dispersion layer 220 may be located at substantially the same horizontal level as the lower surface of the third field dispersion layer 230, but the embodiments are not limited thereto.

[0117] In some embodiments, the lower surface of the second field dispersion layer 220 may be located at a higher horizontal level than the upper surface of the gate semiconductor layer 152. The lower surface of the second field dispersion layer 220 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate semiconductor layer 152. Additionally, the lower surface of the third field dispersion layer 230 may be located at a higher horizontal level than the upper surface of the gate semiconductor layer 152. The lower surface of the third field dispersion layer 230 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate semiconductor layer 152.

[0118] In some embodiments, the lower surface of the second field dispersion layer 220 may be located at a higher level than the upper surface of the gate electrode 155. The lower surface of the second field dispersion layer 220 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate electrode 155. Additionally, the lower surface of the third field dispersion layer 230 may be located at a higher level than the upper surface of the gate electrode 155. The lower surface of the third field dispersion layer 230 may be positioned further away from the upper surface of the channel layer 132 than the upper surface of the gate electrode 155. However, the embodiments are not limited to this, and the lower surfaces of the second field dispersion layer 220 and the third field dispersion layer 230 may be located at lower levels than the upper surface of the gate electrode 155.

[0119] The remaining descriptions of the second dispersion layer 220 and the third dispersion layer 230 are consistent with... Figures 1 to 4 The descriptions of the second field dispersion layer 220 and the third field dispersion layer 230 are essentially the same, and therefore will be omitted.

[0120] In the following text, reference will be made to Figures 11 to 15 Describes a semiconductor device according to some embodiments.

[0121] Figures 11 to 14 Each shows a top view of a semiconductor device according to some embodiments. Figure 15 It shows along Figure 14 The cross-sectional view taken by line B-B'.

[0122] Figures 11 to 15 Various examples of modifications to the semiconductor device according to the embodiments are shown. Figures 11 to 15 The modification example shown is the same as Figures 1 to 4 The examples shown are essentially the same, so their descriptions will be omitted and the differences between them will be described primarily. Additionally, the same reference numerals are used for the same parts.

[0123] refer to Figure 11According to some embodiments, the semiconductor device 100_2 may include a plurality of third field dispersion patterns 230P spaced apart from each other along a second direction (Y direction). The plurality of third field dispersion patterns 230P may be positioned to be spaced apart along the second direction (Y direction). Each of the third field dispersion patterns 230P may have a rectangular shape in a top view, but embodiments are not limited thereto. In some embodiments, the side surface of each third field dispersion pattern 230P facing the drain electrode 190 may be aligned with the side surface of the first field dispersion layer 210.

[0124] refer to Figure 12 and Figure 13 Semiconductor devices 100_3 and 100_4, according to some embodiments, may include a plurality of second field dispersion patterns 220P spaced apart from each other along a second direction (Y direction). The plurality of second field dispersion patterns 220P may be positioned to be spaced apart along the second direction (Y direction). Each of the second field dispersion patterns 220P may have a rectangular shape in a top view, but the embodiments are not limited thereto.

[0125] In some embodiments, such as Figure 12 As shown, each second field dispersion pattern 220P can be electrically connected to the first field dispersion layer 210 through a third via CV3. However, the embodiments are not limited to this, as... Figure 13 As shown, some of the second field dispersion patterns 220P of the semiconductor device 100_4 according to some embodiments can be electrically connected to the first field dispersion layer 210 through the third via CV3, and some others can be not electrically connected to (i.e., can be electrically isolated from) the first field dispersion layer 210. That is, some of the second field dispersion patterns 220P can be floating (i.e., not connected to ground or other voltage sources).

[0126] refer to Figure 14 and Figure 15 According to some embodiments, the semiconductor device 100_5 may also include a partition structure 160 located on the first side of the channel layer 132.

[0127] The separator 160 may be located on a first side of the channel layer 132 in the second direction (Y direction), but the embodiments are not limited thereto. In some embodiments, the separator 160 may extend through the barrier layer 136 and the channel layer 132. For example, the separator 160 may be recessed into at least a portion of the substrate 110 by extending through the barrier layer 136, the channel layer 132, the seed layer 121, and the buffer layer 120. However, the embodiments are not limited thereto, and as another example, the separator 160 may extend through the barrier layer 136 and the channel layer 132 and may be recessed into at least a portion of the buffer layer 120.

[0128] In some embodiments, the partition structure 160 can be formed by forming a barrier layer 136 on the channel layer 132 and performing an ion implantation process within a portion of the barrier layer 136. For example, in the region of the channel layer 132 that overlaps with the region where an ion implantation process is performed in the barrier layer 136 along a third direction (Z direction), a two-dimensional electron gas may not be formed or a very small two-dimensional electron gas may be formed. In this case, the ion implantation region of the barrier layer 136 and the corresponding region of the channel layer 132 can correspond to the partition structure 160. As another example, a gate semiconductor layer 152 can be located on the barrier layer 136, and the gate semiconductor layer 152 can be patterned after an ion implantation process is performed on its upper end. Thus, the exposed ion implantation regions of the barrier layer 136, the channel layer 132, and the buffer layer 120 can correspond to the partition structure 160. The material used in the ion implantation process can be argon (Ar) ions.

[0129] However, the embodiments are not limited to this, and the partition structure 160 can be formed by forming a barrier layer 136 on the channel layer 132, forming a trench extending through the barrier layer 136, and then filling the trench with an insulating material. During the process of forming the trench, at least a portion of the channel layer 132 may also be recessed. In this case, the insulating material constituting the partition structure 160 may include the same material as the protective layer 140. For example, the insulating material constituting the partition structure 160 may include oxides such as SiO2 or Al2O3. As another example, the insulating material constituting the partition structure 160 may include nitrides such as SiN or oxide oxynitrides such as SiON. However, the embodiments are not limited to this, and the insulating material constituting the partition structure 160 may include a material different from the material of the protective layer 140.

[0130] In some embodiments, a portion of the first field dispersion layer 210 may be located on the separator structure 160. For example, the first field dispersion layer 210 may include a portion overlapping the channel layer 132 in the third direction (Z direction) and a fourth portion 210_P4 overlapping the separator structure 160. In some embodiments, the first field dispersion layer 210 may overlap the second field dispersion layer 220 and the third field dispersion layer 230 in the third direction (Z direction) around the gate electrode 155. Therefore, the first field dispersion layer 210 may not overlap the gate electrode 155 in the third direction (Z direction) (i.e., it may be offset from the gate electrode 155).

[0131] While this disclosure has been described in conjunction with what is now considered to be actual embodiments, it will be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Channel layer; A barrier layer located on the channel layer, the barrier layer comprising a material having a band gap different from that of the channel layer; Source electrode, the source electrode being located on the channel layer; Drain electrode, the drain electrode being located on the channel layer; A gate electrode, the gate electrode being located on the barrier layer and between the source electrode and the drain electrode; A gate semiconductor layer, wherein the gate semiconductor layer is located between the barrier layer and the gate electrode; A first field dispersion layer is located between the source electrode and the drain electrode, and the first field dispersion layer is connected to the source electrode; A second field dispersion layer is located on the barrier layer and between the gate electrode and the drain electrode, and the second field dispersion layer is connected to the first field dispersion layer; and A third field dispersion layer is located on the barrier layer and between the second field dispersion layer and the drain electrode. The edges of the first field dispersion layer and the third field dispersion layer are aligned vertically.

2. The semiconductor device according to claim 1, wherein, A single third field dispersion layer extends from the first edge of the semiconductor device to the second edge of the semiconductor device, and Wherein, the distance from the side surface of the gate electrode to the side surface of the first field dispersion layer is equal to the distance from the side surface of the gate electrode to the side surface of the third field dispersion layer.

3. The semiconductor device according to claim 1, wherein, The third field dispersion layer completely overlaps with the first field dispersion layer along the vertical direction.

4. The semiconductor device according to claim 3, wherein, The distance between the third field dispersion layer and the drain electrode along the first direction is greater than or equal to the distance between the third field dispersion layer and the gate electrode along the first direction.

5. The semiconductor device according to claim 4, wherein, The distance between the side surface of the gate electrode and the side surface of the first field dispersion layer along the first direction is less than or equal to the distance between the side surface of the third field dispersion layer and the side surface of the drain electrode along the first direction.

6. The semiconductor device according to claim 4, wherein, The width of the third field dispersion layer along the first direction ranges from 180 nanometers to 350 nanometers.

7. The semiconductor device according to claim 1, wherein, The channel layer includes a first region and a second region, the first region overlapping the first field dispersion layer along the vertical direction between the gate electrode and the drain electrode, and the second region offset from the first field dispersion layer along the vertical direction. The third field dispersion layer overlaps with the first region along the vertical direction.

8. The semiconductor device according to claim 1, wherein, The first field dispersion layer is integrally formed with the source electrode and comprises the same material as the source electrode. The second field dispersion layer comprises the same material as the third field dispersion layer.

9. The semiconductor device according to claim 8, wherein, The third field dispersion layer comprises titanium nitride, and the first field dispersion layer comprises a material different from that of the third field dispersion layer.

10. The semiconductor device according to claim 1, wherein, The side surface of the first field dispersion layer has a first surface roughness, and the side surface of the third field dispersion layer has a second surface roughness that is less than or equal to the first surface roughness.

11. The semiconductor device according to claim 1, wherein, The thickness of the first field dispersion layer along the vertical direction is greater than the thickness of the third field dispersion layer along the vertical direction.

12. The semiconductor device according to claim 1, further comprising: A first protective layer is located on the barrier layer and at least partially covers the gate electrode; and A second protective layer is placed on top of the first protective layer. Wherein, the first field dispersion layer is located on the second protective layer, and The second field dispersion layer and the third field dispersion layer are located between the first protective layer and the second protective layer.

13. The semiconductor device of claim 12, further comprising a third protective layer located between the first protective layer and the second protective layer. in, The second field dispersion layer is located between the first protective layer and the third protective layer, and The third field dispersion layer is located between the third protective layer and the second protective layer.

14. The semiconductor device according to claim 1, further comprising: A protective layer, which is located on the barrier layer and at least partially covers the gate electrode; and Upper protective layer, the upper protective layer being located on the protective layer, The source electrode includes: A first source electrode, the first source electrode being located on the channel layer and penetrating the protective layer; and A second source electrode extends through the upper protective layer and connects to the first source electrode. The first field dispersion layer is located on the upper protective layer, and the first field dispersion layer comprises the same material as the second source electrode. The second field dispersion layer and the third field dispersion layer are located between the protective layer and the upper protective layer.

15. A semiconductor device, the semiconductor device comprising: Channel layer; A barrier layer located on the channel layer, the barrier layer comprising a material having a band gap different from that of the channel layer; Source electrode, the source electrode being located on the channel layer; Drain electrode, the drain electrode being located on the channel layer; A gate electrode, the gate electrode being located on the barrier layer and between the source electrode and the drain electrode; A gate semiconductor layer, wherein the gate semiconductor layer is located between the barrier layer and the gate electrode; A first field dispersion layer is located between the source electrode and the drain electrode, and the first field dispersion layer is connected to the source electrode; A second field dispersion layer is located between the barrier layer and the first field dispersion layer and between the gate electrode and the drain electrode, and the second field dispersion layer is connected to the first field dispersion layer; and A third field dispersion layer is located between the barrier layer and the first field dispersion layer, and between the second field dispersion layer and the drain electrode. Wherein, a single third field dispersion layer extends from the first edge of the semiconductor device to the second edge of the semiconductor device, and The distance between the drain electrode and the first field dispersion layer is equal to the distance between the drain electrode and the third field dispersion layer.

16. The semiconductor device according to claim 15, wherein, The second and third field dispersion layers completely overlap the first field dispersion layer along the vertical direction.

17. The semiconductor device according to claim 15, wherein, Along the vertical direction, the upper surface of the third field dispersion layer is closer to the upper surface of the channel layer than the upper surface of the gate electrode.

18. The semiconductor device according to claim 15, wherein, The gate electrode overlaps perpendicularly with the first field dispersion layer and is offset from the second and third field dispersion layers.

19. The semiconductor device according to claim 15, wherein, The third field dispersion layer comprises titanium nitride, and the first field dispersion layer comprises a material different from that of the third field dispersion layer.

20. A semiconductor device, the semiconductor device comprising: A channel layer, the channel layer comprising gallium nitride; A barrier layer, located on the channel layer, and comprising aluminum gallium nitride; Source electrode, the source electrode being located on the channel layer; Drain electrode, the drain electrode being located on the channel layer; A gate electrode, the gate electrode being located on the barrier layer and between the source electrode and the drain electrode; A gate semiconductor layer, the gate semiconductor layer being located between the barrier layer and the gate electrode, the gate semiconductor layer comprising gallium nitride doped with p-type impurities; A first protective layer is located on the barrier layer and at least partially covers the gate electrode; A second protective layer is located on top of the first protective layer; A first field dispersion layer is located on the second protective layer, wherein the first field dispersion layer overlaps with the gate electrode along the vertical direction and is integrally formed with the source electrode; A second field dispersion layer is located between the first protective layer and the second protective layer, wherein the second field dispersion layer overlaps with the first field dispersion layer along the vertical direction and includes titanium nitride; and A third field dispersion layer is located between the first protective layer and the second protective layer, and between the second field dispersion layer and the drain electrode, wherein the third field dispersion layer comprises titanium nitride. Wherein, the distance from the side surface of the gate electrode to the side surface of the first field dispersion layer is equal to the distance from the side surface of the gate electrode to the side surface of the third field dispersion layer.

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