Solar cell, photovoltaic module and photovoltaic system

Abstract

The invention provides a solar cell, a photovoltaic module and a photovoltaic system. The solar cell includes: a semiconductor substrate having a first surface, the first surface including a spacer region, and a first region and a second region located on opposite sides of the spacer region in a first direction parallel to the first surface; the first doped layer is located in the first region, and the second doped layer is located in the second region; and the grid line covers at least part of the spacing region and is in contact with at least one of the first doping layer and the second doping layer.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and more specifically, to a solar cell, a photovoltaic module, and a photovoltaic system. Background Technology

[0002] In existing photovoltaic cell technology, in order to achieve effective separation and collection of charge, the back design of the cell usually includes alternating N-type doped regions and P-type doped regions. These regions are physically isolated by trench (Gap) regions or spacer regions to prevent current from short-circuiting inside the cell.

[0003] However, existing photovoltaic cell designs suffer from two major technical bottlenecks. First, the high concentration of free carriers in the doped regions leads to parasitic absorption in the long wavelength range, thus reducing the cell's photoelectric conversion efficiency. Second, most of the light incident on the trench (gap) region or spacer region results in transmission loss, leading to a significant deterioration in cell performance.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The main objective of this application is to provide a solution that at least addresses the problem of large light transmission loss in the inter-regional areas of the prior art.

[0006] To achieve the above objectives, according to one aspect of this application, a solar cell is provided. The solar cell includes: a semiconductor substrate having a first surface, the first surface including a spacer region and a first region and a second region located on opposite sides of the spacer region in a first direction, the first direction being parallel to the first surface; a first doped layer and a second doped layer, the first doped layer being located in the first region and the second doped layer being located in the second region; and a grid line covering at least a portion of the spacer region and disposed in contact with at least one of the first doped layer and the second doped layer.

[0007] Optionally, the solar cell further includes a trench structure, in which at least a portion of the trench structure is located between the first doped layer and the second doped layer in a first direction, and the spacing region is the bottom surface of at least a portion of the trench structure.

[0008] Optionally, the gate line includes a first fine gate located in a first region and extending along a second direction. In the first direction, the first fine gate extends from the first region to the spacer region. The first fine gate is electrically connected to the first doped layer and electrically insulated from the semiconductor substrate and the second doped layer. The second direction is parallel to the first surface and intersects the first direction.

[0009] Optionally, the first fine grid covers at least a portion of the spacing area.

[0010] Optionally, the first fine gate covers at least a portion of the spacing region and extends onto the second doped layer.

[0011] Optionally, the orthographic projection of the first fine gate on the first surface is a first orthographic projection, and the orthographic projection of the first doped portion on the first surface is a second orthographic projection. The first orthographic projection covers the second orthographic projection and extends along the first direction into the spacer region.

[0012] Optionally, the gate line includes a second fine gate located in the second region and extending along a second direction, and in the first direction extending from the second region to the spacer region, the second fine gate being electrically connected to the second doped layer and electrically insulated from the first doped layer and the semiconductor substrate.

[0013] Optionally, the second fine grid covers at least a portion of the spacing area.

[0014] Optionally, the second fine gate covers at least a portion of the spacing region and extends onto the first doped layer.

[0015] Optionally, the orthographic projection of the second fine gate on the first surface is a third orthographic projection, and the orthographic projection of the second doped layer on the first surface is a fourth orthographic projection. The third orthographic projection covers the fourth orthographic projection and extends along the first direction into the spacer region.

[0016] Optionally, the grid line includes a first fine grid and a second fine grid extending along a second direction, the first fine grid being located in a first region and extending from the first region to the interval region in a first direction, the second fine grid being located in a second region and extending from the second region to the interval region in a first direction, and the first fine grid and the second fine grid being spaced apart in the interval region.

[0017] Optionally, the orthographic projection of the first fine gate on the first surface is a first orthographic projection, the orthographic projection of the first doped layer on the first surface is a second orthographic projection, the first orthographic projection covers the second orthographic projection and extends along the first direction into the spacer region; the orthographic projection of the second fine gate on the first surface is a third orthographic projection, the orthographic projection of the second doped layer on the first surface is a fourth orthographic projection, the third orthographic projection covers the fourth orthographic projection and extends along the first direction into the spacer region.

[0018] Optionally, the area of ​​the interval region is the first area, the sum of the projected areas of the first fine grid and the second fine grid in the interval region is the second area, and the ratio of the second area to the first area is greater than 0.3 and less than 1.

[0019] Optionally, the ratio of the second area to the first area is greater than 0.5 and less than 1.

[0020] Optionally, the first region and the second region are distributed alternately along the first direction.

[0021] Optionally, the first region and the second region are interdigitated along the first direction.

[0022] Optionally, multiple first fine grids are spaced apart along a first direction, and the grid lines also include a first main grid, which is electrically connected to the multiple first fine grids.

[0023] Optionally, multiple second fine grids are spaced apart along the first direction, and the grid lines also include second main grids, which are electrically connected to the multiple second fine grids.

[0024] Optionally, multiple first main gates and multiple second main gates are alternately distributed in the second direction, and at least one first main gate is located between two adjacent second main gates in the second direction.

[0025] Optionally, in the second direction, the first main gate extends from the first region into the spacing region.

[0026] Optionally, multiple first main gates and multiple second main gates are alternately distributed in the second direction, and at least one second main gate is located between two adjacent first main gates and intersects with at least one second fine gate in the second direction.

[0027] Optionally, in the second direction, the second main gate extends from the second region into the interval region.

[0028] Optionally, the solar cell further includes: an insulating dielectric layer covering a portion of the first doped layer, the spacer region, and a portion of the second doped layer; wherein, if the first fine gate extends into the spacer region, the insulating dielectric layer is located between the first fine gate and the semiconductor substrate, and / or, if the second fine gate extends into the spacer region, the insulating dielectric layer is located between the second fine gate and the semiconductor substrate.

[0029] Optionally, the portion of the insulating dielectric layer covering the first doped portion has a first through-hole, and at least a portion of the material of the first fine gate fills the first through-hole; the portion of the insulating dielectric layer covering the second doped portion has a second through-hole, and at least a portion of the material of the second fine gate fills the first through-hole.

[0030] Optionally, the spaced area accounts for more than 20% of the first surface.

[0031] Optionally, the spaced area occupies more than 30% of the first surface.

[0032] Optionally, the spaced area accounts for more than 50% of the first surface.

[0033] Optionally, in the first direction, the width of the first region is greater than 50 μm, the width of the second region is greater than 50 μm, and the width of the interval region is greater than 30 μm.

[0034] Optionally, the first surface is a textured surface.

[0035] Alternatively, the textured surface may include a polished surface or a velvety surface.

[0036] Optionally, the first and second regions are polished surfaces, and the interval region is velvety.

[0037] Optionally, the velvet surface can be a regular pyramid structure or an inverted pyramid structure.

[0038] Optionally, the first doped layer and the second doped layer have the same doping type.

[0039] Optionally, the doping types of the first doped layer and the second doped layer are opposite.

[0040] According to another aspect of this application, a photovoltaic system is provided, including the photovoltaic module as described above.

[0041] Optionally, the photovoltaic system includes an off-grid solar power system, which includes photovoltaic modules.

[0042] This application provides a solar cell comprising a semiconductor substrate, a first doped layer, a second doped layer, and grid lines. The semiconductor substrate has a first surface including a spacer region and a first region and a second region located opposite each other in a first direction. The first doped layer is located in the first region, and the second doped layer is located in the second region. The grid lines cover at least a portion of the spacer region and are in contact with at least one of the first and second doped layers. Thus, the grid lines cover part or all of the spacer region. Due to the high reflectivity of the grid lines, incident light is reflected from the grid line surface, effectively reflecting a portion of the incident light back into the solar cell. This means that light that might otherwise directly penetrate the solar cell from the spacer region can now be effectively captured. Furthermore, by covering at least a portion of the spacer region with grid lines, the light transmission loss in the spacer region of the solar cell is significantly reduced, improving the photoelectric conversion efficiency of the solar cell. In summary, this application solves the problem of large light transmission loss in the spacer region in the prior art. Attached Figure Description

[0043] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0044] Figure 1 A cross-sectional structural schematic diagram of a solar cell according to an embodiment of this application is shown.

[0045] The above figures include the following reference numerals:

[0046] 10. Semiconductor substrate; 201. First doped layer; 202. Second doped layer; 30. Gate line; 301. First fine gate; 302. Second fine gate; 40. Tunneling layer; 50. Front passivation layer; 501. Alumina layer; 502. Silicon nitride layer; 60. Insulating dielectric layer. Detailed Implementation

[0047] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0048] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0051] As described in the background section, existing photovoltaic cell designs suffer from two main technical bottlenecks. First, the high concentration of free carriers in the doped regions leads to parasitic absorption in the long wavelength range, thereby reducing the cell's photoelectric conversion efficiency. Second, most of the light incident on the trench (gap) region or spacer region results in transmission loss, causing a significant deterioration in cell performance. To address the problem of high light transmission loss in the spacer region in existing technologies, embodiments of this application provide a solar cell, a photovoltaic module, and a photovoltaic system.

[0052] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0053] Figure 1 This is a cross-sectional structural diagram of a solar cell according to an embodiment of this application. Figure 1 As shown, the solar cell includes trenches and further includes: a semiconductor substrate 10 having a first surface, the first surface including a spacer region S3 and a first region S1 and a second region S2 located on opposite sides of the spacer region S3 in a first direction A, the first direction A being parallel to the first surface; a first doped layer 201 and a second doped layer 202, the first doped layer 201 being located in the first region S1 and the second doped layer 202 being located in the second region S2; and a grid line 30 covering at least a portion of the spacer region S3 and being in contact with at least one of the first doped layer 201 and the second doped layer 202.

[0054] In this embodiment, the grid lines 30 cover part or all of the spacing region S3. Due to the high reflectivity of the grid lines 30, incident light is reflected from their surface, effectively reflecting a portion of the incident light back into the solar cell. This means that light that would otherwise directly penetrate the solar cell through the spacing region S3 can now be effectively captured. Furthermore, by covering at least part of the spacing region S3 with grid lines 30, the light transmission loss in the spacing region S3 of the solar cell is significantly reduced, improving the photoelectric conversion efficiency of the solar cell. In summary, this application solves the problem of high light transmission loss in the spacing region S3 in the prior art.

[0055] The first doped layer 201 and the second doped layer 202 can have the same doping type, or they can have different doping types. When the first doped layer 201 and the second doped layer 202 have the same doping type, the solar cell can be a tunneling oxide passivated contact cell (TOPCon cell), and the first doped layer 201 and the second doped layer 202 form a polyfin structure of the TOPCon cell. When the first doped layer 201 and the second doped layer 202 have opposite doping types, the solar cell can be a back contact cell (BC cell).

[0056] Optionally, the material of the gate line 30 includes a metallic material. Further, the metallic material may include copper. For example, the gate line 30 is a copper gate line 30.

[0057] It should be noted that, in a direction perpendicular to the first surface, the spacer region S3 may protrude beyond the first region S1 and the second region S2. For example, the spacer region S3 may be flush with the surface of the first doped layer away from the semiconductor substrate and the surface of the second doped layer away from the semiconductor substrate.

[0058] Alternatively, the aforementioned interval region S3 may be flush with the first region S1 and the second region S2, or the first region S1 and the second region S2 may protrude from the interval region S3 in a direction perpendicular to the first surface. Figure 1 As shown, in some optional embodiments, the solar cell further includes a trench structure (not shown in the figure), in which at least part of the trench structure is located between the first doped layer 201 and the second doped layer 202 in the first direction A, and the spacing region S3 is the bottom surface of at least part of the trench structure.

[0059] Alternatively, in some optional embodiments, the trench structure includes a first portion and a second portion that are connected. The first portion may be located between the first doped layer 201 and the second doped layer 202, and the second portion may be formed by recessing the spacer region S3 in the first surface into the semiconductor substrate 10.

[0060] like Figure 1 As shown, in some optional embodiments, the gate line 30 includes a first fine gate 301, which is located in the first region S1 and extends along a second direction. In the first direction A, the first fine gate 301 extends from the first region S1 to the spacer region S3. The first fine gate 301 is electrically connected to the first doped layer 201 and electrically insulated from the semiconductor substrate 10 and the second doped layer 202. The second direction is parallel to the first surface and intersects the first direction A.

[0061] In the above embodiments, the first fine grid 301 can cover at least a portion of the first doped layer 201 located in the first region S1 and be in contact with the first doped layer 201, thereby enabling the first fine grid 301 and the first doped layer 201 to form a good electrical connection, ensuring effective current collection and transmission. Furthermore, the first fine grid 301 can also cover at least a portion of the spacer region S3. Thus, the presence of the first fine grid 301 can significantly enhance light reflection, which helps the incident light to reflect in the spacer region S3, reduces the possibility of the incident light directly penetrating the solar cell in the spacer region S3, reduces the light transmission loss in the spacer region S3 of the solar cell, increases the residence time of the incident light in the solar cell, and thereby improves the photoelectric conversion efficiency of the solar cell.

[0062] like Figure 1 As shown, it can be understood that the first fine gate 301 is spaced apart from the semiconductor substrate 10 and the second doped layer 202, so that the first fine gate 301 is electrically insulated from the semiconductor substrate 10 and from the second doped layer 202.

[0063] In some exemplary embodiments, to save on the cost of the grid lines 30, the first fine grid 301 covers a portion of the spacer region S3; or in other exemplary embodiments, the first fine grid 301 covers the entire spacer region S3, thus increasing the area of ​​the spacer region S3 covered by the first fine grid 301, thereby further reducing the light transmission loss of incident light in the spacer region S3; or in yet another exemplary embodiment, the first fine grid 301 covers at least a portion of the spacer region S3 and extends to the second doped layer 202. In this way, since the first fine grid 301 can also act as a back reflector in the solar cell, the design of extending the first fine grid 301 to the second doped layer 202 increases the reflective area. This means that more light penetrating to the back of the solar cell (first surface) will be reflected back into the cell by the first fine grid 301, increasing the chance of secondary light absorption, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0064] like Figure 1 As shown, in some optional embodiments, the orthographic projection of the first fine gate 301 on the first surface is a first orthographic projection, the orthographic projection of the first doped layer 201 on the first surface is a second orthographic projection, the first orthographic projection covers the second orthographic projection and extends along the first direction A into the spacer region S3.

[0065] In the above embodiments, the first orthographic projection corresponding to the first fine grid 301 covers the second orthographic projection corresponding to the first doped layer 201. This means that the coverage area of ​​the first fine grid 301 is wider, which allows more light penetrating to the back of the solar cell to be reflected back into the cell by the first fine grid 301, further increasing the opportunity for secondary light absorption and thus further improving the photoelectric conversion efficiency of the solar cell. In addition, if the first orthographic projection corresponding to the first fine grid 301 also extends along the first direction A into the spacer region S3, it means that the first fine grid 301 covers at least part of the spacer region S3 in addition to covering the first doped layer 201. In this way, the high reflectivity of the first fine grid 301 can significantly reduce the light transmission loss of incident light in the spacer region S3, thereby significantly improving the photoelectric conversion efficiency of the solar cell.

[0066] like Figure 1 As shown, in some optional embodiments, the gate line 30 includes a second fine gate 302 located in the second region S2 and extending along the second direction, and in the first direction A, the second fine gate 302 extends from the second region S2 into the trench, the second fine gate 302 is electrically connected to the second doped layer 202 and electrically insulated from the first doped layer 201 and the semiconductor substrate 10.

[0067] In the above embodiments, the second fine grid 302 can cover at least a portion of the second doped layer 202 located in the second region S2 and be in contact with the second doped layer 202, thereby forming a good electrical connection between the second fine grid 302 and the second doped layer 202, ensuring effective current collection and transmission. Furthermore, the second fine grid 302 can also cover at least a portion of the spacer region S3. Thus, the presence of the second fine grid 302 can significantly enhance light reflection, which helps the incident light to reflect in the spacer region S3, reduces the possibility of the incident light directly penetrating the solar cell in the spacer region S3, reduces the light transmission loss in the spacer region S3 of the solar cell, increases the residence time of the incident light in the solar cell, and thereby improves the photoelectric conversion efficiency of the solar cell.

[0068] It is understood that the second fine gate 302 is spaced apart from both the semiconductor substrate 10 and the first doped layer 201, so that the second fine gate 302 is electrically insulated from the semiconductor substrate 10 and from the first doped layer 201.

[0069] like Figure 1As shown, in some exemplary embodiments, to save the cost of the grid line 30, the second fine grid 302 covers part of the spacing region S3; or in other exemplary embodiments, the second fine grid 302 covers the entire spacing region S3, thus increasing the area of ​​the spacing region S3 covered by the second fine grid 302, thereby further reducing the light transmission loss of incident light in the spacing region S3; or in some exemplary embodiments, the second fine grid 302 covers at least part of the spacing region S3 and extends to the first doped layer 201. In this way, since the second fine grid 302 can also act as a back reflector in the solar cell, the design of extending the second fine grid 302 to the first doped layer 201 increases the reflective area. This means that more light that penetrates to the back of the solar cell (first surface) will be reflected back into the cell by the second fine grid 302, increasing the chance of secondary light absorption, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0070] like Figure 1 As shown, in some optional embodiments, the orthographic projection of the second fine gate 302 on the first surface is a third orthographic projection, and the orthographic projection of the second doped layer 202 on the first surface is a fourth orthographic projection. The third orthographic projection covers the fourth orthographic projection and extends along the first direction A into the spacer region S3.

[0071] In the above embodiment, the third orthographic projection corresponding to the second fine grid 302 covers the fourth orthographic projection corresponding to the second doped layer 202. This means that the second fine grid 302 has a wider coverage area, which allows more light penetrating to the back of the solar cell to be reflected back into the cell by the second fine grid 302, further increasing the chance of secondary light absorption and thus further improving the photoelectric conversion efficiency of the solar cell. Furthermore, if the third orthographic projection corresponding to the second fine grid 302 also extends along the first direction A to the spacing region S3, it means that the second fine grid 302 covers at least part of the spacing region S3 in addition to covering the second doped layer 202. Thus, the high reflectivity of the second fine grid 302 can significantly reduce the light transmission loss of incident light in the spacing region S3, thereby significantly improving the photoelectric conversion efficiency of the solar cell.

[0072] like Figure 1 As shown, in some alternative embodiments, the grid line 30 includes a first fine grid 301 and a second fine grid 302 extending along a second direction, respectively. The first fine grid 301 is located in a first region S1 and extends from the first region S1 to the interval region S3 in a first direction A. The second fine grid 302 is located in a second region S2 and extends from the second region S2 to the interval region S3 in a first direction A. The first fine grid 301 and the second fine grid 302 are spaced apart in the interval region S3.

[0073] Thus, the first fine grid 301 and the second fine grid 302 respectively cover part of the spacing region S3, which causes the light that penetrates into the solar cell spacing region S3 to be reflected back into the cell by the first fine grid 301 and the second fine grid 302, thereby reducing the light transmission loss of the incident light in the spacing region S3.

[0074] Furthermore, the orthographic projection of the first fine gate 301 on the first surface is the first orthographic projection, the orthographic projection of the first doped layer 201 on the first surface is the second orthographic projection, the first orthographic projection covers the second orthographic projection and extends along the first direction A into the spacer region S3; the orthographic projection of the second fine gate 302 on the first surface is the third orthographic projection, the orthographic projection of the second doped layer 202 on the first surface is the fourth orthographic projection, the third orthographic projection covers the fourth orthographic projection and extends along the first direction A into the spacer region S3.

[0075] Similarly, in the above embodiments, the first orthographic projection corresponding to the first fine grid 301 covers the second orthographic projection corresponding to the first doped layer 201, which means that the coverage area of ​​the first fine grid 301 is wider; the third orthographic projection corresponding to the second fine grid 302 covers the fourth orthographic projection corresponding to the second doped layer 202, which means that the coverage area of ​​the second fine grid 302 is wider. This also means that more light penetrating the back of the solar cell is reflected back into the cell by the first fine grid 301 and the second fine grid 302, further increasing the opportunity for secondary absorption of light, thereby further improving the photoelectric conversion efficiency of the solar cell. In addition, when the first orthographic projection corresponding to the first fine grid 301 and the third orthographic projection corresponding to the second fine grid 302 also extend along the first direction A into the spacer region S3, it means that the first fine grid 301 and the second fine grid 302 also cover at least part of the spacer region S3. Thus, the high reflectivity of the first fine grid 301 and the second fine grid 302 can significantly reduce the light transmission loss of incident light in the spacer region S3, thereby significantly improving the photoelectric conversion efficiency of the solar cell.

[0076] like Figure 1 As shown, in some optional embodiments, the area of ​​the spacer region S3 is a first area, and the sum of the projected areas of the first fine grating 301 and the second fine grating 302 in the spacer region S3 is a second area. To improve the light reflectivity of the spacer region S3, the ratio of the second area to the first area is greater than 0.3 and less than 1. Thus, the area of ​​the spacer region S3 covered by the grating lines 30 is larger, thereby helping to reduce the light transmission loss of incident light in the spacer region S3. To further improve the light reflectivity of the spacer region S3, the ratio of the second area to the first area can be greater than 0.5 and less than 1.

[0077] Of course, when only the first fine grid 301 extends into the spacer region S3 (at least part of the spacer region S3 is covered by the first fine grid 301), the projected area of ​​the first fine grid 301 on the bottom surface can be the second area described above. Thus, the ratio of the area covered by the first fine grid 301 in the spacer region S3 to the first area described above is greater than 0.3 and less than 1. Alternatively, the ratio of the area covered by the first fine grid 301 in the spacer region S3 to the first area described above is greater than 0.5 and less than 1.

[0078] When only the second fine grid 302 extends into the spacer region S3 (at least part of the spacer region S3 is covered by the second fine grid 302), the projected area of ​​the second fine grid 302 on the bottom surface can be the second area described above. Thus, the ratio of the area covered by the second fine grid 302 in the spacer region S3 to the first area described above is greater than 0.3 and less than 1. Alternatively, the ratio of the area covered by the second fine grid 302 in the spacer region S3 to the second area described above is greater than 0.5 and less than 1.

[0079] In some optional embodiments, the first region S1 and the second region S2 are alternately distributed along the first direction A. This allows the first doped layer 201 and the second doped layer 202 to be alternately distributed along the first direction A, meaning that the distribution of the first doped layer 201 and the second doped layer 202 on the entire first surface of the solar cell is more uniform. This is beneficial for the transport of photogenerated carriers inside the solar cell, thereby improving the stability and reliability of the cell and optimizing the overall output of the solar cell. Furthermore, the first region S1 and the second region S2 are interdigitated along the first direction A. This further reduces the movement path of photogenerated carriers, thereby further reducing energy loss during carrier transport and further improving the overall efficiency of the solar cell.

[0080] In some alternative embodiments, multiple first fine grids 301 are spaced apart along a first direction A, and the grid line 30 also includes a first main grid. The first main grid is electrically connected to the multiple first fine grids 301. In this way, the first main grid can be electrically connected to the multiple first fine grids 301 and the current of the multiple first fine grids 301 can be collected, thereby shortening the current collection path, reducing the series resistance, and ensuring that the current can be efficiently transferred from the inside of the battery to the external circuit.

[0081] In some alternative embodiments, multiple second fine grids 302 are spaced apart along a first direction A. The grid line 30 also includes a second main grid, which is electrically connected to the multiple second fine grids 302. Similarly, this allows the second main grid to be electrically connected to the multiple second fine grids 302 and to collect the current of the multiple second fine grids 302, thereby shortening the current collection path, reducing the series resistance, and ensuring that the current can be efficiently transferred from the inside of the battery to the external circuit.

[0082] In some optional embodiments, to further shorten the current collection path and reduce series resistance, multiple first main grids and multiple second main grids are alternately distributed in a second direction. The multiple first main grids and multiple second main grids satisfy at least one of the following: at least one first main grid is located between two adjacent second main grids in the second direction; or at least one first main grid is located between two adjacent second main grids in the second direction. Where at least one first main grid is located between two adjacent second main grids or where at least one first main grid is located between two adjacent second main grids in the second direction, this arrangement also helps to form a more uniform back electric field on the back of the solar cell, thereby improving the photoelectric conversion efficiency of the cell.

[0083] It should be noted that the first main gate extending along the first direction A can be located on the first doped layer 201 or on the first fine gate 301 on the first doped layer 201, that is, the first main gate and the first fine gate 301 have the same polarity. Furthermore, the second doped layer 202 can also be spaced apart from the first doped layer 201 in the second direction through a spacing region S3, thus, the first main gate and the second fine gate 302 are spaced apart in the second direction.

[0084] In some alternative embodiments, only the first main gate extends from the first region S1 into the interval region S3 in the second direction; in other alternative embodiments, only the second main gate extends from the second region S2 into the interval region S3 in the second direction; in still other alternative embodiments, in the second direction, the first main gate extends from the first region S1 into the interval region S3, and the second main gate extends from the second region S2 into the interval region S3.

[0085] In the above embodiments, based on the first main gate extending into the spacer region S3 and the second doped layer 202 being spaced apart from the first doped layer 201 in the second direction through the spacer region S3, by setting the first main gate to extend from the first region S1 into the spacer region S3 in the second direction, the first main gate can cover at least a portion of the spacer region S3; or, based on the second main gate extending into the spacer region S3 and the first doped layer 201 being spaced apart from the second doped layer 202 in the second direction through the spacer region S3, by setting the second main gate to extend from the second region S2 into the spacer region S3 in the second direction, the second main gate can cover at least a portion of the spacer region S3. Both embodiments allow light that might have directly penetrated the solar cell from the spacer region S3 to be effectively captured, thereby further significantly reducing the light transmission loss in the spacer region S3 of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0086] like Figure 1As shown, it should be noted that the above-mentioned gate lines 30 (including the first fine gate 301, the second fine gate 302, the first main gate and the second main gate) can be formed by copper electroplating process (which has the characteristics of non-burn-through).

[0087] like Figure 1 As shown, optionally, the solar cell further includes an insulating dielectric layer 60 covering a portion of the first doped layer 201, the spacer region S3, and a portion of the second doped layer 202. In some optional embodiments, when the first fine gate 301 extends into the spacer region S3, the insulating dielectric layer 60 is located between the first fine gate 301 and the semiconductor substrate 10; in other optional embodiments, when the second fine gate 302 extends into the spacer region S3, the insulating dielectric layer 60 is located between the second fine gate 302 and the semiconductor substrate 10; in still other optional embodiments, when both the first fine gate 301 and the second fine gate 302 extend into the spacer region S3, the insulating dielectric layer 60 is located between the first fine gate 301 and the semiconductor substrate 10, and also between the second fine gate 302 and the semiconductor substrate 10.

[0088] In the above embodiments, when the insulating dielectric layer 60 is disposed between the first fine gate 301 and the semiconductor substrate 10, or when the insulating dielectric layer 60 is disposed between the second fine gate 302 and the semiconductor substrate 10, the insulating dielectric layer 60 can passivate the interface, thereby reducing carrier recombination and ultimately improving the photoelectric conversion efficiency of the solar cell.

[0089] It is understandable that, even when the doping types of the first doped layer 201 and the second doped layer 202 are opposite, electrical insulation can still be achieved between the first fine gate 301 and the second doped layer 202, and between the second fine gate 302 and the first doped layer 201, through the aforementioned insulating dielectric layer 60. Thus, the increased insulation performance of the insulating dielectric layer 60, coupled with the non-burn-through characteristic of copper metallization technology, prevents damage and leakage even if the first fine gate 301 covers the trench region or even the second doped region, or the second fine gate 302 covers the spacer region S3 or even the first doped region.

[0090] The material of the insulating dielectric layer 60 may include, but is not limited to, alumina, SiN x SiO x SiO x N y At least one of them.

[0091] like Figure 1As shown, in some optional embodiments, in order to enhance or supplement the surface passivation effect of the first doped layer 201 on the semiconductor substrate 10 and to ensure that the first fine gate 301 can effectively contact the first doped layer 201, the portion of the insulating dielectric layer 60 covering the first doped layer 201 has a first via, and at least a portion of the material of the first fine gate 301 fills the first via; in order to enhance or supplement the surface passivation effect of the second doped layer 202 on the semiconductor substrate 10 and to ensure that the second fine gate 302 can effectively contact the second doped layer 202, the portion of the insulating dielectric layer 60 covering the second doped portion has a second via, and at least a portion of the material of the second fine gate 302 fills the first via.

[0092] In some optional embodiments, the spacer region S3 occupies more than 20% of the first surface. This minimizes the proportion of the first region S1 and the second region S2 on the first surface, thereby mitigating the long-wavelength parasitic problems caused by the first doped layer 201 in the first region S1 and the second doped layer 202 in the second region S2. To further improve the parasitic problems caused by the first doped layer 201 and the second doped layer 202, the spacer region S3 can be set to occupy more than 30% of the first surface, or even more than 50%. In summary, by increasing the coverage area of ​​the spacer region S3 by the gate line 30 and increasing the coverage area of ​​the spacer region S3 itself on the (first surface), the optical performance of the battery can be further improved, resulting in better optical performance.

[0093] In some optional embodiments, in the first direction A, the width of the first region S1 is greater than 50 μm, and in some optional embodiments, the width of the second region S2 is greater than 50 μm, and the width of the interval region S3 is greater than 30 μm.

[0094] In the above embodiments, the width of the first region S1 in the first direction A is greater than 50 μm, which means that when the first fine gate 301 covers the first doped layer 201 located in the first region S1, the width of the first fine gate 301 in the first direction A is greater than 50 μm; the width of the second region S2 in the first direction A is greater than 50 μm, which means that when the second fine gate 302 covers the second doped layer 202 located in the second region S2, the width of the second fine gate 302 in the first direction A is greater than 50 μm; the width of the spacer region S3 in the first direction A is greater than 30 μm, which means that when the first fine gate 301 or the second fine gate 302 covers the spacer region S3, the width of the first fine gate 301 or the second fine gate 302 in the first direction A is greater than 30 μm.

[0095] In some alternative embodiments, the first surface is a textured surface. This can enhance the light absorption efficiency of the solar cell. Exemplarily, the textured surface includes a velvety surface and a polished surface.

[0096] In some optional embodiments, the first region S1 and the second region S2 are polished surfaces, and the spacer region S3 is textured. By setting the first region S1 and the second region S2 as polished surfaces, surface defects in the semiconductor substrate 10 are reduced. By setting the spacer region S3 as textured, when the first fine gate 301 or the second fine gate 302 covers the spacer region S3, the spacer region S3 can form an ideal light-trapping effect with the first fine gate 301 or the second fine gate 302 covering the spacer region S3, capturing more incident light and significantly reducing light transmission loss and light reflection loss in the spacer region S3, thereby significantly improving the performance and stability of the battery.

[0097] In some alternative implementations, the textured surface has an upright pyramid structure or an inverted pyramid structure. Thus, when the metal corresponding to the gate line 30 is located in the trench, the pyramid + high-reflectivity metal layer provides better light trapping effect, while the surface morphology remains controllable.

[0098] In some alternative embodiments, to further optimize the surface passivation effect of the semiconductor substrate 10, the solar cell further includes a tunneling layer 40 located between the semiconductor substrate 10 and the first doped layer 201 and between the semiconductor substrate 10 and the second doped layer 202.

[0099] It should be noted that, when the first doped layer 201 and the second doped layer 202 have the same doping type, in some alternative embodiments, the first fine gate 301 covers a portion of the spacer region S3 and is in contact with the first doped layer 201, and the second fine gate 302 covers a portion of the spacer region S3 and is in contact with the second doped layer 202. The first fine gate 301 and the second fine gate 302 can be in contact with each other within the spacer region S3. In this way, the spacer region S3 can be covered by the gate line 30, thereby further reducing the light transmission loss in the corresponding region of the trench.

[0100] In some alternative embodiments, when the doping types of the first doped layer 201 and the second doped layer 202 are opposite, the gate line 30 covers at least a portion of the spacing region S3 and is in contact with one of the first doped layer 201 and the second doped layer 202. This ensures that the gate line 30 in contact with the first doped layer 201 does not contact the second doped layer 202, or that the gate line 30 in contact with the second doped layer 202 does not contact the first doped layer 201, thereby guaranteeing the reliability of the battery.

[0101] The aforementioned solar cell can be a back-contact cell. Exemplarily, the aforementioned solar cell also includes a front passivation layer 50 located on the second surface. The front passivation layer 50 may include, but is not limited to, a stacked aluminum oxide layer 501 and a silicon nitride layer 502. The aluminum oxide layer 501 may be located between the semiconductor substrate 10 and the silicon nitride layer 502.

[0102] In some alternative embodiments, the semiconductor substrate 10 is a silicon substrate; and / or, at least one of the first doped layer 201 and the second doped layer 202 comprises polycrystalline silicon. Polycrystalline silicon has good conductivity and can be easily transformed into a P-type or N-type semiconductor through doping, forming effective charge collection and transport paths. Furthermore, the polycrystalline silicon layer can form a lower contact resistance when in contact with a metal. Additionally, when the solar cell includes the first tunneling layer, it can provide excellent surface passivation with the first tunneling layer.

[0103] According to an embodiment of this application, a photovoltaic module is provided, comprising: any of the solar cells described above. Since at least a portion of the spaced areas of any of the solar cells described above are covered by grid lines, the photovoltaic module comprising any of the solar cells described above can reduce light loss within the module, which helps to improve the overall power output of the module.

[0104] According to an embodiment of this application, a photovoltaic system is also provided, including the photovoltaic module as described above. The increase in the parallel resistance of the photovoltaic module helps to improve the electrical stability of the photovoltaic system.

[0105] Furthermore, the aforementioned photovoltaic system includes off-grid solar power generation systems. Of course, the aforementioned photovoltaic system can also be a grid-connected solar power generation system, and both off-grid and grid-connected solar power generation systems include the aforementioned photovoltaic modules.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes: A semiconductor substrate having a first surface, the first surface including a spacer region and a first region and a second region located on opposite sides of the spacer region in a first direction, the first direction being parallel to the first surface; A first doped layer and a second doped layer, wherein the first doped layer is located in the first region and the second doped layer is located in the second region; A gate line that covers at least a portion of the spacing region and is disposed in contact with at least one of the first doped layer and the second doped layer.

2. The solar cell according to claim 1, characterized in that, The solar cell further includes a trench structure, at least a portion of which is located between the first doped layer and the second doped layer in the first direction, and the gap region is the bottom surface of at least a portion of the trench structure.

3. The solar cell according to claim 1 or 2, characterized in that, The gate line includes a first fine gate located in the first region and extending along a second direction, and in the first direction the first fine gate extends from the first region to the spacing region. The first fine gate is electrically connected to the first doped layer and electrically insulated from the semiconductor substrate and the second doped layer. The second direction is parallel to the first surface and intersects the first direction.

4. The solar cell according to claim 3, characterized in that, The first fine grid covers at least a portion of the spaced area.

5. The solar cell according to claim 3, characterized in that, The first fine gate covers at least a portion of the spacer region and extends onto the second doped layer.

6. The solar cell according to claim 3, characterized in that, The orthographic projection of the first fine gate on the first surface is a first orthographic projection, and the orthographic projection of the first doped layer on the first surface is a second orthographic projection. The first orthographic projection covers the second orthographic projection and extends along the first direction into the spacing region.

7. The solar cell according to claim 1 or 2, characterized in that, The gate line includes a second fine gate located in the second region and extending along a second direction, and in the first direction extending from the second region to the spacer region, the second fine gate being electrically connected to the second doped layer and electrically insulated from the first doped layer and the semiconductor substrate.

8. The solar cell according to claim 7, characterized in that, The second fine grid covers at least a portion of the interval region.

9. The solar cell according to claim 7, characterized in that, The second fine gate covers at least a portion of the spacer region and extends onto the first doped layer.

10. The solar cell according to claim 7, characterized in that, The orthographic projection of the second fine gate on the first surface is a third orthographic projection, and the orthographic projection of the second doped layer on the first surface is a fourth orthographic projection. The third orthographic projection covers the fourth orthographic projection and extends along the first direction into the spacing region.

11. The solar cell according to claim 1 or 2, characterized in that, The grid line includes a first fine grid and a second fine grid extending along a second direction, the first fine grid being located in the first region and extending from the first region to the interval region in the first direction, the second fine grid being located in the second region and extending from the second region to the interval region in the first direction, and the first fine grid and the second fine grid being spaced apart in the interval region.

12. The solar cell according to claim 11, characterized in that, The orthographic projection of the first fine gate on the first surface is the first orthographic projection, and the orthographic projection of the first doped layer on the first surface is the second orthographic projection. The first orthographic projection covers the second orthographic projection and extends along the first direction into the spacing region. The orthographic projection of the second fine gate on the first surface is a third orthographic projection, and the orthographic projection of the second doped layer on the first surface is a fourth orthographic projection. The third orthographic projection covers the fourth orthographic projection and extends along the first direction into the spacing region.

13. The solar cell according to claim 11, characterized in that, The area of ​​the interval region is the first area, and the sum of the projected areas of the first fine grid and the second fine grid in the interval region is the second area. The ratio of the second area to the first area is greater than 0.3 and less than 1.

14. The solar cell according to claim 13, characterized in that, The ratio of the second area to the first area is greater than 0.5 and less than 1.

15. The solar cell according to claim 11, characterized in that, The first region and the second region are distributed alternately along the first direction.

16. The solar cell according to claim 15, characterized in that, The first region and the second region are interdigitated along the first direction.

17. The solar cell according to claim 15, characterized in that, Multiple first fine grids are spaced apart along the first direction, and the grid line also includes a first main grid, which is electrically connected to the multiple first fine grids.

18. The solar cell according to claim 17, characterized in that, Multiple second fine grids are spaced apart along the first direction, and the grid line also includes a second main grid, which is electrically connected to the multiple second fine grids.

19. The solar cell according to claim 18, characterized in that, Multiple first main gates and multiple second main gates are alternately distributed in the second direction, and at least one first main gate is located between two adjacent second main gates in the second direction.

20. The solar cell according to claim 19, characterized in that, In the second direction, the first main gate extends from the first region into the interval region.

21. The solar cell according to claim 18, characterized in that, Multiple first main gates and multiple second main gates are alternately distributed in the second direction, and at least one second main gate is located between two adjacent first main gates and intersects with at least one second fine gate in the second direction.

22. The solar cell according to claim 21, characterized in that, In the second direction, the second main gate extends from the second region into the interval region.

23. The solar cell according to claim 11, characterized in that, The solar cell also includes: An insulating dielectric layer covers a portion of the first doped layer, the spacer region, and a portion of the second doped layer; When the first fine gate extends into the spacer region, the insulating dielectric layer is located between the first fine gate and the semiconductor substrate, and / or, when the second fine gate extends into the spacer region, the insulating dielectric layer is located between the second fine gate and the semiconductor substrate.

24. The solar cell according to claim 23, characterized in that, The portion of the insulating dielectric layer covering the first doped portion has a first through-hole, and at least a portion of the material of the first fine gate fills the first through-hole; The portion of the insulating dielectric layer covering the second doped portion has a second through-hole, and at least a portion of the material of the second fine gate fills the first through-hole.

25. The solar cell according to claim 1 or 2, characterized in that, The interval region accounts for more than 20% of the first surface.

26. The solar cell according to claim 25, characterized in that, The spaced area accounts for more than 30% of the first surface.

27. The solar cell according to claim 26, characterized in that, The interval region accounts for more than 50% of the first surface.

28. The solar cell according to claim 1 or 2, characterized in that, In the first direction, the width of the first region is greater than 50 μm, the width of the second region is greater than 50 μm, and the width of the interval region is greater than 30 μm.

29. The solar cell according to claim 1 or 2, characterized in that, The first surface is a textured surface.

30. The solar cell according to claim 29, characterized in that, The textured surface includes a polished surface or a velvety surface.

31. The solar cell according to claim 30, characterized in that, The first region and the second region are the polished surfaces, and the interval region is the velvety surface.

32. The solar cell according to claim 31, characterized in that, The velvet surface has a regular pyramid structure or an inverted pyramid structure.

33. The solar cell according to claim 1 or 2, characterized in that, The first doped layer and the second doped layer have the same doping type.

34. The solar cell according to claim 1 or 2, characterized in that, The first doped layer and the second doped layer have opposite doping types.

35. A photovoltaic module, characterized in that, include: The solar cell as described in any one of claims 1 to 34.

36. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 35.

37. The photovoltaic system according to claim 36, characterized in that, The photovoltaic system includes an off-grid solar power generation system, and the off-grid solar power generation system includes the photovoltaic modules.

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