Solar cell, photovoltaic module and photovoltaic system

Abstract

The invention provides a solar cell, a photovoltaic module and a photovoltaic system. The solar cell comprises a trench and a semiconductor substrate, the semiconductor substrate is provided with a first surface and a second surface opposite to the first surface, and the first surface comprises a spacer region, and a first region and a second region which are located on two opposite sides of the spacer region in a first direction; the doping layer comprises a first doping layer and a second doping layer, the first doping layer comprises a first doping part and a second doping part which are arranged at an interval in the first direction, at least part of a groove is formed between the first doping part and the second doping part, the bottom surface of the groove comprises an interval region and is a suede surface, and the second doping layer is located on the second surface; the doping types of the first doping layer and the second doping layer are opposite; and the first grid line covers at least part of the bottom surface of the groove and is in contact with at least one of the first doping part and the second doping part. According to the invention, the problem of limitation of the grid line design of the solar cell in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and more specifically, to a solar cell, a photovoltaic module, and a photovoltaic system. Background Technology

[0002] In the existing technology, the use of a polyfin design on the back of solar cells has become a common practice. This means that a first electrode is formed on the second surface of the photovoltaic cell through local boron diffusion, while a structure consisting of a phosphorus-doped polycrystalline silicon passivation region and an undoped smooth region is formed on the opposite second surface.

[0003] However, this design has several significant limitations. First, the grid lines have poor ductility on smooth, polished surfaces, making precise control difficult. This directly affects the grid line width design, thus limiting the potential for improving battery efficiency. Second, the contact resistance between the metal and silicon on smooth surfaces is high, reducing photoelectric conversion efficiency. Finally, insufficient adhesion between the metal grid lines and the polished silicon surface can lead to grid line detachment during long-term operation or under extreme working conditions, thereby reducing battery reliability and lifespan.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This application provides a solar cell, a photovoltaic module, and a photovoltaic system to address the limitations of the grid line design in existing solar cells.

[0006] To achieve the above objectives, according to one aspect of this application, a solar cell is provided. The solar cell includes a trench and further includes: a semiconductor substrate having a first surface and a second surface opposite thereto, the first surface including a spacer region and a first region and a second region located on opposite sides of the spacer region in a first direction, the first direction being parallel to the first surface; a doped layer including a first doped layer and a second doped layer, the first doped layer including a first doped portion and a second doped portion spaced apart along the first direction, the first doped portion being located in the first region, the second doped portion being located in the second region, and at least a partial trench being formed between the first doped portion and the second doped portion, the bottom surface of the trench including the spacer region and having a textured bottom surface, the second doped layer being located on the second surface; the first doped layer and the second doped layer having opposite doping types; and a first grid line covering at least a portion of the bottom surface of the trench and in contact with at least one of the first doped portion and the second doped portion.

[0007] Optionally, the velvet surface can be a regular pyramid structure or an inverted pyramid structure.

[0008] Optionally, the first gate line covers at least a portion of the bottom surface of the trench and is disposed in contact with the first doped portion, and the length of the first gate line in the first direction is greater than the length of the first doped portion in the first direction; and / or the first gate line covers at least a portion of the bottom surface of the trench and is disposed in contact with the second doped portion, and the length of the first gate line in the first direction is greater than the length of the second doped portion in the first direction.

[0009] Optionally, the first doped portion and the second doped portion have the same doping type.

[0010] Optionally, the doping types of the first doped portion and the second doped portion are opposite.

[0011] Optionally, the area of ​​the bottom surface of the trench is the first area, and the total area of ​​the projection of the first grid line in the bottom surface of the trench is the second area, wherein the ratio of the second area to the first area is greater than 0.3 and less than 1.

[0012] Optionally, the ratio of the second area to the first area is greater than 0.5 and less than 1.

[0013] Optionally, the first grid line includes a first sub-grid line and a second sub-grid line disposed adjacent to each other along a first direction;

[0014] The first sub-gate line covers a portion of the bottom surface of the trench and is in contact with the first doped portion; the second sub-gate line is located on the side of the second doped portion away from the semiconductor substrate and is in contact with the second doped portion; and / or the second sub-gate line covers a portion of the bottom surface of the trench and is in contact with the second doped portion; the first sub-gate line is located on the side of the first doped portion away from the semiconductor substrate and is in contact with the first doped portion.

[0015] Optionally, the first gate line includes a first sub-gate line and a second sub-gate line. The first sub-gate line covers a portion of the bottom surface of the trench and is in contact with the first doped portion. The second sub-gate line covers a portion of the bottom surface of the trench and is in contact with the second doped portion. The first sub-gate line and the second sub-gate line are spaced apart in the trench along a first direction.

[0016] Optionally, the first gate line includes a first sub-gate line and a second sub-gate line disposed adjacent to each other along a first direction; the first sub-gate line covers the entire bottom surface of the trench and is disposed in contact with the first doped portion, and the second sub-gate line is located on the side of the second doped portion away from the semiconductor substrate and is disposed in contact with the second doped portion; or the second sub-gate line covers the entire bottom surface of the trench and is disposed in contact with the second doped portion, and the first sub-gate line is located on the side of the first doped portion away from the semiconductor substrate and is disposed in contact with the first doped portion.

[0017] Optionally, when the doping types of the first doped portion and the second doped portion are opposite, the first sub-gate line and the second sub-gate line are spaced apart, and the first sub-gate line is spaced apart from the second doped portion, and the second sub-gate line is spaced apart from the first doped portion.

[0018] Optionally, the first gate line includes a first sub-gate line and a second sub-gate line disposed adjacent to each other along a first direction. The first sub-gate line covers a portion of the bottom surface of the trench and is disposed in contact with the first doped portion. The second sub-gate line covers a portion of the bottom surface of the trench and is disposed in contact with the second doped portion. The first sub-gate line and the second sub-gate line are disposed in contact with each other along the first direction in the trench.

[0019] Optionally, the solar cell further includes a tunneling layer located between the semiconductor substrate and the first doped portion and / or between the semiconductor substrate and the second doped portion.

[0020] Optionally, the tunnel layer includes a multi-layered structure stacked together.

[0021] Optionally, the material of the tunneling layer includes SiO2 and SiN. x SiO x N y At least two of them.

[0022] Optionally, the tunneling layer is a membrane with a porous structure.

[0023] Optionally, the solar cell further includes: a passivation layer covering a portion of the first doped portion, the trench, and a portion of the second doped portion; the portion of the passivation layer located in the trench is situated between the first gate line and the semiconductor substrate in a second direction, the second direction being perpendicular to the first surface.

[0024] Optionally, when the first gate line covers at least a portion of the bottom surface and is in contact with the first doped portion, the portion of the passivation layer covering the first doped portion has a first via, and at least a portion of the material of the first gate line fills the first via; when the first gate line covers at least a portion of the bottom surface and is in contact with the second doped portion, the portion of the passivation layer covering the second doped portion has a second via, and at least a portion of the material of the first gate line fills the second via.

[0025] Optionally, the first region and the second region are distributed alternately along the first direction.

[0026] Optionally, the first region and the second region are interdigitated along the first direction.

[0027] Optionally, in the first direction, the width of the first region is greater than 50 μm, the width of the second region is greater than 50 μm, and the width of the interval region is greater than 30 μm.

[0028] Optionally, the spaced area accounts for more than 20% of the first surface.

[0029] Optionally, the spaced area occupies more than 30% of the first surface.

[0030] Optionally, the spaced area accounts for more than 50% of the first surface.

[0031] Optionally, the first gate line is a copper-containing metal and / or a copper-containing alloy.

[0032] Optionally, the doping element of the second doped layer includes boron.

[0033] Optionally, the solar cell further includes grid lines, including a first grid line and a second grid line, wherein the second grid line is at least partially disposed on the second doped layer and at least partially in contact with the second doped layer.

[0034] Optionally, the first doped portion is a phosphorus-doped polycrystalline silicon material.

[0035] According to another aspect of this application, a photovoltaic system is provided, including the photovoltaic module as described above.

[0036] Optionally, the photovoltaic system includes an off-grid solar power system, which includes photovoltaic modules.

[0037] This application provides a solar cell comprising a trench, a semiconductor substrate, a doped layer, and a first grid line. The semiconductor substrate has a first surface and a second surface opposite thereto. The first surface includes a spacer region and a first region and a second region located on opposite sides of the spacer region in a first direction parallel to the first surface. The doped layer includes a first doped layer and a second doped layer. The first doped layer includes a first doped portion and a second doped portion spaced apart along the first direction. The first doped portion is located in the first region, and the second doped portion is located in the second region. At least a partial trench is formed between the first doped portion and the second doped portion. The bottom surface of the trench includes the spacer region and has a textured surface. The second doped layer is located on the second surface. The doping types of the first doped layer and the second doped layer are opposite. The first grid line covers at least a portion of the bottom surface of the trench and is in contact with at least one of the first doped portion and the second doped portion. By forming alternating first and second regions on the first surface of the semiconductor substrate and creating a trench between them, with the bottom of the trench having a textured surface, not only is light scattering and absorption increased, and light transmission loss reduced, but the pyramidal morphology of the trench region further enhances the light trapping effect, improving the optical performance of the cell. The first grid line, locally positioned on the bottom surface of the trench, not only optimizes the charge collection path and reduces contact resistance, but also overcomes the problems of limited grid line width, high contact resistance, and poor adhesion in traditional back electrode designs due to the application of metallization technology. This improves charge transport speed and efficiency while ensuring good adhesion and durability between the metal grid line and the trench area. Furthermore, by increasing the proportion of the metal grid line covering the trench and increasing the proportion of the trench itself covering the back surface, the optical performance of the cell is further enhanced. Simultaneously, no additional processes are required during production, facilitating integration and large-scale production, bringing significant cost benefits and performance optimization to the photovoltaic industry. In summary, this application solves the limitations of existing solar cell grid line designs. Attached Figure Description

[0038] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 A cross-sectional structural schematic diagram of a solar cell according to an embodiment of this application is shown.

[0040] The above figures include the following reference numerals:

[0041] 10. Semiconductor substrate; 20. Doped layer; 210. First doped layer; 220. Second doped layer; 211. First doped portion; 212. Second doped portion; 30. Gate line; 310. First gate line; 320. Second gate line; 311. First sub-gate line; 312. Second sub-gate line; 40. Tunneling layer; 50. Passivation layer. Detailed Implementation

[0042] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0043] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0046] As described in the background section, existing photovoltaic cells employing a polyfin design on the back side suffer from three main technical bottlenecks. First, the extension of the grid lines is difficult to control on a polished, smooth surface, leading to uncontrollable linewidth design. Second, the metal / silicon contact resistance on the polished surface is too high. Finally, the adhesion between the grid lines and the surface is insufficient, making them prone to detachment and failure during long-term aging. To address the limitations of existing grid designs, embodiments of this application provide a solar cell, a photovoltaic module, and a photovoltaic system.

[0047] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0048] Figure 1 This is a cross-sectional structural diagram of a solar cell according to an embodiment of this application. Figure 1 As shown, the solar cell includes a trench and further includes: a semiconductor substrate 10 having a first surface and a second surface opposite thereto; the first surface including a spacer region S3 and a first region S1 and a second region S2 located on opposite sides of the spacer region S3 in a first direction A, the first direction A being parallel to the first surface; a doped layer 20 including a first doped layer 210 and a second doped layer 220; the first doped layer 210 including a first doped portion 211 and a second doped portion 212 spaced apart along the first direction A; the first doped portion 211 being located in the first region S1 and the second doped portion 212 being located in the second region S2; at least a partial trench is formed between the first doped portion 211 and the second doped portion 212; the bottom surface of the trench includes the spacer region S3 and has a textured surface; the second doped layer 220 is located on the second surface; the doping types of the first doped layer 210 and the second doped layer 220 are opposite; and a first grid line 310 covering at least a portion of the bottom surface of the trench and contacting at least one of the first doped portion 211 and the second doped portion 212.

[0049] In this embodiment, by setting alternating first regions S1 and second regions S2 on the first surface of the semiconductor substrate 10, and forming a trench between them, the bottom of the trench is textured. This not only increases light scattering and absorption and reduces light transmission loss, but also utilizes the pyramidal morphology of the trench region to further enhance the light trapping effect, thus improving the optical performance of the battery. The first grid line 310, partially set on the bottom surface of the trench, not only optimizes the charge collection path and reduces contact resistance, but also overcomes the problems of limited grid line width, high contact resistance, and poor adhesion in traditional back electrode designs due to the application of metallization technology. This improves charge transfer speed and efficiency while ensuring good adhesion and durability between the metal grid line and the trench region. Furthermore, by increasing the coverage area ratio of the metal grid line to the trench, and increasing the coverage area ratio of the trench itself on the back side, the optical performance of the battery is further improved. Simultaneously, no additional processes are required during production, facilitating integration and large-scale production, bringing significant cost benefits and performance optimization to the photovoltaic industry.

[0050] In this process, the first doped layer 210 and the second doped layer 220 have opposite doping types, creating an effective pn junction. This allows the photovoltaic cell to convert light energy into electrical energy. When light shines on the cell surface, the photon energy excites electrons in the silicon atoms, causing them to jump from the valence band to the conduction band, generating electron-hole pairs. Under the electric field of the pn junction, electrons are pulled towards the n-type side, and holes are pushed towards the p-type side, thereby generating a voltage difference across the cell and forming a current.

[0051] In the above embodiments, the material of the grid line 30 includes a metallic material.

[0052] In some alternative implementations, the textured surface has an upright pyramid structure or an inverted pyramid structure. Thus, when the metal corresponding to the first gate line 310 is located in the trench, the pyramid + high-reflectivity metal layer has a better light-trapping effect, while the surface morphology is controllable.

[0053] In some alternative embodiments, the first gate line 310 covers at least a portion of the bottom surface of the trench and is disposed in contact with the first doped portion 211, the length of the first gate line 310 in the first direction A being greater than the length of the first doped portion 211 in the first direction A and / or the first gate line 310 covers at least a portion of the bottom surface of the trench and is disposed in contact with the second doped portion 212, the length of the first gate line 310 in the first direction A being greater than the length of the second doped portion 212 in the first direction A.

[0054] Specifically, the first grid line 310 covers a portion of the bottom surface of the trench and extends beyond the length of the first doped portion 211 or the second doped portion 212 that contacts it. This effectively enhances the charge collection capability of the solar cell, reduces the series resistance, improves the photoelectric conversion efficiency, and enhances the adaptability of the cell under different lighting conditions. At the same time, it maintains the simplicity of the process and the controllability of the cost, providing strong technical support for the performance improvement and commercial application of solar cells.

[0055] In some alternative embodiments, the doping types of the first doped portion 211 and the second doped portion 212 can be the same or opposite. When the doping types of the first doped portion 211 and the second doped portion 212 are the same, the solar cell can be a tunnel oxide passivated contact cell (TOPCon cell), and the first doped portion 211 and the second doped portion 212 form a polyfin structure of the TOPCon cell. When the doping types of the first doped portion 211 and the second doped portion 212 are opposite, the solar cell can be a back contact cell (BC cell).

[0056] In some alternative embodiments, the area of ​​the bottom surface of the trench is a first area, and the total projected area of ​​the first grid lines 310 on the bottom surface of the trench is a second area. To improve the light reflectivity of the trench region, the ratio of the second area to the first area is greater than 0.3 and less than 1. Thus, the area of ​​the trench region covered by the first grid lines 310 is larger, thereby helping to reduce the light transmission loss of incident light in the trench region. To further improve the light reflectivity of the trench, the ratio of the second area to the first area can be greater than 0.5 and less than 1.

[0057] like Figure 1 As shown, in some optional embodiments, the first gate line 310 includes a first sub-gate line 311 and a second sub-gate line 312 disposed adjacent to each other along a first direction A; the first sub-gate line 311 covers a portion of the bottom surface of the trench and is in contact with the first doped portion 211, the second sub-gate line 312 is located on the side of the second doped portion 212 away from the semiconductor substrate 10 and is in contact with the second doped portion 212 and / or the second sub-gate line 312 covers a portion of the bottom surface of the trench and is in contact with the second doped portion 212, and the first sub-gate line 311 is located on the side of the first doped portion 211 away from the semiconductor substrate 10 and is in contact with the first doped portion 211.

[0058] In the above embodiment, the first sub-gate line 311 covers a portion of the bottom surface of the trench and is in contact with the first doped portion 211, thereby forming a good electrical connection between the first sub-gate line 311 and the first doped portion 211. The second sub-gate line 312 is located on the side of the second doped portion 212 away from the semiconductor substrate 10 and is in contact with the second doped portion 212, thereby forming a good contact between the second sub-gate line 312 and the second doped portion 212, ensuring effective current collection and transmission. The arrangement of the first sub-gate line 311 partially covering the bottom surface of the trench can reduce the obstruction of incident light by the gate line. At the same time, the textured surface treatment of the trench helps to increase light scattering, reduce light reflection and penetration, form a light trapping effect, and further improve the light absorption and photoelectric conversion efficiency of the battery. The second sub-gate line 312 covers a portion of the bottom surface of the trench and is in contact with the second doped portion 212. The first sub-gate line 311 is located on the side of the first doped portion 211 away from the semiconductor substrate 10 and is in contact with the first doped portion 211. Specifically, the same principle applies as described above.

[0059] In some alternative embodiments, the first sub-gate line 311 covers a portion of the bottom surface of the trench and is in contact with the first doped portion 211, and the second sub-gate line 312 covers a portion of the bottom surface of the trench and is in contact with the second doped portion 212. The first sub-gate line 311 and the second sub-gate line 312 are spaced apart along the first direction A in the trench. The first sub-gate line 311 and the second sub-gate line 312 only cover a portion of the bottom surface of the trench, reducing direct shading of incident light by the gate lines, lowering light-blocking losses, and improving the light absorption rate on the back of the battery. The portion of the trench not covered by the gate lines can utilize the light-scattering effect of the textured surface treatment. Especially when the trench is pyramidal, it can further enhance light scattering and absorption, forming a good light-trapping effect and improving the photoelectric conversion efficiency.

[0060] In some alternative embodiments, the first sub-gate line 311 covers the entire bottom surface of the trench and is in contact with the first doped portion 211, while the second sub-gate line 312 is located on the side of the second doped portion 212 away from the semiconductor substrate 10 and is in contact with the second doped portion 212; or the second sub-gate line 312 covers the entire bottom surface of the trench and is in contact with the second doped portion 212, while the first sub-gate line 311 is located on the side of the first doped portion 211 away from the semiconductor substrate 10 and is in contact with the first doped portion 211. In the above alternative embodiments, when the doping types of the first doped portion 211 and the second doped portion 212 are opposite, the first sub-gate line 311 and the second sub-gate line 312 are spaced apart, and the first sub-gate line 311 is spaced apart from the second doped portion 212, and the second sub-gate line 312 is spaced apart from the first doped portion 211. In this way, the charge collected by each sub-grid line is ensured to correspond to the type of its contact doped part, avoiding unnecessary charge recombination, improving charge transport efficiency, thereby enabling the solar cell to effectively collect and separate the generated charge, reducing series resistance, and improving the photoelectric conversion efficiency of the cell.

[0061] In some alternative embodiments, the first sub-gate line 311 covers a portion of the bottom surface of the trench and is in contact with the first doped portion 211, while the second sub-gate line 312 covers a portion of the bottom surface of the trench and is in contact with the second doped portion 212. The first and second sub-gate lines 311 and 312 are in contact along a first direction A within the trench. Specifically, when the first and second sub-gate lines 311 and 312 are in contact along the first direction A at the bottom of the trench, they effectively form a continuous electrical path. This indicates that charges generated at the bottom surface of the trench, whether electrons or holes, have a higher probability of being rapidly collected, thereby reducing the possibility of charge recombination and improving charge collection efficiency. Simultaneously, the continuous contact sub-gate line design provides more stable electrical contact, helping to reduce the resistance in the contact area and simplify the process flow. By increasing the proportion of the metal gate area covering the trench and increasing the proportion of the trench itself covering the back side, the optical performance of the battery can be improved.

[0062] In some optional embodiments, the solar cell further includes a tunneling layer 40, which is located between the semiconductor substrate 10 and the first doped portion 211 and / or between the semiconductor substrate 10 and the second doped portion 212. In the above optional embodiments, the tunneling layer 40 comprises a multilayer structure stacked together. Different materials have different passivation mechanisms and effects; by combining them in a stacked manner, a more comprehensive and deeper passivation effect can be achieved, reducing surface recombination and improving the open-circuit voltage and efficiency of the cell. The materials of the tunneling layer 40 include SiO2 and SiN. x SiO x N yAt least two of them. In some alternative embodiments, the tunneling layer 40 is a film layer with a porous structure, which can reduce the contact resistance between the metal electrode and the semiconductor material.

[0063] In the above optional embodiments, the tunneling layer 40 also contacts the textured surface with a pyramid structure. At the apex of the pyramid, the tunneling layer 40 is torn by the gravitational forces at the corners, resulting in high-density pores and a decrease in series resistance. The non-corner areas limit the pore density and inward expansion, leading to improved passivation performance and overall better passivation contact performance. After the pyramid surface and the tunneling layer 40 are combined, their respective advantages are retained while overcoming their respective disadvantages, resulting in a better technical effect and thus solving the problems of metal grid line extension, high metal / silicon contact resistivity, and insufficient adhesion on polished surfaces.

[0064] like Figure 1 As shown, in some optional embodiments, the solar cell further includes a passivation layer 50. The passivation layer 50 covers a portion of the first doped portion 211, the trench, and a portion of the second doped portion 212. The portion of the passivation layer 50 located in the trench is situated in a second direction B between the first gate line 310 and the semiconductor substrate 10, with the second direction B perpendicular to the first surface. In the above embodiments, the passivation layer 50 can passivate the interface, thereby reducing carrier recombination and ultimately improving the photoelectric conversion efficiency of the solar cell.

[0065] It is understandable that, even when the doping types of the first doped portion 211 and the second doped portion 212 are opposite, electrical insulation can still be achieved between the first sub-gate line 311 and the second doped portion 212, and between the second sub-gate line 312 and the first doped portion 211, through the aforementioned passivation layer 50. Thus, the increased insulation performance of the passivation layer 50, combined with the non-burn-through characteristic of copper metallization technology, prevents damage and leakage even if the first sub-gate line 311 covers the trench region or even the second doped portion 212, or the second sub-gate line 312 covers the spacer region S3 or even the first doped portion 211. The material of the passivation layer 50 can be polycrystalline silicon.

[0066] In some alternative embodiments, when the first gate line 310 covers at least a portion of the bottom surface and is in contact with the first doped portion 211, the portion of the passivation layer 50 covering the first doped portion 211 has a first through-hole, and at least a portion of the material of the first gate line 310 fills the first through-hole; when the first gate line 310 covers at least a portion of the bottom surface and is in contact with the second doped portion 212, the portion of the passivation layer 50 covering the second doped portion 212 has a second through-hole, and at least a portion of the material of the first gate line 310 fills the second through-hole.

[0067] Specifically, in order to enhance or supplement the surface passivation effect of the first doped portion 211 on the semiconductor substrate 10 and to ensure that the first gate line 310 can effectively contact the first doped portion 211, the portion of the passivation layer 50 covering the first doped portion 211 has a first via, and at least a portion of the material of the first gate line 310 fills the first via; in order to enhance or supplement the surface passivation effect of the second doped layer 220 on the semiconductor substrate 10 and to ensure that the first gate line 310 can effectively contact the second doped layer 220, the portion of the passivation layer 50 covering the second doped portion 212 has a second via, and at least a portion of the material of the first gate line 310 fills the first via.

[0068] In some optional embodiments, the first region S1 and the second region S2 are alternately distributed along the first direction A. This allows the first doped portion 211 and the second doped portion 212 to be alternately distributed along the first direction A, meaning that the distribution of the first doped portion 211 and the second doped portion 212 on the entire first surface of the solar cell is more uniform. This is beneficial for the transport of photogenerated carriers inside the solar cell, thereby helping to improve the stability and reliability of the cell and also helping to optimize the overall output of the solar cell. Furthermore, the first region S1 and the second region S2 are interdigitated along the first direction A. This further reduces the movement path of photogenerated carriers, thereby further reducing energy loss during carrier transport and further improving the overall efficiency of the solar cell.

[0069] In some alternative implementations, in the first direction A, the width of the first region S1 is greater than 50 μm, the width of the second region S2 is greater than 50 μm, and the width of the interval region S3 is greater than 30 μm.

[0070] In the above embodiments, the width of the first region S1 in the first direction A is greater than 50 μm, which means that when the first sub-gate line 311 covers the first doped portion 211 located in the first region S1, the width of the first sub-gate line 311 in the first direction A can be greater than 50 μm; the width of the second region S2 in the first direction A is greater than 50 μm, which means that when the second sub-gate line 312 covers the second doped portion 212 located in the second region S2, the width of the second sub-gate line 312 in the first direction A can be greater than 50 μm; the width of the spacer region S3 in the first direction A is greater than 30 μm, which means that when the first sub-gate line 311 or the second sub-gate line 312 covers the spacer region S3, the width of the first sub-gate line 311 or the second sub-gate line 312 in the first direction A is greater than 30 μm.

[0071] In some alternative implementations, the spacer region S3 occupies more than 20% of the first surface. This minimizes the proportions of the first region S1 and the second region S2 on the first surface, thereby mitigating the long-wavelength parasitic problems caused by the first doped portion 211 in the first region S1 and the second doped portion 212 in the second region S2. To further improve the parasitic problems caused by the first doped portion 211 and the second doped portion 212, the spacer region S3 can be set to occupy more than 30% of the first surface, or even more than 50%. In summary, by increasing the coverage area of ​​the first gate line 310 over the spacer region S3, and by increasing the coverage area of ​​the spacer region S3 itself on the (first surface), the optical performance of the battery can be further improved, resulting in better optical performance.

[0072] In some alternative implementations, the first gate line 310 is a copper-containing metal and / or a copper-containing alloy.

[0073] In the above optional embodiments, the first grid line 310 can be formed using a copper electroplating process (which has the characteristic of not burning through). Copper metallization technology solves the cost problem caused by excessively wide grid lines, as well as the damage and leakage problems caused by covering trench / irregular areas. By increasing the width of the grid line to cover the trench area, the high long-wave reflectivity of the metal solves the optical bottleneck problem in the trench area. Especially when it is a trench-shaped pyramid surface, covering it with a high long-wave reflectivity metal actually creates an ideal light-trapping effect, and no additional processes are required, facilitating production and integration.

[0074] In some alternative embodiments, the doping element of the second doped layer 220 includes boron.

[0075] Specifically, in photovoltaic cell technology, the dopant element of the second doped layer 220 is usually boron, mainly to form a p-type semiconductor region, thereby forming a pn junction with the first surface of the cell, enabling the photovoltaic cell to convert light energy into electrical energy. Boron, as a typical p-type dopant, is widely used in silicon-based photovoltaic cells because its energy level in silicon is close to the valence band top, which can effectively provide holes and increase the conductivity of the material.

[0076] In some alternative embodiments, the solar cell further includes grid lines, including a first grid line 310 and a second grid line 320, wherein the second grid line 320 is at least partially disposed on the second doped layer 220 and at least partially in contact with the second doped layer 220.

[0077] In some alternative embodiments, the first doped portion 211 is a phosphorus-doped polycrystalline silicon material.

[0078] According to an embodiment of this application, a photovoltaic module is provided, comprising: any of the solar cells described above. Since at least a portion of the trenches of any of the solar cells described above are covered by the first grid line 310, the photovoltaic module comprising any of the solar cells described above can reduce light loss within the module, which helps to improve the overall power output of the module.

[0079] According to an embodiment of this application, a photovoltaic system is also provided, including the photovoltaic module as described above. The increase in the parallel resistance of the photovoltaic module helps to improve the electrical stability of the photovoltaic system.

[0080] Furthermore, the aforementioned photovoltaic system includes off-grid solar power generation systems. Of course, the aforementioned photovoltaic system can also be a grid-connected solar power generation system, and both off-grid and grid-connected solar power generation systems include the aforementioned photovoltaic modules.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized in that, The solar cell includes trenches, and the solar cell further includes: A semiconductor substrate having a first surface and a second surface opposite thereto, the first surface including a spacer region and a first region and a second region located on opposite sides of the spacer region in a first direction, the first direction being parallel to the first surface; The doped layer includes a first doped layer and a second doped layer. The first doped layer includes a first doped portion and a second doped portion spaced apart along the first direction. The first doped portion is located in the first region, and the second doped portion is located in the second region. At least a portion of the trench is between the first doped portion and the second doped portion. The bottom surface of the trench includes the spaced region and the bottom surface is textured. The second doped layer is located on the second surface. The first doped layer and the second doped layer have opposite doping types; A first gate line covers at least a portion of the bottom surface of the trench and is disposed in contact with at least one of the first doped portion and the second doped portion.

2. The solar cell according to claim 1, characterized in that, The velvet surface has a regular pyramid structure or an inverted pyramid structure.

3. The solar cell according to claim 1, characterized in that, The first gate line covers at least a portion of the bottom surface of the trench and is disposed in contact with the first doped portion, and the length of the first gate line in the first direction is greater than the length of the first doped portion in the first direction; and / or; The first gate line covers at least a portion of the bottom surface of the trench and is disposed in contact with the second doped portion, wherein the length of the first gate line in the first direction is greater than the length of the second doped portion in the first direction.

4. The solar cell according to claim 1, characterized in that, The first doped portion and the second doped portion have the same doping type.

5. The solar cell according to claim 1, characterized in that, The first doped portion and the second doped portion have opposite doping types.

6. The solar cell according to any one of claims 1 to 5, characterized in that, The area of ​​the bottom surface of the trench is the first area, and the total area of ​​the projection of the first grid lines on the bottom surface of the trench is the second area. The ratio of the second area to the first area is greater than 0.3 and less than 1.

7. The solar cell according to claim 6, characterized in that, The ratio of the second area to the first area is greater than 0.5 and less than 1.

8. The solar cell according to claim 6, characterized in that, The first gate line includes a first sub-gate line and a second sub-gate line arranged adjacent to each other along the first direction; The first sub-gate line covers a portion of the bottom surface of the trench and is disposed in contact with the first doped portion; the second sub-gate line is located on the side of the second doped portion away from the semiconductor substrate and is disposed in contact with the second doped portion. and / or; The second sub-gate line covers a portion of the bottom surface of the trench and is disposed in contact with the second doped portion, while the first sub-gate line is located on the side of the first doped portion away from the semiconductor substrate and is disposed in contact with the first doped portion.

9. The solar cell according to claim 6, characterized in that, The first gate line includes a first sub-gate line and a second sub-gate line. The first sub-gate line covers a portion of the bottom surface of the trench and is in contact with the first doped portion. The second sub-gate line covers a portion of the bottom surface of the trench and is in contact with the second doped portion. The first sub-gate line and the second sub-gate line are spaced apart in the trench along the first direction.

10. The solar cell according to any one of claims 1 to 5, characterized in that, The first gate line includes a first sub-gate line and a second sub-gate line arranged adjacent to each other along the first direction; The first sub-gate line covers the entire bottom surface of the trench and is in contact with the first doped portion; the second sub-gate line is located on the side of the second doped portion away from the semiconductor substrate and is in contact with the second doped portion; or The second sub-gate line covers the entire bottom surface of the trench and is in contact with the second doped portion, while the first sub-gate line is located on the side of the first doped portion away from the semiconductor substrate and is in contact with the first doped portion.

11. The solar cell according to claim 10, characterized in that, When the doping types of the first doped portion and the second doped portion are opposite, the first sub-gate line and the second sub-gate line are spaced apart, and the first sub-gate line is spaced apart from the second doped portion, and the second sub-gate line is spaced apart from the first doped portion.

12. The solar cell according to any one of claims 1 to 4, characterized in that, The first gate line includes a first sub-gate line and a second sub-gate line arranged adjacent to each other along the first direction. The first sub-gate line covers a portion of the bottom surface of the trench and is in contact with the first doped portion. The second sub-gate line covers a portion of the bottom surface of the trench and is in contact with the second doped portion. The first sub-gate line and the second sub-gate line are in contact with each other in the trench along the first direction.

13. The solar cell according to any one of claims 1 to 5, characterized in that, The solar cell further includes a tunneling layer located between the semiconductor substrate and the first doped portion and / or between the semiconductor substrate and the second doped portion.

14. The solar cell according to claim 13, characterized in that, The tunneling layer comprises a multi-layered structure stacked together.

15. The solar cell according to claim 14, characterized in that, The tunneling layer is made of materials including SiO2 and SiN. x SiO x N y At least two of them.

16. The solar cell according to claim 13, characterized in that, The tunneling layer is a membrane layer with a porous structure.

17. The solar cell according to any one of claims 1 to 5, characterized in that, The solar cell also includes: A passivation layer covers a portion of the first doped portion, the trench, and a portion of the second doped portion; The portion of the passivation layer located in the trench is situated in a second direction between the first gate line and the semiconductor substrate, the second direction being perpendicular to the first surface.

18. The solar cell according to claim 17, characterized in that, When the first gate line covers at least a portion of the bottom surface and is disposed in contact with the first doped portion, the portion of the passivation layer covering the first doped portion has a first via, and at least a portion of the material of the first gate line fills the first via; When the first gate line covers at least a portion of the bottom surface and is disposed in contact with the second doped portion, the portion of the passivation layer covering the second doped portion has a second via, and at least a portion of the material of the first gate line fills the second via.

19. The solar cell according to claim 1, characterized in that, The first region and the second region are distributed alternately along the first direction.

20. The solar cell according to claim 19, characterized in that, The first region and the second region are interdigitated along the first direction.

21. The solar cell according to any one of claims 1 to 5, characterized in that, In the first direction, the width of the first region is greater than 50 μm, the width of the second region is greater than 50 μm, and the width of the interval region is greater than 30 μm.

22. The solar cell according to any one of claims 1 to 5, characterized in that, The interval region accounts for more than 20% of the first surface.

23. The solar cell according to any one of claims 1 to 5, characterized in that, The spaced area accounts for more than 30% of the first surface.

24. The solar cell according to any one of claims 1 to 5, characterized in that, The interval region accounts for more than 50% of the first surface.

25. The solar cell according to claim 1, characterized in that, The first gate line is a copper-containing metal and / or a copper-containing alloy.

26. The solar cell according to claim 1, characterized in that, The second doped layer contains boron as a doping element.

27. The solar cell according to claim 1, characterized in that, The solar cell further includes grid lines, which include a first grid line and a second grid line. The second grid line is at least partially disposed on the second doped layer and is at least partially in contact with the second doped layer.

28. The solar cell according to claim 1, characterized in that, The first doped portion is phosphorus-doped polycrystalline silicon material.

29. A photovoltaic module, characterized in that, include: The solar cell as described in any one of claims 1 to 28.

30. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 29.

31. The photovoltaic system according to claim 30, characterized in that, The photovoltaic system includes an off-grid solar power generation system, and the off-grid solar power generation system includes the photovoltaic modules.

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