TOPCon solar cell, preparation method thereof and photovoltaic module
By designing patterned opening regions and undoped pyramid structures in TOPCon solar cells, the problems of optical parasitic absorption and film stress in the n+poly-Si layer were solved, improving the photocurrent and mass production yield of the cells and achieving high-efficiency photovoltaic module performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU RUNERGY CENTURY PHOTOVOLTAIC TECH CO LTD
- Filing Date
- 2026-01-05
- Publication Date
- 2026-05-19
AI Technical Summary
In existing TOPCon solar cells, the optical parasitic absorption and film stress problems of the n+poly-Si layer lead to low photocurrent and insufficient mass production yield. In particular, the fully covered n+poly-Si layer has strong absorption of long-wave infrared light, and the large-area polycrystalline silicon thin film generates internal stress during preparation and heat treatment, which increases the risk of silicon wafer warping and film peeling.
The design employs patterned opening regions on the silicon wafer surface, an undoped pyramid structure, and a tunneling oxide layer and an n+ polysilicon layer outside the patterned opening regions to reduce the coverage area of polysilicon. Patterning is achieved through laser processing, stainless steel masking, inkjet printing, or photolithography, thereby reducing optical loss and releasing stress.
It significantly reduces infrared free carrier absorption loss, alleviates film stress risk, improves the bifaciality and mechanical reliability of solar cells, and enhances cell conversion efficiency and mass production yield.
Smart Images
Figure CN122069836A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of solar cell technology, and in particular to a TOPCon solar cell and its preparation method, and a photovoltaic module. Background Technology
[0002] Currently, based on monolayer phosphorus-doped polycrystalline silicon (n... + Poly-Si / tunneling silicon oxide (SiOx) passivated contact (TOPCon) solar cells have a market share exceeding 80%. The main processes for forming a monolayer of phosphorus-doped polycrystalline silicon are low-pressure chemical vapor deposition (LPCVD) and ion-enhanced chemical vapor deposition (PECVD). However, regardless of whether LPCVD or PECVD is used, a fully covered n-type contact is fabricated on the back of the cell. + Poly-Si layers are used to achieve passivation contacts, but they have the following drawbacks: 1) Severe optical parasitic absorption: n + The poly-Si layer contains a large number of free charge carriers, which have a strong absorption effect on incident light (especially long-wave infrared light). This severely limits the generation of photocurrent and directly leads to low bifaciality of the battery. 2) Film stress and reliability risk: Large-area polycrystalline silicon thin films will generate large internal stress during preparation and heat treatment, which increases the risk of silicon wafer warping and film peeling ("film bursting"), affecting mass production yield. Summary of the Invention
[0003] This disclosure provides a TOPCon solar cell, including a hole-selective emitter layer disposed on a first main surface of an n-type silicon wafer and an electron-selective passivation contact structure disposed on a second main surface of the silicon wafer. The passivation contact structure includes a tunneling oxide layer and an n-type silicon wafer. + A polycrystalline silicon layer; a patterned opening region is provided on the first main surface and / or the second main surface, the patterned opening region including a passivation film covering the silicon wafer surface and an anti-reflection film covering the passivation film surface; the silicon wafer surface of the patterned opening region forms an undoped pyramid structure.
[0004] According to the TOPCon solar cell described in this disclosure, in the patterned opening region, the coverage area of the pyramid structure accounts for more than 80% of the area of the patterned opening region.
[0005] According to the TOPCon solar cell of this disclosure, on the first main surface or the second main surface, the area of the patterned opening region accounts for 5%-95% of the area of the first main surface or the second main surface.
[0006] According to the TOPCon solar cell described in this disclosure, the linewidth of the patterned opening region is 50-700 μm.
[0007] According to the TOPCon solar cell described in this disclosure, the passivated contact structure is located outside the patterned opening region, and the equivalent thickness of the tunneling oxide layer is 0.8-2.5 nm. + The thickness of the polycrystalline silicon layer is 60-300nm, and the sheet resistance is 30-500Ω / □.
[0008] According to the TOPCon solar cell described in this disclosure, the emitter layer includes a p-type electrode located outside the patterned opening region. + The doped region, the p + The doping concentration of the doped region is 1×10 17 cm - ³ to 5×10 21 cm - ³, with a chip resistance of 60-1000 Ω / □ and a junction depth of 100-2000 nm.
[0009] This disclosure also provides a photovoltaic module comprising multiple TOPCon solar cells according to this disclosure, encapsulated in a series-parallel manner within a double-glass structure.
[0010] This disclosure also provides a method for fabricating a TOPCon solar cell, comprising: forming a hole-selective emitter layer on a first main surface of an n-type silicon wafer; and forming an electron-selective passivation contact structure on a second main surface of the silicon wafer, the passivation contact structure comprising a tunneling oxide layer and an n-type silicon wafer. + A polycrystalline silicon layer; patterning the first main surface side and / or the second main surface side to form a patterned opening region that exposes the silicon wafer, and forming an undoped pyramid structure on the silicon wafer surface in the patterned opening region; forming a passivation film and an antireflection film.
[0011] According to the method for fabricating TOPCon solar cells as described in this disclosure, in the patterned opening region, the coverage area of the pyramid structure accounts for more than 80% of the area of the patterned opening region.
[0012] According to the TOPCon solar cell fabrication method described in this disclosure, on the first main surface or the second main surface, the area of the patterned opening region accounts for 5%-95% of the area of the first main surface or the second main surface.
[0013] According to the method for fabricating TOPCon solar cells described in this disclosure, the linewidth of the patterned opening region is 50-700 μm.
[0014] According to the TOPCon solar cell fabrication method described in this disclosure, the first main surface side and / or the second main surface side are patterned by one or a combination of laser processing, stainless steel mask, inkjet printing patterning, or photolithography.
[0015] According to the method for fabricating a TOPCon solar cell as described in this disclosure, metallization is performed on the first main surface side and the second main surface side, with the metal located in a region outside the patterned opening region.
[0016] The TOPCon solar cells described in this disclosure can reduce infrared free carrier absorption loss, alleviate film stress and the risk of film bursting, and have strong process flexibility and adjustability. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of the TOPCon solar cell described in this disclosure.
[0018] Figure 2 This is a schematic diagram of the patterned structure on the silicon wafer surface of the TOPCon solar cell described in this disclosure.
[0019] Figure 3 This is a schematic flowchart of the method for fabricating the TOPCon solar cell described in this disclosure. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of this disclosure will be described in detail below with reference to the accompanying drawings.
[0021] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.
[0022] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.
[0023] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.
[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.
[0025] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.
[0026] This disclosure provides a TOPCon solar cell, with reference to... Figure 1 It includes a hole-selective emitter layer disposed on a first main surface of an n-type silicon wafer and an electron-selective passivation contact structure disposed on a second main surface of the silicon wafer, wherein the passivation contact structure includes a tunneling oxide layer and an n-type silicon wafer. + Polycrystalline silicon layer; such as Figure 2 As shown, a patterned opening region is provided on the first main surface and / or the second main surface. The patterned opening region includes a passivation film covering the silicon wafer surface and an anti-reflection film covering the passivation film surface. An undoped pyramid structure is formed on the silicon wafer surface of the patterned opening region.
[0027] According to the TOPCon solar cell described in this disclosure, in the patterned opening region, the coverage area of the pyramid structure accounts for more than 80% of the area of the patterned opening region.
[0028] According to the TOPCon solar cell of this disclosure, on the first main surface or the second main surface, the area of the patterned opening region accounts for 5%-95% of the area of the first main surface or the second main surface.
[0029] According to the TOPCon solar cell described in this disclosure, the linewidth of the patterned opening region is 50-700 μm.
[0030] According to the TOPCon solar cell described in this disclosure, the passivated contact structure is located outside the patterned opening region, and the equivalent thickness of the tunneling oxide layer is 0.8-2.5 nm. + The thickness of the polycrystalline silicon layer is 60-300nm, and the sheet resistance is 30-500Ω / □.
[0031] According to the TOPCon solar cell described in this disclosure, the emitter layer includes a p-type electrode located outside the patterned opening region. + The doped region, the p + The doping concentration of the doped region is 1×10 17 cm - ³ to 5×10 21 cm - ³, with a chip resistance of 60-1000 Ω / □ and a junction depth of 100-2000 nm.
[0032] This disclosure also provides a photovoltaic module comprising multiple TOPCon solar cells according to this disclosure, encapsulated in a series-parallel manner within a double-glass structure.
[0033] In this disclosure, the bifaciality of the photovoltaic module can reach over 85%.
[0034] The TOPCon solar cell provided in this disclosure will be further described below with reference to a specific embodiment.
[0035] This disclosure provides a TOPCon solar cell, including a hole-selective emitter layer located on a first main surface of an n-type silicon wafer and an electron-selective passivation contact structure located on a second main surface of the silicon wafer. The passivation contact structure includes a tunneling oxide layer and an n-type silicon wafer. + Polycrystalline silicon layer; (1) The first main surface and the second main surface have patterned openings, the openings being grooves that penetrate each layer of the silicon wafer surface and expose the silicon wafer; the exposed silicon wafer surface in the groove has a pyramid structure, and the coverage area of the pyramid structure accounts for more than 80% of the area of the groove. (2) The surface area of the openings within the first and second main surfaces accounts for 5%-95% of the total surface area; and (3) The silicon wafers exposed at the bottom and sidewalls of the groove have not undergone additional doping treatment.
[0036] In the TOPCon solar cell described in this disclosure, the n-type silicon wafer can be (M)CZ silicon with a resistivity of 0.5-30.0 Ω·cm and a thickness of 50-300 μm.
[0037] In the TOPCon solar cell described in this disclosure, the linewidth of the openings in the first and second main surfaces is 50-700 μm.
[0038] In the TOPCon solar cell described in this disclosure, the equivalent thickness of the tunneling oxide layer is 0.8-2.5 nm, and the tunneling oxide layer is SiO formed by thermal oxidation or plasma / ozone-assisted oxidation. x .
[0039] According to the TOPCon solar cell described in this disclosure, wherein the n + The thickness of the polycrystalline silicon layer is 60-300nm, and the sheet resistance is 30-500Ω / □.
[0040] The n + The polycrystalline silicon layer is prepared by LPCVD to form intrinsic a-Si followed by doping and activation, LPCVD in-situ doping, or PECVD to form a-Si:H followed by solid-phase crystallization.
[0041] According to the TOPCon solar cell described in this disclosure, wherein the n + The polycrystalline silicon layer is located in a non-patterned opening region in the metal contact area facing the solar cell, thereby reducing the series resistance.
[0042] According to the TOPCon solar cell described in this disclosure, p + The doped regions are formed by BBr3 tubular diffusion or ion implantation, with a doping concentration of 1×10¹. 9 cm - ³ to 5×10 21 cm - ³, with a chip resistance of 60-1000 Ω / □ and a junction depth of 100-2000 nm.
[0043] This disclosure also provides a method for preparing a TOPCon solar cell, referring to... Figure 3 ,include: S1. A hole-selective emitter layer is formed on the first primary surface of an n-type silicon wafer; S2. An electron-selective passivation contact structure is formed on the second main surface of the silicon wafer. The passivation contact structure includes a tunneling oxide layer and an n + Polycrystalline silicon layer; S3. Pattern the first main surface side and / or the second main surface side to form a patterned opening region that exposes the silicon wafer, and form an undoped pyramid structure on the silicon wafer surface in the patterned opening region; form a passivation film and an antireflection film.
[0044] According to the TOPCon solar cell described in this disclosure, in the patterned opening region, the coverage area of the pyramid structure accounts for more than 80% of the area of the patterned opening region.
[0045] According to the TOPCon solar cell of this disclosure, on the first main surface or the second main surface, the area of the patterned opening region accounts for 5%-95% of the area of the first main surface or the second main surface.
[0046] According to the TOPCon solar cell described in this disclosure, the linewidth of the patterned opening region is 50-700 μm.
[0047] According to the TOPCon solar cell described in this disclosure, the first main surface side and / or the second main surface side are patterned by one or a combination of laser processing, stainless steel masking, inkjet printing patterning, or photolithography.
[0048] After etching the desired pattern openings on both the front and back sides, a pyramid structure can be formed at the openings using wet chemical texturing. In the exposed silicon wafer area, a pyramid light-trapping structure is formed through wet chemical processing, and this area is not additionally doped, thus preserving the intrinsic electrical properties of the substrate.
[0049] According to the TOPCon solar cell of this disclosure, metallization is performed on the first main surface side and the second main surface side, with the metal located in a region outside the patterned opening region.
[0050] The following specific embodiment further illustrates the fabrication method of the TOPCon solar cell provided in this disclosure.
[0051] The method for fabricating TOPCon solar cells disclosed herein includes: A hole-selective emitter layer is formed on the first primary surface of the pretreated n-type silicon wafer; A tunneling oxide layer is formed on the second primary surface of the silicon wafer; n are formed on the tunneling oxide layer + A polycrystalline silicon layer is then formed and doped. The first and second main surfaces of the silicon wafer are patterned to form openings that expose the silicon wafer, and a pyramid light-trapping structure is formed on the exposed silicon wafer surface; Deposit passivation / antireflection films on the first and / or second main surfaces of the silicon wafer; Metallization is performed on the first and second main surfaces of the silicon wafer to form gate lines and busbars.
[0052] In this disclosure, the tunnel oxide layer can be formed using dry thermal oxidation, ozone hydrothermal oxidation, or plasma oxidation. In this disclosure, intrinsic a-Si can be formed using LPCVD followed by POCl3 / ion implantation doping, or in-situ doping using LPCVD, or a-Si:H can be formed using PECVD followed by solid-state crystallization. In this disclosure, the patterning method is one or a combination of laser processing, stainless steel masking, inkjet printing patterning, or photolithography. After etching the desired pattern openings on both the front and back sides, a pyramid structure can be formed at the openings using wet chemical texturing. A pyramid light-trapping structure is formed in the exposed silicon wafer area through wet chemical processing.
[0053] According to the method for fabricating a TOPCon solar cell described in this disclosure, the metallization is performed only in the non-opening regions of the first and second main surfaces of the silicon wafer, wherein the metal on the first main surface is in electrical contact with the hole-selective emitter layer, and the metal on the second main surface is in electrical contact with the n-hole selective emitter layer. + The polysilicon layer has electrical contacts, and the metal does not directly cover the area with the pyramid light-trapping structure at the opening. In other words, the metal gate lines are only printed in the non-opening areas, and are connected to the p-type on the front side. + n on the emitter or back side + The polysilicon layer forms an ohmic contact, thus completely avoiding the optical region of the opening. Subsequent passivation film deposition and metallization processes must ensure that the electrode is precisely aligned with the planned non-opening contact area.
[0054] The passivation / antireflection film can be a conventionally used film layer, such as a single layer or a combination of SiOx, SiNx, SiNxOy, AlOx, etc. For example, the first and / or second main surface and the groove can be made of Al2O3 / SiN x The layers are stacked and deactivated at around 700°C to enhance the passivation effect.
[0055] The metal on the first main surface can be Ag-containing gate lines, and the metal on the second main surface can be Ag-containing or Ag / Al composite gate lines. The metal gate line width is 5-40 μm, and the number of gate lines is 50-500. The metallization of the first and / or second main surfaces can be achieved using copper plate / copper foil hard contact or electroplated copper busbars, wherein the busbars are copper alloy strips, with 5-18 main gates on both the front and back sides, and can be welded to the back copper plate or electroplated copper structure. The metallization of the second main surface is achieved by screen printing Ag-containing or Ag / Al metal gate lines, electroplating copper, or copper plate hard contact connection.
[0056] The TOPCon solar cell described in this disclosure has the following significant advantages in terms of structural design and performance optimization: 1) Reduce infrared free carrier absorption loss By designing adjustment trenches that penetrate between the poly layer and the dielectric layer in the poly layer, the coverage area of polycrystalline silicon is effectively reduced, thereby significantly reducing free carrier absorption (FCA), improving long-wavelength light response and short-circuit current density (Jsc) of the device, and effectively improving the bifaciality of the solar cell. The TOPCon solar cell described in this disclosure has a conversion efficiency ≥25.0%, open-circuit voltage ≥750 mV, fill factor ≥83.0% under standard test conditions, a bifaciality ≥90% tested at AM1.5G, 25℃, and 1000 W / m², and a back-side response EQE peak value ≥80%.
[0057] 2) Mitigating membrane stress and reducing the risk of membrane rupture By locally depositing poly-Si or adjusting the trench cutting structure, the stress generated during the deposition and annealing process of the polycrystalline silicon layer can be released, significantly reducing the risk of film bursting or warping, and improving the mechanical reliability and mass production yield of the battery.
[0058] 3) High degree of process flexibility and adjustability The position and shape of the groove can be adjusted as needed to adapt to different battery designs and process windows, and it has good scalability and process integration compatibility.
[0059] To enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of this disclosure, the technical solutions provided by the embodiments of this disclosure are described in detail below through specific examples. Those skilled in the art should understand that the following examples are for illustrative purposes only and do not constitute a limitation of the present invention.
[0060] Example 1 The process steps include: texture → p + Emitter formation → BSG removal and polishing on the back side → LPCVD preparation of dielectric layer / i-poly-Si → poly doping and crystallization → laser patterning → wet texturing → ALD passivation → metal gate line printing and sintering → component packaging.
[0061] (1) Silicon wafer pretreatment and texturing n-type CZ monocrystalline silicon wafers (1.0-2.0 Ω·cm, 150±20 μm) were selected. After RCA cleaning, the wafers were texturized in 2 wt% KOH + IPA at 80 ℃ for 10-20 min to obtain a textured surface with a pyramid base width of 2-8 μm and a height of 1.5-5 μm.
[0062] (2) p + Emitter Formation BBr3 diffusion was performed at 930 ℃ for 20 min to achieve a doping concentration of 3×10⁻⁶. 20 cm- ³, junction depth 0.3-0.5 μm, sheet resistance 85-120 Ω / □ emitter layer. 120-180 nm BSG formed on both the front and back sides.
[0063] (3) BSG removal and polishing on the back side Remove the backside BSG by spraying with 2 wt% HF on one side (40-80 s), then polish with 2 wt% NaOH (75 ℃) for 1-3 min to remove the 5-10 μm diffusion layer on the backside.
[0064] (4) LPCVD deposition medium layer and intrinsic poly layer A 1.2-1.5 nm tunneling oxide layer (ozone-assisted) is formed on the back side, followed by the deposition of 150-200 nm intrinsic poly-Si by LPCVD at 580 °C and 40 Pa.
[0065] (5) Poly doping and crystallization POCl3 diffusion at 850-880 ℃ for 25–35 min, with a poly doping concentration of 1×10⁻⁶. 20 -5×10 20 cm - ³, sheet resistance 80-150 Ω / □. Subsequent annealing at 820 ℃ for 20 min improves crystallization quality.
[0066] (6) Double-sided laser patterning Through-trench etching was performed using a 355 nm laser: - Line width 80-200 μm - Cycle length 0.6-1.2 mm - Power 2-6 W - Speed 300-800 mm / s The trench penetrates the passivation layer to reach the Si substrate, exposing the undoped silicon.
[0067] (7) Wet process for flocking and calendering The bottom of the trench is texturized by 2 wt% KOH + IPA (80 ℃, 30-90 s) to form a 1-3 μm pyramid with a coverage of ≥85%.
[0068] (8) ALD passivation and PECVD antireflection film - ALD Al2O3: 8-12 nm (200 ℃) - PECVD SiNx: 70-85 nm (n=2.05–2.15) Annealing at 400 ℃ for 20 min improves the passivation effect.
[0069] (9) Metallization Front side: Ag finger grid 22-30 μm, thickness 12-18 μm; Back side: Ag or Ag / Al finger grid 26-35 μm; The peak sintering temperature is 750-770 ℃.
[0070] (10) Component encapsulation Double-glass structure lamination 150 ℃ × 12-15 min.
[0071] Example 2 This embodiment follows the process of Embodiment 1, with the difference being the adjustment of the opening line width and opening ratio.
[0072] - Line width 150-300 μm - Opening ratio 30-40% Example 3 This embodiment follows the process of Embodiment 1, with the difference being the adjustment of the opening line width and opening ratio.
[0073] - Line width 60-100 μm - Opening ratio 10-15% Comparative Example 1 Same as Example 1, but without laser patterning and wet texturing; the back is fully covered with poly-Si and has no open structure.
[0074] The performance of the battery components in each embodiment and comparative example was tested, and the results are shown in the table below: The data above shows that the through-groove + light-trapping structure of this disclosure significantly improves the bifaciality and infrared response; it can achieve a good balance between bifaciality and device electrical performance.
[0075] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.
Claims
1. A TOPCon solar cell, comprising a hole-selective emitter layer disposed on a first main surface of an n-type silicon wafer and an electron-selective passivation contact structure disposed on a second main surface of the silicon wafer, the passivation contact structure comprising a tunneling oxide layer and an n-type silicon wafer. + Polycrystalline silicon layer; characterized in that: A patterned opening region is provided on the first main surface and / or the second main surface. The patterned opening region includes a passivation film covering the silicon wafer surface and an anti-reflection film covering the passivation film surface. An undoped pyramid structure is formed on the silicon wafer surface of the patterned opening region.
2. The TOPCon solar cell according to claim 1, characterized in that, In the graphical opening area, the pyramid structure covers more than 80% of the area of the graphical opening area.
3. The TOPCon solar cell according to claim 2, characterized in that, On the first main surface or the second main surface, the area of the patterned opening region accounts for 5%-95% of the area of the first main surface or the second main surface.
4. The TOPCon solar cell according to claim 3, characterized in that, The linewidth of the patterned opening region is 50-700 μm.
5. The TOPCon solar cell according to any one of claims 1 to 4, characterized in that, The passivated contact structure is located outside the patterned opening region, and the equivalent thickness of the tunneling oxide layer is 0.8-2.5 nm. + The thickness of the polycrystalline silicon layer is 60-300 nm, and the sheet resistance is 30-500 Ω / □.
6. The TOPCon solar cell according to any one of claims 1 to 4, characterized in that, The emitter layer includes p located outside the patterned opening region. + The doped region, the p + The doping concentration of the doped region is 1×10 17 cm - ³ to 5×10 21 cm - ³, with a chip resistance of 60-1000 Ω / □ and a junction depth of 100-2000 nm.
7. A photovoltaic module, characterized in that, The TOPCon solar cell according to any one of claims 1 to 6 comprises multiple cells encapsulated in a series-parallel manner within a double-glass structure.
8. A method for preparing a TOPCon solar cell, characterized in that, include: A hole-selective emitter layer is formed on the first primary surface of an n-type silicon wafer; An electron-selective passivation contact structure is formed on the second main surface of the silicon wafer. The passivation contact structure includes a tunneling oxide layer and an n... + Polycrystalline silicon layer; The first main surface side and / or the second main surface side are patterned to form a patterned opening region that exposes the silicon wafer, and an undoped pyramid structure is formed on the silicon wafer surface in the patterned opening region. A passivation film and an antireflection film are formed.
9. The method for preparing a TOPCon solar cell according to claim 8, characterized in that, In the graphical opening area, the pyramid structure covers more than 80% of the area of the graphical opening area.
10. The method for preparing a TOPCon solar cell according to claim 8, characterized in that, On the first main surface or the second main surface, the area of the patterned opening region accounts for 5%-95% of the area of the first main surface or the second main surface.
11. The method for preparing a TOPCon solar cell according to claim 10, characterized in that, The linewidth of the patterned opening region is 50-700 μm.
12. The method for preparing a TOPCon solar cell according to any one of claims 8 to 11, characterized in that, The first main surface side and / or the second main surface side are patterned using one or a combination of laser processing, stainless steel masking, inkjet printing patterning, or photolithography.
13. The method for preparing a TOPCon solar cell according to any one of claims 8 to 11, characterized in that, Metallization is performed on the first main surface side and the second main surface side, with the metal located in the area outside the patterned opening region.