Solar slice cell surface passivation structure, preparation method thereof, solar slice cell and photovoltaic module

Abstract

The invention provides a solar slice cell surface passivation structure, a preparation method thereof, a solar slice cell and a photovoltaic module, the surface passivation structure comprises a silicon substrate, one side surface or two opposite side surfaces of the silicon substrate are laser cutting surfaces, and the front / back surface of the silicon substrate comprises a base region located in the middle and small textured regions located at four side edges. A boron emitting electrode is arranged on the base region, the boron emitting electrode and the small suede region are covered with a front passivation anti-reflection layer, the surfaces of the boron emitting electrode and the small suede region are of pyramid suede structures, and the pyramid size of the base region is larger than that of the small suede region. According to the invention, pn junctions at the cutting edge and other edge positions of the slice cell are removed, and a small-size pyramid suede structure is formed, so that the negative influence of edge carrier recombination on the efficiency can be reduced, the efficiency difference of each point position of the slice cell is reduced, and the overall efficiency of the slice cell and the power of a corresponding assembly are improved.

Description

Technical Field

[0001] This invention relates to the field of crystalline silicon solar cell fabrication technology, and more specifically, to a surface passivation structure for a solar cell slice, its fabrication method, the solar cell slice, and a photovoltaic module. Background Technology

[0002] In recent years, breakthroughs in photovoltaic slicing technology have brought about a new revolution in the photovoltaic industry. Slicing technology reduces series resistance losses and increases module output power by cutting standard-sized solar cells into identical half-cells or multiple cells along a direction perpendicular to the main grid lines of the cells, and then welding them in series.

[0003] However, for sliced ​​solar cells, the edge surfaces of laser-cut cells exhibit significant carrier recombination, which worsens as the perimeter-to-area ratio of small-sized cells increases. For TOPCon (Top-Tunneling Silicon Oxide Passivated Contact) sliced ​​solar cells, the efficiency impact of edge recombination is particularly pronounced. To address the efficiency loss in TOPCon sliced ​​solar cells caused by slicing, edge passivation technology is widely used in the industry, which involves depositing a certain thickness (approximately 50 nm) of aluminum oxide (Al₂O₃) at the slice edge. x Edge passivation is performed. However, the edge passivation equipment is not compatible with existing TOPCon production lines. The equipment requires a large footprint, has high investment costs, and requires long processing times and large amounts of special gases, resulting in high production costs and low cost-effectiveness for industrial applications. Additionally, AlO₂... x The material is highly absorbent and deposits AlO₂. x If the remaining half of the cell is left unused for too long, passivation failure may occur; simultaneously, AlO₂ deposits at the edges may also fail. x During passivation film application, the wafers need to be pressed firmly together. x The deposition of these deposits can cause the wafers to stick together, leading to a significant increase in the breakage rate, typically reaching 0.3% to 0.5%. Furthermore, this edge passivation technology has an upper limit of 1% on the increase in module power.

[0004] To address the shortcomings of edge passivation technology, patent CN116230810A provides a TOPCon solar cell slicing technology that removes the pn junction at the cutting axis and edges, reducing carrier recombination at the cell slice edges and improving the photoelectric conversion efficiency of the cell slice. However, this patented technology has the following problems: using a single laser etching, screen printing, photolithography, or chemical etching method to remove the pn junction cannot guarantee the pn junction removal effect, and the morphology of the etched area cannot be controlled; the laser cutting of the etched area requires high power, and there are a large number of dislocation defects at the cut edge, which adversely affects the cell efficiency; furthermore, because the degree of damage at the cut edge of the sliced ​​cell is different from that at other edges, the carrier recombination situation is different, resulting in a large efficiency difference between the edge points and the center point of the sliced ​​cell prepared using the above-mentioned patented technology, with the maximum difference exceeding 0.3%, which adversely affects the overall efficiency of the photovoltaic module. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a sliced ​​battery technology suitable for industrial applications, which suppresses the combined effects of defects from laser-cut edges and other non-laser-cut edges, thereby improving the efficiency of the entire complete battery cell; at the same time, it improves the efficiency of sliced ​​batteries, reduces the efficiency difference between different points in the sliced ​​battery, and thus increases the power of the corresponding components.

[0006] To achieve the above objectives, the first aspect of the present invention provides a surface passivation structure for a solar cell, comprising a silicon substrate, one side or opposite two sides of the silicon substrate being a laser-cut surface, the front / back surface of the silicon substrate comprising a base region located in the center and a first small textured surface region, a second small textured surface region, a third small textured surface region, and a fourth small textured surface region located at the four sides, the first small textured surface region being disposed on the side corresponding to the laser-cut surface, or the first small textured surface region and the second small textured surface region being disposed on the sides corresponding to the laser-cut surface, respectively, a boron emitter being disposed on the base region, the boron emitter, the first small textured surface region, the second small textured surface region, the third small textured surface region, and the fourth small textured surface region being covered with a front passivation antireflection layer, the surfaces of the boron emitter, the first small textured surface region, the second small textured surface region, the third small textured surface region, and the fourth small textured surface region being a pyramid textured structure, and the pyramid size of the base region being larger than the pyramid size of the first small textured surface region, the second small textured surface region, the third small textured surface region, and the fourth small textured surface region.

[0007] This invention removes pn junctions from the cutting edge and other edge locations of the sliced ​​battery and forms a small-sized pyramidal textured structure, which can reduce the negative impact of edge carrier recombination on efficiency, reduce the efficiency difference between different points of the sliced ​​battery, and improve the overall efficiency of the sliced ​​battery.

[0008] In a preferred or optional embodiment, the pyramid height of the first small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm; and / or, the pyramid height of the second small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm; and / or, the pyramid height of the third small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm; and / or, the pyramid height of the third small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm.

[0009] This invention limits the pyramid size of each edge small textured area. This small pyramid structure can induce dislocations on the laser-cut surface and reduce dislocation defects. Compared with planar or large textured structures, this small textured structure is beneficial to reduce the power required for laser cutting, thereby reducing cutting damage and reducing composites. Furthermore, the small textured structure can reduce optical loss and achieve good surface passivation.

[0010] In a preferred or optional embodiment, the width W1 of the first small pile area is between 10 and 1000 μm; the width W2 of the second small pile area is between 4 and 1000 μm; the width W3 of the third small pile area is between 4 and 800 μm; and the width W4 of the fourth small pile area is between 4 and 800 μm.

[0011] In a preferred or optional embodiment, W1, W2, W3 and W4 satisfy the following relationship: W1≥W2≥W3=W4.

[0012] This invention limits the width of each edge small textured area to ensure edge isolation and eliminate composite loss; by increasing the width of the first small textured area (or the first and second small textured areas) of the laser-cut edge with greater damage, the efficiency difference at each edge point of the sliced ​​battery can be eliminated.

[0013] In a preferred or optional embodiment, the highest pyramid apex among the first, second, third, and fourth small pile areas is lower than the lowest pyramid apex in the base area.

[0014] In a preferred or optional embodiment, the height difference between the tallest pyramid apex in the first small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm; the height difference between the tallest pyramid apex in the second small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm; the height difference between the tallest pyramid apex in the third small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm; and the height difference between the tallest pyramid apex in the fourth small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm.

[0015] Each edge textured area has a certain height difference with the base area, ensuring the surface structure to remove laser damage. This makes the passivation effect of the edge area consistent with that of the base area, without causing additional recombination loss, and makes the efficiency of the sliced ​​cell edge point and center point basically the same.

[0016] A second aspect of the present invention provides a method for preparing the above-mentioned passivation structure on the surface of a solar cell slice, comprising the following steps: Step S1: Prepare the silicon substrate, and texturize the front and / or back surfaces of the silicon substrate; Step S2: Boron diffusion occurs on the front / back surfaces of the silicon substrate to form a boron emitter; Step S3: Perform laser drilling on the surface of the silicon substrate with boron emitters to form a laser processing area with a certain width at the four edges and the corresponding positions of the reserved cutting lines; Step S4: Perform chemical etching and texturing on the laser-processed area to remove the emitter, the textured surface of the silicon substrate, and the laser-damaged layer at the corresponding positions, forming a new small-sized pyramid textured surface structure. Step S5: Passivate the surface of the silicon substrate with the boron emitter to prepare a passivation antireflection layer; Step S6: Align with the reserved cutting line and perform laser cutting.

[0017] The fabrication method of this invention employs a laser-chemical etching process to form a small textured surface region with pn junction isolation at the edge of the sliced ​​cell. This effectively suppresses the effects of laser-cut edges and other edge defects. This technology can improve the efficiency of the entire complete cell, significantly enhance the efficiency of the sliced ​​cell, and reduce the efficiency difference between different points on the slice. Furthermore, this fabrication process is compatible with conventional sliced ​​cell production line processes, requiring only the addition of laser drilling equipment and chemical etching equipment. The equipment is low-cost, requires minimal space, has low production and operating costs, is highly efficient, and is easy to modify production lines and promote industrially.

[0018] In a preferred or optional embodiment, the specific process of chemical etching and texturing in step S4 includes: using a first etchant to etch and remove the emitter; continuing to etch and remove the textured surface structure on the front side of the silicon substrate, and etching to the designed depth to remove the laser damage layer and form a planar structure; using a second etchant to form a small-sized pyramid textured surface structure on the surface of the etched area.

[0019] This invention processes the edge region of a sliced ​​battery through a step-by-step etching process. First, the emitter and the damaged layer of the silicon substrate are etched away to ensure the passivation effect of the edge region. Then, a small-sized textured structure is formed by etching, which reduces the power required for laser cutting, induces dislocations at the cutting edge, and eliminates the efficiency difference at various points of the sliced ​​battery.

[0020] In a preferred or optional embodiment, in step S4, the damaged structures on the four sides are removed during the chemical etching and texturing process.

[0021] In the sliced ​​battery structure, there are various edge defects even at the non-laser-cut edges. These defects are unavoidable damages during the silicon wafer or battery manufacturing process. This invention removes the edge damage structure and reduces the composite material by performing laser treatment and chemical etching on these damaged edges.

[0022] In a preferred or optional embodiment, in step S3, the number of pre-reserved cutting lines is one or more. This technology is suitable for manufacturing two-piece, three-piece, and more segmented batteries.

[0023] A third aspect of this invention provides a solar cell slice, including the aforementioned surface passivation structure, wherein the solar cell slice is selected from TOPCon cells, back-junction cells, and full-back-contact cells. The technology of this invention is applicable to cell slices with various structures, with the small textured edge region located on the pn junction side. This technology can improve the efficiency of the entire cell, significantly improve the efficiency of the cell slice, reduce the efficiency difference between different points on the slice, and increase the overall power of the photovoltaic module.

[0024] A fourth aspect of this invention provides a photovoltaic module including the aforementioned solar cell slices. The edges of the solar cell slices of this invention have small textured areas isolated by pn junctions, improving the efficiency of the slices, reducing efficiency differences between different points, and increasing the overall power of the photovoltaic module after multiple slices are welded and connected in series. This results in an upper limit power increase of approximately 1.2% to 1.4% for two-section modules.

[0025] In summary, the present invention has the following advantages over the prior art: (1) This invention provides a new sliced ​​battery structure, which removes the pn junction at the laser-cut edge and non-laser-cut edge and forms a small-sized pyramidal textured structure, which can reduce the negative impact of edge carrier recombination on efficiency, thereby improving the efficiency of the whole cell when it is not sliced; it also improves the photoelectric conversion efficiency of the sliced ​​battery.

[0026] (2) The present invention forms a small velvety structure at the laser cutting edge, which can induce dislocation generation, reduce the power required for laser cutting, and thus reduce the composite of cutting damage.

[0027] (3) The four sides of the sliced ​​battery of the present invention have a small textured surface structure, which can reduce optical loss and achieve good surface passivation.

[0028] (4) The present invention removes the damage layer at the non-laser edge of the sliced ​​battery, eliminates the additional composite loss caused by the damage, and makes the passivation effect of the edge region consistent with that of the middle region. The efficiency of the edge point and the center point of the sliced ​​battery is basically the same.

[0029] (5) The present invention significantly helps to improve the power of the module, with the upper limit of the module power improvement reaching about 1.2% to 1.4%, which is higher than the upper limit of the module power improvement of about 1% of the existing edge passivation technology.

[0030] (6) This invention provides a method for preparing sliced ​​batteries that is compatible with existing production line processes. The additional equipment required is low-cost, occupies little space, has low production and operating costs, is highly efficient, and is easy to modify production lines and promote in the industry.

[0031] (7) The present invention is compatible with various photovoltaic modules, including two-cell, three-cell and other multi-cell technologies, which can further improve the power of the modules and reduce the production cost. Attached Figure Description

[0032] Figure 1 This is a side view of the solar cell slice structure in a specific embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the front structure of a solar cell slice in a specific embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of the fabrication process of solar cell slices in a specific embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the test points of the solar cell slices in various embodiments and comparative examples of the present invention.

[0036] Figure 5 This is a surface morphology diagram of the etched area of ​​the solar cell slice according to Embodiment 1 of the present invention.

[0037] Figure 6 This is a graph showing the etching depth test results of the solar cell slice in Embodiment 1 of the present invention.

[0038] Figure 7 This is a topographic image of the laser-cut edge of the solar cell slice according to Embodiment 1 of the present invention.

[0039] Figure 8 This is a topographic image of the non-laser-cut edge of the solar cell slice in Embodiment 1 of the present invention.

[0040] Figure 9 This is a topographic image of the laser-cut edge of the solar cell slice of Comparative Example 1 of the present invention.

[0041] Figure 10 This is a topographic image of the non-laser-cut edge of the solar cell slice of Comparative Example 1 of the present invention.

[0042] Explanation of reference numerals in the attached figures: 1-Silicon substrate, 11-First small textured region, 12-Second small textured region, 13-Third small textured region, 14-Fourth small textured region, 15-Base region, 16-Laser-cut surface, 2-Boron emitter, 3-Front-side passivation and anti-reflection layer, 4-Front-side electrode, 5-Tunneling oxide layer, 6-Phosphorus-doped polycrystalline silicon layer, 7-Back-side passivation and anti-reflection layer, 8-Back-side electrode. Detailed Implementation

[0043] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of the present invention, and are not intended to limit the parameter range described in the present invention. Reasonable variations derived therefrom are still within the protection scope of the claims of the present invention.

[0044] It should be noted that the endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0045] The present invention provides a surface passivation structure for solar cell slices, including various cell structures such as TOPCon cells, back junction cells, and back contact cells. The surface passivation structure is located on one side of the pn junction, which can suppress the combined effect of defects from laser-cut edges and other non-laser-cut edges, thereby improving the efficiency of the entire cell. At the same time, it improves the efficiency of the sliced ​​cells, reduces the efficiency difference between different points of the sliced ​​cells, and improves the overall power of the photovoltaic module.

[0046] Combination Figure 1 and Figure 2 As shown, taking a two-slice TOPCon battery as an example, the sliced ​​battery includes a silicon substrate 1, and one side of the silicon substrate 1 is a laser-cut surface 16. This technology is also applicable to three-slice and more sliced ​​batteries. In the corresponding embodiment, the two opposite sides of the silicon substrate 1 are laser-cut surfaces 16.

[0047] The front surface of the silicon substrate 1 includes a base region 15 in the center and four small textured regions on its four edges, defined as a first textured region 11, a second textured region 12, a third textured region 13, and a fourth textured region 14, respectively. The first textured region 11 is located on the side corresponding to the laser-cut surface 16. The surface of the base region 15 has a pyramid textured structure, and the surfaces of the first textured region 11, the second textured region 12, the third textured region 13, and the fourth textured region 14 have small-sized pyramid textured structures. The pyramid size of these edge textured regions is smaller than the pyramid size of the base region 15.

[0048] In a specific embodiment, the pyramid height of each small textured area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm. This pyramid textured structure helps to reduce the efficiency difference at different points in the sliced ​​cell and improve the overall efficiency of the sliced ​​cell; furthermore, the small textured structure can induce dislocations on the laser-cut surface 16, reducing the power required for laser cutting and minimizing dislocation defects and cutting damage.

[0049] Combination Figure 1 As shown, a boron emitter 2 is disposed on the base region 15 of the positive surface of the silicon substrate 1, while no boron emitter 2 is disposed on the small textured area at the edges. This forms a pn junction isolation structure at the four edges, which can eliminate edge recombination. A front passivation antireflection layer 3 is covered on the boron emitter 2 and the small textured areas on the four sides. The small textured structure can reduce optical loss and achieve good surface passivation. A typical structure of the front passivation antireflection layer 3 is a stack of aluminum oxide and silicon nitride thin films. The front electrode 4 passes through the front passivation antireflection layer 3 and contacts the boron emitter 2.

[0050] Furthermore, the tallest pyramid apex in each small textured area is lower than the shortest pyramid apex in the base area 15, with the height difference ΔH between them ranging from 1 to 10 μm. This ensures the removal of laser-damaged surface structures from the silicon substrate 1, making the passivation of the edge regions consistent with the passivation effect of the base area 15, without introducing additional recombination losses.

[0051] The back surface of the silicon substrate 1 is sequentially covered with a tunneling oxide layer 5, a phosphorus-doped polycrystalline silicon layer 6, and a back passivation antireflection layer 7. The tunneling oxide layer 5 is typically made of silicon oxide and has a typical thickness of 0.5–3 nm. The back passivation antireflection layer 7 is typically a silicon nitride thin film stack, and the back electrode 8 passes through the back passivation antireflection layer 7 to contact the phosphorus-doped polycrystalline silicon layer 6.

[0052] Combination Figure 2 As shown, the width of the first small textured area 11 is W1, the width of the second small textured area 12 is W2, the width of the third small textured area 13 is W3, and the width of the fourth small textured area 14 is W4. In a preferred embodiment, the width dimensions of each edge small textured area are limited: W1 is between 10 and 1000 μm, W2 is between 4 and 800 μm, W3 is between 4 and 800 μm, and W4 is between 4 and 800 μm, to ensure edge isolation and eliminate composite loss. Furthermore, W2, W3, and W4 are generally equal to ensure consistent efficiency at all points on the non-laser-cut edge. The width of the first small textured area 11 can be equal to the width of the other small textured areas, or the size of W1 can be slightly increased according to the degree of laser cutting damage, i.e., W1 ≥ W2 = W3 = W4, thereby eliminating the efficiency difference between the laser-cut edge of the sliced ​​battery and other non-laser-cut edges.

[0053] In the embodiments of three-segment and multi-segment batteries, the two opposite sides of the silicon substrate 1 are laser-cut surfaces 16, and the first small textured area 11 and the second small textured area 12 are respectively set on the corresponding side of the two laser-cut surfaces 16. At this time, W1, W2, W3 and W4 satisfy the relationship: W1=W2≥W3=W4.

[0054] The above-mentioned sliced ​​cells have advantages such as no leakage, low saturation current density, high fill factor, and high cell efficiency. Moreover, the efficiency difference between each point is very small. After welding and connecting multiple sliced ​​cells in series, a photovoltaic module is obtained, and its overall power is significantly improved.

[0055] Combination Figure 3 As shown, the process flow for fabricating the above-mentioned solar cell slices is as follows: Step a: Prepare the silicon substrate, texturize both sides of the silicon substrate, and perform standard RCA cleaning.

[0056] Step b: Boron diffusion on the front side of the silicon substrate forms a boron emitter.

[0057] Step c: Polish the back side of the silicon substrate to prepare a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the back side.

[0058] Step d: Clean the four sides of the front of the silicon substrate and the pre-cut lines ( Figure 3 The area corresponding to the dashed line (in the middle) has a certain width and is laser-drilled to form a laser-processed area.

[0059] Step e: Perform chemical etching and texturing on the laser-processed area to remove the emitter, the textured surface of the silicon substrate, and the laser-damaged layer at the corresponding positions, forming a new small-sized pyramid textured surface structure.

[0060] In a specific embodiment, a step-by-step etching process is used for surface treatment. The specific process is as follows: First, the emitter is removed by etching with a first etchant; then, the textured surface structure on the front side of the silicon substrate is removed by etching to form a planar structure; etching continues to reach the designed depth to remove the laser-damaged layer; then, a second etchant is used to treat the surface of the etched area to form a small-sized pyramid textured surface structure. In a specific embodiment, the typical components of the first etchant include sodium hydroxide, hydrogen peroxide, alkaline polishing additives, and deionized water; the typical components of the second etchant include sodium hydroxide, texturing additives, and deionized water. By adjusting the etching time and selecting different etchants, the etching effect can be controlled to obtain the designed small-sized pyramid textured surface structure.

[0061] Step f: Passivate the silicon substrate on both sides to prepare a front passivation antireflection layer and a back passivation antireflection layer.

[0062] Step g: Perform double-sided metallization, fabricating a front electrode on the front side of the silicon substrate and a back electrode on the back side; Step h: Align with the pre-reserved cutting line and perform laser cutting to obtain solar cell slices.

[0063] The above-mentioned preparation process is compatible with conventional wafer cell production line processes. It only requires the addition of laser drilling equipment and chemical etching equipment. The equipment is low-cost, occupies little space, has low production and operating costs, and is highly efficient. It has a significant effect on reducing the efficiency difference at various points of wafer cells and improving the efficiency of photovoltaic modules, and has a very good prospect for industrial application and promotion.

[0064] The technical solution and effects of the present invention are illustrated below through specific embodiments. In each embodiment and comparative example, the performance of the solar cell slices was tested using Suns-Voc, and the test points are located as follows: Figure 4 As shown in the figure, point A corresponds to the laser-cut edge.

[0065] Example 1 The steps for preparing solar cell slices are as follows: Prepare an n-type silicon wafer, perform front-side texturing, back-side polishing, and standard RCA cleaning. Boron diffusion is applied to the front side of the wafer to form a boron emitter; the back side is polished to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-cut areas of a certain width are formed on the four edges of the front side of the silicon substrate and at the locations corresponding to pre-cut lines, creating laser-processed areas. The width of the laser-processed area at the four edges is 40µm, and the width of the laser-processed area at the locations corresponding to the pre-cut lines is 80µm, with the pre-cut lines positioned at the center of these areas. Chemical etching is then performed on the laser-processed areas. A first etchant is used to etch away the emitter and the textured surface of the front side of the silicon substrate, forming a planar structure. Etching continues until a depth of 5.6µm is reached. A second etchant is then used to form a surface layer on the etched area. Figure 5 The small-sized pyramid-shaped textured structure shown has a height ranging from 0.2 to 2 μm and a width ranging from 0.5 to 5 μm. The height difference between the apex of the pyramid on the etched area and the apex of the pyramid on the non-etched area was measured using a profilometer, and the results are as follows: Figure 6 As shown, an alumina thin film was prepared on the front side of the sample, followed by a silicon nitride thin film deposited on both sides. A passivation sheet was then subjected to double-sided metallization. Laser cutting was performed along the pre-defined cutting lines at a power of 114 W to obtain the solar cell slices.

[0066] The laser-cut edge morphology of solar cell slices is as follows Figure 7 (The red box in the image shows the laser-cut edge.) As can be seen, there are almost no jagged edges, thus ensuring low edge composite. The morphology of a non-laser-cut edge is as follows: Figure 8 (The red box in the image indicates the edge area) As shown, the edge is relatively smooth with almost no damage, thus ensuring a low level of edge composite.

[0067] The performance of various parts of the sliced ​​battery prepared in this embodiment was tested (test locations are shown in the figure). Figure 4 The results (shown in Table 1) and overall performance of the sliced ​​battery are shown in Table 1 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery is 0.12%, and the standard deviation is 4.39 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 26.07%.

[0068] Table 1. Performance test results of sliced ​​batteries in Example 1 (Suns-Voc test method) Example 1 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 735 41.68 85.22 26.02 Point B 739 41.82 85.25 26.14 Point C 736 41.72 85.40 26.07 Point D 737 41.72 85.53 26.06 Point E 737 41.55 85.54 26.09 overall 737 41.75 85.41 26.07 Example 2 The steps for preparing solar cell slices are as follows: Prepare an n-type silicon wafer, perform front-side texturing, back-side polishing, and standard RCA cleaning. Boron diffusion is applied to the front side of the wafer to form a boron emitter; the back side is polished to remove borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-treated areas of a certain width are created on the four edges of the front side of the silicon substrate and at the locations corresponding to pre-cut lines, forming laser-treated areas. The width of the laser-treated area at the four edges is 40µm, and the width of the laser-treated area at the locations corresponding to the pre-cut lines is 100µm, with the pre-cut lines positioned at the center of these areas. Chemical etching is then performed on the laser-treated areas. A first etchant is used to remove the emitter and the textured surface of the front side of the silicon substrate, forming a planar structure. Etching continues until a depth of 4µm is reached. A second etchant is used to form a small-sized pyramid textured surface on the etched area, with the pyramid height ranging from 0.2 to 2 μm and the width ranging from 0.5 to 5 μm. An alumina thin film was prepared on the front side of the sample, followed by the deposition of silicon nitride thin films on both sides. The passivation sheet underwent double-sided metallization. Laser cutting was performed along pre-defined cutting lines at a power of 114 W to obtain solar cell slices.

[0069] The performance of each part and the overall structure of the sliced ​​battery prepared in this embodiment was tested, and the results are shown in Table 2 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.08%, and the standard deviation was 3.0 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 26.12%.

[0070] Table 2 Performance test results of sliced ​​batteries in Example 2 (Suns-Voc test method) Example 2 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 736 41.63 85.32 26.07 Point B 740 41.81 85.35 26.15 Point C 736 41.71 85.41 26.10 Point D 738 41.69 85.53 26.09 Point E 737 41.60 85.54 26.11 overall 738 41.77 85.42 26.12 Example 3 The steps for preparing solar cell slices are as follows: Prepare an n-type silicon wafer, perform front-side texturing, back-side polishing, and standard RCA cleaning. Boron diffusion is applied to the front side of the wafer to form a boron emitter; the back side is polished to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-etched areas of a certain width are formed on the four edges of the front side of the silicon substrate and at the corresponding positions of the pre-cut lines, creating laser-processed areas. The width of the laser-processed areas at the four edges is 40µm, and the width of the laser-processed areas at the corresponding positions of the pre-cut lines is 80µm, with the pre-cut lines located at the center line of these areas. Chemical etching is performed on the laser-processed areas. A first etchant is used to remove the emitter and the textured surface of the front side of the silicon substrate, forming a planar structure. Etching continues until a depth of 4µm is reached. A second etchant is used to form a small-sized pyramid textured surface structure on the etched area, with the pyramid height ranging from 0.2 to 2 μm and the width ranging from 0.5 to 5 μm. An alumina thin film was prepared on the front side of the sample, followed by the deposition of silicon nitride thin films on both sides. The passivation sheet underwent double-sided metallization. Laser cutting was performed along pre-defined cutting lines at a power of 130W to obtain solar cell slices.

[0071] The performance of each part and the overall structure of the sliced ​​battery prepared in this embodiment was tested, and the results are shown in Table 3 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.13%, and the standard deviation was 4.7 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 26.04%.

[0072] Table 3 Performance test results of sliced ​​batteries in Example 3 (Suns-Voc test method) Example 3 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 735 41.71 85.32 25.99 Point B 738 41.80 85.30 26.12 Point C 737 41.71 85.40 26.06 Point D 737 41.61 85.34 26.07 Point E 737 41.63 85.35 26.08 overall 737 41.75 85.40 26.04 Example 4 The steps for preparing solar cell slices are as follows: Prepare an n-type silicon wafer, perform front-side texturing, back-side polishing, and standard RCA cleaning. Boron diffusion is applied to the front side of the wafer to form a boron emitter; the back side is polished to remove borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-treated areas of a certain width are formed on the four edges of the front side of the silicon substrate and at the locations corresponding to pre-cut lines, creating laser-treated areas. The width of the laser-treated areas at the four edges is 40µm, and the width of the laser-treated areas at the locations corresponding to the pre-cut lines is 80µm, with the pre-cut lines positioned at the center of these areas. Chemical etching is then performed on the laser-treated areas. A first etchant is used to remove the emitter and the textured surface of the front side of the silicon substrate, forming a planar structure. Etching continues until a depth of 10µm is reached. A second etchant is used to form a small-sized pyramid textured surface on the etched area, with the pyramid height ranging from 0.2 to 2 μm and the width ranging from 0.5 to 5 μm. An alumina thin film was prepared on the front side of the sample, followed by the deposition of silicon nitride thin films on both sides. The passivation sheet underwent double-sided metallization. Laser cutting was performed along pre-defined cutting lines at a power of 114 W to obtain solar cell slices.

[0073] The performance of each part and the overall structure of the sliced ​​battery prepared in this embodiment was tested, and the results are shown in Table 4 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.10%, and the standard deviation was 3.8 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 26.11%.

[0074] Table 4 Performance test results of sliced ​​battery in Example 4 (Suns-Voc test method) Example 4 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 736 41.78 85.41 26.06 Point B 739 41.83 85.45 26.16 Point C 737 41.77 85.35 26.09 Point D 737 41.72 85.34 26.10 Point E 737 41.77 85.35 26.08 overall 738 41.78 85.41 26.11 Example 5 2000 sliced ​​solar cells were prepared using the method in Example 1, and their efficiency was tested using an IV curve analyzer. The average efficiency of the sliced ​​solar cells was measured to be 26.21%, and the average value of each key parameter of the cells was V. oc =742.5 mV, FF=84.94%, I sc =13.7658 A. The battery efficiency is higher than that of Comparative Example 5.

[0075] Example 6 Sliced ​​cells were prepared using the method of Example 1, and ten 108-cell TOPCon cell modules were fabricated, each module measuring 9.1 cm × 18.2 cm. Testing showed that the average power of the modules was 446.6 W, significantly higher than that of Comparative Example 6.

[0076] Comparative Example 1 The steps for preparing solar cell slices are as follows: An n-type silicon wafer was prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion was performed on the front side of the wafer to form a boron emitter; the back side was polished to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon were sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. An alumina film was prepared on the front side of the sample, followed by double-sided deposition of silicon nitride films. The passivated wafer underwent double-sided metallization. Laser cutting was performed along the pre-defined cutting lines at a laser power of 130W. ALD was used to deposit a 30nm thick alumina film on the laser-cut surface to obtain a solar cell slice.

[0077] The edge morphology of laser-cut solar cell slices is as follows Figure 9 (The red box in the image shows the laser-cut edge.) As can be seen, cutting a large-sized textured surface results in significant serrated defects at the edge, and these defects are very severe. Laser cutting of a flat surface produces even more pronounced edge defects. The morphology of a non-laser-cut edge is shown below. Figure 10 (The red box in the image shows the edge area.) As shown, even if this area has not been laser-cut, there are various edge damage defects, which will increase edge composite.

[0078] The performance of each part and the overall structure of the sliced ​​battery prepared in this comparative example were tested, and the results are shown in Table 5 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.28%, and the standard deviation was 10.2 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 25.82%.

[0079] Table 5 Performance test results of the sliced ​​battery in Comparative Example 1 (Suns-Voc test method) Comparative Example 1 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 735 41.78 85.32 25.69 Point B 738 41.83 85.31 25.97 Point C 736 41.76 85.41 25.81 Point D 737 41.71 85.34 25.88 Point E 737 41.78 85.35 25.85 overall 735 41.78 85.36 25.82 Comparative Example 2 The steps for preparing solar cell slices are as follows: Prepare an n-type silicon wafer, texturing the front side and polishing the back side, followed by standard RCA cleaning. Boron diffusion is performed on the front side of the wafer to form a boron emitter; the back side is polished to remove borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-etched areas of a certain width corresponding to pre-cut lines on the silicon substrate are formed, creating a laser-processed area with a width of 80µm. The pre-cut lines are positioned at the center line of this area. Chemical etching is performed on the laser-processed area. A first etchant is used to remove the emitter and the texturing structure on the front side of the silicon substrate, forming a planar structure. Etching continues to a depth of 4µm. A second etchant is used to form a small-sized pyramidal texturing structure on the surface of the etched area, with the pyramid height ranging from 0.2 to 2 μm and the width ranging from 0.5 to 5 μm. An alumina film is prepared on the front side of the sample, followed by double-sided deposition of silicon nitride films. The passivated wafer is then double-sided metallized. Laser cutting is performed along the pre-defined cutting lines with a laser power of 130W to obtain solar cell slices.

[0080] The performance of each part and the overall structure of the sliced ​​battery prepared in this comparative example were tested, and the results are shown in Table 6 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.19%, and the standard deviation was 8.5 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) was 25.94%.

[0081] Table 6 Performance test results of the sliced ​​battery in Comparative Example 2 (Suns-Voc test method) Comparative Example 2 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 736 41.77 85.33 25.95 Point B 739 41.84 85.42 26.09 Point C 737 41.77 85.36 25.89 Point D 737 41.71 85.34 25.92 Point E 737 41.78 85.39 25.88 overall 737 41.77 85.37 25.94 Comparative Example 3 The steps for preparing solar cell slices are as follows: An n-type silicon wafer was prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion was performed on the front side of the wafer to form a boron emitter; the back side was polished to remove the borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon were sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-treated areas of a certain width were created on the four edges of the front side of the silicon substrate and at the locations corresponding to pre-cut lines, forming laser-treated areas. The width of the laser-treated areas on the four edges was 40µm, and the width of the laser-treated areas at the locations corresponding to the pre-cut lines was 80µm, with the pre-cut lines positioned at the center of these areas. Chemical etching was performed on the laser-treated areas, using the first etchant to remove the emitter and the texturing structure on the front side of the silicon substrate, forming a planar structure. Etching continued until a depth of 4µm was achieved. An alumina film was prepared on the front side of the sample, followed by double-sided deposition of silicon nitride films. The passivated wafer was then double-sided metallized. Laser cutting was performed along the pre-cut lines at a laser power of 141W to obtain a solar cell slice.

[0082] The performance of each part and the overall structure of the sliced ​​battery prepared in this comparative example was tested, and the results are shown in Table 7 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.22%, and the standard deviation was 8.2 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 25.97%.

[0083] Table 7 Performance test results of the 3-slice battery in Comparative Example 3 (Suns-Voc test method) Comparative Example 3 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 735 41.78 85.32 25.88 Point B 739 41.85 85.33 26.10 Point C 737 41.78 85.43 25.99 Point D 737 41.74 85.34 26.02 Point E 737 41.73 85.35 26.05 overall 737 41.79 85.39 25.97 Comparative Example 4 The steps for preparing solar cell slices are as follows: Prepare an n-type silicon wafer, perform front-side texturing, back-side polishing, and standard RCA cleaning. Boron diffusion is applied to the front side of the wafer to form a boron emitter; the back side is polished to remove borosilicate glass. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivated wafer. Laser-treated areas of a certain width are formed on the four edges of the front side of the silicon substrate and at the locations corresponding to pre-cut lines, creating laser-treated areas. The width of the laser-treated areas at the four edges is 40µm, and the width of the laser-treated areas at the locations corresponding to the pre-cut lines is 80µm, with the pre-cut lines positioned at the center of these areas. Chemical etching is then performed on the laser-treated areas. A first etchant is used to remove the emitter and the textured surface of the silicon substrate, forming a planar structure. Etching continues until a depth of 0.5µm is reached. A second etchant is used to form a small-sized pyramid textured surface on the etched area, with the pyramid height ranging from 0.2 to 2 μm and the width ranging from 0.5 to 5 μm. An alumina thin film was prepared on the front side of the sample, followed by the deposition of silicon nitride thin films on both sides. The passivation sheet underwent double-sided metallization. Laser cutting was performed along pre-defined cutting lines at a power of 114 W to obtain solar cell slices.

[0084] The performance of each part and the overall structure of the sliced ​​battery prepared in this comparative example were tested, and the results are shown in Table 8 below. The maximum difference in pseudoefficiency (pEff) among different parts of the sliced ​​battery was 0.15%, and the standard deviation was 5.4 × 10⁻⁶. -4 The overall pseudoefficiency (pEff) is 26.01%.

[0085] Table 8 Performance test results of the 4-slice battery in Comparative Example 4 (Suns-Voc test method) Comparative Example 4 <![CDATA[pV oc (mV)]]> <![CDATA[pJ sc (mA / cm 2 )]]> pFF(%) pEff(%) Point A 736 41.77 85.35 25.96 Point B 739 41.86 85.40 26.11 Point C 738 41.76 85.43 26.05 Point D 737 41.72 85.34 26.02 Point E 737 41.73 85.37 26.04 overall 737 41.76 85.34 26.01 Comparative Example 5 2000 sliced ​​solar cells were prepared using the method of Comparative Example 1, and their efficiency was tested. The average efficiency of the sliced ​​solar cells was measured to be 26.13%, and the average value of each key parameter of the cells was V. oc =741.4 mV, FF=84.73%, I sc=13.7782 A.

[0086] Comparative Example 6 Sliced ​​cells were prepared using the method described in Comparative Example 1, and ten 108-cell TOPCon cell modules were fabricated, each measuring 9.1 cm × 18.2 cm. The average power output of the modules was measured to be 442.1 W.

[0087] The above embodiments take TOPCon batteries as an example. Applying the surface passivation structure of the present invention to back junction batteries and full back contact batteries can also achieve similar technical effects.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A surface passivation structure for a solar cell slice, characterized in that, The device includes a silicon substrate, one side or opposite two sides of which are laser-cut surfaces. The front / back surface of the silicon substrate includes a base region located in the center and a first, second, third, and fourth small textured surface regions located on the four sides. The first small textured surface region is disposed on the side corresponding to the laser-cut surface, or the first and second small textured surface regions are respectively disposed on the sides corresponding to the laser-cut surface. A boron emitter is disposed on the base region. A front passivation antireflection layer is covered on the boron emitter, the first, second, third, and fourth small textured surface regions. The surfaces of the boron emitter, the first, second, third, and fourth small textured surface regions have a pyramid textured structure, and the pyramid size of the base region is larger than the pyramid size of the first, second, third, and fourth small textured surface regions.

2. The surface passivation structure of the solar cell slice according to claim 1, characterized in that, The pyramid height of the first small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm; and / or, the pyramid height of the second small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm; and / or, the pyramid height of the third small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm; and / or, the pyramid height of the third small velvet area ranges from 0.2 to 2 μm, and the width ranges from 0.5 to 5 μm.

3. The surface passivation structure of the solar cell slice according to claim 1, characterized in that, The width W1 of the first small pile area is between 10 and 1000 μm; the width W2 of the second small pile area is between 4 and 1000 μm; the width W3 of the third small pile area is between 4 and 800 μm; and the width W4 of the fourth small pile area is between 4 and 800 μm.

4. The surface passivation structure of the solar cell slice according to claim 3, characterized in that, W1, W2, W3, and W4 satisfy the relation: W1 ≥ W2 ≥ W3 = W4.

5. The surface passivation structure of a solar cell slice according to any one of claims 1-4, characterized in that, The highest pyramid apex in the first, second, third, and fourth small pile areas is lower than the lowest pyramid apex in the base area.

6. The surface passivation structure of the solar cell slice according to claim 5, characterized in that, The height difference between the tallest pyramid apex in the first small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm; the height difference between the tallest pyramid apex in the second small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm; the height difference between the tallest pyramid apex in the third small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm; the height difference between the tallest pyramid apex in the fourth small velvet area and the shortest pyramid apex in the base area is between 1 and 10 μm.

7. A method for preparing a surface passivation structure for a solar cell slice as described in any one of claims 1-6, characterized in that, Includes the following steps: Step S1: Prepare the silicon substrate, and texturize the front and / or back surfaces of the silicon substrate; Step S2: Boron diffusion occurs on the front / back surfaces of the silicon substrate to form a boron emitter; Step S3: Perform laser drilling on the surface of the silicon substrate with boron emitters to form a laser processing area with a certain width at the four edges and the corresponding positions of the reserved cutting lines; Step S4: Perform chemical etching and texturing on the laser-processed area to remove the emitter, the textured surface of the silicon substrate, and the laser-damaged layer at the corresponding positions, forming a new small-sized pyramid textured surface structure. Step S5: Passivate the surface of the silicon substrate with the boron emitter to prepare a passivation antireflection layer; Step S6: Align with the reserved cutting line and perform laser cutting.

8. The method for preparing the surface passivation structure of a solar cell slice according to claim 7, characterized in that, In step S4, the specific process of chemical etching and texturing includes: using a first etchant to etch and remove the emitter; continuing to etch and remove the textured surface structure on the front side of the silicon substrate, and etching to the designed depth to remove the laser damage layer and form a planar structure; using a second etchant to form a small-sized pyramid textured surface structure on the surface of the etched area.

9. The method for preparing the passivation structure on the surface of a solar cell slice according to claim 7, characterized in that, In step S4, during the chemical etching and texturing process, the damaged structures on the four sides are removed.

10. The method for preparing the surface passivation structure of a solar cell slice according to claim 7, characterized in that, In step S3, the number of reserved cutting lines is one or more.

11. A solar cell slice, characterized in that, Includes the surface passivation structure of the solar cell slice as described in any one of claims 1-6, wherein the solar cell slice is selected from TOPCon cells, back junction cells, and full back contact cells.

12. A photovoltaic module, characterized in that, Including the solar cell slices as described in claim 11.

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