Solar cell

Abstract

The invention relates to the field of solar cells, and discloses a solar cell piece. According to the method, an insulating dielectric film is pre-constructed at the edge of a silicon wafer through a special combined process of'direct oxidation-indirect deposition-high-temperature annealing '+ 'high-temperature densification + boron doping', so that an edge winding and plating area is insulated and isolated from a silicon wafer substrate, and therefore, even if a winding and plating layer exists at the edge of a finished TBC solar cell, the winding and plating part does not generate relatively large electric leakage; and secondly, the insulating dielectric film also has an excellent passivation effect, can further passivate the side surface area of the silicon wafer, and is beneficial to improving the electrical property of the battery. And finally, compared with a conventional TBC solar cell with all edges being pyramid suede surfaces, the edge part of the silicon wafer is the pyramid suede surface, the edge part of the silicon wafer is the polished surface, the edge suede-shaped silicon wafer is easier to cause silicon wafer fragments under the action of external force, and the polished surface is more beneficial to improving the yield of the cell.

Description

This application is a divisional application of patent application CN202411641021.1, filed on November 18, 2024, entitled "A method for preparing a TBC solar cell with an edge-wrap coating". Technical Field

[0001] This invention relates to the field of solar cells, and more particularly to a solar cell. Background Technology

[0002] TBC solar cells combine the superior tunneling oxide / doped polycrystalline silicon passivation contact technology of mainstream TOPCon solar cells with the contact characteristics of the back electrode. They represent the next generation of mainstream crystalline silicon solar cells and have features such as high efficiency and aesthetic appeal.

[0003] Currently, in the fabrication process of TBC solar cells, multiple depositions of poly-Si on the back of the silicon wafer using tubular vacuum equipment inevitably result in a coating layer around the front and edges of the wafer. To reduce the leakage current caused by this coating layer, a wet process is often used to remove it, thus reducing the leakage current of the solar cell. The common method for removing the coating layer from the edges of TBC solar cells is a chain-type acid polishing process. However, due to the difficulty in maintaining a consistently horizontal roller on the chain machine over long-term use, the silicon wafer vibrates during the polishing process, making it impossible to effectively remove the coating layer from the edges. Consequently, some coating layer remains at the edges of the actual cell, which undoubtedly increases the leakage current and affects the final performance of the cell. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a solar cell and its fabrication method. This invention utilizes a unique combination of "direct oxidation-indirect deposition" and "high-temperature densification + boron doping" processes to pre-construct an insulating dielectric film at the edge of the silicon wafer, effectively isolating the edge-coated area from the silicon substrate. Therefore, even if the edge of the finished TBC solar cell has a coating, the coated portion will not experience significant leakage. Secondly, this insulating dielectric film also exhibits excellent passivation effects, further passivating the side areas of the silicon wafer and improving the cell's electrical performance. Furthermore, compared to conventional TBC solar cells where the entire edge is pyramidally textured, the silicon wafer of this invention has a pyramidally textured edge and a polished edge. Textured edges are more prone to fragmentation under external forces, while polished edges contribute to higher cell yield.

[0005] The specific technical solution of the present invention is as follows: a method for preparing a TBC solar cell with an edge-wrap coating, specifically including the following steps: S1. Polish both sides of the N-type silicon wafer.

[0006] S2. Stack several silicon wafers in a "layered" manner to form a cubic silicon wafer assembly.

[0007] Because a single silicon wafer is relatively thin, it is difficult to deposit an insulating dielectric film directly on its edges. Therefore, this invention cleverly stacks multiple silicon wafers into a cubic wafer assembly, which effectively increases the deposition area, facilitates the deposition process, and improves efficiency.

[0008] S3. A first silicon oxide layer and a second silicon oxide layer are formed sequentially at the edge of the silicon wafer through direct oxidation and indirect deposition. The two layers are combined to form an insulating dielectric film.

[0009] After depositing insulating dielectric films on the four sides of the silicon wafer edge, the silicon wafer substrate and subsequent coating layers are isolated, preventing leakage. The first silicon oxide layer is formed by direct oxidation of the shallow surface silicon atoms at the edge of the N-type silicon wafer. Because the atoms on the silicon wafer substrate surface are densely packed, a relatively dense first silicon oxide layer can be directly generated; however, since the silicon wafer substrate is N-type doped, the number of mobile electrons within the substrate is greater than that of intrinsic silicon oxide, resulting in a lower dielectric constant and weaker insulating properties for the formed first silicon oxide layer. Therefore, this invention further deposits a second silicon oxide layer on its surface via indirect deposition. Unlike direct oxidation, which transforms the shallow surface layer at the silicon wafer edge into a first silicon oxide layer, the deposition method adds an intrinsic silicon oxide film (i.e., a second silicon oxide layer) to the surface of the first silicon oxide layer. This second silicon oxide layer has fewer mobile electrons within its substrate and better insulating properties. These two steps can be performed sequentially in the same tubular PECVD equipment, effectively reducing process time. In summary, this invention utilizes a special "direct oxidation-indirect deposition" process to effectively form an insulating dielectric film on all four sides of the silicon wafer edge, without any significant negative impact even if a coating layer is present.

[0010] S4. Remove the silicon oxide layer on the back of the silicon wafer.

[0011] During the S3 high-temperature deposition process, a partial silicon oxide layer will inevitably be generated on the back side of the silicon wafer, so it is necessary to remove the back silicon oxide layer.

[0012] S5. A tunneling oxide layer and an intrinsic polycrystalline silicon layer are sequentially deposited on the back side of the silicon wafer.

[0013] While the tunneling oxide layer and the intrinsic polysilicon layer are deposited sequentially on the back side of the silicon wafer, a wrap-around coating (i.e., the tunneling oxide layer and the intrinsic polysilicon layer located at the edge of the silicon wafer) will inevitably be generated on the front side and edge areas of the silicon wafer.

[0014] S6. Two-step source-source boron diffusion transforms the inner and outer layers of the intrinsic polycrystalline silicon layer into a boron diffusion layer and a BSG layer, respectively. The insulating dielectric film is densified at high temperature and boron atoms are doped.

[0015] In the above two-step source-source boron diffusion process, in addition to converting the inner and outer layers of the intrinsic polycrystalline silicon layer into boron diffusion layers and BSG layers respectively, the insulating dielectric film was also simultaneously annealed and boron-doped. The effects are as follows: (1) The intrinsic silicon oxide film (i.e. the second silicon oxide layer) deposited by PECVD in S3 has a high porosity, which will reduce the effective density of the material and thus reduce the dielectric constant (insulation is reduced); high-temperature annealing can reduce the porosity in the intrinsic silicon oxide film, making the film more compact, thereby increasing the dielectric constant; (2) The introduction of boron atoms will change the microstructure and charge distribution of the insulating dielectric film, thereby affecting its dielectric properties; specifically: (a) Regarding charge distribution: the presence of boron atoms in the insulating dielectric film will introduce additional charges, which will respond to the electric field, thereby increasing the polarization ability of the material and increasing the dielectric constant; (b) Regarding microstructure: the introduction of boron atoms will change the microstructure of the insulating dielectric, increase the non-uniformity of the material, which will also increase its dielectric constant.

[0016] S7. Laser-guided patterning removes the BSG layer from the phosphorus diffusion and isolation zones in a single process.

[0017] Removing the BSG layer from the surface of the phosphorus diffusion zone and isolation zone design area can pave the way for subsequent alkaline cleaning.

[0018] S8. Alkaline cleaning. During the alkaline cleaning process, since the BSG layer on the surface of the S7 trench area is removed, the various deposited layers at the bottom will be corroded and removed by the alkaline solution, exposing the silicon wafer substrate; while in the non-trench area, since the surface is protected by the BSG layer, the deposited layers at the bottom are retained.

[0019] S9, backside secondary deposition of tunneling oxide layer and intrinsic polycrystalline silicon layer.

[0020] While the tunneling oxide layer and the intrinsic polysilicon layer are deposited sequentially on the back side of the silicon wafer, a wrap-around coating will inevitably be generated again on the front side and edge areas of the silicon wafer.

[0021] S10, phosphorus diffusion, transforms the inner and outer layers of the intrinsic polycrystalline silicon layer into a phosphorus diffusion layer and a PSG layer, respectively.

[0022] S11. The PSG layer in the boron diffusion zone and isolation zone design area is removed by laser secondary patterning on the back side.

[0023] Removing the PSG layer from the surface of the boron diffusion zone and isolation zone design area can prepare the ground for subsequent cleaning and texturing.

[0024] S12, Removal of Wrap-on Plating: The silicon wafer is acid-polished using a chain machine to remove the wrap-on plating layer on the front and edges of the silicon wafer. However, due to the difficulty in keeping the rollers of the chain machine horizontal during long-term use, the silicon wafer vibrates up and down during the acid polishing process. The wrap-on plating on the front can be basically removed, but it cannot effectively remove all the wrap-on plating on the edges of the silicon wafer. Therefore, there are some wrap-on plating areas on the edges of the battery.

[0025] S13. Cleaning and Texturing: The silicon wafers with the removed coating are placed in an alkaline texturing tank for integrated wet cleaning and texturing. Since the front side of the wafer has no oxide areas after the coating removal, a pyramidal textured surface can be formed during texturing (a pyramidal textured surface will also be formed on the edges of the wafer where the coating has been completely removed). For the phosphorus diffusion layer on the back side of the wafer, its bottom deposition layer is preserved due to the PSG layer's protection. For the isolation area on the back side of the wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, leaving the silicon substrate unprotected, forming an isolation area and generating a pyramidal textured surface. For the boron diffusion layer, since its surface PSG layer has also been removed, its bottom phosphorus diffusion layer and tunneling oxide layer will be corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer will block the alkaline solution's erosion, protecting its bottom deposition layer. Subsequently, the texturing tank is equipped with an acid (HF / HCl) cleaning tank to further remove any remaining PSG and BSG layers on the back side of the wafer.

[0026] S14, double-sided coating.

[0027] S15, screen printing, sintering, light injection, to obtain TBC solar cells with edge-wrap coating.

[0028] Preferably, in S2, the number of silicon wafers stacked each time is 100 to 300, and after stacking, the front and back sides of adjacent silicon wafers are in contact, and the four edge sides are flush.

[0029] Preferably, in S3, insulating dielectric films are sequentially constructed on the four edge sides of the stacked silicon wafer.

[0030] Preferably, in S3, the thickness of the first silicon oxide layer is 5-30 nm; and the thickness of the second silicon oxide layer is 10-200 nm.

[0031] Preferably, in S3, the direct oxidation includes: introducing N2O to oxidize the shallow surface of the silicon wafer edge into a first silicon oxide layer.

[0032] Further preferred, the conditions for direct oxidation are: N2O flow rate 100-500 sccm, radio frequency power 1000-10000 W, pressure 10-200 Torr, temperature 300-500℃, and time 5-30 min.

[0033] Preferably, in S3, the indirect deposition includes: introducing SiH4 and N2O to deposit a second silicon oxide layer on the surface of the first oxide layer.

[0034] Further preferred, the conditions for the indirect deposition are: a SiH4 to N2O flow ratio of 1:5 to 1:10, a radio frequency power of 1000 to 10000 W, a pressure of 100 to 500 Torr, a temperature of 300 to 500 °C, and a time of 10 to 80 min.

[0035] Preferably, in S4, a chain machine is used to remove the silicon oxide layer on the back of the silicon wafer by acid etching, using a 20-60 wt% HF aqueous solution as the acid etching solution, and a belt speed of 1-10 m / min.

[0036] Preferably, in S5 and S9, the deposition conditions of the tunneling oxide layer are: O2 flow rate 10000-80000 sccm, reaction temperature 400-800℃, time 200-1000 s, and tunneling oxide layer thickness 2-10 nm; the deposition conditions of the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300-2000 sccm, reaction temperature 500-700℃, time 2-4 h, working gas pressure 100-500 mTorr, and intrinsic polycrystalline silicon layer thickness 100-300 nm.

[0037] Preferably, in S6, the conditions for the two-step boron diffusion process are as follows: Step 1: A mixed gas of BCl3 and O2 is introduced at a temperature of 800–950°C, a diffusion time of 5–50 min, a BCl3 gas flow rate of 50–500 sccm, and an O2 flow rate of 500–2000 sccm; Oxidation propulsion: A temperature of 900–1050°C, a propulsion time of 30–80 min, and an O2 flow rate of 5000–30000 sccm; Step 2: A mixed gas of BCl3 and O2 is introduced at a temperature of 800–950°C, a diffusion time of 2–30 min, a BCl3 flow rate of 20–100 sccm, and an O2 flow rate of 200–1000 sccm.

[0038] Because the boron atom concentration is relatively low during conventional one-step boron diffusion, the concentration of boron atoms introduced into the insulating dielectric film during this process is also low. In order to increase the boron atom concentration in the edge insulating dielectric film, this invention specifically adds a post-source process (i.e., the final re-source process) on the basis of conventional boron diffusion. This aims to increase the boron atom concentration in the insulating dielectric film and improve the dielectric constant of the layer. At the same time, because there is a BSG layer blocking the boron diffusion surface on the back side, the post-source process will not affect the initial performance of the boron diffusion layer on the back side.

[0039] Preferably, in S10, the conditions for phosphorus diffusion are: temperature 750–850℃, diffusion time 5–30 min, POCl3 carried by nitrogen gas at a flow rate of 500–1200 sccm, O2 flow rate of 500–1000 sccm, oxidation propulsion temperature 850–950℃, O2 flow rate of 1000–10000 sccm, and propulsion time of 20–60 min.

[0040] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention pre-deposits an insulating dielectric film on the edge of the silicon wafer to make the edge-wrapped area insulated and isolated from the silicon wafer substrate. Therefore, even if there is a wrap-around coating on the edge of the finished TBC solar cell, the wrap-around part will not have a large leakage current.

[0041] (2) The insulating dielectric film formed by the present invention through a special combination process of "direct oxidation-indirect deposition" + "high temperature densification + boron doping" has high density and high dielectric constant, thus exhibiting excellent insulation performance and effectively isolating the edge-wrap coating from the silicon wafer substrate.

[0042] (3) The silicon oxide dielectric film of the present invention also has excellent passivation effect, which can further passivate the side area of ​​the silicon wafer, which is beneficial to improving the electrical performance of the battery.

[0043] (4) Compared with the pyramidal textured edge of conventional TBC solar cells, the edge of the silicon wafer of the present invention is partially pyramidal textured and partially polished. The textured edge silicon wafer is more prone to silicon wafer fragmentation under external force, while the polished surface is more conducive to improving the yield of the cell. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of a silicon wafer after double-sided polishing.

[0045] Figure 2 This is a schematic diagram of the structure after an insulating layer is deposited on the side of a silicon wafer.

[0046] Figure 3 This is a schematic diagram of the structure of a silicon wafer after the first tunneling oxide layer and the first intrinsic polycrystalline silicon layer are deposited in one step.

[0047] Figure 4 This is a schematic diagram of the structure of a silicon wafer after boron diffusion.

[0048] Figure 5 A schematic diagram of the structure of a silicon wafer after laser patterning and grooving of the BSG layer followed by cleaning.

[0049] Figure 6 This is a schematic diagram of the structure after the secondary deposition of the second tunneling oxide layer and the second intrinsic polycrystalline silicon layer on the silicon wafer.

[0050] Figure 7This is a schematic diagram of the structure of a silicon wafer after phosphorus diffusion.

[0051] Figure 8 This is a schematic diagram of the structure of a silicon wafer after decoupling and plating.

[0052] Figure 9 This is a schematic diagram of the structure of a silicon wafer after laser-patterned secondary grooving of the PSG layer followed by cleaning and texturing (the pyramidal texturing layer is not shown in the diagram because it is thinner at the edge of the silicon wafer).

[0053] Figure 10 This is a schematic diagram of the structure of a finished TBC solar cell (the pyramid textured surface at the edge of the silicon wafer is thinner and therefore not shown in the diagram).

[0054] The attached figures are labeled as follows: 1. N-type monocrystalline silicon wafer; 2. Insulating dielectric film; 3. First tunneling oxide layer; 4. First intrinsic polycrystalline silicon layer; 5. Boron diffusion layer; 6. BSG layer; 7. Second tunneling oxide layer; 8. Second intrinsic polycrystalline silicon layer; 9. Phosphorus diffusion layer; 10. PSG layer; 11. Pyramid textured surface; 12. Passivation antireflection layer; 13. Electrode layer. Detailed Implementation

[0055] The present invention will be further described below with reference to embodiments.

[0056] A method for preparing a TBC solar cell with an edge-wrap coating includes the following steps: S1, polishing both sides of an N-type silicon wafer.

[0057] In some preferred embodiments, the N-type monocrystalline silicon wafer 1 is immersed in an alkaline polishing bath containing alkaline solution and polished on both sides at 75–85°C for 6–8 minutes, achieving a polishing thickness of 3–7 μm and a thinning amount of 0.35–0.45 g. Figure 1 As shown.

[0058] S2. Stack several silicon wafers in a "layered" manner to form a cubic silicon wafer assembly.

[0059] In some preferred embodiments, silicon wafers are stacked in layers, in groups of 100 to 300 wafers. After stacking, the front and back sides of adjacent silicon wafers are in contact, and the four edges are flush with the sides facing upwards, in preparation for the subsequent deposition of insulating dielectric films on the four edges of the silicon wafers.

[0060] S3. A first silicon oxide layer and a second silicon oxide layer are sequentially formed at the four edges of the silicon wafer assembly through direct oxidation and indirect deposition. The two layers combine to form an insulating dielectric film 2, as shown below. Figure 2 As shown.

[0061] In some preferred embodiments, in S3, the thickness of the first silicon oxide layer is 5-30 nm; and the thickness of the second silicon oxide layer is 10-200 nm.

[0062] In some preferred embodiments, in S3, the direct oxidation includes: introducing N2O to oxidize the shallow surface of the silicon wafer edge into a first silicon oxide layer.

[0063] Further preferred, the conditions for direct oxidation are: N2O flow rate 100-500 sccm, radio frequency power 1000-10000 W, pressure 10-200 Torr, temperature 300-500℃, and time 5-30 min.

[0064] In some preferred embodiments, in step S3, the indirect deposition includes: introducing SiH4 and N2O to deposit a second silicon oxide layer on the surface of the first oxide layer. More preferably, the conditions for the indirect deposition are: a SiH4 to N2O flow rate ratio of 1:5 to 1:10, a radio frequency power of 1000 to 10000 W, a pressure of 100 to 500 Torr, a temperature of 300 to 500 °C, and a time of 10 to 80 min. Step S4: Remove the silicon oxide layer from the back side of the silicon wafer.

[0065] In some preferred embodiments, a chain etching machine is used to remove the silicon oxide layer on the back of the silicon wafer, using a 20-60 wt% HF aqueous solution as the etching solution, with a belt speed of 1-10 m / min.

[0066] S5. A tunneling oxide layer and an intrinsic polycrystalline silicon layer are sequentially deposited on the back side of the silicon wafer.

[0067] In some preferred embodiments, a first tunneling oxide layer 3 is deposited on the back side of the silicon wafer using LPCVD in a single step. The O2 gas flow rate is 10,000–80,000 sccm, the reaction temperature is 400–800°C, the reaction time is 200–1000 s, and the thickness of the first tunneling oxide layer is 2–10 nm. Immediately following, a first intrinsic polysilicon layer 4 is deposited on the first tunneling oxide layer. The SiH4 gas flow rate is 300–2000 sccm, the reaction temperature is 500–700°C, the reaction time is 2–4 h, the working pressure is 100–500 mTorr, and the thickness of the first intrinsic polysilicon layer is 100–300 nm. Because tubular vacuum equipment inevitably produces a coating around the front / back surface and edge areas of the silicon wafer (i.e., the first tunneling oxide layer 3 and the first intrinsic polysilicon layer 4 located at the edge of the silicon wafer), the structural schematic diagram is shown below. Figure 3 As shown.

[0068] S6. Two-step source-source boron diffusion transforms the inner and outer layers of the first intrinsic polycrystalline silicon layer into boron diffusion layer 5 and BSG layer 6, respectively, while simultaneously densifying and boron-doping the insulating dielectric film. A schematic diagram of the silicon wafer structure is shown below. Figure 4 As shown.

[0069] In some preferred embodiments, the two-step boron diffusion conditions are as follows: first, a mixed gas of BCl3 and O2 is introduced at a temperature of 800–950°C for a diffusion time of 5–50 min, with a BCl3 flow rate of 50–500 sccm and an O2 flow rate of 500–2000 sccm; then, O2 is introduced for oxidation propagation at a temperature of 900–1050°C for a propagation time of 30–80 min, with an O2 flow rate of 5000–30000 sccm; finally, a mixed gas of BCl3 and O2 is introduced at a temperature of 800–950°C for a diffusion time of 2–30 min, with a BCl3 flow rate of 20–100 sccm and an O2 flow rate of 200–1000 sccm, resulting in a BSG layer with a thickness of 30–70 nm.

[0070] S7. Laser-guided patterning removes the BSG layer from the phosphorus diffusion and isolation zones in a single process.

[0071] In some preferred implementations, a picosecond laser is used to perform a patterned grooving BSG layer. The laser wavelength is 200–600 nm, the frequency is 400–800 kHz, the marking speed is 40,000–60,000 mm / s, the power is 10–50 W, and the processing time is 1–20 s.

[0072] S8. Alkaline Cleaning. During alkaline cleaning, the BSG layer on the surface of the S7 trench area is removed, thus the various deposited layers at the bottom are etched away by the alkaline solution, exposing the silicon wafer substrate. In contrast, the non-trenched areas are protected by the BSG layer 6, allowing the bottom deposited layers to remain. A schematic diagram of the silicon wafer structure is shown below. Figure 5 As shown.

[0073] In some preferred embodiments, the silicon wafer after laser patterning and grooving is placed in an alkaline solution for cleaning. The alkaline concentration is 1.5–2.5 wt%, the temperature is 70–85 °C, the time is 100–400 s, and the etching depth is 1–5 μm.

[0074] S9, backside secondary deposition of tunneling oxide layer and intrinsic polycrystalline silicon layer.

[0075] In some preferred embodiments, a second tunneling oxide layer 7 is grown a second time on the back surface of the silicon wafer using LPCVD. The O2 gas flow rate is 10,000–80,000 sccm, the temperature is 400–800°C, and the time is 200–1000 s. The thickness of the grown second tunneling oxide layer is 2–10 nm. Then, a second intrinsic polycrystalline silicon layer 8 is grown on top of the second tunneling oxide layer. The SiH4 gas flow rate is 300–2000 sccm, the reaction temperature is 500–700°C, the time is 2–4 h, the working pressure is 100–500 mTorr, and the thickness of the second intrinsic polycrystalline silicon layer is 100–300 nm. Because tubular vacuum equipment inevitably produces a coating around the front / back surface and edge areas of the silicon wafer, a schematic diagram is shown below. Figure 6 As shown.

[0076] S10, phosphorus diffusion, transforms the inner and outer layers of the second intrinsic polycrystalline silicon layer into a phosphorus diffusion layer 9 and a PSG layer 10, respectively. A schematic diagram of the silicon wafer structure is shown below. Figure 7 As shown.

[0077] In some preferred embodiments, the phosphorus diffusion conditions are as follows: phosphorus diffusion temperature 750–850℃, diffusion time 5–30 min, POCl3 carried by nitrogen at a flow rate of 500–1200 sccm, O2 flow rate of 500–1000 sccm, oxidation propulsion temperature 850–950℃, O2 flow rate of 1000–10000 sccm, propulsion time of 20–60 min, and PSG layer thickness of 30–70 nm.

[0078] S11. The PSG layer in the boron diffusion zone and isolation zone design area is removed by laser secondary patterning on the back side.

[0079] In some preferred implementations, the conditions for laser secondary patterning grooving are: laser wavelength of 200–600 nm, frequency of 400–800 kHz, marking speed of 40,000–60,000 mm / s, power of 10–50 W, and processing time of 1–20 s.

[0080] S12. Removal of the coating: The silicon wafer is acid-polished using a chain machine to remove the coating from the front and edges. However, due to the difficulty in maintaining a consistently horizontal roller on the chain machine over long-term use, the silicon wafer vibrates up and down during acid polishing. While the coating on the front can be largely removed, it cannot effectively remove all the coating from the edges. Therefore, some coating remains at the edges of the cell, such as... Figure 8 As shown.

[0081] In some preferred embodiments, the chain machine acid polishing process conditions are as follows: the volume ratio of hydrofluoric acid solution to nitric acid solution in the acid tank is 1:1 to 1:10 (the concentration of hydrofluoric acid solution is 49wt%, and the concentration of nitric acid solution is 69wt%), and the belt speed is 1 to 10 m / min.

[0082] S13. Cleaning and Texturing: The silicon wafers with the removed coating are placed in an alkaline texturing tank for integrated wet cleaning and texturing. Since the front side of the wafer has no oxide areas after the coating has been removed, a pyramidal texture 11 can be formed during the texturing process (a pyramidal texture will also be formed on the edges of the wafer where the coating has been completely removed). For the phosphorus diffusion layer on the back side of the wafer, its bottom deposition layer is preserved due to the PSG layer's protection. For the isolation area on the back side of the wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, leaving the wafer substrate unprotected, forming an isolation area and generating a pyramidal texture 11. For the boron diffusion layer, since its surface PSG layer has also been removed, its bottom phosphorus diffusion layer and tunneling oxide layer will be corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer will block the alkaline solution from eroding, protecting its bottom deposition layer. Subsequently, the texturing tank is equipped with an acid (HF / HCl) cleaning tank to further remove the remaining PSG and BSG layers on the back side of the wafer. A schematic diagram of the silicon wafer structure is shown below. Figure 9 As shown.

[0083] In some preferred embodiments, the KOH solution concentration in the alkaline texturing tank is 1.5–2.2 wt%, the temperature is maintained at 75–85 °C, the time is 6–12 min, and the weight loss is 0.30–0.50 g.

[0084] S14. Double-sided coating to form a passivation and antireflection layer 12 on the front and back sides of the silicon wafer.

[0085] In some preferred embodiments, AlO is deposited on both sides of the processed silicon wafer using ALD deposition. x The first layer, formed by the reaction of Al(CH3)3 with water vapor, has a thickness of 5–10 nm and is processed at a temperature of 200–300 °C. Subsequently, SiN is deposited on both sides of the silicon wafer using a tubular PECVD system. x The layer has a thickness of 80–120 nm and a refractive index of 1.9–2.2. The reaction gases in the tubular cavity are SiH4 and NH3. The working pressure is 1000–2000 mTorr, the power is 10000–20000 W, the temperature is 400–600 °C, the SiH4 gas flow rate is 500–2000 sccm, the NH3 gas flow rate is 5000–10000 sccm, and the deposition time is 5–20 min.

[0086] S15, screen printing, sintering, light injection, to obtain TBC solar cells with edge-wrap coating.

[0087] In some preferred embodiments, the coated silicon wafer is screen-printed onto the back to form metal contacts, which are then sintered at 700–800°C to form Ag-Si ohmic contacts (i.e., electrode layer 13). Finally, the finished TBC solar cell is obtained through light injection repair, as shown in the schematic diagram below. Figure 10 As shown.

[0088] Specific embodiments and comparative examples.

[0089] Example 1 A method for fabricating a TBC solar cell with an edge-wrap coating specifically includes the following steps: S1. Immerse the diamond wire-cut N-type single-crystal silicon wafer 1 in an alkaline polishing bath containing alkaline solution, and polish both sides at 75°C for 6 minutes, achieving a polishing thickness of 4μm and a thinning amount of 0.42g. Figure 1 As shown.

[0090] S2. Stack the silicon wafers in layers of 200 wafers to form a cubic silicon wafer assembly. After stacking, the front and back sides of adjacent silicon wafers are in contact, and the four edges are flush with the sides facing upwards, in preparation for the subsequent deposition of insulating layers on the four edges of the silicon wafers.

[0091] S3. With the sides of the stacked silicon wafers facing upwards, the PECVD process is used. Specifically, the first silicon oxide layer and the second silicon oxide layer are formed sequentially at the four edges of the silicon wafer assembly through direct oxidation and indirect deposition. The two layers combine to form the insulating dielectric film 2, as shown in the schematic diagram. Figure 2 As shown. The conditions for direct oxidation were: N₂O flow rate 300 sccm, RF power 3000 W, pressure 120 Torr, temperature 450℃, time 20 min, resulting in a first silicon oxide layer thickness of approximately 12 nm. The conditions for indirect deposition were: SiH₄ to N₂O flow rate ratio 1:7, RF power 7800 W, pressure 230 Torr, temperature 470℃, time 50 min, resulting in a second silicon oxide layer thickness of approximately 180 nm.

[0092] S4. The silicon oxide layer on the back of the silicon wafer is removed by acid etching using a chain machine with a 40wt% HF aqueous solution as the etching solution and a belt speed of 1.6m / min.

[0093] S5. A first tunneling oxide layer 3 is deposited on the back side of the silicon wafer using LPCVD in a single step. The O2 gas flow rate is 40000 sccm, the reaction temperature is 600℃, and the reaction time is 600s. The thickness of the first tunneling oxide layer is approximately 3nm. Immediately afterwards, a first intrinsic polysilicon layer 4 is deposited on the first tunneling oxide layer. The SiH4 gas flow rate is 920 sccm, the reaction temperature is 550℃, the reaction time is 3.3h, and the working pressure is 300mTorr. The thickness of the first intrinsic polysilicon layer is approximately 290nm. Due to the use of tubular vacuum equipment, it is unavoidable to generate a coating around the front / back surface and edge areas of the silicon wafer (i.e., the first tunneling oxide layer 3 and the first intrinsic polysilicon layer 4 located at the edge of the silicon wafer). A schematic diagram of this structure is shown below. Figure 3 As shown.

[0094] S6. Two-step source-source boron diffusion transforms the inner and outer layers of the first intrinsic polycrystalline silicon layer into boron-diffused layer 5 and BSG layer 6, respectively. Simultaneously, it densifies the insulating dielectric film and does boron doping. A schematic diagram of the silicon wafer structure is shown below. Figure 4 As shown. Specifically, the two-step boron diffusion conditions are as follows: First, a mixed gas of BCl3 and O2 is introduced at a temperature of 850℃ for a diffusion time of 10 min, with a BCl3 gas flow rate of 200 sccm and an O2 flow rate of 1200 sccm; then, O2 is introduced for oxidation propagation at a temperature of 950℃ for a propagation time of 30 min and an O2 flow rate of 7000 sccm; finally, a mixed gas of BCl3 and O2 is introduced at a temperature of 860℃ for a diffusion time of 25 min, with a BCl3 flow rate of 70 sccm and an O2 flow rate of 500 sccm, resulting in a BSG layer with a thickness of approximately 45 nm.

[0095] S7. The BSG layer in the phosphorus diffusion and isolation zones of the design area is removed by a single patterned grooving using a picosecond laser. The laser wavelength used is 532nm, the frequency is 600KHz, the marking speed is 45000mm / s, the power is 50W, and the processing time is 3s.

[0096] S8. The silicon wafer, after laser patterning and grooving, is placed in an alkaline solution for cleaning. The alkaline concentration is 2.0 wt%, and the temperature is 75°C. During the alkaline cleaning process, because the BSG layer on the surface of the grooved area in S7 is removed, the various deposited layers at the bottom are corroded and removed by the alkaline solution, exposing the silicon wafer substrate. The non-grooved areas, however, are protected by the BSG layer 6, thus preserving the bottom deposited layers. A schematic diagram of the silicon wafer structure is shown below. Figure 5 As shown.

[0097] S9. A second tunneling oxide layer 7 is grown on the back surface of the silicon wafer using LPCVD. The O2 gas flow rate is 30000 sccm, the temperature is 600℃, and the time is 450s. The thickness of the grown second tunneling oxide layer is approximately 2.5nm. Then, a second intrinsic polycrystalline silicon layer 8 is grown on top of the second tunneling oxide layer. The SiH4 gas flow rate is 920 sccm, the reaction temperature is 550℃, the time is 1.5h, and the working pressure is 300mTorr. The thickness of the second intrinsic polycrystalline silicon layer is approximately 180nm. Due to the use of tubular vacuum equipment, a coating layer inevitably forms on the front / back surface and edge areas of the silicon wafer. A schematic diagram of this structure is shown below. Figure 6 As shown.

[0098] S10, phosphorus diffusion, transforms the inner and outer layers of the second intrinsic polycrystalline silicon layer into a phosphorus diffusion layer 9 and a PSG layer 10, respectively. A schematic diagram of the silicon wafer structure is shown below. Figure 7 As shown. Specifically, the phosphorus diffusion conditions are: phosphorus diffusion temperature 790℃, diffusion time 15min, POCl3 carried by nitrogen at a flow rate of 1000sccm, O2 flow rate of 650sccm, oxidation propulsion temperature 890℃, O2 flow rate of 3000sccm, propulsion time 20min, and PSG layer thickness of approximately 39nm.

[0099] S11. The PSG layer in the boron diffusion region and isolation region of the silicon wafer is removed by secondary patterning and grooving on the back side using a picosecond laser. Specifically, the conditions for secondary patterning and grooving with the laser are: laser wavelength of 532nm, frequency of 600KHz, marking speed of 45000mm / s, power of 25W, and processing time of 2.7s.

[0100] S12. Removal of Coating Wrap: The silicon wafer is acid-polished using a chain machine to remove the coating wrapping layer from the front and edges. The chain machine acid polishing process conditions are: a volume ratio of hydrofluoric acid solution to nitric acid solution in the acid bath of 1:4 (hydrofluoric acid solution concentration of 49wt%, nitric acid solution concentration of 69wt%), and a belt speed of 1.3m / min. However, due to the difficulty in maintaining a consistently horizontal roller on the chain machine during long-term use, the silicon wafer vibrates up and down during the acid polishing process. While the coating wrapping layer on the front can be largely removed, it cannot effectively remove all the coating wrapping layer from the edges of the silicon wafer. Therefore, some coating wrapping areas remain at the edges of the cell, such as... Figure 8 As shown.

[0101] S13. Cleaning and Texturing: The silicon wafers with the removed coating are placed in an alkaline texturing bath for integrated wet cleaning and texturing. The KOH solution concentration in the alkaline texturing bath is 1.7 wt%, the temperature is maintained at 82℃, and the time is 7 minutes. Since the front side of the silicon wafer has no oxide areas after the coating is removed, a pyramidal textured surface 11 can be formed during the texturing process (a pyramidal textured surface will also be formed on the edge of the silicon wafer where the coating is completely removed). For the phosphorus diffusion layer on the back side of the silicon wafer, its bottom deposition layer is preserved because the surface is protected by the PSG layer. For the isolation area on the back side of the silicon wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, causing the silicon substrate to lose protection, forming an isolation area and generating a pyramidal textured surface 11. For the boron diffusion layer, since its surface PSG layer has also been removed, its bottom phosphorus diffusion layer and tunneling oxide layer will be corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer will block the alkaline solution from eroding and protect its bottom deposition layer. The texturing tank then includes an acid (HF / HCl) cleaning tank to further remove any remaining PSG and BSG layers from the back of the silicon wafer. A schematic diagram of the silicon wafer structure is shown below. Figure 9 As shown.

[0102] S14. A passivation and antireflection layer 12 is deposited on both sides of the processed silicon wafer using ALD deposition. This passivation and antireflection layer includes AlO₂. x Layers and SiN x Layer. Among them, AlO x The layer, approximately 8 nm thick, was formed by the reaction of Al(CH3)3 with water vapor, and the process temperature was 250°C. Subsequently, SiN was deposited on both sides of the silicon wafer using a tubular PECVD system. x The layer has a thickness of approximately 82 nm and a refractive index of approximately 2.0. The reaction gases inside the tubular cavity are SiH4 and NH3. The working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, and the deposition time is 10 min.

[0103] S15. The coated silicon wafer is screen-printed onto the back to form metal contacts, and then sintered at 770℃ to form Ag-Si ohmic contacts (i.e., electrode layer 13). Finally, light injection is used to repair the coating to obtain a TBC solar cell with wires around the edge of the coating. Its structural schematic diagram is shown below. Figure 10 As shown.

[0104] Example 2 The difference between Example 2 and Example 1 lies in S4 (the rest of the steps are the same), where laser treatment combined with alkaline cleaning is used to remove the oxide layer coated on the back of the silicon wafer. Specific conditions are as follows: S4. The oxide layer on the back of the silicon wafer is treated by laser grooving. The laser conditions are as follows: picosecond laser, laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 50W, and processing time 3s. The treated silicon wafer is then subjected to alkaline cleaning to remove the silicon oxide layer on the back. The alkaline cleaning conditions are: alkaline concentration 2.0wt%, temperature 75℃.

[0105] Comparative Example 1 The main difference between Comparative Example 1 and Example 1 is that an insulating dielectric film was not pre-constructed at the edge of the silicon wafer, i.e., S2-S4 are not included.

[0106] S1. Immerse the diamond wire-cut N-type single crystal silicon wafer in an alkaline polishing bath containing alkaline solution, and polish both sides at 75°C for 6 minutes. The polishing thickness is 4μm, and the thinning amount is 0.42g.

[0107] S2. A first tunneling oxide layer is deposited on the back side of the silicon wafer using LPCVD in a single step. The O2 gas flow rate is 40,000 sccm, the reaction temperature is 600℃, and the reaction time is 600 s. The thickness of the first tunneling oxide layer is approximately 3 nm. Immediately afterwards, a first intrinsic polysilicon layer is deposited on the first tunneling oxide layer. The SiH4 gas flow rate is 920 sccm, the reaction temperature is 550℃, the reaction time is 3.3 h, and the working pressure is 300 mTorr. The thickness of the first intrinsic polysilicon layer is approximately 290 nm.

[0108] S3. Boron diffusion transforms the inner and outer layers of the first intrinsic polycrystalline silicon layer into a boron-diffused layer and a BSG layer, respectively. Specifically, the boron diffusion conditions are as follows: first, a mixed gas of BCl3 and O2 is introduced at a temperature of 850°C for 10 min, with a BCl3 gas flow rate of 200 sccm and an O2 flow rate of 1200 sccm; then, O2 is introduced for oxidation propagation at a temperature of 950°C for 30 min, with an O2 flow rate of 7000 sccm, resulting in a BSG layer approximately 45 nm thick.

[0109] S4. The BSG layer in the phosphorus diffusion and isolation zones of the design area is removed by a single patterned grooving process using a picosecond laser. The laser wavelength used is 532nm, the frequency is 600KHz, the marking speed is 45000mm / s, the power is 50W, and the processing time is 3s.

[0110] S5. The silicon wafer, after laser patterning and grooving, is placed in an alkaline solution for cleaning. The alkaline concentration is 2.0 wt%, and the temperature is 75°C. During the alkaline cleaning process, since the BSG layer on the surface of the grooved area in S4 is removed, the deposited layers at the bottom will be corroded and removed by the alkaline solution, exposing the silicon wafer substrate. In contrast, the bottom deposited layers in the non-grooved area are preserved because the surface is protected by the BSG layer.

[0111] S6. A second tunneling oxide layer is grown on the back surface of the silicon wafer using LPCVD. The O2 gas flow rate is 30000 sccm, the temperature is 600℃, and the time is 450s. The thickness of the grown second tunneling oxide layer is approximately 2.5nm. Then, a second intrinsic polycrystalline silicon layer is grown on the basis of the second tunneling oxide layer. The SiH4 gas flow rate is 920 sccm, the reaction temperature is 550℃, the time is 1.5h, and the working pressure is 300mTorr. The thickness of the second intrinsic polycrystalline silicon layer is approximately 180nm.

[0112] S7. Phosphorus diffusion transforms the inner and outer layers of the second intrinsic polycrystalline silicon layer into a phosphorus diffusion layer and a PSG layer, respectively. Specifically, the phosphorus diffusion conditions are: phosphorus diffusion temperature 790℃, diffusion time 15 min, POCl3 carried by nitrogen at a flow rate of 1000 sccm, O2 flow rate of 650 sccm, oxidation propulsion temperature 890℃, O2 flow rate of 3000 sccm, propulsion time 20 min, and PSG layer thickness approximately 39 nm.

[0113] S8. The PSG layer in the boron diffusion region and isolation region of the silicon wafer is removed by secondary patterning and grooving on the back side using a picosecond laser. Specifically, the conditions for secondary patterning and grooving with the laser are: laser wavelength of 532nm, frequency of 600KHz, marking speed of 45000mm / s, power of 25W, and processing time of 2.7s.

[0114] S9. Removal of Wrap-on Plating: The silicon wafer is acid-polished using a chain machine to remove the wrap-on plating layer from the front and edges of the wafer. The chain machine acid-polishing process conditions are as follows: the volume ratio of hydrofluoric acid solution to nitric acid solution in the acid bath is 1:4 (hydrofluoric acid solution concentration is 49wt%, nitric acid solution concentration is 69wt%), and the belt speed is 1.3m / min.

[0115] S10. Cleaning and Texturing: The silicon wafers with the removed coating are placed in an alkaline texturing bath for integrated wet cleaning and texturing. The KOH solution concentration in the alkaline texturing bath is 1.7 wt%, the temperature is maintained at 82℃, and the time is 7 minutes. Since the front side of the silicon wafer has no oxide areas after the coating is removed, a pyramidal textured surface can be formed during the texturing process. For the phosphorus diffusion layer on the back side of the silicon wafer, the bottom deposition layer is preserved due to the protection of the PSG layer. For the isolation area on the back side of the silicon wafer, since the surface PSG layer has been removed, the alkaline solution can effectively corrode the bottom deposition layer, leaving the silicon substrate unprotected, forming an isolation area and generating a pyramidal textured surface. For the boron diffusion layer, since its surface PSG layer has also been removed, the bottom phosphorus diffusion layer and tunneling oxide layer are corroded and removed by the alkaline solution until the bottom BSG layer is exposed. The BSG layer blocks the alkaline solution from eroding, protecting the bottom deposition layer. Subsequently, the texturing bath is equipped with an acid (HF / HCl) cleaning tank to further remove the remaining PSG and BSG layers on the back side of the silicon wafer.

[0116] S11. A passivation and antireflection layer is deposited on both sides of the processed silicon wafer using the ALD deposition method. This passivation and antireflection layer includes AlO₂. x Layers and SiN x Layer. Among them, AlO x The layer, approximately 8 nm thick, was formed by the reaction of Al(CH3)3 with water vapor, and the process temperature was 250°C. Subsequently, SiN was deposited on both sides of the silicon wafer using a tubular PECVD system. x The layer has a thickness of approximately 82 nm and a refractive index of approximately 2.0. The reaction gases inside the tubular cavity are SiH4 and NH3. The working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, and the deposition time is 10 min.

[0117] S12. The coated silicon wafer is screen-printed onto the back to form metal contacts, and then sintered at 770℃ to form Ag-Si ohmic contacts. Finally, TBC solar cells are obtained by light injection repair.

[0118] Comparative Example 2 The main difference between Comparative Example 2 and Example 1 is that only the first silicon oxide layer is formed in S3, that is, the second silicon oxide layer is not indirectly deposited. The specific conditions are as follows: S3, the silicon wafers stacked in a "layered" manner are placed with the sides facing up, and an insulating dielectric film is oxidized on the side of the silicon wafer using the PECVD process. The conditions for direct oxidation are: N2O flow rate 300 sccm, RF power 3000 W, pressure 120 Torr, temperature 450°C, time 20 min, and the thickness of the first silicon oxide layer is about 12 nm.

[0119] Comparative Example 3 The main difference between Comparative Example 3 and Example 1 is that no additional source was used during the boron diffusion process in S6. The specific conditions are as follows: S3. Boron diffusion transforms the inner and outer layers of the first intrinsic polycrystalline silicon layer into a boron-diffused layer and a BSG layer, respectively. Specifically, the boron diffusion conditions are as follows: first, a mixed gas of BCl3 and O2 is introduced at a temperature of 850°C for 10 min, with a BCl3 gas flow rate of 200 sccm and an O2 flow rate of 1200 sccm; then, O2 is introduced for oxidation propagation at a temperature of 950°C for 30 min, with an O2 flow rate of 7000 sccm, resulting in a BSG layer approximately 45 nm thick.

[0120] Performance testing The electrical performance of the solar cells prepared in the above embodiments and comparative examples was tested, and the data are shown in the table below: Serial Number η(%) <![CDATA[V oc (mv)]]> <![CDATA[J sc (mA / cm 2 )]]> FF (%) Irev(A) Dielectric constant of silicon oxide Example 1 26.79 745.6 42.57 84.40 0.15 4.37 Example 2 26.75 745.1 42.54 84.39 O.16 4.35 Comparative Example 1 26.37 743.2 42.34 83.80 0.79 / Comparative Example 2 26.53 744.0 42.41 84.08 0.47 3.98 Comparative Example 3 26.68 744.7 42.50 84.30 0.22 4.21 The data comparison in the table above shows that: First, in Example 1, since a high dielectric constant insulating dielectric film is pre-deposited on the edge of the silicon wafer, the overall leakage current of the battery is low. At the same time, some edge positions are further passivated by the insulating dielectric film, resulting in better electrical performance of the battery and thus the best overall electrical performance.

[0121] Secondly, in Example 2, a laser method was used to remove the oxide layer around the back of the silicon wafer, and then alkaline cleaning was used to obtain a relatively flat surface without the oxide layer. Compared with Example 1, the use of a laser method will cause damage to the silicon substrate, so the overall performance is slightly lower than that of Example 1.

[0122] For Comparative Example 1, the side coating cannot be effectively removed during the battery manufacturing process (especially during the decoating process on the front / side sides), resulting in significant edge leakage and the worst overall electrical performance.

[0123] For Comparative Example 2, since only the "direct oxidation" method was used to form the first silicon oxide layer at the edge of the silicon wafer, the insulating dielectric film was thinner and had a lower dielectric constant. It could not effectively block the entry of doped atoms during the subsequent high-temperature diffusion process, which increased the risk of battery leakage and limited the overall performance improvement of the battery, but it was higher than that of Comparative Example 1.

[0124] For Comparative Example 3, the low concentration of boron atoms introduced into the edge insulating dielectric film during the conventional one-step source-through boron diffusion process limits the improvement of the dielectric constant of the insulating dielectric film. Compared with Examples 1-2, the overall electrical performance is lower, but still better than Comparative Examples 1-2.

[0125] Unless otherwise specified, the raw materials and equipment used in this invention are all commonly used in the field; unless otherwise specified, the methods used in this invention are all conventional methods in the field.

[0126] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, alterations, and equivalent transformations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: The edges of the solar cells have a pyramidal velvet surface, while some are polished.

2. The solar cell according to claim 1, characterized in that: The solar cell is a back-contact cell.

3. The solar cell according to claim 2, characterized in that: The solar cell is a TBC solar cell.

4. The solar cell according to claim 1, characterized in that: The isolation area on the back of the solar cell has a pyramidal textured surface.

5. The solar cell according to claim 1, characterized in that: A passivation and antireflection layer is formed on the front and / or back of the solar cell.

6. The solar cell according to claim 1, characterized in that: A coating is formed around the edge region of the solar cell.

7. The solar cell according to claim 1, characterized in that: The back of the solar cell is sequentially deposited with a tunneling oxide layer and an intrinsic polycrystalline silicon layer.

8. The solar cell according to claim 7, characterized in that: The solar cell is screen-printed onto the back side to form a metal contact.

9. The solar cell according to claim 8, characterized in that: The metal contacts of the solar cell are sintered at 700~800°C to form Ag-Si ohmic contacts.

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