Structures and techniques for optically defined semiconductor elements with selective dielectric constant reduction

Abstract

A semiconductor element may include a substrate. The semiconductor element may also include a dielectric material at least partially characterized by a dielectric constant. The semiconductor element may include a metal path formed in the dielectric material. The semiconductor element may include a region around the metal path of the semiconductor element, the region may include a plurality of air gaps within the dielectric material, and the air gaps are arranged in three dimensions throughout the region, where the region may include a dielectric constant that is lower than the dielectric constant of the dielectric material.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Non-Provisional Application No. 18 / 482,544, filed on October 6, 2023, entitled “STRUCTURE AND TECHNIQUE OF PHOTO-DEFINED SEMICONDUCTOR DEVICE WITH SELECTIVE DIELECTRIC CONSTANTREDUCTION”, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to lithographic printing systems. More specifically, this disclosure relates to forming semiconductor elements with different dielectric constants. Background Technology

[0004] As the spacing between structures on a semiconductor device decreases, interference between structures may increase. For example, to increase the input / output (I / O) count on a semiconductor device, vias (or paths, lines, etc.) may be reduced in size. As vias shrink, their capacitance increases. Furthermore, the resistance may increase due to the reduced physical size of the vias. This increase in resistance and capacitance (RC) values ​​can degrade the performance of the vias. In some semiconductor devices where temperature is not a manufacturing limiting factor, the materials used in the manufacturing process can be varied to change the dielectric constant and overcome the increase in RC values. However, in temperature-sensitive devices, additional techniques and systems may be required. Summary of the Invention

[0005] A method for constructing a redistribution layer of a semiconductor element may include identifying, via a computing device, three-dimensional regions in the semiconductor element where paths can be formed. The material used to fabricate the semiconductor element may include a dielectric constant, and desired signal integrity along the paths may require a lower dielectric constant. The method may include generating a deposition plan by the computing device, the deposition plan characterized by air gaps formed in the three-dimensional regions in the semiconductor element where paths can be formed. The method may include determining, by the computing device, that the deposition plan at least satisfies mechanical characteristic constraints associated with the three-dimensional regions of the semiconductor element. In response to determining that the deposition plan at least satisfies the mechanical characteristic constraints associated with the three-dimensional regions of the semiconductor element, the method may also include providing the deposition plan to a semiconductor processing system by the computing device, such that the semiconductor processing system executes the deposition plan and forms a semiconductor element, the semiconductor element including paths through the three-dimensional regions characterized by a lower dielectric constant, thereby achieving desired signal integrity.

[0006] In some embodiments, the semiconductor processing system is configured to produce semiconductor devices using two-photon lithography. In some embodiments, the semiconductor device may include an advanced packaged device. This path may be formed using a copper damascene process. The air gaps and material of the three-dimensional region may be formed into a lattice pattern characterized by at least one of cubic air gaps, hexagonal prism air gaps, and pyramidal air gaps. The mechanical properties of the three-dimensional region may be determined at least in part by the mechanical strength required by the three-dimensional region. The mechanical properties of the three-dimensional region may include the heat resistance of the three-dimensional region. The three-dimensional region may be identified at least in part by determining the characteristics of a second semiconductor device to be formed above the three-dimensional region and the characteristics of a third semiconductor device to be formed below the three-dimensional region. The deposition schedule may be generated in part by calculating the total capacitance of the three-dimensional region, which may include air gaps.

[0007] A system may include a semiconductor processing chamber configured to receive a substrate. The system may include a stencil printing tool configured to perform two-photon stencil printing. The system may include a computing device, and may also include one or more processors and a non-transitory computer-readable medium including instructions. When executed by one or more processors, the computing device performs operations. According to these operations, the computing system may identify a three-dimensional region in a semiconductor element where a path can be formed, wherein the material used to manufacture the semiconductor element comprises a dielectric constant, and a lower dielectric constant is required for desired signal integrity along the path. The computing system may generate a deposition plan characterized by an air gap formed in the three-dimensional region in the semiconductor element where the path can be formed. The computing system may determine that the deposition plan at least satisfies mechanical characteristic constraints associated with the three-dimensional region of the semiconductor element. In response to determining that the deposition plan at least satisfies the mechanical characteristic constraints associated with the three-dimensional region of the semiconductor element, the computing system may provide the deposition plan to a semiconductor processing system, such that the semiconductor processing system executes the deposition plan and forms a semiconductor element, which may include a path through the three-dimensional region characterized by a lower dielectric constant, thereby achieving desired signal integrity.

[0008] In some implementations, a deposition schedule may be generated using at least part of chip-package interactive analysis. Identifying the three-dimensional region may include context-aware analysis, wherein system requirements, including multiple structures on the semiconductor element, are used to identify the three-dimensional region. Context-aware analysis may include determining the characteristics of a second semiconductor element to be formed above the three-dimensional region and determining the characteristics of a third semiconductor element to be formed below the three-dimensional region. The air gaps of the three-dimensional region and the material of the region may form a lattice pattern, characterized by at least one of cubic air gaps, hexagonal prism air gaps, and pyramidal air gaps.

[0009] A semiconductor device may include a substrate. The semiconductor device may also include at least a portion of a dielectric material characterized by a dielectric constant. The semiconductor device may include metal pathways formed in the dielectric. The semiconductor device may include a region surrounding the metal pathways of the semiconductor device, the region including a plurality of air gaps within the dielectric material, and the air gaps being arranged three-dimensionally throughout the region, wherein the region may include a dielectric constant lower than that of the dielectric material.

[0010] In some embodiments, adjacent regions of the semiconductor element may be characterized by the absence of air gaps. The location of the metal path may be determined based on length matching requirements associated with the corresponding metal path. A second plurality of air gaps may be configured such that the dielectric constant of the second region alters the signal integrity of the second metal path, corresponding to the signal integrity of the metal path. The semiconductor element may include a redistribution layer. Each of the plurality of air gaps may include a size ranging from 100 nanometers to 1 micrometer, encompassing both 100 nanometers and 1 micrometer. Attached Figure Description

[0011] The nature and advantages of various embodiments can be further understood by referring to the remainder of the specification and the accompanying drawings, in which the same reference numerals are used to indicate similar parts. In some cases, sub-labels are associated with reference numerals to identify one of a plurality of similar parts. When reference numerals are used without specifying existing sub-labels, it is intended to refer to all such plurality of similar parts.

[0012] Figure 1 This is a perspective view of a flatbed printing system according to some embodiments.

[0013] Figure 2 A cross-sectional view of the package according to some embodiments is shown.

[0014] Figure 3 A semiconductor device having a modified region is shown according to certain embodiments.

[0015] Figure 4 A semiconductor device having a modified region is shown according to certain embodiments.

[0016] Figures 5A to 5D A process flow for manufacturing semiconductor devices with selectively reduced dielectric constants, according to certain embodiments, is shown.

[0017] Figure 6 A method for selectively reducing the dielectric constant of a semiconductor element according to certain embodiments is shown.

[0018] Figure 7 An exemplary computer system is shown, in which various implementation methods can be carried out. Detailed Implementation

[0019] A package may include two or more semiconductor elements constructed or assembled together. A redistribution layer (RDL) connects the packaged semiconductor elements by providing connections or vias between the various structures of each semiconductor element. As semiconductor manufacturing technology improves, the size of structures within semiconductor elements tends to decrease. The spacing between structures also tends to decrease. RDLs are no exception; as more semiconductor elements are included on each layer of the package, the number of vias on the RDL increases. However, the physical space within the RDL is finite, so the via spacing within the RDL may decrease. As the spacing decreases, the tunability of the various materials within the semiconductor becomes impractical, making it impossible to modify the material at the scale necessary for smaller spacing.

[0020] For example, a first signal may be transmitted along with a second signal through two different vias, where the second signal is out of phase with the first signal (e.g., 180° out of phase or opposite). To read the data included in the first and second signals, the device may need to receive both signals simultaneously. While one via (e.g., the first via) may be straight through, the other via may require routing along a longer path. Because the two vias are of different lengths, the time-of-flight (TOF) of the two signals may differ. If the TOF of the two signals varies too much, the receiving device may misinterpret the data included in both signals. To balance the TOF of the two signals, the path of the first via can be lengthened to ensure that both signals arrive at the device simultaneously. However, as vias and other structures in the RDL become increasingly congested, such routing can become overly complex in design and manufacturing.

[0021] One solution is to manipulate the characteristics of a via to electrically short-circuit a second via, matching its TOF to that of the first via. The “speed” of a signal transmitted through a via is partly controlled by the resistance and capacitance factors (RC factor) of the material through which the signal propagates. The RC factor is in turn partly controlled by the dielectric constant (k) of the material. One way to manipulate the RC factor along a via is to utilize different materials. For example, the via can travel through materials commonly used to manufacture semiconductor devices. This material may include polyimide, SiO2, SiN, SiCN, SiCOH, SiCO, and / or other suitable materials. This material is typically polymer-based, where variations in the polymer are used to increase or decrease the dielectric constant of the material. However, as multi-chip modules (e.g., packages) become larger, variations in the mechanical properties of the polymer may prevent the dielectric constant from decreasing sufficiently to achieve the desired performance.

[0022] Another solution is to modify the density of the material. For example, during the design phase of a semiconductor device, vias that require a lower RC factor than the material used to manufacture the semiconductor device can be identified. Subsequently, the region surrounding the via and the specific RC factor that would otherwise allow signals to pass through the via as desired (e.g., matching a TOF to a corresponding via used in differential signal transmission) can be identified. A deposition plan can then be generated for the semiconductor device, where the dielectric constant of the region is reduced by creating an air gap in the area surrounding the via. Because this region includes the air gap (and therefore less material), the material in this region may be weaker than in the unmodified region. The deposition plan can then be validated against the mechanical property limitations of the entire semiconductor device to ensure that the modified region does not cause mechanical failures in the semiconductor device. The semiconductor device can then be manufactured according to the deposition plan to include the via and the region with the air gap.

[0023] By altering the material density using an air gap, the effective dielectric constant of the material surrounding the via can be reduced. This, in turn, reduces the speed at which signals travel through the via. This region can be fabricated in three dimensions at a resolution of 100 nm to 500 nm (inclusive) using lithography techniques such as two-photon lithography. Due to this resolution, a selected region of the RDL immediately surrounding the via can be tuned, rather than the entire layer or a plane within the layer. Therefore, the performance of the via can be selectively tuned without affecting the performance of other regions within the RDL. The systems and methods described herein can provide selective dielectric constant reduction within semiconductor devices, thereby enabling improved semiconductor device performance.

[0024] Figure 1 This is a perspective view of a flatbed printing system 100 according to some embodiments. System 100 includes a base frame 110, a flatbed 120, a platform 130, and a processing device 160. System 100 can be configured to perform two-photon flatbed printing technology. The base frame 110 rests on the base plate of the manufacturing facility and supports the flatbed 120. A passive air isolator 112 is located between the base frame 110 and the flatbed 120. In some embodiments, the flatbed 120 is a single piece of granite, and the platform 130 is mounted on the flatbed 120. A substrate 140 is supported by the platform 130. A plurality of holes (not shown) are formed in the platform 130 to allow a plurality of lifting rods (not shown) to extend through these holes. In some embodiments, the lifting rods rise to an extended position to receive the substrate 140, such as from one or more transfer robots (not shown). One or more transfer robots are used to load and unload the substrate 140 from the platform 130.

[0025] The substrate 140 comprises any suitable material, such as quartz used for flat panel display components. In other embodiments, the substrate 140 is made of other materials. In some embodiments, the substrate 140 has a photoresist layer formed thereon. The photoresist is sensitive to radiation. Positive photoresist includes portions of the photoresist that, when exposed to radiation, are soluble in a photoresist developer applied to the photoresist after a pattern is written onto it. Negative photoresist includes portions of the photoresist that, when exposed to radiation, are insoluble in a photoresist developer applied to the photoresist after a pattern is written onto it. The chemical composition of the photoresist determines whether it is a positive or negative photoresist. Examples of photoresists include, but are not limited to, at least one of diazonaphthoquinone, phenolic resin, poly(methyl methacrylate), poly(methylglutarimide), and SU-8. In this manner, patterns are formed on the surface of the substrate 140 to form an electronic circuit system.

[0026] System 100 includes a pair of support members 122 and a pair of tracks 124. The pair of support members 122 are mounted on a plate 120, and the plate 120 and the pair of support members 122 are made of a single piece of material. The pair of tracks 124 are supported by the pair of support members 122, and a platform 130 moves along the tracks 124 in the X direction. In one embodiment, the pair of tracks 124 are a pair of parallel magnetic channels. As shown, each track 124 of the pair of tracks 124 is linear. In other embodiments, one or more tracks 124 are non-linear. An encoder 126 is coupled to the platform 130 to provide position information to a controller (not shown).

[0027] The processing apparatus 160 includes a support 162 and a processing unit 164. The support 162 is mounted on a flat plate 120 and includes an opening 166 for a platform 130 to pass through below the processing unit 164. The processing unit 164 is supported by the support 162. In some embodiments, the processing unit 164 is a pattern generator configured to expose photoresist in a photolithography process. In some embodiments, the pattern generator is configured to perform a maskless photolithography process. The processing unit 164 includes a plurality of image projection devices (such as...). Figure 2 (As shown). In some embodiments, processing unit 164 includes up to 84 image projection devices. Each image projection device is housed in housing 165. Processing device 160 can be used to perform maskless direct patterning.

[0028] During operation, platform 130 moved from the X direction... Figure 1The loading position shown moves to the processing position. The processing position is one or more positions of the platform 130 as it passes under the processing unit 164. During operation, the platform 130 is lifted by a plurality of air bearings (not shown) and moves along the pair of tracks 124 from the loading position to the processing position. A plurality of vertical guide air bearings (not shown) are coupled to the platform 130 and located near the inner wall 128 of each support 122 to stabilize the movement of the platform 130. The platform 130 also moves in the Y direction by moving along track 150 for processing and / or indexing the substrate 140. The platform 130 is capable of operating independently and can scan the substrate 140 in one direction and step in another.

[0029] The metrology system measures the X and Y lateral position coordinates of each platform 130 in real time, enabling each of the multiple image projection devices to accurately position the pattern being written into the photoresist-covered substrate. The metrology system also provides real-time measurement of the angular position of each platform 130 around the vertical or Z-axis. Angular position measurements can be used to maintain a constant angular position during scanning via a servo mechanism, or to apply correction to the position of the pattern written on the substrate 140 via the image projection devices.

[0030] Figure 2 A cross-sectional view of package 204-1 according to some embodiments is shown. The package can be formed on substrate 202, which may be alternatively referred to as a carrier when substrate 202 is divided into individual packages. Pillars 220 can be formed by standard semiconductor manufacturing processes. For example, a mask layer may be formed with gaps at the locations where pillars 220 will be positioned, and a metal layer may then be deposited into these gaps using a deposition process to form pillars 220. The mask layer may then be removed, exposing pillars 220. Because the manufacturing process of pillars 220 can use very precise existing deposition and etching processes, the position of pillars 220 can generally be considered correctly positioned. Therefore, as described above, in some embodiments, pillars 220 may be used as alignment features of package 204-1.

[0031] Unlike pillars 220, which are typically fabricated directly on substrate 202, die 222 is not usually fabricated directly on substrate 202. Instead, die 222 is fabricated using other semiconductor processes and subsequently adhered to substrate 202. For example, some embodiments may first deposit a layer of epoxy resin or other adhesive on substrate 202, and die 222 may be placed in a predetermined position within the epoxy resin based on the design of package 204-1. Unlike the very precise placement of pillars 220 using deposition and etching processes in a semiconductor manufacturing chamber, the final physical placement position of die 222 can vary considerably after epoxy resin curing. For example, a pick-and-place machine can place die 222 in a position on package 204-1. However, machine and substrate 202 tolerances can introduce errors in the physical placement position of die 222. Even if die 222 is placed precisely in the correct position on package 204-1, the relatively high viscosity of epoxy resin may allow die 222 to move after placement.

[0032] The difference between the intended design location of die 222 and its actual physical location after physical placement during manufacturing can negatively impact the accuracy of interconnects on package 2041. For example, some embodiments may use a conformal coating or epoxy resin to fill any voids on package 204-1 to protect individual components. This coating may be polished to expose the surface of pillar 220, input / output (I / O) pads on die 222, and / or any other connection surfaces that form part of package 204-1. In some embodiments, substrate 202 may be placed in digital lithography system 100, and the aforementioned digital lithography technology may be used to deposit metal traces 230 and other features on the surface of package 204-1 to form interconnects. If die 222 is not in the intended location, this highly precise wiring of traces 230 formed by digital lithography may miss the intended I / O pads on die 222, potentially rendering package 204-1 inoperable and reducing the effective yield of the semiconductor process.

[0033] Figure 3 A semiconductor element 300 having a modified region 308 according to certain embodiments is shown. The semiconductor element 300 may at least partially utilize a digital lithography system (such as...) Figure 1 The semiconductor device 300 is manufactured using two-photon flatbed printing performed by system 100. Figure 2Some or all of the packages 204-1 are included. Semiconductor element 300 may include chip 302, vias 304a to e, unmodified regions 306 and 307, and modified region 308. Vias 304a to e may include metal paths connecting chip 302 to one or more other structures. Other structures may include pillars, I / O pads, or any other such structures. Unmodified regions 306 to 307 and modified region 308 may include negative-tone photosensitive polyimide (n-PSPI), as described above for... Figure 1 As stated above.

[0034] Furthermore, the modified region 308 and / or the unmodified regions 306 and 307 can be three-dimensional regions. For example, the modified region 308 can extend along the length of the through-hole 304c and extend horizontally a certain distance from the side of the through-hole 304c (e.g., Figure 3 As shown). Considering system 300 above and below (e.g., including in systems such as... Figure 2 In accordance with the requirements of the device in package 204-1, the modified region 308 may also extend above and below the via 304c (e.g., extending inside or outside the page, such as...). Figure 3 (As shown).

[0035] As part of the design process for semiconductor device 300, via 304c can be identified as a via that requires a lower dielectric constant than other vias 304a to b and 304d to e. For example, via 304c can be used in conjunction with certain other vias to provide differential signal transmission from chip 302 to another chip or device. To match the TOF of via 304c with that of another via, the dielectric constant is first determined such that the TOF of via 304c matches that of the other via. Based at least in part on the dielectric constant, the material density in the modified region 308 can be determined such that the material in the modified region includes the dielectric constant. Subsequently, the number of air gaps can be determined based on the density.

[0036] After identifying the air gap included in the modified region 308, the design of the semiconductor device 300 can be verified against the mechanical property limitations of the semiconductor device 300. For example, the modified region 308 may have lower mechanical property limitations (e.g., mechanical strength and / or thermal limit), indicating that the modified region 308 may not be a critical structural region of the semiconductor device 300. In other words, the modified region 308 may be structurally weaker than the unmodified regions 306 and 307 without compromising the structural integrity of the semiconductor device 300. In other instances, the modified region 308 may be identified as having significant structural importance. Subsequently, a new path for at least the via 304c can be identified, and a new region around the via 304c can be identified, where the dielectric constant can be reduced.

[0037] The requirements for other vias 304a to b and 304d to e may differ from those for via 304c. In some embodiments, the other vias 304a to b and 304d to e may be implemented in an acceptable manner without modifying the material within unmodified regions 306 and 307. In other embodiments, unmodified regions 306 and 307 may also include air gaps, thereby altering the dielectric constant of unmodified regions 306 and 307. Unmodified regions 306 and 307 may include the same dielectric constant or different dielectric constants.

[0038] The design process can be iterated continuously until all vias and corresponding regions with reduced dielectric constants are identified and the mechanical limitations of semiconductor element 300 are verified. Furthermore, considering the dielectric constants required by other structures surrounding the modified region 308, the design process can be "context-aware," for example, a second semiconductor element can be placed on top of semiconductor element 300 (for...). Figure 3 (Outside the page). The region of the second semiconductor element directly above the modified region 308 may require a higher dielectric constant than the modified region 308. Therefore, the modified region 308 can be as shallow as possible so that the dielectric constant within the second semiconductor element meets the required dielectric constant. In other words, the modified region 308 can be configured not only according to the structural requirements within the modified region 308, but also according to the overall requirements of the package.

[0039] Figure 4 A semiconductor element 400 having a modified region 410 according to some embodiments is shown. The semiconductor element 400 may be similar to... Figure 2 The package 204-1 includes similar features and functions. Semiconductor element 400 may include a redistribution layer (RDL) 402, dies 404a to c, pillars 406a to c, and vias 408a to d. Each die 404a to c may include a chip (e.g., Figure 3 This can be a chip 302 in the RDL or other semiconductor elements on a multi-chip module or package. The RDL 402 can be a single layer that distributes signals from one layer of chips to another. For example, a first signal can be transmitted from die 404c through pillar 406c. The signal can then be propagated through RDL 402 to die 404a using via 408a. Subsequently, via 408d can be used to transmit the first signal from die 404a to another die using pillar 406a through RDL 402. A second signal can be transmitted from die 404c to die 404b using pillar 406c and via 408b (in RDL 402). Subsequently, via 408c and pillar 406b can be used to transmit the second signal from die 404b to another die.

[0040] Semiconductor components 400 can be designed using an environment-aware approach, as described above. Figure 3 During the design process, via 408a can be identified as requiring a lower dielectric constant than the material used to construct RDL 402. For example, via 408a may be combined with another via (not shown) for differential signal transmission. The system requirements of multiple structures included on semiconductor element 400 can be used to identify the three-dimensional region surrounding via 408a. Subsequently, the dielectric constant of the material surrounding via 408a can be reduced so that the TOF of the signal in via 408a matches the TOF of the signal in another via. For this purpose, region 410a can be configured to include an air gap within region 410a, thereby reducing the dielectric constant of the material within region 410a. In contrast, via 408d can follow a path determined using the dielectric constant of RDL 402. Therefore, region 410a can extend only toward via 408d such that the dielectric constant of region 410a meets the required value, while the dielectric constant around via 408d remains unchanged. In contrast, region 410b may extend to include some or all of the vias 408c. This is likely because the dielectric constant of the material surrounding the vias 408c is not important (e.g., via 408c is grounded).

[0041] Figures 5A to 5D A process flow for manufacturing a semiconductor device 500 with selectively reduced dielectric constant is shown according to certain embodiments. Figure 5A In this embodiment, semiconductor device 500 may include a substrate 502 and a dielectric layer 504. The substrate may be a polycrystalline substrate, including materials such as silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide, and others of this kind. The dielectric layer 504 may include n-PSPI, such as SU8, acrylate, and / or other resin systems. The dielectric layer 504 may be characterized at least partially by a dielectric constant. The dielectric material may be deposited onto the substrate 502 by spin coating or any other suitable method.

[0042] exist Figure 5B In this process, a mask can be applied to dielectric layer 504 according to a deposition plan. The deposition plane may include vias 506 and air gaps 508a. Vias 506 can be identified during process design as requiring a lower dielectric constant (e.g., to match TOF during differential signal transmission). To achieve a lower dielectric constant, the number of air gaps 508a to d can be determined, thereby reducing the density of dielectric layer 504. The dielectric constant of the dielectric layer can be selectively tuned so that only vias 506 are affected. For example, semiconductor device 500 may be similar to... Figure 4 The RDL of RDL 402 in the middle. Subsequently, via 506 can correspond to via 408a and requires a lower dielectric constant, while via 408d requires the dielectric constant of dielectric layer 504.

[0043] Although air gaps 508a to d are illustrated in two dimensions, they can be arranged in a three-dimensional manner around the via 506 and include three-dimensional shapes and / or lattices. For example, air gaps 508a to d can be cubic, pyramidal, hexahedral, octahedral, pentahedral, or any other such three-dimensional shape. The scale of air gaps 508a to d can be from 100 nanometers to 1 micrometer (inclusive). Those skilled in the art will recognize many different possibilities and configurations.

[0044] exist Figure 5C In this process, dielectric layer 504 may be exposed to light during a flatbed printing process (e.g., two-photon flatbed printing). Due to exposure to light radiation, the material of dielectric layer 504 may become insoluble in the photoresist developer applied to dielectric layer 504 after exposure. Therefore, when photoresist developer is applied to dielectric layer 504, vias 506 and air gaps 508a to d can form hollow spaces within dielectric layer 504. Subsequently, in Figure 5D The via 506 can be filled with metal to form a metal-filled path. The metal can be a copper-containing material, such as copper (deposited through an inlay process) or another suitable metal.

[0045] Therefore, the resulting semiconductor device 500 may include a substrate 502, a dielectric layer 504, and a metal via 506. The dielectric layer 504 may include a first region comprising air gaps 508a to d, and a second region without any air gaps. The second region may be adjacent to the first region. Therefore, the dielectric constant of the first region may be lower than that of the second region. In some embodiments, the second region may also include air gaps. The second region may include more air gaps (resulting in a lower dielectric constant) or fewer air gaps (resulting in a higher dielectric constant than the first region). The second region may also include a second via, wherein the dielectric constant of the second region modifies the signal integrity of the second via.

[0046] The specific path of via 506 can be determined at least in part based on the length matching requirements of the corresponding via. For example, via 506 can be used for differential signal transmission. Therefore, via 506 can be electrically short-circuited by reducing the dielectric constant of the material surrounding via 506. As described above, a second via in the second region can also be used for differential signal transmission. The dielectric constant of the second region can be configured to modify the signal integrity of the second via to correspond to the signal integrity of via 506.

[0047] Figure 6 A method 600 for selectively reducing the dielectric constant of a semiconductor element according to certain embodiments is illustrated. Method 600 can be implemented using the systems described herein (e.g., Figure 1 System 100 in the middle) executes to manufacture some or all of the components (e.g., Figure 3 and 4(Semiconductor elements 300 and 400 in the process). Some steps of method 600 may be performed in a different order than described, or may be skipped together. In some embodiments, some steps of method 600 may be skipped entirely.

[0048] In step 602, method 600 may include identifying three-dimensional regions of a semiconductor device (e.g., advanced packaged devices, such as...) via a computing device. Figure 2 In the package 204-1), a path can be formed (e.g., Figure 3 (e.g., via 304c in Figure 5). The material used to fabricate the semiconductor device may have a dielectric constant. The desired signal integrity of the path may require a dielectric constant lower than that of the material. For example, the path may be a via used in differential signal transmission (e.g., via 506 in Figure 5). A lower dielectric constant may electrically short-circuit the signal TOF in the via, causing the signal to correspond to a second signal in another via.

[0049] In step 604, method 600 may include generating a deposition plan by a computing device, characterized by air gaps formed in a three-dimensional region where a path can be formed. The air gaps can reduce the density of the material in the three-dimensional region, thereby reducing the dielectric constant of the material. The air gaps can be any three-dimensional shape or lattice, as described with respect to FIG. 5. The deposition plan may also be generated at least in part by calculating the total capacitance of the three-dimensional region including the air gaps.

[0050] Deposition plans can be generated in an environment-aware manner, such as through chip packaging interaction analysis. In other words, during the design process that generates the deposition plan, the requirements of the regions above, below, and / or adjacent to the three-dimensional region can be considered. For example, if the region above the three-dimensional region needs to be substantially equal to the dielectric constant of the material used to construct the semiconductor device, the deposition plan will constrain the three-dimensional region. By constraining the three-dimensional region, the dielectric constant of the aforementioned region can be substantially equal to the dielectric constant of the material used to construct the semiconductor device.

[0051] In step 606, method 600 may include determining, via a computing device, that the deposition pattern at least meets mechanical characteristic constraints associated with a three-dimensional region of the semiconductor device. Mechanical characteristic constraints may include mechanical strength, heat resistance, and other such characteristics. Mechanical characteristic constraints may also be determined in a context-aware manner. In other words, the mechanical characteristics of the three-dimensional region may be analyzed to determine the effect of the mechanical characteristics on the semiconductor device as a whole. For example, mechanical characteristic constraints may be used to determine whether a three-dimensional region, including an air gap, will cause mechanical and / or thermal failures in the semiconductor device (e.g., during the manufacturing process).

[0052] In response to determining that the deposition plan at least meets the mechanical property constraints associated with the three-dimensional region of the semiconductor device, in step 608, method 600 may include communicating via a computing device to a semiconductor processing system (e.g., Figure 1System 100 provides a deposition plan, which is then executed by a semiconductor processing system. Semiconductor elements can then be formed by the semiconductor processing system, such that the semiconductor elements include paths through a three-dimensional region. The three-dimensional region is characterized by a low dielectric constant, thereby achieving the desired signal integrity.

[0053] In some implementations, a copper damascene process can be used to form the paths. For example, a semiconductor device can be formed by developing n-PSPI material on a substrate. Developing the n-PSPI material can form air gaps and / or cavities in the paths. After developing the n-PSPI material, the paths can be filled with a metal such as copper using a damascene process.

[0054] Each method described herein (e.g., method 600) can be implemented by a computer system. Each step of such methods can be performed automatically by the computer system and / or may provide input / output involving a user. For example, a user may provide input for each step of the method, and each of such inputs may respond to a specific output requested for that input, wherein the output is generated by the computer system. Each input may be received in response to a corresponding requested output. Furthermore, input may be received from a user, as a data stream from another computer system, retrieved from a memory location, retrieved via a network, requested from a network service, etc. Similarly, output may be provided as a data stream to a user, another computer system, stored in a memory location, sent via a network, provided to a network service, etc. In short, each step of the methods described herein can be performed by a computer system and may involve any number of round trips to the computer system, including inputs, outputs, and / or requests, which may or may not involve a user. Those steps that do not involve a user may be referred to as being performed automatically by the computer system without human intervention. Therefore, it will be understood from this disclosure that each step of each method described herein may be modified to include round trips to user input and output, or may be performed automatically by a computer system without human intervention, wherein any determination is made by a processor. Furthermore, some implementations of each method described herein may be implemented as a set of instructions stored on a tangible, non-transitory storage medium to form a tangible software product.

[0055] Figure 7 An exemplary computer system 700 is illustrated, in which various implementations can be carried out. System 700 can be used to implement any of the computer systems described above. As shown in the figures, computer system 700 includes a processing unit 704 that communicates with a plurality of peripheral subsystems via a bus subsystem 702. These peripheral subsystems may include a processing acceleration unit 706, an I / O subsystem 708, a storage subsystem 718, and a communication subsystem 724. Storage subsystem 718 includes a tangible computer-readable storage medium 722 and system memory 710.

[0056] Bus subsystem 702 provides a mechanism for enabling various components and subsystems of computer system 700 to communicate with each other as intended. Although bus subsystem 702 is schematically shown as a single bus, alternative implementations of the bus subsystem may utilize multiple buses. Bus subsystem 702 can be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses, and local buses using any of various bus architectures. For example, such architectures may include Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses, each of which can be implemented as a mezzanine bus manufactured according to the IEEE P1386.1 standard.

[0057] A processing unit 704, which may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of a computer system 700. The processing unit 704 may include one or more processors. These processors may include single-core or multi-core processors. In some embodiments, the processing unit 704 may be implemented as one or more independent processing units 732 and / or 734, each including a single-core or multi-core processor. In other embodiments, the processing unit 704 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0058] In various implementations, processing unit 704 can execute multiple programs in response to program code and can maintain multiple concurrently executing programs or processes. At any given time, some or all of the program code to be executed may reside in processor 704 and / or storage subsystem 718. Through suitable programming, processor 704 can provide the various functions described above. Computer system 700 may additionally include processing acceleration unit 706, which may include digital signal processor (DSP), dedicated processor, and the like.

[0059] I / O subsystem 708 may include user interface input devices and user interface output devices. User interface input devices may include keyboards, pointing devices such as mice or trackballs, touchpads or touchscreens integrated into the display, scroll wheels, click wheels, dial pads, buttons, switches, keypads, audio input devices with voice command recognition systems, microphones, and other types of input devices. User interface input devices may include, for example, motion sensing and / or gesture recognition devices, sensors that enable users to control and interact with the input device through a natural user interface using gestures and verbal commands. User interface input devices may also include eye gesture recognition devices that detect eye movements from the user (e.g., "blinking" when taking a photo and / or making menu selections) and translate eye gestures as input to the input device. Furthermore, user interface input devices may include voice recognition sensing devices that enable users to interact with voice recognition systems (e.g., Siri® navigation devices) via voice commands.

[0060] User interface input devices may also include, but are not limited to, three-dimensional (3D) mice, joysticks or pointing sticks, game consoles and graphics tablets, and audio / video devices such as speakers, digital cameras, digital video cameras, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser rangefinders, and eye-tracking devices. Furthermore, user interface input devices may include, for example, medical imaging input devices such as computed tomography (CT), magnetic resonance imaging (MRI), positional emission computed tomography (PECT), and medical ultrasound examination devices. User interface input devices may also include, for example, audio input devices such as MIDI keyboards, digital musical instruments, and the like.

[0061] User interface output devices may include display subsystems, indicator lights, or non-visual displays such as audio output devices. Display subsystems may be cathode ray tubes (CRTs), flat panel devices such as those using liquid crystal displays (LCDs) or plasma displays, projection devices, touchscreens, and the like. Generally, the term "output device" is intended to encompass all possible types of means and mechanisms for outputting information from computer system 700 to a user or other computer. For example, user interface output devices may include, but are not limited to, various display devices that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, voice output devices, and modems.

[0062] Computer system 700 may include a storage subsystem 718, which includes software elements shown as currently located in system memory 710. System memory 710 may store program instructions that can be loaded and executed on processing unit 704, and data generated during the execution of such programs.

[0063] Depending on the configuration and type of the computer system 700, system memory 710 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that the processing unit 704 can immediately access and / or is currently operating and executing. In some embodiments, system memory 710 may include various types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some embodiments, the basic input / output system (BIOS) may typically be stored in ROM, which contains basic routines such as those that facilitate the transfer of information between components within the computer system 700 at startup. By way of example and not limitation, system memory 710 also includes application programs 712 (which may include client applications, web browsers, middleware applications, relational database management systems (RDBMS), etc.), program data 714, and operating system 716.

[0064] The storage subsystem 718 may also provide a tangible computer-readable storage medium for storing basic programming and data structures that provide functionality in certain implementations. Software (programs, code modules, instructions) that provides these functions when executed by a processor may be stored in the storage subsystem 718. These software modules or instructions may be executed by the processing unit 704. The storage subsystem 718 may also provide a repository for storing data used according to some implementations.

[0065] Storage subsystem 718 may also include a computer-readable storage medium reader 720, which may be further connected to a computer-readable storage medium 722. Together with system memory 710 (and where applicable), computer-readable storage medium 722 may comprehensively represent remote, local, fixed and / or removable storage devices, and storage media for temporarily and / or more permanently containing, storing, transmitting and retrieving computer-readable information.

[0066] The computer-readable storage medium 722 containing code or partial code may also include any suitable medium, including storage media and communication media, such as, but not limited to, volatile and non-volatile, removable and non-removable media implemented in any way or by any technique, for storing and / or transmitting information. This may include tangible computer-readable storage media, such as RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory or other storage technologies, CD-ROM, digital versatile disk (DVD) or other optical storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or other tangible computer-readable media. This may also include intangible computer-readable media, such as data signals, data transmissions, or any other medium that can be used to transmit the required information and is accessible by the computing system 700.

[0067] For example, computer-readable storage medium 722 may include hard disk drives that read and write to non-removable non-volatile magnetic media, disk drives that read and write to removable non-volatile disks, and optical disc drives that read and write to removable non-volatile optical discs (such as CD-ROMs, DVDs, or other optical media). Computer-readable storage medium 722 may include, but is not limited to, flash memory cards, universal serial bus (USB) flash drives, secure digital (SD) cards, DVDs, digital videotapes, etc. Computer-readable storage medium 722 may also include solid-state drives (SSDs) based on non-volatile memory, such as flash-based SSDs, enterprise flash drives, solid-state ROMs, etc.; SSDs based on volatile memory, such as solid-state RAM, dynamic RAM, static RAM, DRAM-based SSDs, magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs using a combination of DRAM-based and flash-based SSDs. Disk drives and their associated computer-readable media provide non-volatile storage for computer-readable instructions, data structures, program modules and other data for computer system 700.

[0068] The communication subsystem 724 provides an interface to other computer systems and networks. The communication subsystem 724 serves as an interface for receiving data from the computer system 700 and transmitting data to other systems. For example, the communication subsystem 724 enables the computer system 700 to connect to one or more devices via the Internet. In some embodiments, the communication subsystem 724 may include radio frequency (RF) transceiver components for accessing wireless voice and / or data networks, for example, using cellular telephone technology, advanced data network technologies such as 3G, 4G, or EDGE (Enhanced Data Rate Global Evolution), WiFi (IEEE 802.11 series standards or other mobile communication technologies, or any combination thereof), global positioning system (GPS) receiver components, and / or other components. In some embodiments, in addition to, or as an alternative to, a wireless interface, the communication subsystem 724 may provide a wired network connection (e.g., Ethernet).

[0069] In some implementations, the communication subsystem 724 may also use the identities of one or more users of the computer system 700 to receive input communications in the form of structured and / or unstructured data feeds 726, event streams 728, event updates 730, etc.

[0070] For example, the communication subsystem 724 may be configured to receive data feeds 726 in real time from users of social networks and / or other communication services, web feeds such as Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0071] Furthermore, the communication subsystem 724 can also be configured to receive data in the form of a continuous data stream, which may include an event stream 728 and / or event updates 730 of real-time events. These event streams 728 and / or event updates 730 may be continuous or unbounded in nature, without a definite end. Examples of applications that generate continuous data may include, for example, sensor data applications, financial market recorders, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, vehicle traffic monitoring, and the like.

[0072] The communication subsystem 724 can also be configured to output structured and / or unstructured data feeds 726, event streams 728, event updates 730, etc., to one or more databases, which can communicate with one or more streaming data source computers coupled to the computer system 700. The computer system 700 can be of various types, including handheld portable devices, wearable devices, PCs, workstations, mainframe computers, kiosks, server racks, or any other data processing system.

[0073] Due to the constantly evolving nature of computers and networks, the description of the computer system 1000 illustrated in the accompanying drawings is merely a specific example. Many other configurations with more or fewer components than the system illustrated in the drawings are possible. For example, custom hardware may be used, and / or specific elements may be implemented in hardware, firmware, software (including applets), or combinations thereof. Furthermore, connections to other computing devices, such as network input / output devices, may be used. Other ways and / or methods of implementing various embodiments should be apparent based on the disclosure and teachings provided herein.

[0074] In the foregoing description, numerous specific details have been set forth for illustrative purposes to provide a comprehensive understanding of the various embodiments. However, it will be apparent that some embodiments may be implemented without such specific details. In other instances, well-known structures and apparatuses are shown in block diagram form.

[0075] The foregoing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of some embodiments set forth in the appended claims.

[0076] Specific details have been provided in the foregoing description to offer a comprehensive understanding of the implementation methods. However, it will be understood that these implementation methods may be practiced without such specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form to avoid obscuring the implementation methods with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without containing unnecessary details in order to avoid obscuring the implementation methods.

[0077] It should also be noted that individual implementations may have been described as processes, which are illustrated as flowcharts, diagrams, data flow charts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. When an operation of a process is completed, the process terminates, but there may be additional steps not included in the figures. A process may correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0078] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction may represent a program, function, subroutine, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, forwarded, or transmitted by any suitable means, including memory sharing, message passing, symbol passing, network transmission, etc.

[0079] Furthermore, the implementation can be carried out by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments that perform the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0080] In the foregoing description, features have been described with reference to specific embodiments thereof; however, it should be understood that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used alone or in combination. Furthermore, embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of this specification. Therefore, the description and drawings should be considered illustrative rather than restrictive.

[0081] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in alternative embodiments, these methods may be performed in a different order than described. It should also be understood that the above methods may be executed by hardware components or may be embodied in a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or instruction-programmed logic circuit) to execute these methods. These machine-executable instructions may be stored on one or more machine-readable media, such as CD-ROMs or other types of optical discs, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic cards or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, these methods may be executed by a combination of hardware and software.

Claims

1. A method for constructing a redistribution layer of a semiconductor device, the method comprising: The computing device identifies three-dimensional regions in the semiconductor element where paths can be formed, wherein the material used to manufacture the semiconductor element has a dielectric constant, and the desired signal integrity along the path requires a low dielectric constant. The computing device generates a deposition plan, the deposition plan being characterized by an air gap formed in the three-dimensional region in the semiconductor element where the path can be formed; The computing device determines that the deposition plan at least meets the mechanical property constraints associated with the three-dimensional region of the semiconductor element; and In response to determining that the deposition plan at least satisfies the mechanical property constraints associated with the three-dimensional region of the semiconductor device: The computing device provides the deposition plan to the semiconductor processing system, causing the semiconductor processing system to execute the deposition plan and form the semiconductor element including the path through the three-dimensional region, the three-dimensional region being characterized by the lower dielectric constant, thereby achieving the desired signal integrity.

2. The method of claim 1, wherein the semiconductor processing system is configured to use two-photon lithography to produce semiconductor elements.

3. The method of claim 1, wherein the semiconductor element includes an advanced packaged element.

4. The method of claim 1, wherein the path is formed using a copper inlay process.

5. The method of claim 1, wherein the air gap in the three-dimensional region and the material in the three-dimensional region form a lattice pattern, the lattice pattern being characterized by at least one of a cubic air gap, a hexagonal prism air gap, and a pyramid air gap.

6. The method of claim 1, wherein the mechanical properties of the three-dimensional region are at least partially determined by the mechanical strength required for the three-dimensional region.

7. The method of claim 1, wherein the mechanical properties of the three-dimensional region include the heat resistance of the three-dimensional region.

8. The method of claim 1, wherein the three-dimensional region is identified at least in part by determining the characteristics of a second semiconductor element to be formed above the three-dimensional region and the characteristics of a third semiconductor element to be formed below the three-dimensional region.

9. The method of claim 1, wherein the deposition plan is generated in part by calculating the total capacitance of the three-dimensional region including the air gap.

10. A system comprising: A semiconductor processing chamber configured to receive a substrate; A flatbed printing tool configured to perform two-photon flatbed printing; and Computing device, the computing device comprising: One or more processors; and A non-transitory computer-readable medium, the non-transitory computer-readable medium comprising instructions, which, when executed by the one or more processors, cause the computing device to perform operations to: Identify three-dimensional regions in a semiconductor device where paths can be formed, wherein the material used to manufacture the semiconductor device has a dielectric constant, and the desired signal integrity along the path requires a low dielectric constant; A deposition plan is generated, characterized by an air gap formed in the three-dimensional region in the semiconductor element where the path may be formed; The deposition plan is determined to at least satisfy the mechanical property constraints associated with the three-dimensional region of the semiconductor device; and In response to determining that the deposition plan at least satisfies the mechanical property constraints associated with the three-dimensional region of the semiconductor device: The deposition plan is provided to a semiconductor processing system, which then executes the deposition plan and forms a semiconductor element including a path through the three-dimensional region, the three-dimensional region being characterized by the lower dielectric constant, thereby achieving the desired signal integrity.

11. The system of claim 10, wherein the deposition schedule is generated using at least a portion of chip package interaction analysis.

12. The system of claim 10, wherein identifying the three-dimensional region includes context-aware analysis, including system requirements for identifying the three-dimensional region of a plurality of structures on the semiconductor element.

13. The system of claim 12, wherein the context-aware analysis includes determining the characteristics of a second semiconductor element to be formed above the three-dimensional region and determining the characteristics of a third semiconductor element to be formed below the three-dimensional region.

14. The system of claim 10, wherein the air gap of the three-dimensional region and the material of the region form a lattice pattern, the lattice pattern being characterized by at least one of a cubic air gap, a hexagonal prism air gap, and a pyramid air gap.

15. A semiconductor element, the semiconductor element comprising: substrate; A dielectric material, wherein the dielectric material is at least partially characterized by a dielectric constant; Metal pathways formed in the dielectric material; and A region, the region surrounding the metal path of the semiconductor element, the region including a plurality of air gaps within the dielectric material and arranged in a three-dimensional manner throughout the region, wherein the region includes a dielectric constant lower than the dielectric constant of the dielectric material.

16. The semiconductor element of claim 15, wherein the adjacent regions of the semiconductor element are characterized by having no air gap.

17. The semiconductor device of claim 15, wherein the position of the metal path is determined according to a length matching requirement associated with the corresponding metal path.

18. The semiconductor element of claim 15, further comprising: Second metal path; and A second region, surrounding the second metal path, includes a second plurality of air gaps within the dielectric material and is arranged in a three-dimensional manner throughout the second region, wherein the second plurality of air gaps are configured such that the dielectric constant of the second region alters the signal integrity of the second metal path, corresponding to the signal integrity of the metal path.

19. The semiconductor element of claim 15, wherein the semiconductor element includes a redistribution layer.

20. The semiconductor device of claim 15, wherein each of the plurality of air gaps comprises a size in the range of 100 nanometers to 1 micrometer, including 100 nanometers and 1 micrometer.

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