Memory system, memory controller, and memory device

Abstract

A memory system, a memory controller, and a memory device are provided. The memory system includes a memory device, a control circuit, and a memory controller. The memory device includes a plurality of memory regions, a candidate register group storing a plurality of candidate parameter sets corresponding to temperature ranges, respectively, and a mode register group storing the temperature ranges and refresh management parameter sets. The control circuit stores a first candidate parameter set of the plurality of candidate parameter sets as a refresh management parameter set in a mode register set based on a temperature range. The memory controller obtains a refresh management parameter set from the memory device based on the updated temperature range, counts an activation count of the plurality of memory regions, and provides a refresh management command to the memory device based on the activation count and the refresh management parameter set.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0165887, filed on November 20, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This application relates to memory systems, memory controllers, and memory devices. Background Technology

[0003] Typically, Dynamic Random Access Memory (DRAM) performs refresh operations to maintain the data stored in the cell capacitors. With advancements in process technology, the integration density of memory cells increases, and the gaps between memory cells gradually narrow. As the gaps between memory cells narrow, interference caused by adjacent memory cells or word lines has a greater impact on the memory cells. If interference is concentrated on a specific memory cell, row hammering can occur, causing changes to the data stored in neighboring memory cells. Summary of the Invention

[0004] The example implementation provides a memory device, a memory controller, and a memory system that enables the memory controller to control the target refresh operation of the memory device in a timely manner.

[0005] According to an example embodiment, a memory system includes: a memory device, comprising: a plurality of memory regions, a candidate group, storing a plurality of candidate parameter sets respectively corresponding to a temperature range, a mode register group, storing the temperature range and a refresh management parameter set, and control logic circuitry, storing a first candidate parameter set from the plurality of candidate parameter sets as a refresh management parameter set in the mode register group based on the temperature range; and a memory controller, obtaining the refresh management parameter set from the memory device based on the updated temperature range, counting the activation counts of the plurality of memory regions, and providing a refresh management command to the memory device based on the activation counts and the refresh management parameter set.

[0006] According to an example embodiment, a memory controller includes: a refresh management circuit configured to: provide an activation command to a memory device and count activation counts for a plurality of memory regions of the memory device, respectively; and a memory configured to: store an activation count threshold for the activation counts. The refresh management circuit is configured to: receive a temperature range from the memory device; receive a revised count threshold from the memory device based on the temperature range update; update the activation count threshold stored in the memory based on the received count threshold to provide an updated activation count threshold; and provide a refresh management command for a target memory region among the plurality of memory regions based on the activation count reaching the updated activation count threshold.

[0007] According to an example embodiment, a memory device includes: a plurality of memory regions having a plurality of memory cells; a register storing a plurality of candidate parameter sets corresponding to a plurality of temperature ranges respectively; a mode register group storing a first temperature range in a first register region and storing a refresh management parameter set in a second register region; and a control circuit that, based on the first temperature range, stores the first candidate parameter set in the plurality of candidate parameter sets as a refresh management parameter set in the second register region, outputs the first temperature range based on a first read request for the first register region, and outputs the refresh management parameter set based on a second read request for the second register region. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a diagram illustrating a memory system according to some example embodiments; Figure 2 This is a block diagram illustrating a memory device according to some example embodiments; Figure 3 This is a diagram illustrating the refresh management commands; Figure 4 This is a diagram showing the mode register; Figure 5 This is a diagram illustrating a portion of a memory device according to some example embodiments; Figure 6 This is a diagram illustrating a refresh management circuit according to some example implementations; Figure 7 This is a diagram illustrating the interaction between a memory controller and a memory device according to some example embodiments; Figure 8 This is a diagram illustrating a memory module according to some example embodiments; and Figure 9 This is a diagram illustrating a semiconductor package including stacked semiconductor chips according to some example embodiments. Detailed Implementation

[0009] In the following description, some exemplary embodiments will be described with reference to the accompanying drawings.

[0010] This disclosure relates to memory devices, memory controllers for controlling memory devices, and memory systems including memory devices.

[0011] To prevent row hammering, a target refresh operation can be performed on a specified memory region of the memory device. Using the refresh management (RFM) interface, the memory controller can determine the target memory region and set the time for the "target refresh of the target memory region".

[0012] Figure 1 This is a diagram illustrating a memory system according to some example implementations.

[0013] Reference Figure 1 The memory system 10 may include a memory device 200 and a memory controller 100 for controlling the memory device 200.

[0014] The memory system 10 can be implemented as included in a personal computer (PC) or a mobile electronic device. The mobile electronic device can be implemented as a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, mobile internet device (MID), wearable computer, Internet of Things (IoT) device, Internet of Everything (IoE) device, or drone.

[0015] The memory device 200 can store data. In some example embodiments, the memory device 200 may be implemented as a volatile memory device. For example, the volatile memory device may be implemented as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), or low-power double data rate (LPDDR) DRAM.

[0016] The memory controller 100 can be implemented to control the memory device 200 to read data stored in the memory device 200 or to write data to the memory device 200. The memory controller 100 can control write or read operations on the memory device 200 by providing commands CMD and addresses ADDR to the memory device 200 in synchronization with the clock CLK. Furthermore, data input / output to the data signal DQ line can be sent and received between the memory controller 100 and the memory device 200 in synchronization with the data transfer clock WCK.

[0017] In addition, the memory controller 100 provides an interface connection between the host and the memory device 200. The memory controller 100 can exchange data and signals with the memory device 200 through the clock CLK signal line, command / address lines CMD / ADD, data transfer clock signal line WCK, data signal line DQ, etc.

[0018] The memory device 200 may include a memory cell array (MCA) 241, control logic circuitry 210, a mode register set (MRS) 212, and a register set (or candidate register set) 213.

[0019] Each of the memory cell array 241 may include multiple memory cells (MCs) connected to word lines (WL) and bit lines (BL).

[0020] The control logic circuit 210 can control the memory device 200 as a whole. For example, the control logic circuit 210 can control read operations, write operations and refresh operations for the memory cell array 241.

[0021] The mode register group 212 may include multiple mode registers that store values ​​for setting the operating mode. Specifically, the mode register group 212 may store parameters for controlling the refresh operation.

[0022] The memory device 200 stores data by storing charge in memory cells. In the case of a volatile memory device, the charge stored in the memory cells decreases over time due to leakage current, etc., and the data stored in the memory cells may be lost.

[0023] A refresh operation can represent the process of recovering data before it is lost from a memory cell. For example, if the data values ​​of the rows in the memory cells to be refreshed are loaded into a sense amplifier, the data stored in the memory cells can also be refreshed.

[0024] The time from when data is written to a memory cell until the data is lost and cannot be read is called the hold time. A refresh operation should be performed on each memory cell in the memory device 200 before its hold time has elapsed, so that the data can be maintained. A refresh operation performed periodically on all memory cells is called a normal refresh operation. The memory controller 100 can provide a normal refresh command to the memory device 200 so that all memory cells can be periodically refreshed.

[0025] For example, memory controller 100 may provide a normal refresh command to memory device 200 at each refresh interval time tREFIe (or the refresh interval for normal refresh). Memory controller 100 may guarantee memory device 200 a time equal to the refresh cycle time tRFC used for each normal refresh command. For example, memory controller 100 may not provide additional commands to memory device 200 during the refresh cycle time tRFC. Memory device 200 can perform refresh operations on memory cells during the hold time by utilizing the refresh cycle time tRFC.

[0026] The retention time of a memory cell can vary depending on the temperature of the memory device 200. For example, as the temperature of the memory device 200 increases, the amount of leakage current increases and the retention time may shorten. The refresh interval tREFIe, which is the period during which a normal refresh operation is performed, can be determined based on the temperature range of the memory device 200 (i.e., the temperature range to which the temperature of the memory device 200 belongs). For example, the higher the temperature range of the memory device 200 (e.g., the upper and lower limits of the temperature range), the shorter the refresh interval tREFIe can be.

[0027] If a row is activated multiple times in memory device 200, row hammering can occur, resulting in changes to data stored in neighboring rows. Rows are refreshed periodically through normal refresh operations, but if a row is activated too many times between cycles of performing a normal refresh operation, row hammering can occur in neighboring rows. To prevent row hammering, a refresh operation performed in a target area based on the number of row activations can be called a targeted refresh operation. For example, memory device 200 may perform a normal refresh operation during the refresh cycle time tRFC and a targeted refresh operation for the remaining time.

[0028] As the integration density of memory cells increases, the gaps between memory cells gradually narrow. Row hammering becomes more severe due to the narrowing gaps between memory cells. In order to maintain data despite more severe row hammering, the memory device 200 may require a relatively longer time to perform the target refresh operation.

[0029] To provide sufficient time for the memory device 200 to perform the target refresh operation, a refresh management (RFM) interface can be configured. The memory controller 100 can provide additional time for the target refresh operation by providing a refresh management command RFM_CMD to the memory device 200 based on the activation count of the memory region. The refresh management command may also be referred to as an RFM command.

[0030] The memory controller 100 can guarantee the memory device 200 a time equal to the refresh management time tRFM used for each refresh management command. The memory device 200 can perform the target refresh operation during the refresh management time tRFM.

[0031] The memory controller 100 may determine whether to provide a refresh management command RFM_CMD to the memory device 200 based on the activation count of the memory region and a set of refresh management parameters (e.g., a refresh management parameter set) associated with the activation count. In one example, the memory controller 100 may determine a target memory region based on the activation count and the refresh management parameter set, and provide a refresh management command RFM_CMD for the target memory region to the memory device 200.

[0032] For example, memory controller 100 may include refresh management circuitry 110 and memory 120. Refresh management circuitry 110 may count the activation count for each memory region of memory device 200 and provide refresh management command RFM_CMD to memory device 200 based on the activation count. The activation count may also be referred to as rolling cumulative activation (RAA) count.

[0033] Memory 120 may store a refresh management parameter set (or, a refresh management parameter set and a temperature range) obtained from mode register set 212. The refresh management parameter set may define a threshold for the activation count and control the activation count.

[0034] If the refresh management parameter set is fixed regardless of the temperature of the memory device 200, it may be difficult to perform the target refresh operation in a timely manner in relation to the normal refresh operation performed at each refresh interval tREFIe determined according to the temperature range.

[0035] For example, refresh management commands can be configured to be skipped when the refresh interval tREFIe is shorter than a threshold determined based on the activation count. If the refresh management parameter set is fixed, refresh management commands can be skipped under high-temperature conditions where normal refresh operations are executed in short cycles, and it may be difficult to prevent row hammering in specific memory regions.

[0036] On the other hand, in low-temperature environments where normal refresh operations are performed over long periods, target refresh operations can be performed relatively frequently, reducing the time available for executing other commands. Specifically, the processing efficiency of the memory system 10 may decrease.

[0037] According to some exemplary embodiments of this disclosure, the refresh management parameter set can be dynamically adjusted according to the temperature of the memory device 200, and the period of the target refresh operation can be dynamically controlled.

[0038] The memory device 200 can store candidate parameter sets corresponding to multiple temperature ranges in register group 213. Based on the currently measured temperature range, the memory device 200 can store one of the candidate parameter sets as a refresh management parameter set in mode register group 212.

[0039] When the measured temperature range is updated, the memory controller 100 can obtain the refresh management parameter set stored in the mode register group 212, update the refresh management parameter set of the memory 120, and control the target refresh operation based on the updated refresh management parameter set.

[0040] According to some example implementations, the memory device 200 can perform a target refresh operation in a timely manner in relation to its normal refresh operation, the cycle of which varies with temperature. Therefore, when the data stored in the memory device 200 can be protected from row hammering, the performance degradation of the memory system 10 can be significantly reduced.

[0041] Before describing the memory system 10 according to some example embodiments in detail below, the structure of the memory device 200 will be described in detail.

[0042] Figure 2 This is a block diagram illustrating a memory device according to some example embodiments.

[0043] Reference Figure 2 The memory device 200 may include control logic circuitry 210, address register 221, memory bank control circuitry 222, refresh counter 223, row address multiplexer (RA MUX) 224, column address (CA) latch 225, row decoder (or memory bank row decoder) 226, column decoder 227, memory cell array 241, sensing (SA) amplifier (or SA circuit) 242, input / output (I / O) gate circuitry 243, and data input / output buffer 250.

[0044] The control logic circuit 210 can control the operation of the memory device 200. For example, the control logic circuit 210 can generate control signals to cause the memory device 200 to perform read operations, write operations, refresh operations, etc. For example, the control logic circuit 210 can generate control signals for activation operations for read operations, write operations, and refresh operations.

[0045] The control logic circuit 210 may include a command decoder 211 for decoding commands CMD received from the memory controller 100, a mode register group 212 for setting the operating mode of the memory device 200, and a register group 213 for storing data related to the operation of the memory device 200.

[0046] For example, the command decoder 211 can decode the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc., to generate control signals corresponding to the command CMD.

[0047] The memory cell array 241 may include multiple memory cell arrays (241a to 241h). In addition, multiple row decoders (226a to 226h), multiple column decoders (227a to 227h), and multiple sense amplifiers (242a to 242h) may be connected to the multiple memory cell arrays 241a to 241h respectively.

[0048] Multiple memory cell arrays 241a to 241h, multiple column decoders 227a to 227h, multiple row decoders 226a to 226h, and multiple sense amplifiers 242a to 242h can each be configured with multiple memory storage units.

[0049] Multiple memory cell arrays 241a to 241h may include multiple word lines, multiple bit lines, and multiple memory cells connected to the multiple word lines and multiple bit lines. A memory cell connected to a word line may be referred to as a memory cell row.

[0050] Multiple sensing amplifiers 242a to 242h can detect and amplify voltage changes on multiple bit lines. For example, in response to an activation command, a row of memory cells in a memory bank can be activated, allowing data stored in the row of memory cells to be transferred to the sensing amplifiers.

[0051] Address register 221 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from a memory controller connected to memory device 200. Address register 221 can provide the received bank address BANK_ADDR to memory bank control circuit 222, provide the received row address ROW_ADDR to row address multiplexer 224, and provide the received column address COL_ADDR to column address latch 225.

[0052] The memory bank control circuit 222 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the row decoder corresponding to the memory bank address BANK_ADDR among the plurality of row decoders 224a to 224h can be activated, and the column decoder corresponding to the memory bank address BANK_ADDR among the plurality of column decoders 227a to 227h can be activated.

[0053] The row address multiplexer 224 can receive the row address ROW_ADDR from the address register 221 and the refresh row address REF_ADDR from the refresh counter 223. The row address multiplexer 224 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 224 can be applied to each of the multiple row decoders 226a to 226h.

[0054] The refresh counter 223 can increase or decrease the refresh row address REF_ADDR according to the control logic circuit 210.

[0055] Among the multiple row decoders 226a to 226h, the row decoder activated by the memory bank control circuit 222 can decode the row address RA output from the row address multiplexer 224 and activate the word line corresponding to the row address. For example, the activated row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0056] Column address latch 225 can receive and temporarily store the column address COL_ADDR from address register 221. Furthermore, column address latch 225 can incrementally increase the received column address COL_ADDR in burst mode. Column address latch 225 can apply the temporarily stored or incrementally increased column address COL_ADDR to each of the plurality of column decoders 227a to 227h.

[0057] Among the multiple column decoders 227a to 227h, the column decoder activated by the memory bank control circuit 222 can activate the sense amplifier corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the corresponding input / output gate circuit 243.

[0058] The input / output gating circuit 243 may include circuitry for gating input / output data, input data masking logic, a read data latch for storing data output from the plurality of memory cell arrays 241a to 241h, and a write driver for writing data to the plurality of memory cell arrays 241a to 241h.

[0059] The data signal DQ read from one of the multiple memory cell arrays 241a to 241h can be detected by a sense amplifier corresponding to that memory cell array and stored in a read data latch. The data signal DQ stored in the read data latch can be provided to the memory controller together with the data strobe signal DQS.

[0060] The data signal DQ to be written to one of the memory cell arrays 241a to 241h can be provided to the input / output gating circuit 243 by the data input / output buffer 250. The input / output gating circuit 243 can write the data signal DQ to the target page of the memory cell array 241a through the write driver.

[0061] The data input / output buffer 250 can provide the data signal DQ to the input / output gating circuit 243 during a write operation, and can provide the data signal DQ provided by the input / output gating circuit 243 to the memory controller during a read operation.

[0062] According to some example implementations, mode register group 212 may store a set of refresh management parameters associated with refresh management commands and measured temperature ranges. Although in Figure 2 The term is omitted, but the memory device 200 may also include a temperature sensor that detects the temperature of the memory device 200 to determine the temperature range to be measured.

[0063] Register group 213 may include candidate parameter sets corresponding to multiple temperature ranges. Control logic circuit 210 may store one of the multiple candidate parameter sets as a refresh management parameter set in mode register group 212 based on the measured temperature range.

[0064] According to some exemplary embodiments, the memory device 200 may be as described with reference to Figure 1 The measured temperature range is provided in response to a request from the memory controller 100, and refresh management parameters can be provided based on the measured temperature range. The memory device 200 can perform a target refresh operation in a timely manner by obtaining a refresh management time tRFM based on the measured temperature range from the memory controller 100.

[0065] Figure 3 This is a diagram showing the refresh management parameters.

[0066] Reference Figure 3 The refresh management parameter set (RFM parameter set) may include at least one of the refresh management (RFM) parameters stored in the mode register MR27, the rolling cumulative activation initial management threshold (RAAIMT) and the rolling cumulative activation multiplier (RAAMULT), the rolling cumulative activation decrement (RAADEC) and the mode (MODE) stored in the mode register MR57.

[0067] The period at which refresh management commands are provided from memory controller 100 to memory device 200 can be adjusted according to RAAIMT and RAAMULT. Specifically, memory controller 100 performs an activation count for each memory region of memory device 200, and when a target memory region whose activation count has reached a count threshold is detected, memory controller 100 may provide a refresh management command for the target memory region to memory device 200. For example, the count threshold stored in memory controller 100 may also be referred to as the activation count threshold.

[0068] RAAIMT can be a unit threshold used for refresh management, and RAAMULT can be a multiplier value multiplied by the unit threshold. The count threshold can be determined as the product of the unit threshold RAAIMT and the multiplier value RAAMULT. In one example, refresh management circuitry 110 may receive an updated count threshold from memory device 200 based on a temperature range update, and update the activation count threshold in memory controller 100 based on the updated count threshold.

[0069] In some example implementations, if the refresh management threshold time RFMTH (or target refresh threshold), determined by the product of the unit threshold RAAIMT and the activation time tRC, is greater than or equal to the refresh interval time tREFIe, the memory controller 100 may skip the operation of providing a refresh management command to the memory device 200. The activation time tRC may be a predetermined parameter "obtained by adding the row precharge time and the row activation time".

[0070] RAADEC can be a decrement of the activation count (or a count decrement). For example, when the memory controller 100 provides a refresh management command for the target memory region to the memory device 200 once, the activation count of the target memory region can be reduced by RAADEC.

[0071] RFM indicates whether refresh management is on or off, and MODE indicates the refresh management mode.

[0072] Figure 4 This is a diagram showing the mode register.

[0073] The mode register group 212 may include multiple mode registers for defining various operating modes of the memory device 200. Figure 4 The diagram shows mode registers MR4, MR27, and MR57, among several mode registers.

[0074] The mode register MR4 can store the measured temperature range and the temperature update flag TUF. The memory device 200 can determine the refresh rate (e.g., refresh interval tREFIe) for normal refresh operations based on the temperature range stored in the mode register MR4. The refresh rate based on the temperature range can be predetermined. For example, the higher the measured temperature range, the shorter the refresh interval tREFIe can be, so that normal refresh operations can be performed at shorter intervals as the current temperature of the memory device 200 increases.

[0075] The temperature update flag TUF indicates whether the measured temperature range has been updated after it has been provided to the memory controller 100. For example, the temperature update flag TUF may have a first state when the measured temperature range is provided to the memory controller 100, and a second state when the measured temperature range is updated in the mode register MR4.

[0076] Mode register MR27 can store references Figure 3 The multiplier value RAAMULT and the unit threshold RAAIMT are described, and the mode register MR57 can store the reference. Figure 3 The reduction RAADEC is described. According to some example implementations, the multiplier value RAMULT, the unit threshold RAAIMT, and the reduction RAADEC can be stored in mode registers MR27 and MR57 during system initialization and can be updated based on the measured temperature range stored in mode register MR4.

[0077] In the following text, refer to Figure 5 The method for updating and refreshing the management parameter set of memory device 200 is described in detail.

[0078] Figure 5 This is a diagram illustrating a portion of a memory device according to some example embodiments.

[0079] Reference Figure 5 The memory device 200 may include a mode register group 212, a register group 213 and a multiplexer 214.

[0080] The mode register group 212 can store the temperature range in the first register region R1 and store the refresh management parameter set in the second register region R2. The first register region R1 can correspond to the reference. Figure 4 The described mode register MR4, and the second register region R2 may correspond to the reference. Figure 4 The described mode registers are MR27 and MR57.

[0081] Register set 213 can store candidate parameter sets corresponding to multiple temperature ranges (Temp. Range 00001 to 01111).

[0082] In some example implementations, a set of candidate parameters based on temperature ranges can be experimentally determined. For example, for various temperature ranges that the first register region R1 may have, multiple combinations of refresh management parameters can be used to test refresh operations, and combinations of refresh management parameters can be determined such that metrics representing the degree of interference in memory cell rows and metrics representing the efficiency of the memory system can be optimized based on the length of the refresh management time tRFM.

[0083] In some example implementations, the unit threshold RAAIMT and the multiplier value RAAMULT can be determined such that the counting threshold has the same or smaller value for higher temperature ranges. Furthermore, the decrement RAADEC can be determined to have the same or a higher value for higher temperature ranges. For example, the first unit threshold RAAIMT corresponding to a first temperature range has a value less than or equal to the value of the second unit threshold RAAIMT corresponding to a second temperature range, where the second temperature range is lower than the first temperature range. For example, the first decrement RAADEC corresponding to a first temperature range has a value greater than or equal to the value of the second decrement RAADEC corresponding to a second temperature range, where the second temperature range is lower than the first temperature range. Here, the second temperature range being lower than the first temperature range can indicate that the upper limit of the second temperature range is lower than the lower limit of the first temperature range.

[0084] The multiplexer 214 can receive a set of candidate parameters as an input signal, receive a temperature range stored in the mode register group 212 as a selection signal, and output one of the candidate parameter sets as a refresh management parameter set according to the temperature range.

[0085] Mode register group 212, register group 213 and multiplexer 214 may be included in control logic circuit 210 and may be implemented as circuits separate from control logic circuit 210.

[0086] The memory controller 100 can obtain a refresh management parameter set updated according to the temperature range from the memory device 200, and provide refresh management commands to the memory device 200 at a period determined based on the refresh management parameter set.

[0087] Figure 6 This is a diagram illustrating a refresh management circuit according to some example implementations.

[0088] Reference Figure 6 Including in reference Figure 1 The refresh management circuitry 110 in the described memory controller 100 may include an activation counter (or rolling cumulative activation counter) 111, a count register 112, and a comparator (CMP) 113.

[0089] The activation counter 111 can count the activation counts for each memory region. For example, a memory region may correspond to a memory bank. However, this disclosure is not limited thereto, and the range of a memory region may vary.

[0090] The counter register 112 can store the activation count of the memory region counted by the activation counter 111.

[0091] Comparator 113 compares the activation count stored in counter register 112 with a count threshold. (See reference...) Figure 3 The counting threshold can be determined as the product of a unit threshold RAAIMT and a multiplier value RAAMULT. Comparator 113 can detect a target memory region among a plurality of memory regions whose activation count has reached the counting threshold.

[0092] Activation counter 111 can stop the activation count of the target memory region and prevent the provision of activation commands for the target memory region to memory device 200.

[0093] Comparator 113 can provide a refresh management command requesting a target refresh operation for a target memory region to memory device 200. Additionally, comparator 113 can decrement the activation count of the target memory region by RAADEC.

[0094] The refresh management parameter set (such as RAAIMT, RAAMULT, and RAADEC) used in the refresh management circuit 110 can be obtained from, as referenced Figure 1 The memory 120 is obtained. The refresh management parameter set stored in the memory 120 can be updated according to the temperature change of the memory device 200.

[0095] The following describes a method for operating a memory system, which includes updating a set of refresh management parameters via a memory controller 100.

[0096] Figure 7 This is a diagram illustrating the interaction between a memory controller and a memory device according to some example embodiments.

[0097] Figure 7 The memory controller 100 and memory device 200 may correspond to the reference. Figure 1 The memory controller 100 and memory device 200 are described.

[0098] In operation S101, the memory controller 100 may provide activation commands to memory regions and count the activation counts of memory regions. For example, each memory region may correspond to a memory bank of the memory device 200.

[0099] In operation S102, the memory device 200 may update the temperature range. For example, the memory device 200 may periodically measure the temperature using an internal temperature sensor, and if the measured temperature exceeds the temperature range currently stored in the first register region R1, the temperature range stored in the first register region R1 may be changed. For example, the first register region R1 may correspond to the mode register MR4.

[0100] In operation S103, the memory device 200 may update the refresh management parameter set. According to some example embodiments, the memory device 200 may store the parameter set corresponding to the updated temperature range from a pre-stored candidate parameter set for each temperature range in a second register region R2 as the refresh management parameter set. For example, the second register region R2 may include mode registers MR27 and MR57.

[0101] In operation S104, the memory controller 100 (e.g., refresh management circuitry 110) may provide the memory device 200 with a first mode register read command MRR_R1 for the first register region R1. Operation S104 may be executed periodically.

[0102] In operation S105, memory device 200 may provide the memory controller 100 with a temperature range and temperature update flag TUF stored in a first register region R1 in response to a first mode register read command MRR_R1. In some example embodiments, memory controller 100 may control the normal refresh operation of memory device 200 based on the temperature range obtained from memory device 200.

[0103] If the temperature update flag TUF indicates that the temperature range has been updated, the memory controller 100 may provide a second mode register read command MRR_R2 for the second register region R2 in operation S106.

[0104] In operation S107, memory device 200 may provide a set of refresh management parameters stored in the second register region R2 to memory controller 100 in response to the second mode register read command MRR_R2. That is, memory controller 100 may obtain the set of refresh management parameters from memory device 200 based on the updated temperature range.

[0105] In operation S108, the memory controller 100 can update the refresh management parameter set by storing the refresh management parameter set received from the memory device 200 in the internal memory.

[0106] In operation S109, the memory controller 100 may provide the refresh management command RFM_CMD to the memory device 200 based on the updated refresh management parameter set.

[0107] According to some example implementations, the memory controller 100 can control a target refresh operation of the memory device 200 based on a set of refresh management parameters determined according to the temperature of the memory device 200. Therefore, while the efficiency reduction of the memory system caused by the target refresh operation can be mitigated, the data in the memory device 200 can be protected from row hammering.

[0108] For example, memory controller 100 can control memory device 200 such that as the temperature range of memory device 200 increases, normal refresh operations are performed at shorter cycles. Furthermore, as referred to... Figure 3 If the refresh management threshold time RFMTH determined based on the unit threshold RAAIMT is greater than or equal to the refresh interval time tREFIe, then the memory controller 100 may skip the operation of providing the refresh management command to the memory device 200.

[0109] According to some example implementations, the memory device 200 may have a unit threshold RAAIMT and a multiplier value RAAMULT that "keeps the count threshold low over a higher temperature range." For example, in a higher temperature range, a target refresh operation can be performed for the memory region even if a small number of activation counts have accumulated in the memory region. Furthermore, since the refresh management threshold time RFMTH can be shorter than the refresh interval time tREFIe, skipping the target refresh operation due to relatively frequent normal refresh operations can be prevented. Therefore, when the memory device 200 is placed in a high-temperature environment, data can be protected from row hammering.

[0110] Conversely, in lower temperature ranges, target refresh operations can be performed on memory regions even when a large number of activation counts have accumulated. When the memory device 200 is placed in a low-temperature environment, it prevents the target refresh operations from being performed too frequently, thereby reducing the processing efficiency of the memory system 10.

[0111] The following describes means for applying a memory system according to some example implementations.

[0112] Figure 8 The diagram illustrates a memory module according to some example implementations.

[0113] Figure 8 This is a diagram illustrating a memory module 1000 according to some example embodiments. (Refer to...) Figure 8 The memory module 1000 may include multiple memory chips DRAM, a buffer chip RCD, and a power management chip PMIC. Each of the multiple memory chips DRAM includes a memory cell array, and the buffer chip RCD is used to route the transmit / receive signals with the memory controller or manage the memory operations of the memory chips.

[0114] The RCD can control the DRAM memory chip and the PMIC power management chip according to the control of the memory controller. For example, the RCD can receive command signals, control signals, and clock signals from the memory controller. The DRAM memory chip is connected to the corresponding data buffer in the data buffer DB through corresponding data transmission lines, and can send and receive data signals DQ and data strobe signals DQS.

[0115] The memory controller sends commands to the individual channels of the DRAM memory chip. Each channel has independent commands, addresses, and buses, allowing them to operate in parallel. A channel has one or more memory rank, and each memory rank has an independent DRAM device. Furthermore, all memory rank in a channel operates in parallel. Each memory rank has multiple memory banks, and the DRAM cells exist in the memory banks in a two-dimensional array. The individual memory banks can operate in parallel.

[0116] In some example implementations, the memory row may include eight memory bank groups. Each memory bank group may include four memory banks. In some example implementations, the memory chips may be divided into memory chips dedicated to a first channel (Channel 1) and memory chips dedicated to a second channel (Channel 2).

[0117] According to some example implementations, each of a plurality of memory chips DRAM can be as described in reference Figures 1 to 7 The internal temperature is measured, and a candidate parameter set corresponding to the measured temperature range is updated from the candidate parameter set corresponding to the temperature range as a refresh management parameter set. The memory controller can obtain the updated refresh management parameter set from the memory chip in which the measured temperature range has been updated, and control the target refresh operation of the memory chip based on the refresh management parameter set and the activation count of the memory region.

[0118] Figure 9 This is a diagram illustrating a semiconductor package including stacked semiconductor chips according to some example embodiments.

[0119] Reference Figure 9 The semiconductor package 3000 may be a memory module including at least one stacked semiconductor chip 3300 and a system-on-a-chip (SoC) 3400 mounted on a package substrate 3100 (such as a printed circuit board). Alternatively, an interposer 3200 may be disposed on the package substrate 3100. The stacked semiconductor chip 3300 may be formed as a chip-on-a-chip (CoC).

[0120] The stacked semiconductor chip 3300 may include at least one memory chip 3320 stacked on a buffer chip 3310 (such as a logic chip). The buffer chip 3310 and the at least one memory chip 3320 may be interconnected via through-silicon vias (or through-silicon vias, TSVs). The buffer chip 3310 may perform training operations on the memory chip 3320. The stacked semiconductor chip 3300 may be a high-bandwidth memory (HBM).

[0121] According to some example embodiments, the semiconductor package 3000 can dynamically change a refresh management parameter set based on the internal temperature of the memory chip 3320, the refresh management parameter set determining the triggering cycle of refresh management commands. Therefore, the semiconductor package 3000 can improve its processing efficiency while protecting data from row hammering based on the internal temperature of the memory chip 3320. For example, the semiconductor package 3000 can control the cycle of normal refresh operations based on the internal temperature of the memory chip 3320, and can execute a target refresh operation with an optimized cycle related to the cycle of normal refresh operations.

[0122] As described above, a memory device according to some example embodiments can perform normal refresh operations at temperature-dependent cycles and can provide a set of refresh management parameters determined according to temperature to the memory controller.

[0123] A memory controller according to some example embodiments can control a memory device such that a target refresh operation is performed in a timely manner based on a set of refresh management parameters according to temperature. Therefore, while the performance efficiency of the memory system can be improved, the data in the memory device can be protected from row hammering.

[0124] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope or claimable scope of any invention, but rather as descriptions of features specific to particular embodiments of a particular invention. Specific features described in this specification within the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may involve sub-combinations or variations of sub-combinations.

[0125] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A memory system, comprising: Memory device, comprising: Multiple memory regions, The candidate register set is configured to store multiple sets of candidate parameters corresponding to multiple temperature ranges. The mode register set is configured to store the temperature range and refresh management parameter set, and The control logic circuit is configured to: store a first candidate parameter set from the plurality of candidate parameter sets as a refresh management parameter set in a mode register group based on a temperature range; and The memory controller is configured as follows: The refresh management parameter set is obtained from the memory device based on the updated temperature range. The activation counts of the plurality of memory regions are counted, and The refresh management command is provided to the memory device based on the multiple activation counts and refresh management parameter sets.

2. The memory system as claimed in claim 1, wherein, The refresh management parameter set includes the initial management threshold for rolling cumulative activation, the rolling cumulative activation multiplier, and the rolling cumulative activation decrement.

3. The memory system as claimed in claim 2, wherein, The memory controller is also configured to skip providing refresh management commands based on a target refresh threshold being greater than the normal refresh interval, wherein the target refresh threshold is based on the product of the rolling cumulative activation initial management threshold and the activation time.

4. The memory system of claim 3, wherein, The memory device is also configured to perform normal refreshes on the plurality of memory regions at a period based on a temperature range.

5. The memory system of claim 3, wherein, The memory device is also configured to reduce the normal refresh cycle of the plurality of memory regions based on the increase in temperature range.

6. The memory system of claim 2, wherein, The mode register group includes: The first register region is configured to store the temperature range. The second register region is configured to store the initial management threshold and the rolling cumulative activation multiplier for rolling cumulative activation, and The third register area is configured to store the rolling cumulative activation decrement.

7. The memory system of claim 1, wherein, The memory controller is configured as follows: Provides a mode register read command for the first register region, and Receive a temperature range from a memory device based on a mode register read command, wherein a first register region is configured to store the temperature range.

8. The memory system of claim 7, wherein, The memory controller is also configured to receive a flag signal indicating that the temperature range has been updated.

9. The memory system according to any one of claims 1 to 8, wherein, Each of the plurality of memory regions includes a memory storage unit.

10. A memory controller, comprising: The refresh management circuit is configured to: provide an activation command to the memory device and count multiple activation counts for multiple memory regions of the memory device, respectively; as well as The memory is configured to store an activation count threshold. The refresh management circuit is configured as follows: Receive temperature range from memory device. The updated count threshold is received from the memory device based on the temperature range. The activation count threshold in memory is updated based on the revised count threshold to provide the updated activation count threshold, and Based on the detection of a target memory region among the plurality of memory regions, a refresh management command is provided for the target memory region, wherein the activation count of the target memory region reaches the updated activation count threshold.

11. The memory controller of claim 10, wherein, The memory is also configured to store the count decrement of the plurality of activation counts, and The refresh management circuit is also configured as follows: The temperature range-based update receives the updated count decrement from the memory device. The count decrement stored in memory is revised based on the updated count decrement to provide the revised count decrement, and Based on the refresh management command, the activation count of the target memory region is reduced by the revised count reduction.

12. The memory controller of claim 11, wherein, The refresh management circuit is configured as follows: Provides a mode register read command for the first register region of the memory device, and Receive temperature range, wherein the first register region is configured to store temperature range.

13. The memory controller of claim 11, wherein, The revised counting threshold is based on the product of the unit threshold and the multiplier value.

14. The memory controller of claim 13, wherein, The refresh management circuit is configured as follows: Provides a mode register read command for the second register region of the memory device, and Then, the unit threshold, multiplier, and updated count decrement are received from the second register area.

15. The memory controller of claim 11, wherein, The refresh management circuit is configured to disable activation commands for the target memory region based on the fact that the activation count of the target memory region has reached the updated activation count threshold.

16. A memory device, comprising: Multiple memory regions, each containing multiple memory units; The register is configured to store multiple sets of candidate parameters corresponding to multiple temperature ranges. The mode register is configured to store a first temperature range in a first register area and store a refresh management parameter set in a second register area. as well as The control logic circuit is configured as follows: Based on the first temperature range, the first candidate parameter set from the plurality of candidate parameter sets is stored as a refresh management parameter set in the second register area. The first temperature range is output based on the first read request for the first register region, and The management parameter set is refreshed based on the second read request for the second register region.

17. The memory device of claim 16, wherein, The refresh management parameter set includes the initial management threshold for rolling cumulative activation, the rolling cumulative activation multiplier, and the rolling cumulative activation decrement.

18. The memory device of claim 17, wherein, The first rolling cumulative activation initial management threshold corresponding to the first temperature range has a value that is less than or equal to the value of the second rolling cumulative activation initial management threshold corresponding to the second temperature range, wherein the second temperature range is lower than the first temperature range.

19. The memory device of claim 17, wherein, The first rolling cumulative activation decrement corresponding to the first temperature range has a value greater than or equal to the value of the second rolling cumulative activation decrement corresponding to the second temperature range, wherein the second temperature range is lower than the first temperature range.

20. The memory device of claim 16, wherein, The control logic circuit is also configured to perform a target refresh operation on the target memory region based on a refresh management command for the target memory region, wherein the target memory region is determined based on multiple activation counts and refresh management parameter sets of the plurality of memory regions.

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