Porous vcsel chip, vcsel packaging structure and preparation method thereof

Abstract

The application provides a multi-hole VCSL chip, a VCSL packaging structure and a preparation method thereof. A plurality of laser holes are formed in a single VCSL chip, and the hole spacing is large, so that the formed light beams can be more uniformly irradiated on a target object or surface, and a single VCSL chip can replace a plurality of conventional VCSL chips. Since normal power is adopted and the light beams emitted by the laser holes do not interfere with each other, the light beams are uniformly distributed, and the "red storm" phenomenon caused by the use of high-power VCSL chips in the conventional mode and the "burning screen" problem that may occur after long-term use can be effectively avoided. By controlling the number and arrangement mode of the laser holes, the packaging structure of the multi-hole VCSL chip has the same size as the conventional single VCSL packaging structure, and can achieve similar detection effects as the four VCSL packaging structures in the conventional mode. Compared with the conventional four-VCSEL structure, the size is reduced by 75%, the occupied space is significantly reduced, and the product miniaturization is facilitated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a porous VCSEEL chip, a VCSEEL packaging structure, and a method for fabricating the same. Background Technology

[0002] The proximity sensor beneath the OLED screen in a smartphone typically consists of a vertical-cavity surface-emitting laser (VCSEL) and a digital receiver. It detects the distance between the user and the phone, thus automatically turning off the display. To achieve optimal detection performance with sufficient light power, four VCSEL chips are usually arranged in a square to better distribute the light power and improve detection accuracy. However, this design occupies a significant amount of space, hindering the thinning and miniaturization of the product, posing a challenge for smartphone manufacturers pursuing thinner and more compact designs.

[0003] To address this issue, a single or two-chip solution with higher power VCSELs can be used instead of the original four VCSEL chips. Theoretically, increasing the output power of a single chip can reduce the number of chips required, thus shrinking the footprint. However, in practical applications, it has been found that while this solution does reduce the number of components and the overall space required to some extent, the excessive concentration of light spots on the display can cause red-hot or burn-in phenomena on the OLED display due to prolonged high energy density concentrated in a small area. Summary of the Invention

[0004] To overcome the above shortcomings, this invention provides a porous VCSEL chip, a VCSEL packaging structure and its preparation method. While ensuring the detection effect, it not only occupies little space, but also avoids the red glow or screen burn-in problems caused by high-power VCSELs acting on OLED displays.

[0005] The technical solution provided by this invention is as follows: On one hand, the present invention provides a porous VCSEL chip, wherein the chip structure surface of the porous VCSEL chip includes a light-emitting surface, and the surface of the light-emitting layer in the chip structure extends to the light-emitting surface to form a plurality of laser holes for emitting specific wavelengths, and the shortest distance between the outer edges of two adjacent laser holes is greater than 160 μm.

[0006] On the other hand, the present invention provides a VCSEL packaging structure for use in under-display proximity sensors, the VCSEL packaging structure comprising: The packaging substrate has conductive lines formed on its surface; As described above, a porous VCSEL chip is die-bonded onto the packaging substrate, and a Zener diode is die-bonded onto the packaging substrate in parallel with the porous VCSEL chip. A transparent protective adhesive layer is formed on the surface of the packaging substrate, encapsulating the porous VCSEL chip, Zener diode, and bonding wires.

[0007] Furthermore, this invention provides a method for fabricating a VCSEL packaging structure, applicable to under-display proximity sensors, comprising the following steps: A packaging substrate is provided, on which mutually insulated positive and negative pads are formed; The porous VCSEL chip described above is die-bonded to the negative electrode pad surface of the packaging substrate, and a Zener diode is die-bonded to the positive electrode pad surface of the packaging substrate. The porous VCSEL chip and the Zener diode are wire bonded separately. The P electrode of the light-emitting surface of the porous VCSEL chip is conductively connected to the positive electrode pad through the wire bond, and the N electrode on the upper surface of the Zener diode is conductively connected to the negative electrode pad through the wire bond. The porous VCSEL chip and the Zener diode form a parallel structure. A transparent protective adhesive layer is prepared by molding on the surface of a packaging substrate, and the transparent protective adhesive layer encapsulates the porous VCSEEL chip, Zener diode and bonding wires; The packaging substrate is cut along the preset cutting groove to obtain a single VCSEL package structure.

[0008] The porous VCSEL chip, VCSEL packaging structure, and fabrication method provided by this invention have at least the following beneficial effects: 1. A single multi-aperture VCSEL chip contains multiple laser apertures with a large aperture spacing, allowing the generated beam to be more evenly irradiated onto the target object or surface. One chip can replace multiple traditional VCSEL chips. Furthermore, because it uses normal power and the beams emitted by each laser aperture do not interfere with each other and are evenly distributed, it can effectively avoid the "red glow" phenomenon caused by using high-power VCSEL chips in traditional methods, as well as the "burn-in" problem that may occur after long-term use.

[0009] 2. When this multi-hole VCSEL chip is applied to proximity sensors under OLED displays, although the VCSEL chip contains multiple laser holes with a larger hole spacing, the area occupied by the multi-hole VCSEL chip can be minimized by controlling the number and arrangement of the laser holes. The packaging structure containing a single multi-hole VCSEL chip has the same size as the traditional single VCSEL packaging structure, while achieving a similar detection effect as the traditional four-VCSEL packaging structure. Compared with the traditional four-VCSEL structure, the size is reduced by 75%, significantly reducing the space occupied and facilitating product miniaturization. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the existing VCSEL chip structure; Figure 2 This is a top view schematic diagram of a porous VCSEL chip structure according to an embodiment of the present invention; Figure 3 This is a top view of the VCSEL packaging structure in one embodiment of the present invention; Figure 4 for Figure 3 A cross-sectional schematic diagram of the VCSEL package structure.

[0011] Figure label: 1-Packaging substrate, 11-Negative electrode pad, 12-Positive electrode pad, 2-Multi-hole VCSEL chip, 21-Laser hole, 3-Zener diode, 4-Transparent protective adhesive layer. Detailed Implementation

[0012] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0013] In one embodiment of the present invention, a porous VCSEL chip is disclosed. The chip structure surface of the porous VCSEL chip includes a light-emitting surface, and the surface of the light-emitting layer in the chip structure extends to the light-emitting surface to form multiple laser apertures for emitting specific wavelengths. The shortest distance between the outer edges of two adjacent laser apertures is greater than 160 μm. The VCSEL chip is generally a vertical structure, and the VCSEL chip structure is a multilayer structure made of multiple different materials, including two mirrors and a light-emitting layer sandwiched between the two mirrors. The multiple laser apertures extend outward from the surface of the light-emitting layer, pass through one of the mirrors, and reach the surface of the light-emitting surface, facilitating the emission of light generated in the light-emitting layer from the laser apertures. Thus, the light is emitted outward perpendicular to the light-emitting surface of the VCSEL. The mirrors are usually made of highly reflective materials, such as highly reflective distributed Bragg reflectors (DBRs).

[0014] The VCSEL chip has P-electrodes and N-electrodes formed on two surfaces, respectively, which are connected to external circuits for injecting current to drive the chip. One electrode is located above or below the light-emitting layer, while the other electrode is located on the other side of the chip. When the P-electrodes and N-electrodes in the VCSEL chip are connected to the circuit, current flows through the chip, and electrons and holes are injected into the light-emitting layer, recombine, and release energy in the form of photons. The light wave is reflected back and forth vertically in the resonant cavity formed by two mirrors and emitted vertically from the light-emitting surface of the VCSEL through the laser aperture. The laser aperture is used to emit laser light of a specific wavelength. The specific wavelength needs to be designed according to the application. For example, in one example, a multi-aperture VCSEL chip is used in an under-display proximity sensor, and its laser aperture emits a laser with a wavelength of 940nm. In this embodiment, there are multiple laser apertures in the chip structure, and each laser aperture can emit a beam of light. That is, when the VCSEL chip is connected to current, the current flows through the chip, and each laser aperture emits a laser beam with a wavelength of 940nm. Multiple beams of 940nm light can be emitted simultaneously. It should be understood that in practical applications, the laser aperture mentioned only needs to be able to emit laser light, and does not need to be a physical through hole. For example, a transparent layer can be formed above the light-emitting aperture on the surface of the light-emitting layer, as long as it does not affect the laser emission. In addition, this embodiment does not specifically limit the chip structure of the multi-hole VCSEL chip, as long as its light-emitting surface is equipped with the corresponding laser aperture. Subsequent applications can be adapted to the specific chip structure, and it can also be a flip-chip structure, etc.

[0015] like Figure 1 As shown, Figure 1 (a) For traditional single-aperture VCSEL chips, when using the normal power mode (the average optical power of a single laser aperture is 3.5mW-6mW), four VCSEL chips are required to achieve a better detection effect. When using the high power mode, the number of VCSELs is reduced compared to the normal mode, but the optical power is high. When the excessively high energy density is applied to the proximity sensor under the OLED screen, it can easily lead to red glow and screen burn-in problems on the OLED screen. Figure 1 (b) is a traditional 3-hole VCSEL chip. The three laser holes are arranged in a triangular pattern, with the center of each laser hole located at the three vertices of the triangle. Although it has more laser holes than a single-hole chip, the laser holes are arranged more compactly, and the spacing between them is generally less than 10μm. In normal power mode, multiple VCSEL chips are still required to achieve better detection results. In high power mode, the number of VCSELs is reduced compared to normal mode, which will also lead to excessively high energy density acting on a certain area of ​​the OLED screen, causing red glow and screen burn-in problems.

[0016] In this embodiment, the shortest distance between the outer edges of two adjacent laser holes is greater than 160μm, that is, the shortest straight-line distance between the edge of one laser hole and the edge of another laser hole is greater than 160μm. It should be understood that each laser hole is in the same position in the vertical direction, that is, they all extend from the surface of the light-emitting layer to the light-emitting surface, but their positions in the horizontal plane are different. That is, from the top view, the coordinates of multiple laser holes are different. When the positions of each laser hole are connected in sequence on the same horizontal plane, the pattern formed is a symmetrical figure, which may be axially symmetrical or centrally symmetrical. In this embodiment, when the multi-aperture VCSEL chip is applied to a proximity sensor, each laser aperture emits a 940nm wavelength laser, with an average single laser aperture optical power of 3.5mW-6mW. Furthermore, the distance between two adjacent laser apertures (i.e., the shortest distance between the outer edges of two adjacent laser apertures) is greater than 160μm. This large distance ensures effective detection while preventing interference between the beams emitted from adjacent laser apertures, resulting in a more uniform light spot illumination of the target object or surface. When applied to OLED displays, a normal power (average single laser aperture optical power of 3.5mW-6mW) is used. With a power of mW, it can effectively avoid the "red glow" phenomenon caused by traditional high-power VCSEL chips and the "burn-in" problem that may occur after long-term use. Moreover, due to the presence of multiple laser holes with large spacing, the light spot distribution is more dispersed and uniform. One multi-hole VCSEL chip can achieve a similar detection effect as the traditional method using four VCSEL chips (the distance between the laser hole and the side of the chip only needs to meet the VCSEL chip light emission standard), and significantly reduce the space occupied, which is conducive to product miniaturization.

[0017] The number and arrangement of laser holes within a multi-hole VCSEL chip need to be designed according to the specific requirements. Fewer laser holes result in a smaller overall chip area, but relatively poorer detection performance; more laser holes result in a larger overall chip area, but relatively better detection performance. The arrangement can form shapes such as lines, triangles, squares, and polygons. During packaging, the size of a multi-hole VCSEL chip is typically larger than that of a Zener diode. The final packaged size largely depends on the multi-hole VCSEL chip itself. Therefore, employing an appropriate number and arrangement of laser holes to minimize the chip's size is crucial. To achieve product miniaturization, the design should minimize the chip area while ensuring detection performance, which helps reduce the packaged area of ​​the multi-hole VCSEL chip. For example, a VCSEL chip with only two laser holes has lower detection accuracy than one with three laser holes, but its chip area is smaller. In practical applications, the design should be tailored to the specific application requirements.

[0018] Besides detection accuracy, light emission uniformity is also an important indicator to consider. To meet both requirements simultaneously, one could... Figure 2 As shown, four laser holes 21 are configured in the porous VCSEL chip 2. The four laser holes are arranged in a square at the center of the light-emitting surface, and are located at the four vertices of the square from a top view (the dashed lines in the figure represent the distance between two adjacent laser holes, not the physical structure). The diameter of each laser hole 21 is 15μm, and the distance d between two adjacent laser holes 21 is 200μm. That is, the side length of each side of the square is 200μm plus the radius of the two laser holes. The square formed by connecting the laser holes in sequence is both a centrally symmetric and an axially symmetric figure. The size of the VCSEL chip itself is 11mil×11mil (mil, which is 279.4μm after conversion). The average light power of each laser hole is 3.5mW-6mW. This arrangement meets the requirements of detection accuracy and light emission uniformity while making the porous VCSEL chip have the smallest area and the smallest size after packaging.

[0019] When this multi-hole VCSEL chip is applied to a proximity sensor under an OLED display, normal power is sufficient, avoiding "red glow" or burn-in issues on the OLED display. A VCSEL package structure containing only one multi-hole VCSEL chip achieves good detection results. Compared to the traditional method of using four VCSEL chips to achieve similar detection performance, this significantly reduces the space required, facilitating product miniaturization. In another example, the multi-hole VCSEL chip also has four laser holes arranged in a straight line from a top view. This arrangement can also be used in proximity sensors, but the actual size is larger than the square arrangement of four laser holes in the previous example, hindering product miniaturization.

[0020] Another embodiment of the present invention is applied to an under-display proximity sensor, wherein the VCSEL package structure includes: The packaging substrate has conductive lines formed on its surface; a porous VCSEL chip as described above is die-bonded on the packaging substrate, and a Zener diode is die-bonded on the packaging substrate in parallel with the porous VCSEL chip; a transparent protective adhesive layer is formed on the surface of the packaging substrate, encapsulating the porous VCSEL chip, the Zener diode and the bonding wires.

[0021] The packaging substrate is used to support other components in the VCSEEL package structure, and its surface is designed with corresponding conductive lines according to the actual application requirements to facilitate subsequent control of the electrical components on its surface (such as porous VCSEEL chips and Zener diodes). The packaging substrate can be made of multilayer PCB boards, copper-clad aluminum nitride ceramic substrates, etc., as long as suitable conductive lines are formed on the surface and can provide stable support for the electronic components on its surface. The design of the conductive lines should be based on the structure and performance of the components, facilitating die bonding and soldering, and ensuring that the connected electrical components can perform their corresponding functions normally. For example, the porous VCSEEL chip can emit light normally, and the Zener diode can regulate the voltage on the line to make it stable. The conductive lines used to connect the porous VCSEEL chip and the Zener diode should facilitate their parallel connection.

[0022] This package structure has only one porous VCSEL chip and one Zener diode connected in parallel with the porous VCSEL chip on its surface. The size of the porous VCSEL chip is larger than that of the Zener diode, and the overall size of the package depends mainly on the porous VCSEL chip. Therefore, to achieve product miniaturization, it is crucial to use a porous VCSEL chip with the smallest possible size. For the packaging substrate, ensuring conductivity while designing the pattern and position of the conductive lines to minimize their area also contributes to the miniaturization of both the packaging substrate and the final product.

[0023] In this embodiment, as Figure 3 and Figure 4As shown, the conductive lines formed on the surface of the packaging substrate include a negative electrode pad 11 and a positive electrode pad 12 that are insulated from each other. There is an insulating material between the negative electrode pad 11 and the positive electrode pad 12 to isolate them from each other. The porous VCSEL chip and Zener diode used are both vertical structure chips, that is, the P electrode and the N electrode are respectively set on opposite surfaces. The porous VCSEL chip 2 is die-bonded to the surface of the negative electrode pad 11, the N electrode on the lower surface is conductively connected to the negative electrode pad, and the P electrode on the light-emitting surface is conductively connected to the positive electrode pad 12 through a bonding wire. The Zener diode 3 is die-bonded to the surface of the positive electrode pad 12, the P electrode on the lower surface is conductively connected to the positive electrode pad, and the N electrode on the upper surface is conductively connected to the negative electrode pad 11 through a bonding wire. The porous VCSEL chip and Zener diode are fixed to the positive and negative electrode pads, respectively. The electrode on the lower surface (P or N electrode) is connected to the corresponding pad on the substrate, while the electrode on the upper surface (with opposite polarity to the lower surface electrode) is connected to the corresponding pad on the lower surface of the other device via a bonding wire. This achieves parallel connection of the two devices between the positive and negative electrode pads. The transparent protective adhesive layer 4 on the surface of the packaging substrate 1 completely encapsulates the porous VCSEL chip 2 and Zener diode 3, covering their sides and upper surfaces. The bonding wire is also encapsulated in the transparent protective adhesive layer. The transparent protective adhesive layer protects the internal porous VCSEL chip 2 and Zener diode 3, possessing certain mechanical strength and chemical stability to prevent damage or performance degradation caused by external environmental factors such as dust and moisture. Being a transparent insulating material, it does not affect light emission or the internal electrical structure and can be made from colorless and transparent resin materials.

[0024] For packaging substrates, ensuring conductivity while minimizing the area occupied by the pad patterns and positions also contributes to the miniaturization of the packaging substrate and the final product. In this embodiment, the pads include a chip area for die bonding and a soldering area for wire bonding. The negative pad includes a first chip area for die bonding of the porous VCSEL chip and a first soldering area for Zener diode wire bonding. The positive pad includes a second chip area for die bonding of the Zener diode and a second soldering area for bonding the porous VCSEL chip wire bonding. To facilitate die bonding, the size of the first chip area is designed to match the size of the porous VCSEL chip, and the size of the second chip area is designed to match the size of the Zener diode. Both the first soldering area and the second pad area extend towards the insulating region between the first chip area and the second chip area.

[0025] Since the size of the packaged structure mainly depends on the porous VCSEL chip, in this example, a porous VCSEL chip with four laser holes arranged in a square, as described above, was selected. This porous VCSEL chip meets the requirements of detection accuracy and light emission uniformity while minimizing its area. Figure 3 As shown, the selected porous VCSEL chip contains four square laser holes, which occupy a small area and provide good detection performance. The packaging substrate 1 also has the smallest possible size. The negative electrode pad 11 is located on the left side of the packaging substrate, with the first chip area below for die bonding of the porous VCSEL chip 2, and the first welding area above it. The first welding area is more to the right relative to the first chip area, which facilitates die bonding of the Zener diode wires on the right side. The positive electrode pad 12 is located on the right side of the packaging substrate, with the second chip area above it for die bonding of the Zener diode 3, and the second welding area below it. The second welding area is more to the left relative to the second chip area, which facilitates die bonding of the porous VCSEL chip wires on the left side. That is, the first welding area in the negative electrode pad and the second welding area in the positive electrode pad both extend into the insulating area between the two pads.

[0026] In this embodiment, the laser holes of the multi-hole VCSEL chip and the arrangement of the pads on the packaging substrate are designed to minimize its size. The overall length of the VCSEL packaging structure is no greater than 1.0 mm, and the overall width is no greater than 0.5 mm. Figure 3 As shown, the length x is 1.0mm and the width y is 0.5mm, which is basically the same as the package size of a traditional single VCSEL chip. That is, the multi-hole VCSEL chip used has multiple laser holes and a large hole spacing, so the size of the multi-hole VCSEL chip itself (approximately 11mil × 11mil) is slightly larger than the size of a traditional single VCSEL chip (approximately 6mil × 6mil). However, the final VCSEL package structure is consistent with the size of a traditional single VCSEL package. Without high power, a single VCSEL package structure can achieve a detection effect similar to the four VCSEL structure used in the traditional method. It avoids the red glow and screen burn-in problems in high power mode, as well as the problem of large space occupation caused by using multiple VCSEL structures in normal power mode. Compared with the traditional four VCSEL structure, the size is reduced by 75%.

[0027] Another embodiment of the present invention discloses a method for fabricating a VCSEL packaging structure, applied to an under-display proximity sensor, comprising the following steps: S01 provides a packaging substrate with mutually insulated positive and negative pads formed on its surface.

[0028] The packaging substrate is used to support other components in the VCSEL package structure. Its surface is designed with mutually insulated positive and negative pads according to the actual application requirements, facilitating subsequent control of the electrical components on its surface (such as porous VCSEL chips and Zener diodes). The packaging substrate can be made of multilayer PCB boards, copper-clad aluminum nitride ceramic substrates, etc., as long as suitable positive and negative pads are formed on the surface to provide stable support for the electronic components. The design of the positive and negative pads should be based on the structure and performance of the components, facilitating die bonding and soldering, and ensuring that the connected electrical components can perform their corresponding functions. For example, porous VCSEL chips should emit light normally, and Zener diodes should regulate and stabilize the voltage on the circuit. The pads used to connect porous VCSEL chips and Zener diodes should facilitate parallel connection between them. For the packaging substrate, while ensuring conductivity, designing the pattern and position of the pads to minimize their area also contributes to the miniaturization of the packaging substrate and the final product.

[0029] In this embodiment, the pads include a chip region for die bonding and a welding region for wire bonding. The negative pad includes a first chip region for die bonding of the porous VCSEL chip and a first welding region for welding Zener diode wires. The positive pad includes a second chip region for die bonding of the Zener diode and a second welding region for welding porous VCSEL chip wires. To facilitate die bonding, the size of the first chip region is designed to match the size of the porous VCSEL chip, and the size of the second chip region is designed to match the size of the Zener diode. Both the first welding region in the negative pad and the second welding region in the positive pad extend into the insulating region between the two pads.

[0030] S02 involves die bonding the aforementioned porous VCSEL chip to the negative electrode pad surface of the packaging substrate, and simultaneously die bonding a Zener diode to the positive electrode pad surface of the packaging substrate. An insulating material separates the negative and positive electrode pads on the packaging substrate surface, isolating them from each other. The porous VCSEL chip and Zener diode are fixed to the positive and negative electrode pad surfaces, respectively. The electrode (P-pole or N-pole) on the lower surface is connected to the corresponding pad on the substrate, while the electrode on the upper surface (with the opposite polarity to the lower surface electrode) is connected via a bonding wire to the corresponding pad on the lower surface of the other device. This achieves parallel connection of the two devices between the positive and negative electrode pads.

[0031] S03 performs wire bonding on the porous VCSEL chip and the Zener diode respectively. The P electrode of the light-emitting surface of the porous VCSEL chip is conductively connected to the positive electrode pad through the wire bonding, and the N electrode on the upper surface of the Zener diode is conductively connected to the negative electrode pad through the wire bonding. The porous VCSEL chip and the Zener diode form a parallel structure. In this example, the size of the porous VCSEL chip is larger than that of the Zener diode. The packaged size mainly depends on the porous VCSEL chip. Therefore, to achieve product miniaturization, it is crucial to use an appropriate number and arrangement of laser holes to reduce the size of the porous VCSEL chip. Since the packaged structure size mainly depends on the porous VCSEL chip, in this example, a porous VCSEL chip with four laser holes arranged in a square, as described above, was selected. This porous VCSEL chip meets the requirements for detection accuracy and light emission uniformity while minimizing the chip area. Figure 3 As shown, the porous VCSEL chip 2 is die-bonded to the surface of the negative electrode pad, the N electrode on the lower surface is connected to the negative electrode pad, and the P electrode on the upper surface is connected to the corresponding positive electrode pad on the lower surface of the Zener diode 3 via a bonding wire; the Zener diode 3 is die-bonded to the surface of the positive electrode pad, the P electrode on the lower surface is connected to the positive electrode pad, and the N electrode on the upper surface is connected to the corresponding negative electrode pad on the lower surface of the porous VCSEL chip via a bonding wire; in this way, the porous VCSEL chip 2 and the Zener diode 3 are connected in parallel between the positive and negative electrode pads, which helps the Zener diode maintain the voltage stability on the circuit and ensures that the porous VCSEL chip can work under a stable voltage.

[0032] S04 involves molding a transparent protective layer onto the surface of the packaging substrate. This layer encapsulates the porous VCSEL chip, Zener diode, and bonding wires. The transparent protective layer is molded using a pre-designed mold pressed onto the surface of the packaging substrate. A liquid or semi-solid transparent material is injected into the mold, and then cured under appropriate pressure and temperature conditions, depending on the material's properties. After curing, the mold is removed. The transparent protective layer completely encapsulates the porous VCSEL chip and Zener diode on the substrate, covering their sides and top surfaces. The bonding wires are also encapsulated within the transparent protective layer. This layer can be made of a colorless and transparent resin material, serving to protect the internal porous VCSEL chip and Zener diode without affecting light emission.

[0033] S05 cuts the packaging substrate along the preset cutting groove to obtain a single VCSEL packaging structure.

[0034] This embodiment minimizes the size of the multi-hole VCSEL chip by designing the arrangement of the laser holes and pads on the packaging substrate. The resulting single VCSEL package structure has a length of 1.0 mm and a width of 0.5 mm, which is basically the same as the package size of a traditional single VCSEL chip. While the multi-hole VCSEL chip using light has multiple laser holes with a relatively large hole spacing, resulting in a slightly larger size (approximately 11 mil × 11 mil) than a traditional single VCSEL chip (approximately 6 mil × 6 mil), the final VCSEL package structure is the same size as a traditional single VCSEL package. This single VCSEL package structure achieves a similar detection effect to the traditional four-VCSEL structure without requiring high power, avoiding red-light and burn-in issues in high-power mode and the space-consuming problem of multiple VCSEL structures in normal power mode. Compared to the traditional four-VCSEL structure, the size is reduced by 75%.

[0035] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-hole VCSEL chip, characterized in that, The surface of the porous VCSEL chip includes a light-emitting surface, and the surface of the light-emitting layer in the chip structure extends to the light-emitting surface to form multiple laser holes for emitting specific wavelengths. The shortest distance between the outer edges of two adjacent laser holes is greater than 160 μm.

2. The multi-hole VCSER chip as described in claim 1, characterized in that, The laser aperture in the porous VCSEL chip emits a laser with a wavelength of 940nm.

3. The multi-hole VCSEL chip as described in claim 1 or 2, characterized in that, The porous VCSEL chip has four laser holes, which are arranged in a square shape in the middle of the light-emitting surface.

4. A VCSEL packaging structure, characterized in that, The VCSEL package structure, used in under-display proximity sensors, includes: The packaging substrate has conductive lines formed on its surface; A porous VCSEL chip as described in any one of claims 1-3 is die-bonded on the packaging substrate, and a Zener diode is die-bonded on the packaging substrate in parallel with the porous VCSEL chip. A transparent protective adhesive layer is formed on the surface of the packaging substrate, encapsulating the porous VCSEL chip, Zener diode, and bonding wires.

5. The VCSEL packaging structure as described in claim 4, characterized in that, The conductive lines formed on the surface of the packaging substrate include mutually insulated positive and negative pads. The porous VCSEEL chip and Zener diode are vertical structure chips. The porous VCSEL chip is die-bonded to the surface of the negative electrode pad, and the P electrode of the light-emitting surface is conductively connected to the positive electrode pad through a bonding wire; the Zener diode is die-bonded to the surface of the positive electrode pad, and the N electrode on the upper surface is conductively connected to the negative electrode pad through a bonding wire.

6. The VCSEL packaging structure as described in claim 5, characterized in that, The size of the porous VCSEEL chip is larger than the size of the Zener diode; The surface of the packaging substrate includes a negative electrode pad comprising a first chip region for die bonding of the porous VCSEL chip and a first welding region for bonding Zener diode wires; and a positive electrode pad comprising a second chip region for die bonding of the Zener diode and a second welding region for bonding porous VCSEL chip wires. The size of the first chip region matches the size of the porous VCSEL chip, the size of the second chip region matches the size of the Zener diode, and both the first welding region and the second electrode pad region extend toward the insulating region between the first chip region and the second chip region.

7. The VCSEL packaging structure as described in claim 4, 5, or 6, characterized in that, The transparent protective adhesive layer is made of colorless and transparent resin material.

8. The VCSEL packaging structure as described in claim 4, 5, or 6, characterized in that, The overall length of the VCSEL package structure is no more than 1.0 mm, and the overall width is no more than 0.5 mm.

9. A method for fabricating a VCSEL packaging structure, characterized in that, The application to under-display proximity sensors includes the following steps: A packaging substrate is provided, on which mutually insulated positive and negative pads are formed; The porous VCSEL chip as described in any one of claims 1-3 is die-bonded to the surface of the negative electrode pad of the packaging substrate, and a Zener diode is die-bonded to the surface of the positive electrode pad of the packaging substrate. The porous VCSEL chip and the Zener diode are wire bonded separately. The P electrode of the light-emitting surface of the porous VCSEL chip is conductively connected to the positive electrode pad through the wire bond, and the N electrode on the upper surface of the Zener diode is conductively connected to the negative electrode pad through the wire bond. The porous VCSEL chip and the Zener diode form a parallel structure. A transparent protective adhesive layer is prepared by molding on the surface of a packaging substrate, and the transparent protective adhesive layer encapsulates the porous VCSEEL chip, Zener diode and bonding wires; The packaging substrate is cut along the preset cutting groove to obtain a single VCSEL package structure.

10. The method for fabricating the VCSEL packaging structure as described in claim 9, characterized in that, The overall length of the VCSEL package structure is no more than 1.0 mm, and the overall width is no more than 0.5 mm.

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