Circuit board and manufacturing method thereof

Abstract

A circuit board comprises at least two circuit structures, at least two electroplated layers, a plurality of air holes and two protective layers. One of the at least two circuit structures includes a first conductive layer, a first dielectric layer, a plurality of conductive elements, a first adhesive layer, a second adhesive layer, a second dielectric layer, a second conductive layer, a third adhesive layer, a third dielectric layer and a third conductive layer. The first dielectric layer is located between the first conductive layer and the plurality of conductive elements. The second adhesive layer is arranged on the first adhesive layer. The second dielectric layer is located between the second adhesive layer and the second conductive layer. The third dielectric layer is located between the third adhesive layer and the third conductive layer. The at least two electroplated layers respectively cover the at least two circuit structures. A plurality of pores are formed in the second conductive layer and the at least two electroplated layers. The two protective layers cover the at least two electroplated layers and the plurality of air holes. Therefore, the process is simplified.

Description

Technical Field

[0001] This application relates to a circuit board and a method for manufacturing the same, and more particularly to a circuit board and a method for manufacturing the same that eliminates the need for surface treatment processes and reduces manufacturing costs. Background Technology

[0002] In existing high-speed transmission solutions, differential lines offer significant advantages: strong anti-interference capabilities, effectively canceling external electromagnetic interference; reduced electromagnetic radiation, complying with electromagnetic compatibility (EMC) standards; support for higher data rates and better common-mode noise suppression; lower power consumption; and ease of implementation of balanced drive and simplified termination matching. These characteristics make them one of the preferred solutions in high-performance electronic systems.

[0003] However, with the increasing frequency of use of terminal products and the increasingly stringent requirements for signal integrity, commonly used mass-producible high-frequency materials are gradually becoming insufficient to meet the demands. Simultaneously, end-customers' demands for product miniaturization and lightweighting have significantly increased the difficulty of installation. The following are some technical challenges: First, excessive wiring density. Existing differential transmission lines require a ground wire (GND) between each pair of lines for isolation. While this effectively achieves isolation between lines, it leads to a larger overall wiring area, making high-density installation difficult. Second, air-cable installation. Since simply replacing the high-frequency materials may not meet the requirements of terminal transmission specifications, an air-cable transmission solution has been proposed. This solution promises better transmission performance. However, this approach also has some drawbacks. The air-cable needs to be supported by GND, and the metal layer inside the air-cable must undergo surface treatment to prevent oxidation, such as electroless nickel / immersion gold (ENIG) or organic solderability preservative (OSP). These additional processing steps increase the product's cost and manufacturing complexity.

[0004] Therefore, how to improve circuit board performance while reducing costs and simplifying processes remains a pressing technical challenge for the industry. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a circuit board that can improve its performance while effectively reducing costs and simplifying the process.

[0006] One embodiment of this application provides a circuit board comprising at least two circuit structures, at least two electroplated layers, a plurality of pores, and two protective layers. The at least two circuit structures are arranged at intervals, and each of the at least two circuit structures includes a first conductive layer, a first dielectric layer, a plurality of conductive elements, a first adhesive layer, a second adhesive layer, a second dielectric layer, a second conductive layer, a third adhesive layer, a third dielectric layer, and a third conductive layer. The first dielectric layer is disposed on the surface of the first conductive layer. The plurality of conductive elements are spaced apart on the surface of the first dielectric layer, and the first dielectric layer is located between the first conductive layer and the plurality of conductive elements. The first adhesive layer covers the plurality of conductive elements and the surface of the first dielectric layer located between the plurality of conductive elements. The second adhesive layer is disposed on the surface of the first adhesive layer, and the first adhesive layer is located between the second adhesive layer and the first dielectric layer. The second dielectric layer is disposed on the surface of the second adhesive layer, and the second adhesive layer is located between the second dielectric layer and the first adhesive layer. The second conductive layer is disposed on the surface of the second dielectric layer, and the second dielectric layer is located between the second adhesive layer and the second conductive layer. The third adhesive layer is disposed on the other surface of the first conductive layer, and the first conductive layer is located between the first dielectric layer and the third adhesive layer. The third dielectric layer is disposed on the surface of the third adhesive layer, and the third adhesive layer is located between the first conductive layer and the third dielectric layer. The third conductive layer is disposed on the surface of the third dielectric layer, and the third dielectric layer is located between the third adhesive layer and the third conductive layer. The at least two electroplated layers respectively cover the at least two circuit structures. The plurality of pores are formed in the second conductive layer and the at least two electroplated layers. The two protective layers cover the at least two electroplated layers and the plurality of pores, and the at least two electroplated layers and the at least two circuit structures are located between the two protective layers. The second adhesive layer has a hollow portion, forming a cavity between the first adhesive layer, the second adhesive layer, and the second dielectric layer.

[0007] In some embodiments, the height of the cavity is between 15 μm and 100 μm.

[0008] In some embodiments, the circuit board further includes two adhesive layers disposed between the two protective layers and the at least two electroplated layers.

[0009] In some embodiments, the materials of the two protective layers are selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer.

[0010] In some embodiments, the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene, and hydrocarbon polymer.

[0011] In some embodiments, each of the at least two circuit structures further includes a protective layer disposed between the first adhesive layer and the second adhesive layer, and the material of the protective layer is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer.

[0012] In some embodiments, the circuit board further includes at least two static regions and at least one bending region. The at least two static regions are arranged at intervals. The at least one bending region is located between the at least two static regions. The cavity and the plurality of vents are located in each of the at least two static regions, and one side of the cavity in each of the at least two static regions has a retention distance from the adjacent at least one bending region.

[0013] Another embodiment of this application provides a method for manufacturing a circuit board, comprising the following steps: A first dielectric layer is disposed on the surface of a first conductive layer. A plurality of conductive elements are spaced apart on the surface of the first dielectric layer, with the first dielectric layer located between the first conductive layer and the plurality of conductive elements. A first adhesive layer is applied to cover the plurality of conductive elements and the surface of the first dielectric layer located between the plurality of conductive elements to form a first multilayer structure. A second dielectric layer is disposed on the surface of a second conductive layer. A second adhesive layer is disposed on the surface of the second dielectric layer, with the second dielectric layer located between the second adhesive layer and the second conductive layer to form a second multilayer structure. A third dielectric layer is disposed on the surface of a third conductive layer. A third adhesive layer is disposed on the surface of the third dielectric layer, with the third dielectric layer located between the third adhesive layer and the third conductive layer to form a third multilayer structure. The first multilayer structure, the second multilayer structure, and the third multilayer structure are pressed together, such that the first adhesive layer and the second adhesive layer are positioned opposite each other, and the second multilayer structure is located between the first multilayer structure and the third multilayer structure to form a circuit structure. The circuit structure is covered by an electroplated layer, and a second conductive layer and the electroplated layer form multiple pores to form an electroplated circuit structure. At least two of the electroplated circuit structures are arranged in an array. The at least two electroplated circuit structures are covered by two protective layers, with the at least two electroplated circuit structures located between the two protective layers, to obtain the circuit board. The second adhesive layer has a cutout portion, forming a cavity between the first adhesive layer, the second adhesive layer, and the second dielectric layer.

[0014] In some embodiments, before covering the at least two electroplated circuit structures with the two protective layers, the at least two electroplated circuit structures are first covered with two adhesive layers, such that the two adhesive layers are respectively located between the two protective layers and the at least two electroplated layers.

[0015] In some embodiments, before pressing the first layer, the second layer, and the third layer together, a protective layer is first disposed on the surface of the first adhesive layer, and after pressing, the protective layer is located between the first adhesive layer and the second adhesive layer. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of a circuit board according to one embodiment of this application;

[0017] Figure 2 This is a cross-sectional schematic diagram of a circuit board according to another embodiment of this application;

[0018] Figure 3 This is a schematic flowchart illustrating a method for manufacturing a circuit board according to one embodiment of this application.

[0019] Figure 4 A schematic flowchart illustrating a method for manufacturing a circuit board according to another embodiment of this application;

[0020] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a circuit board according to another embodiment of this application.

[0021] Figure 6 Comparison graphs of insertion loss simulation data for two embodiments of this application and prior art circuit boards; and

[0022] Figure 7 This is a partial schematic diagram of a circuit board according to another embodiment of this application. Detailed Implementation

[0023] The following application provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements, values, operations, materials, configurations, and the like are described below to simplify this application. Of course, these are merely examples and are not intended to be limiting. Other elements, values, operations, materials, configurations, and the like should also be considered. For example, in the following description, forming a first feature over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or words may be repeated in various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0024] In the following text, to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, and depth) of elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the size and shape of the elements, but should cover the dimensions, shapes, and deviations thereof caused by actual manufacturing steps and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of this application are mainly for illustration and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the claims of this application.

[0025] Please see Figure 1 ,in Figure 1 This is a cross-sectional schematic diagram of a circuit board 100 according to one embodiment of this application. In some embodiments of this application, the circuit board 100 includes at least two circuit structures 110, at least two electroplated layers 120, a plurality of vents AH, and two protective layers 130.

[0026] In detail, each of the at least two circuit structures 110 includes a first conductive layer 111, a first dielectric layer 112, a plurality of conductive elements 113, a first adhesive layer 114, a second adhesive layer 115, a second dielectric layer 116, a second conductive layer 117, a third adhesive layer 171, a third dielectric layer 172, and a third conductive layer 173. The first dielectric layer 112 is disposed on the surface of the first conductive layer 111. The plurality of conductive elements 113 are spaced apart on the surface of the first dielectric layer 112, and the first dielectric layer 112 is located between the first conductive layer 111 and the plurality of conductive elements 113. The first adhesive layer 114 covers the plurality of conductive elements 113 and the surface of the first dielectric layer 112 located between the plurality of conductive elements 113. The second adhesive layer 115 is disposed on the surface of the first adhesive layer 114, and the first adhesive layer 114 is located between the second adhesive layer 115 and the first dielectric layer 112. A second dielectric layer 116 is disposed on the surface of a second adhesive layer 115, and the second adhesive layer 115 is located between the second dielectric layer 116 and the first adhesive layer 114. A second conductive layer 117 is disposed on the surface of a second dielectric layer 116, and the second dielectric layer 116 is located between the second adhesive layer 115 and the second conductive layer 117. A third adhesive layer 171 is disposed on the other surface of a first conductive layer 111, and the first conductive layer 111 is located between a first dielectric layer 112 and the third adhesive layer 171. A third dielectric layer 172 is disposed on the surface of a third adhesive layer 171, and the third adhesive layer 171 is located between the first conductive layer 111 and the third dielectric layer 172. A third conductive layer 173 is disposed on the surface of a third dielectric layer 172, and the third dielectric layer 172 is located between the third adhesive layer 171 and the third conductive layer 173.

[0027] At least two circuit structures 110 are arranged at intervals, and at least two electroplated layers 120 respectively cover at least two circuit structures 110. That is, the electroplated layers 120 may cover the surface of the first conductive layer 111 away from the first dielectric layer 112, the surface of the second conductive layer 117 away from the second dielectric layer 116, and the sides of the circuit structures 110, but this application is not limited to the coverage area of ​​the electroplated layers 120. A plurality of pores AH are formed on the second conductive layer 117 and the at least two electroplated layers 120. Two protective layers 130 cover the at least two electroplated layers 120 and the plurality of pores AH, and the at least two electroplated layers 120 and the at least two circuit structures 110 are located between the two protective layers 130.

[0028] It should be noted that, in Figure 1 Although only two circuit structures 110 and two electroplating layers 120 are shown in the embodiment, in the actual manufacturing process, the number of circuit structures 110 and electroplating layers 120 can be increased as needed, and each of the circuit structures 110 and each of the electroplating layers 120 can have the same or similar structural settings. Therefore, this application is not limited to the number and form of the circuit structures 110 and electroplating layers 120.

[0029] The aforementioned second adhesive layer 115 has a cutout (not labeled), forming a cavity 140 between the first adhesive layer 114, the second adhesive layer 115, and the second dielectric layer 116. Compared to the prior art, the cavity 140 has no exposed metal layer (i.e., conductive element 113), thereby reducing surface treatment steps and further lowering costs. This structure not only improves process efficiency but also helps reduce unnecessary process steps, achieving more cost-effective production. Furthermore, the height of the cavity 140 is between 15 μm and 100 μm. This allows for improved circuit transmission efficiency, reduced losses, and increased product stability without affecting electrical performance. Additionally, it helps simplify the process and control costs.

[0030] Therefore, by setting up the multiple air holes AH, the phenomenon of board explosion caused by the expansion of water vapor inside cavity 140 due to heat can be avoided in subsequent high-temperature processes (such as reflow soldering).

[0031] Please continue reading. Figure 1The first conductive layer 111 and the second conductive layer 117 can be made of copper foil, aluminum foil, beryllium copper alloy foil, or other flexible conductive films. Adhesives can be used to bond the first conductive layer 111 to the first dielectric layer 112 and the second dielectric layer 116 to the second conductive layer 117. The materials of the first dielectric layer 112, the second dielectric layer 116, and the third dielectric layer 172 are selected from the group consisting of polyimide (PI), modified polyimide (MPI), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and hydrocarbon polymer (HCP). These materials all have excellent electrical properties, and the specific material selection will be determined based on factors such as the structural requirements of the circuit board 100, the application scenario, and cost. This flexibility in material selection not only ensures high performance and high reliability but also allows for adjustments based on different application requirements, thereby achieving optimal cost-effectiveness.

[0032] In detail, the first adhesive layer 114 and the second adhesive layer 115 need to be dried and fully cured after pressing. This treatment helps to improve the bonding strength and stability of the adhesive layers. Complete curing ensures that no delamination or deformation will occur under high temperature or mechanical stress, thereby enhancing the reliability and durability of the overall structure and extending the service life of the circuit board 100. Furthermore, although this application describes the first adhesive layer 114 and the second adhesive layer 115, in actual structures, the first adhesive layer 114 and the second adhesive layer 115 can also be a single adhesive layer, meaning there may be no obvious delamination between them, or the structure of the first adhesive layer 114 and the second adhesive layer 115 can be completed simultaneously through a single-layer structure. Therefore, this application is not limited to this.

[0033] The electroplated layer 120 is made of copper, but is not limited to this. Copper has high flexibility, allowing it to be bent and shaped, meeting the needs of high-density and complex configurations. It is worth noting that the number of electroplated layers 120 in this application depends on the number of circuit structures 110. Therefore, the electroplated layer 120 has good conductivity, corrosion resistance, and high processing flexibility, while also providing relatively economical cost-effectiveness.

[0034] The two protective layers 130 are made of materials selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene, and hydrocarbon polymers. This selection of materials provides strong protective performance, adapts to various working environments, and meets the requirements of high efficiency and high reliability.

[0035] Furthermore, both the second dielectric layer 116 and the protective layer 130 covering the multiple pores AH are polymer network cross-linked structures, rather than dense film materials. This allows gases (such as water vapor) to penetrate the second dielectric layer 116 from within the cavity 140 and flow out through the multiple pores AH and the protective layer 130.

[0036] In some embodiments, the circuit board 100 may further include two adhesive layers 150, which are respectively disposed between the two protective layers 130 and the at least two electroplated layers 120. The adhesive layers 150 may be made of epoxy resin or other materials with good adhesion and stability, such as polyurethane (PU). These materials have excellent bonding properties, effectively ensuring a stable bond between the layers and preventing interlayer detachment or separation.

[0037] Please see Figure 2 ,in Figure 2 This is a cross-sectional view of a circuit board 100a according to another embodiment of this application. The circuit board 100a includes at least two circuit structures 110, at least two electroplated layers 120, and two protective layers 130. However, in this embodiment, each of the at least two circuit structures 110 further includes a protective layer 160, which is disposed between a first adhesive layer 114 and a second adhesive layer 115. The remaining components and structural configurations are the same as or similar to those in the above embodiment, and therefore will not be described again. Furthermore, the material of the protective layer 160 is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene, and hydrocarbon polymers. Therefore, the provision of the protective layer 160 not only improves the reliability and durability of the overall structure but also extends the service life of the circuit board 100a, especially in harsh working environments, ensuring the stability and safety of the circuit.

[0038] Please see Figure 3 ,in Figure 3 This is a schematic flowchart of a circuit board manufacturing method 200 according to an embodiment of this application. The circuit board manufacturing method 200 includes steps 201, 202, 203, 204, 205, 206, 207, 208, 209, 210 and 211.

[0039] Step 201: Deposit a first dielectric layer on the surface of the first conductive layer; in this step, the material of the first dielectric layer is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer. The first conductive layer may be copper foil, aluminum foil, beryllium copper alloy foil or other flexible conductive films.

[0040] Step 202: A plurality of conductive elements are spaced apart on the surface of the first dielectric layer, and the first dielectric layer is located between the first conductive layer and the plurality of conductive elements; in this step, the plurality of conductive elements are signal lines and ground lines.

[0041] Step 203: Cover the plurality of conductive elements and the surface of the first dielectric layer located between the plurality of conductive elements with the first adhesive layer to form a first multilayer structure; in this step, the first adhesive layer is selected from resin materials, such as epoxy resin, polyimide resin, etc.

[0042] Step 204: Deposit a second dielectric layer on the surface of the second conductive layer; in this step, the material of the second dielectric layer is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer. The second conductive layer can be selected from copper foil, aluminum foil, beryllium copper alloy foil or other flexible conductive films.

[0043] Step 205: A second adhesive layer is disposed on the surface of the second dielectric layer, and the second dielectric layer is located between the second adhesive layer and the second conductive layer to form a second multilayer structure; in this step, the second adhesive layer is made of resin material, such as epoxy resin, polyimide resin, etc.

[0044] Step 206: Deposit a third dielectric layer on the surface of the third conductive layer; in this step, the material of the third dielectric layer is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer. The third conductive layer can be selected from copper foil, aluminum foil, beryllium copper alloy foil or other flexible conductive films.

[0045] Step 207: A third adhesive layer is disposed on the surface of the third dielectric layer, and the third dielectric layer is located between the third adhesive layer and the third conductive layer to form a third multilayer structure; in this step, the third adhesive layer is made of resin material, such as epoxy resin, polyimide resin, etc.

[0046] Step 208: Press the first, second, and third composite structures together, so that the first and second adhesive layers are positioned opposite each other, and the second composite structure is located between the first and third composite structures to form a circuit structure. In this step, the first, second, and third adhesive layers need to be dried and fully cured after pressing. Typically, pressure is applied at high temperature to melt the first, second, and third adhesive layers and firmly bond them together. The second adhesive layer has a hollow portion, forming a cavity between the first, second, and third adhesive layers and the second dielectric layer. The height of the cavity is between 15 μm and 100 μm.

[0047] Step 209: The circuit structure is covered with an electroplating layer, and the second conductive layer and the electroplating layer form multiple pores to form an electroplated circuit structure; in this step, copper is selected for electroplating, but it is not limited to this.

[0048] Step 210: Arrange at least two of the electroplating circuit structures; in this step, the at least two electroplating circuit structures are arranged at intervals.

[0049] Step 211: Cover the at least two electroplated circuit structures with two protective layers, and the at least two electroplated circuit structures are located between the two protective layers to obtain the circuit board; in this step, the material of the two protective layers is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer.

[0050] Please see Figure 4 ,in Figure 4 This is a schematic flowchart of a circuit board manufacturing method 300 according to another embodiment of this application. The circuit board manufacturing method 300 includes steps 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, and 312. However, in this embodiment, in step 311, the at least two electroplated circuit structures are first covered with two adhesive layers, and then in step 312, the at least two electroplated circuit structures are covered with two protective layers; that is, the two adhesive layers are covered with two protective layers respectively. This ensures that the two adhesive layers are located between the two protective layers and the at least two electroplated layers, and that the at least two electroplated circuit structures are also located between the two protective layers, thereby obtaining a circuit board. In step 311, the material of the adhesive layer 150 can be epoxy resin or other materials with good adhesion and stability, such as polyurethane. Steps 301, 302, 303, 304, 305, 306, 307, 308, 309, and 310 have the same or similar details as steps 201, 202, 203, 204, 205, 206, 207, 208, 209, and 210 mentioned above, and will not be repeated here. This enhances the structural stability of the multilayer structure, effectively bonds the layers and prevents interlayer separation, thereby improving overall reliability and durability, especially providing stronger anti-interference capabilities and extending service life in harsh environments.

[0051] Please see Figure 5 ,in Figure 5This is a schematic flowchart of a circuit board manufacturing method 400 according to another embodiment of this application. The circuit board manufacturing method 400 includes steps 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, and 412. However, in step 408 of this embodiment, a protective layer is disposed on the surface of the first adhesive layer, and after lamination, the protective layer is located between the first adhesive layer and the second adhesive layer. In step 408, the material of the protective layer is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene, and hydrocarbon polymers. Steps 401, 402, 403, 404, 405, 406, 407, 409, 410, 411, and 412 have the same or similar details as steps 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, and 211 mentioned above, and will not be repeated here. Therefore, by placing the protective layer between the first and second adhesive layers in step 408, not only is the structural stability, reliability, and electrical performance of the circuit board improved, but it also provides significant advantages in enhancing anti-interference capabilities, extending service life, and adapting to harsh working environments. It is particularly suitable for high-end electronic applications with high performance and high reliability requirements.

[0052] Please see Figure 1 , Figure 2 and Figure 6 ,in Figure 6 This is a comparison chart of simulation data for insertion loss of two embodiments of this application and prior art circuit boards. Figure 6 In the diagram, the horizontal axis represents frequency (in GHz), the vertical axis represents decibels (in dB), and the three comparison lines M1, M2, and M3 represent different circuit boards. Specifically, comparison line M1 represents the insertion loss simulation data of existing circuit boards, comparison line M2 represents... Figure 1 The insertion loss simulation data of the circuit board 100 in one embodiment is compared with the line M2 representing... Figure 2 Simulation data for the insertion loss of circuit board 100a in one embodiment of the implementation method. It is worth noting that negative values ​​represent signal transmission loss; the larger the negative value, the greater the loss. Figure 6 The insertion loss (negative dB value) of the comparison line M1 is higher than that of the comparison lines M2 and M3, which means that the signal loss of the circuit board in the prior art is relatively significant. Therefore, the circuit board and its manufacturing method proposed in this application can achieve higher density and higher performance differential transmission requirements without relying on too many complex materials and processes, and significantly improve the insertion loss performance.

[0053] Please see Figure 7 ,in Figure 7 This is a partial schematic diagram of circuit board 100b according to another embodiment of this application. Figure 7 The diagram only shows a portion of the circuit structure of circuit board 100b, which, from top to bottom, consists of a second conductive layer 117, a second dielectric layer (not shown), a second adhesive layer 115, a first adhesive layer 114, a conductive element 113, a first dielectric layer 112, and a first conductive layer 111. In this application, circuit board 100b may further include at least two static regions SA and at least one bending region BA. The at least two static regions SA are arranged at intervals. The at least one bending region BA is located between the at least two static regions SA. The cavity 140 and the plurality of vents AH are located in each of the at least two static regions SA, and one side of the cavity 140 in each of the at least two static regions SA has a retention distance L between it and the adjacent at least one bending region BA. The retention distance L may be at least 0.5 mm. By placing the cavity 140 and the plurality of vents AH in the at least two static areas SA, signal loss during transmission can be reduced, and by setting a retention distance L, the assembly fault tolerance during manufacturing can be increased, preventing the cavity 140 from falling into the bending area BA.

[0054] It should be noted that, in Figure 7 Although only two static regions SA and one bending region BA are shown in the implementation, in the actual manufacturing process, the number of static regions SA and bending regions BA can be increased as needed, and each of the static regions SA and each of the bending regions BA can have the same or similar structural settings. Therefore, this application is not limited to the number and shape of static regions SA and bending regions BA.

[0055] In summary, the circuit board and its manufacturing method of this application have the following advantages: First, they reduce processing steps, simplify the process flow, and improve production efficiency; second, since there is no exposed metal layer in the cavity (i.e., the conductive element of this application), unnecessary metal processing steps are avoided, thereby significantly reducing production costs and achieving higher cost-effectiveness; and third, they improve circuit performance. The cavity setting can effectively improve the circuit transmission efficiency, reduce signal loss, and further improve the stability and reliability of the product without affecting electrical performance.

[0056] Although the present application has disclosed the embodiments as described above, it is not intended to limit the present application. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

[0057] [Symbol Explanation]

[0058] 100, 100a, 100b: Circuit boards

[0059] 110: Circuit Structure

[0060] 111: First conductive layer

[0061] 112: First dielectric layer

[0062] 113: Conductive element

[0063] 114: First adhesive layer

[0064] 115: Second adhesive layer

[0065] 116: Second dielectric layer

[0066] 117: Second conductive layer

[0067] 120: Electroplating layer

[0068] 130: Protective layer

[0069] 140: Cavity

[0070] 150: Adhesive layer

[0071] 160: Protective layer

[0072] 171: Third adhesive layer

[0073] 172: Third dielectric layer

[0074] 173: Third conductive layer

[0075] 200, 300, 400: Circuit board manufacturing methods

[0076] 201,202,203,204,205,206,207,208,209,210,211,301,302,303,304,305,306,307,308,309,310,311,312,401,402,403,404,405,406,407,408,409,410,411,412: Steps

[0077] AH: Stomata

[0078] BA: Bending area

[0079] L: Reservation distance

[0080] M1, M2, M3: Comparison lines

[0081] SA: Static area.

Claims

1. A circuit board, characterized in that, Include: At least two circuit structures are arranged at intervals, and each of the at least two circuit structures includes: First conductive layer; A first dielectric layer is disposed on the surface of the first conductive layer; Multiple conductive elements are spaced apart on the surface of the first dielectric layer, and the first dielectric layer is located between the first conductive layer and the multiple conductive elements; A first adhesive layer covers the plurality of conductive elements and the surface of the first dielectric layer located between the plurality of conductive elements; The second adhesive layer is disposed on the surface of the first adhesive layer, and the first adhesive layer is located between the second adhesive layer and the first dielectric layer; A second dielectric layer is disposed on the surface of the second adhesive layer, and the second adhesive layer is located between the second dielectric layer and the first adhesive layer; A second conductive layer is disposed on the surface of the second dielectric layer, and the second dielectric layer is located between the second adhesive layer and the second conductive layer; A third adhesive layer is disposed on the other surface of the first conductive layer, and the first conductive layer is located between the first dielectric layer and the third adhesive layer; A third dielectric layer is disposed on the surface of the third adhesive layer, and the third adhesive layer is located between the first conductive layer and the third dielectric layer; and A third conductive layer is disposed on the surface of the third dielectric layer, and the third dielectric layer is located between the third adhesive layer and the third conductive layer; At least two electroplated layers respectively cover the at least two circuit structures; Multiple pores are formed in the second conductive layer and the at least two electroplated layers; and Two protective layers cover the at least two electroplated layers and the plurality of pores, and the at least two electroplated layers and the at least two circuit structures are located between the two protective layers; The second adhesive layer has a hollow portion, forming a cavity between the first adhesive layer, the second adhesive layer and the second dielectric layer.

2. The circuit board as described in claim 1, characterized in that, The height of the cavity is between 15 μm and 100 μm.

3. The circuit board as described in claim 1, characterized in that, It also includes two adhesive layers, which are respectively disposed between the two protective layers and the at least two electroplated layers.

4. The circuit board as described in claim 1, characterized in that, The materials of the two protective layers are selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer.

5. The circuit board as described in claim 1, characterized in that, The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer.

6. The circuit board as described in claim 1, characterized in that, Each of the at least two circuit structures further includes a protective layer disposed between the first adhesive layer and the second adhesive layer, and the material of the protective layer is selected from the group consisting of polyimide, modified polyimide, liquid crystal polymer, polytetrafluoroethylene and hydrocarbon polymer.

7. The circuit board as described in claim 1, characterized in that, Also includes: At least two static zones, arranged at intervals; and At least one bending zone is located between the at least two static zones; The cavity and the plurality of pores are located in each of the at least two static regions, and one side of the cavity in each of the at least two static regions has a retention distance from the adjacent at least one bending region.

8. A method for manufacturing a circuit board, characterized in that, Include: The first dielectric layer is disposed on the surface of the first conductive layer; Multiple conductive elements are spaced apart on the surface of the first dielectric layer, and the first dielectric layer is located between the first conductive layer and the multiple conductive elements; A first adhesive layer is applied to cover the plurality of conductive elements and the surface of the first dielectric layer located between the plurality of conductive elements to form a first multilayer structure; The second dielectric layer is disposed on the surface of the second conductive layer; A second adhesive layer is disposed on the surface of the second dielectric layer, and the second dielectric layer is located between the second adhesive layer and the second conductive layer to form a second multilayer structure; The third dielectric layer is disposed on the surface of the third conductive layer; A third adhesive layer is disposed on the surface of the third dielectric layer, and the third dielectric layer is located between the third adhesive layer and the third conductive layer to form a third multilayer structure; The first layer, the second layer, and the third layer are pressed together so that the first adhesive layer and the second adhesive layer are positioned opposite each other, and the second layer is located between the first layer and the third layer to form a circuit structure. The circuit structure is covered with an electroplated layer, and the second conductive layer and the electroplated layer form multiple pores to form an electroplated circuit structure; Arrange at least two of the described electroplating circuit structures; and The circuit board is obtained by covering the at least two electroplated circuit structures with two protective layers, and the at least two electroplated circuit structures are located between the two protective layers; The second adhesive layer has a hollow portion, forming a cavity between the first adhesive layer, the second adhesive layer and the second dielectric layer.

9. The method for manufacturing a circuit board as described in claim 8, characterized in that, Before covering the at least two electroplated circuit structures with the two protective layers, the at least two electroplated circuit structures are first covered with two adhesive layers, such that the two adhesive layers are respectively located between the two protective layers and the at least two electroplated layers.

10. The method for manufacturing a circuit board as described in claim 8, characterized in that, Before pressing the first, second, and third composite structures together, a protective layer is first placed on the surface of the first adhesive layer, and after pressing, the protective layer is located between the first and second adhesive layers.

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