Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board comprises an insulating layer; a conductive pad embedded in an upper side of the insulating layer, at least a portion of an upper surface of the conductive pad being exposed from an upper surface of the insulating layer; a first conductive bump disposed on the upper surface of the conductive pad; a passivation layer disposed on the upper surface of the insulating layer, the passivation layer covering a portion of the upper surface of the conductive pad and a portion of a side surface of the first conductive bump; and a second conductive bump disposed on an upper surface of the passivation layer, the second conductive bump covering another portion of the side surface of the first conductive bump and the upper surface of the first conductive bump.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0168856, filed on November 22, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] The pitch of bumps on the substrate connecting to flip-chip dies is constantly decreasing. In fine-pitch fabrications, risks such as solder ball mounting issues and degraded bonding reliability may arise. Therefore, the application of conductive bumps is being considered. However, conductive bumps may have limitations in terms of height and width resolution. Furthermore, the size of the conductive bumps may be affected by the size of the conductive pads. When conductive bumps are formed smaller than a certain size due to the influence of the conductive pads, the bonding reliability with the die may be weakened. Moreover, this risk may increase as the pitch decreases. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board capable of increasing the height of conductive bumps and increasing the size (e.g., planar size) of conductive bumps.

[0005] A first conductive bump, connected to a conductive pad formed in an insulating layer, may be formed on the conductive pad. A passivation layer having a height lower than that of the first conductive bump may be formed on the insulating layer, such that the upper end of the first conductive bump protrudes from the passivation layer. A second conductive bump, covering the protruding upper end of the first conductive bump, may be formed on the passivation layer. The conductive pad may be embedded in the insulating layer. The insulating layer may include a photosensitive insulating material.

[0006] According to one aspect of this disclosure, a printed circuit board is provided, the printed circuit board comprising: an insulating layer; conductive pads embedded in the upper side of the insulating layer, at least a portion of the upper surface of the conductive pads being exposed from the upper surface of the insulating layer; a first conductive bump disposed on the upper surface of the conductive pads; a passivation layer disposed on the upper surface of the insulating layer, the passivation layer covering the portion of the upper surface of the conductive pads on which the first conductive bumps are not disposed and a portion of the side surface of the first conductive bumps; and a second conductive bump disposed on the upper surface of the passivation layer, the second conductive bump covering the portion of the side surface of the first conductive bumps on which the passivation layer is not covered and the upper surface of the first conductive bumps.

[0007] According to another aspect of this disclosure, a printed circuit board is provided, the printed circuit board comprising: a conductive pad; a first conductive bump connected to an upper surface of the conductive pad; a second conductive bump connected to an upper end of the first conductive bump; an insulating layer in contact with a portion of the conductive pad, the insulating layer being spaced apart from the first conductive bump and the second conductive bump, the insulating layer comprising a photosensitive insulating material; and a passivation layer disposed on the upper surface of the insulating layer, the passivation layer being in contact with the conductive pad and a portion of each of the first conductive bump and the second conductive bump. The upper end of the first conductive bump connected to the second conductive bump may protrude from the upper surface of the passivation layer.

[0008] According to exemplary embodiments of this disclosure, the height of the conductive bumps and the size (e.g., planar dimensions) of the conductive bumps can be increased on a printed circuit board. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic block diagram of an example electronic device system; Figure 2 This is a schematic three-dimensional diagram of an example of an electronic device; Figure 3 This is a schematic cross-sectional view of an example of a printed circuit board; Figure 4 It is manufacturing Figure 3 A schematic process diagram illustrating an example of a method for manufacturing printed circuit boards; Figure 5 This is a schematic cross-sectional view of another example of a printed circuit board; Figure 6 This is a schematic cross-sectional view of another example of a printed circuit board; Figure 7 This is a schematic cross-sectional view of another example of a printed circuit board; Figure 8 This is a schematic cross-sectional view of another example of a printed circuit board; and Figure 9 yes Figure 8 A schematic plan view of the printed circuit board from top to bottom. Detailed Implementation

[0010] In the following description, exemplary embodiments of the present disclosure are illustrated with reference to the accompanying drawings. For clarity, the shapes and dimensions of the components in the drawings may be exaggerated or reduced.

[0011] Figure 1 This is a schematic block diagram of an example electronic device system.

[0012] Reference Figure 1 The electronic device 1000 may house a motherboard 1010. The electronic device 1000 may include chip-related components 1020, network-related components 1030, and other components 1040 that are physically and / or electrically connected to the motherboard 1010. Such components can be connected via various signal lines 1090 to other electronic components described below.

[0013] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, encryption processors, microprocessors, or microcontrollers; and logic chips, such as analog-to-digital converters or application-specific integrated circuits (ASICs). However, chip-related components 1020 are not limited to these and may include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips and / or electronic components.

[0014] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (IEEE 802.11 series, etc.), Global Microwave Access Interoperability (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolved Data Optimized (Ev-DO), Enhanced High-Speed ​​Packet Access+ (HSPA+), Enhanced High-Speed ​​Downlink Packet Access+ (HSDPA+), Enhanced High-Speed ​​Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rate GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), 3G, 4G, and 5G protocols, and any other wireless or wired standards or protocols specified after the foregoing. However, network-related components 1030 are not limited to these and may also include components compatible with or operating according to a variety of other wireless or wired standards or protocols. In addition, the network-related component 1030 can be combined with the aforementioned chip-related component 1020.

[0015] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0016] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other electronic components are not limited to these and may include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Furthermore, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0017] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet computer (PC), laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0018] Figure 2 This is a schematic three-dimensional diagram of an example of an electronic device.

[0019] Reference Figure 2 The electronic device may be, for example, a smartphone 1100. A motherboard 1110 may be housed in the smartphone 1100, and various electronic components 1120 are physically and / or electrically connected to the motherboard 1110. Additionally, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the motherboard 1110 or not physically and / or electrically connected to the motherboard 1110 may be housed in the smartphone 1100. A portion of the electronic components 1120 may be the aforementioned chip-related components, such as component packages 1121, but this disclosure is not limited thereto. Component packages 1121 may be in the form of a printed circuit board on which electronic components (including active and / or passive components) are surface-mounted. The electronic device is not limited to the smartphone 1100, but may be other electronic devices as described above.

[0020] Figure 3 This is a schematic cross-sectional view of an example printed circuit board.

[0021] Reference Figure 3 A printed circuit board 100A according to some example embodiments of the present disclosure may include: an insulating layer 111; a first wiring layer 121 embedded in the upper side of the insulating layer 111, the first wiring layer 121 including conductive pads 121P; a second wiring layer 122 embedded in the lower side of the insulating layer 111; a via layer 131 disposed between the first wiring layer 121 and the second wiring layer 122, the via layer 131 connecting the first wiring layer 121 and the second wiring layer 122 to each other; a first conductive bump 140 disposed on the upper surface of the conductive pads 121P; a passivation layer 181 disposed on the upper surface of the insulating layer 111, the passivation layer 181 covering a portion of the upper surface of the conductive pads 121P and a portion of the side surface of the first conductive bump 140; and a second conductive bump 150 disposed on the upper surface of the passivation layer 181, the second conductive bump 150 covering another portion of the side surface of the first conductive bump 140 and the upper surface of the first conductive bump 140. A first conductive bump 140 may be attached to the upper surface of the conductive pad 121P. The upper end of the first conductive bump 140 may protrude from the upper surface of the passivation layer 181, and a second conductive bump 150 may be attached to the protruding upper end of the first conductive bump 140. An insulating layer 111 may contact a portion of the conductive pad 121P and may be spaced apart from the first conductive bump 140 and the second conductive bump 150. The passivation layer 181 may contact a portion of each of the conductive pad 121P, the first conductive bump 140, and the second conductive bump 150.

[0022] As described above, in the printed circuit board 100A according to some example embodiments, a first conductive bump 140 may be disposed on a conductive pad 121P, a passivation layer 181 may be disposed on an insulating layer 111 at a height lower than that of the first conductive bump 140, and a second conductive bump 150 may cover the portion of the first conductive bump 140 protruding from the passivation layer 181. The conductive pad 121P, passivation layer 181, and the first and second conductive bumps 140 and 150, having this structure, can be suitably applied to the mounting of high-performance dies requiring high-density input / output terminals. For example, the total height of the first and second conductive bumps 140 and 150 can be increased, which can help ensure a standoff height between the die and the substrate, thereby achieving a stable connection with the die (e.g., the bumps on the die) and the formation of underfill. Furthermore, the dimensions (e.g., planar dimensions) of the second conductive bump 150 can be increased independently of the design rules of the conductive pad 121P, thereby improving the connection strength with the die.

[0023] The first wiring layer 121 may be an embedded trace substrate (ETS) patterning layer. For example, the first wiring layer 121 may be embedded in the upper side of the insulating layer 111, and at least a portion of the upper surface of the first wiring layer 121 may be exposed from the upper surface of the insulating layer 111. Furthermore, conductive pads 121P included in the first wiring layer 121 may also be embedded in the upper side of the insulating layer 111, and at least a portion of the upper surface of the conductive pads 121P may be exposed from the upper surface of the insulating layer 111. In this case, a coreless structure can be easily achieved. Therefore, it may be more advantageous for forming high-density wiring. Additionally, the overall thickness of the substrate can be reduced. The upper surface of the conductive pads 121P may be recessed below the upper surface of the insulating layer 111. For example, a recessed step (or recessed space) may be formed between the upper surface of the conductive pads 121P and the upper surface of the insulating layer 111, and the passivation layer 181 may fill a portion of the recessed space to improve adhesion, thereby further enhancing reliability.

[0024] The insulating layer 111 may include a photosensitive insulating material. For example, the insulating layer 111 may include a photosensitive dielectric (PID). In this case, the coreless structure described above can be more easily achieved. Additionally, high-density wiring can be more easily formed in the insulating layer 111. Furthermore, the thickness of the substrate can be further reduced. The photosensitive insulating material may include a liquid-type insulating material or a film-type insulating material. Furthermore, the photosensitive insulating material may include an epoxy-based photosensitive polymer or an acrylic-based photosensitive polymer, and may also include fillers such as silica and / or other additives as needed.

[0025] When the thickness from the upper surface of the conductive pad 121P to the upper surface of the first conductive bump 140 is represented by t1, and the thickness (or protruding height) from the upper surface of the passivation layer 181 to the upper surface of the first conductive bump 140 is represented by t2, (t1×20%) < t2 < (t1×80%), (t1×30%) < t2 < (t1×70%), or (t1×40%) < t2 < (t1×60%) can be satisfied. Additionally, when the thickness from the upper surface of the conductive pad 121P to the upper surface of the passivation layer 181 is represented by t3, (t1×20%) < t3 < (t1×80%), (t1×30%) < t3 < (t1×70%), or (t1×40%) < t3 < (t1×60%) can be satisfied. The protruding height of the first conductive bump 140 may be associated with the bonding reliability of the die, and the thickness of the remaining portion of the first conductive bump 140 that contacts the passivation layer 181 may be associated with ensuring insulation from the first wiring layer 121. Therefore, when the above thickness ranges are satisfied, the bonding reliability and insulation can be optimized. Additionally, it may be more advantageous in terms of managing the variations in the protruding height of the first conductive bump 140 and the thickness of the remaining portion of the first conductive bump 140. When measuring the thicknesses t1, t2, and t3, when the thickness values vary slightly according to the measurement points, that is, when the thickness values are not constant, the average value of the thicknesses measured at five arbitrary points for each of the thicknesses t1, t2, and t3 can be used.

[0026] The second conductive bump 150 may include a seed layer S and a pattern layer M. The seed layer S substantially conformally and continuously covers a part of the upper surface of the passivation layer 181, another part of the side surface of the first conductive bump 140, and the upper surface of the first conductive bump 140. The pattern layer M is provided on the seed layer S. The seed layer S may be formed by electroless plating and may include, for example, electroless copper. The pattern layer M may be formed by electroplating and may include, for example, electroplated copper. For example, the seed layer S and the pattern layer M may be a single layer and may include copper (Cu), but the present disclosure is not limited thereto. The second conductive bump 150 can be formed by using a circuit lithography process and a plating process, and the size of the second conductive bump 150 can be easily set regardless of the conductive pad 121P. Additionally, for the connection between the second conductive bump 150 and the first conductive bump 140, for example, bonding between copper (Cu) and copper (Cu) can be performed, thereby achieving a high bonding strength.

[0027] The upper surface of the passivation layer 181 may have a surface roughness. For example, the passivation layer 181 may be etched to adjust its height. In this case, the upper surface of the passivation layer 181 may have a surface roughness. The interface between the passivation layer 181 and the second conductive bump 150 may also have a surface roughness. Therefore, the passivation layer 181 with a surface roughness can more effectively ensure adhesion to the second conductive bump 150. In addition, the passivation layer 181 with a surface roughness can have a positive impact on the flowability and adhesion of the underfill and the adhesion of the molding material during the packaging operation. The surface roughness of the upper surface of the passivation layer 181 may be greater than the surface roughness of the lower surface of the passivation layer 181 that contacts the insulating layer 111. For example, the surface roughness of the upper surface of the passivation layer 181 may be greater than the surface roughness of the lower surface of the passivation layer 181. For example, the surface roughness of the upper surface of the passivation layer 181 may be from a few micrometers to tens of micrometers, but this disclosure is not limited thereto. Here, surface roughness may refer to average roughness (Ra).

[0028] In the following text, reference will be made to Figure 3 The components of the printed circuit board 100A according to the example are described in more detail.

[0029] Insulating layer 111 may include an insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material formed by impregnating an inorganic filler (such as silica), an organic filler, and / or a core material (such as glass fiber) into a thermosetting or thermoplastic resin. For example, the insulating material may be an insulating material such as a prepreg, Ajinomoto build-up film (ABF), PID, and resin-coated copper (RCC), but this disclosure is not limited thereto. PID may be preferably used, but this disclosure is not limited thereto. Insulating layer 111 may include multiple layers as needed. The multiple layers may include substantially the same insulating material, and the layers may not be clearly distinguishable from each other, but they can be differentiated from one another. Alternatively, the multiple layers may include different insulating materials.

[0030] Each of the first wiring layer 121 and the second wiring layer 122 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. For example, the first wiring layer 121 may include electrolytic copper formed by electroplating as a pattern layer. The first wiring layer 121 may be an embedded pattern layer formed using the ETS method, and therefore may not include a seed layer. The second wiring layer 122 may include chemical copper formed by electroless plating as a seed layer, and may include electrolytic copper formed by electroplating based on the seed layer as a pattern layer. Each of the first wiring layer 112 and the second wiring layer 122 may perform various functions according to its design. For example, each of the first wiring layer 112 and the second wiring layer 122 may include a signal transmission pattern, a power transmission pattern, a ground transmission pattern, etc. The aforementioned patterns may have various pattern shapes, such as lines, traces, planes, pads, and mats. For example, as described above, the first wiring layer 112 may include conductive pads 121P.

[0031] The via layer 131 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. For example, the via layer 131 may include chemical copper formed by electroless plating as a seed layer, and may include electrolytic copper formed by electrolytic plating based on the seed layer as a pattern layer. The via layer 131 may perform various functions according to its design. For example, the via layer 131 may include signal transmission connection vias, power transmission connection vias, ground transmission connection vias, etc. In cross-section, the connection vias included in the via layer 131 may have generally tapered side surfaces with a width at the upper end smaller than the width at the lower end. The connection vias included in the via layer 131 may have a filled plated via structure, but this disclosure is not limited thereto, and may have a conformal plated via structure. The connection vias included in the via layer 131 may be configured as a plurality of connection vias.

[0032] The first conductive bump 140 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. For example, the first conductive bump 140 may include electrolytic copper formed by electrolytic plating as a pattern layer. The conductive pad 121P may be an embedded pattern layer formed using the ETS method described above; therefore, the first conductive bump 140 formed on the conductive pad 121P may include a metal foil (e.g., copper foil) of a carrier used in the ETS method as a seed layer. For example, the metal foil of the carrier may be retained and included in the first conductive bump 140. However, this disclosure is not limited thereto. If necessary, a seed layer may be additionally formed on the metal foil, or the metal foil may be removed first and then the seed layer formed. The first conductive bump 140 may perform various functions according to its design. For example, the first conductive bump 140 may be connected to the second conductive bump 150 and used as a signal transmission bump, a power transmission bump, a ground transmission bump, etc. The first conductive bump 140 may have a generally cylindrical shape, but this disclosure is not limited thereto. The first conductive bump 140 may have a generally vertical side surface, but this disclosure is not limited thereto.

[0033] The second conductive bump 150 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. For example, the second conductive bump 150 may include chemical copper formed by electroless plating as a seed layer S, and may include electrolytic copper formed by electrolytic plating as a pattern layer M. The second conductive bump 150 may perform various functions according to its design. For example, the second conductive bump 150 may be connected to the first conductive bump 140 and used as a signal transmission bump, a power transmission bump, a ground transmission bump, etc. The second conductive bump 150 may substantially cover the protruding upper end of the first conductive bump 140 in the form of a cap, but this disclosure is not limited thereto. The upper surface and side surface of the second conductive bump 150 may transition at a substantially right angle, but are not limited thereto; for example, they may also transition at a substantially rounded corner.

[0034] The passivation layer 181 may include an organic insulating material. The organic insulating material may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or materials in which inorganic fillers and / or organic fillers are mixed into thermosetting or thermoplastic resins. For example, the organic insulating material may be ABF, PID, solder resist (SR), etc., but this disclosure is not limited thereto. The passivation layer 181 may preferably include an SR, and the SR may be a liquid SR or a film SR, but this disclosure is not limited thereto.

[0035] Figure 4 It is manufacturing Figure 3A schematic process diagram illustrating an example of a method for making printed circuit boards.

[0036] Reference Figure 4 First, a first wiring layer 121, a second wiring layer 122, and a via layer 131, including conductive pads 121P, can be formed on the insulating layer 111 using methods such as the ETS method. Next, a first conductive bump 140 can be formed on the conductive pads 121P using photolithography and plating processes. After forming a passivation layer 181 on the insulating layer 111, the height of the passivation layer 181 can be reduced by a thinning process, allowing the upper end of the first conductive bump 140 to protrude. Wet etching or dry etching can be used as the thinning process. Subsequently, a seed layer S can be formed on the passivation layer 181 and the first conductive bump 140. The seed layer S can be formed by electroless plating, but this disclosure is not limited to this, and it can also be formed by sputtering as needed. Subsequently, a dry film resist 201 can be formed on the seed layer S. Furthermore, an opening pattern can be formed on the dry film resist 201 with a desired design using a photolithography process, exposing the seed layer S formed on the protruding upper end of the first conductive bump 140. Subsequently, a pattern layer M can be formed on the seed layer S in the opening pattern of the dry film resist 201 to fill at least a portion of the opening pattern. The pattern layer M can be formed by electroplating. The dry film resist 201 can then be removed. The dry film resist 201 can be physically removed or chemically removed using a stripping agent. Additionally, the portion of the seed layer S from which the dry film resist 201 has been removed can be etched and removed. Thus, the second conductive bump 150 can be formed.

[0037] The printed circuit board 100A described above according to the example can be manufactured through a series of processes. The content described above in conjunction with the printed circuit board 100A according to the example can also be applied to the above manufacturing example in a substantially similar manner.

[0038] Figure 5 This is a schematic cross-sectional view of another example of a printed circuit board.

[0039] Reference Figure 5Compared to the printed circuit board 100A according to some example embodiments described above, the printed circuit board 100B according to another example embodiment of this disclosure may further include a surface treatment layer 160 covering the upper and side surfaces of the second conductive bump 150. The surface treatment layer 160 may include, for example, multiple layers, which sequentially include a nickel (Ni) layer 161 disposed on the second conductive bump 150 and a gold (Au) layer 162 disposed on layer 161. However, this disclosure is not limited thereto, and as will be described below, the surface treatment layer 160 may be formed using various materials and various processes. When the surface treatment layer 160 is formed, reliability can be ensured during die bonding in the packaging operation. Additionally, Cu consumption can be prevented. The surface treatment layer 160 may be formed, for example, by an electroless nickel / immersion gold (ENIG) process, but this disclosure is not limited thereto, and may be formed by processes such as hot air solder leveling (HASL), immersion silver (ImAg), immersion tin (ImSn), etc., or by an organic solderability protection (OSP) process.

[0040] Other contents are substantially the same as those described in conjunction with the printed circuit board 100A according to the example above. Additionally, the contents described in conjunction with the manufacturing example above can also be applied to the printed circuit board 100B according to another example.

[0041] Figure 6 This is a schematic cross-sectional view of another example of a printed circuit board.

[0042] Reference Figure 6 Compared to the printed circuit board 100A according to some example embodiments described above, the second conductive bump 150 of the printed circuit board 100C according to another example embodiment may include seed layers S1 and S2, which comprise different metals. For example, the seed layers S1 and S2 of the second conductive bump 150 may be formed by multiple layers, which sequentially include a first layer S1 comprising titanium (Ti) and a second layer S2 comprising copper (Cu). For example, the seed layers S1 and S2 of the second conductive bump 150 may be formed by a sputtering process, or by a combination of a sputtering process and an electroless plating process. In the sputtering process, a titanium (Ti) film may be formed, or a titanium (Ti) film and a copper (Cu) film may be formed sequentially. In the electroless plating process, electroless copper may be formed. For example, the first layer S1 may comprise sputtered titanium (Ti). Additionally, the second layer S2 may comprise sputtered copper (Cu), or may comprise both sputtered copper (Cu) and electroless copper plating. As described, adhesion strength can be improved when a first layer S1 comprising a metal different from copper (Cu) (e.g., titanium (Ti)) is formed on the surface of the passivation layer 181.

[0043] Other contents are substantially the same as those described in conjunction with the printed circuit board 100A according to the example above. Additionally, the contents described in conjunction with the manufacturing example above can also be applied to the printed circuit board 100C according to another example. Furthermore, the surface treatment layer 160 described in conjunction with the printed circuit board 100B according to another example above can also be applied to the printed circuit board 100C according to another example.

[0044] Figure 7 This is a schematic cross-sectional view of another example of a printed circuit board.

[0045] Reference Figure 7 Compared to the printed circuit board 100A according to some example embodiments described above, in the printed circuit board 100D according to another example, the passivation layer 181 may have a blind cavity C. Therefore, the upper surface of the passivation layer 181 may have a stepped portion due to the blind cavity C. For example, the passivation layer 181 may have a two-stage stepped structure. In this case, the aforementioned conductive pads 121P, the first conductive bump 140, and the second conductive bump 150 may be provided in the region overlapping with the blind cavity C. Here, the region overlapping with the blind cavity C may refer to the region provided in the blind cavity C in the top view and / or side view. For example, the blind cavity C can be formed by irradiating the outer region of the passivation layer 181 with ultraviolet light, curing the outer region, and etching the remaining uncured region of the passivation layer 181. In this case, the upper surface of the passivation layer 181 in the region where the blind cavity C is formed may have the surface roughness described above. Conversely, the upper surface of the passivation layer 181 in the region where the blind cavity C is not formed may have a smooth surface. For example, the upper surface of the passivation layer 181 may have a relatively larger surface roughness in the region where the blind cavity C is formed than the surface roughness of the upper surface of the passivation layer 181 in the region where the blind cavity C is not formed. As described above, the height of the passivation layer 181 can be selectively reduced and the surface of the passivation layer 181 can have a surface roughness only in the region where the die is mounted. Therefore, the die can be mounted more efficiently during the packaging operation, and reliability can be enhanced.

[0046] Other contents are substantially the same as those described in conjunction with the printed circuit board 100A according to the example above. Additionally, the contents described in conjunction with the manufacturing example above can also be applied to the printed circuit board 100D according to another example. Furthermore, the surface treatment layer 160 described in conjunction with the printed circuit board 100B according to another example can also be applied to the printed circuit board 100D according to another example. Additionally, the seed layers S1 and S2 of the second conductive bump 150 described in conjunction with the printed circuit board 100C according to another example can also be applied to the printed circuit board 100D according to another example.

[0047] Figure 8 This is a schematic cross-sectional view of another example of a printed circuit board.

[0048] Figure 9 yes Figure 8 A schematic plan view of the printed circuit board from top to bottom.

[0049] Reference Figure 8 and Figure 9 According to another example embodiment, the printed circuit board 100E may have a multilayer coreless substrate structure. For example, the printed circuit board 100E according to another example may include: an insulating layer 110; a plurality of wiring layers 121, 122, 123 and 124 respectively disposed on or in the insulating layer 110; a plurality of via layers 131, 132 and 133 respectively disposed in the insulating layer 110, the plurality of via layers 131, 132 and 133 connecting the plurality of wiring layers 121, 122, 123 and 124 to each other; a first passivation layer 181 disposed on the upper surface of the insulating layer 110; and a second passivation layer 182 disposed on the lower surface of the insulating layer 110. Among the plurality of wiring layers 121, 122, 123 and 124, the uppermost wiring layer 121 may be an embedded pattern layer buried in the upper side of the insulating layer 110, and may include conductive pads 121P and conductive lines 121L. Conductive pads 121P and conductive lines 121L can be configured as multiple conductive pads 121P and multiple conductive lines 121L, respectively, and a first conductive bump 140 and a second conductive bump 150 can be disposed on each conductive pad 121P. Among the multiple wiring layers 121, 122, 123, and 124, the bottommost wiring layer 124 can be a protruding pattern layer projecting from the lower surface of the insulating layer 110. The first passivation layer 181 can have a blind cavity C. The second passivation layer 182 can have multiple openings that respectively expose at least a portion of the bottommost wiring layer 124. A multilayer coreless substrate with this structure can be used as a packaging substrate and / or an interposer substrate.

[0050] Multiple conductive lines 121L can be connected to portions of multiple conductive pads 121P respectively. Additionally, in a plan view, at least a portion of each of the multiple conductive lines 121L can be disposed between at least two conductive pads 121P. When multiple conductive lines 121L are disposed between multiple conductive pads 121P as described above, under normal circumstances, the risk of degradation in reliability may increase due to various side effects. However, in the case of the printed circuit board 100E according to another example, this risk can be eliminated by forming first conductive bumps 140 and second conductive bumps 150 on the multiple conductive pads 121P respectively.

[0051] Insulating layer 110 may include insulating layer 111, and its details may be substantially the same as those described in connection with insulating layer 111. Additionally, multiple wiring layers 121, 122, 123, and 124 may include wiring layers 121 and 122, and their details may be substantially the same as those described in connection with wiring layers 121 and 122. Furthermore, multiple via layers 131, 132, and 133 may include via layer 131, and their details may be substantially the same as those described in connection with via layer 131. Additionally, passivation layers 181 and 182 may include passivation layer 181, and their details may be substantially the same as those described in connection with passivation layer 181.

[0052] The structure and manufacturing method of the printed circuit board 100A according to the example embodiment described above can be applied to the printed circuit board 100E according to another example embodiment. Additionally, the structure of the printed circuit board 100B according to another example described above can also be applied to the printed circuit board 100E. Furthermore, the structure of the printed circuit board 100C according to another example described above can also be applied to the printed circuit board 100E. Additionally, the structure of the printed circuit board 100D according to another example described above can also be applied to the printed circuit board 100E.

[0053] As used herein, the term "cover" can include not only complete coverage but also partial coverage, and not only direct coverage but also indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling and substantial filling. For example, the term can include situations where gaps, holes, etc., are present. Additionally, the term "surround" can include not only complete surrounding but also partial surrounding and substantial surrounding. Furthermore, the term "expose" can include not only completely exposing a structure but also exposing a portion of a structure, and the term "expose" can mean exposing another component from which a component is embedded. For example, an opening in an exposed pad can expose the pad from the outermost insulating layer or passivation layer, and a surface treatment layer can be applied to the exposed pad.

[0054] As used herein, the term "approximately" may include process errors or positional deviations, measurement errors, etc., that occur during the manufacturing process. For example, "set at approximately the same height" may include not only "set at exactly the same position" but also "set at approximately the same position." Furthermore, "having a generally specific shape" may include not only "having a completely specific shape" but also "having an approximately specific shape." For example, this shape may be determined based on the overall shape. Additionally, "the same insulating material" may mean not only exactly the same insulating material but also the same type of insulating material. Therefore, the composition of the insulating material may be approximately the same, but its specific composition ratio may vary slightly.

[0055] As used in this article, shape in a cross-section can refer to the cross-sectional shape of the object when it is cut vertically, or the shape of the object when viewed in a side view. Additionally, shape in a plan view can refer to the shape of the object when it is cut horizontally, or the planar shape of the object when viewed in a top or bottom view.

[0056] As used herein, for convenience, terms such as "upper side," "upper part," and "upper surface" are used to indicate the upward direction of the cross-section based on the drawings, while "lower side," "lower part," and "lower surface" are used to indicate the opposite direction. However, the above directions are defined for ease of description. Therefore, it should be understood that the scope of the claims is not specifically limited by the above directions, and the concepts of "upper" and "lower" may be changed at any time.

[0057] As used herein, the term "connection" can refer not only to a "direct connection" but also to an "indirect connection" via an adhesive layer, etc. The term "electrical connection" can include cases where components are "physically connected" and cases where components are "not physically connected." Furthermore, the terms "first," "second," etc., can be used to distinguish one component from another and may not imply any particular order and / or importance associated with the components. In some cases, without departing from the scope of the exemplary embodiments, a "first component" may be referred to as a "second component," and similarly, a "second component" may be referred to as a "first component."

[0058] As used herein, thickness, width, length, depth, linewidth, spacing, pitch, distance, and surface roughness can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cross-section can be vertical or horizontal, and each value can be measured based on the desired cross-section. When the values ​​measured in the cross-section of the printed circuit board are inconsistent, the value can be determined as the average of the values ​​measured at any five points.

[0059] As used herein, the term "example" does not mean the same example embodiment and is provided to emphasize distinct features. However, the examples presented above do not preclude implementation by combining features with those of other examples. For example, a particular feature described in one example but not in another may still be understood to apply to the other example unless there is an explicit contradiction or inconsistency with what is described in that other example.

[0060] The terminology used herein describes specific examples only, and this disclosure is not limited thereto. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0061] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Insulating layer; A conductive pad is embedded in the upper side of the insulating layer, such that at least a portion of the upper surface of the conductive pad is exposed from the upper surface of the insulating layer. A first conductive bump is disposed on the upper surface of the conductive pad; A passivation layer is disposed on the upper surface of the insulating layer, the passivation layer covering the portion of the upper surface of the conductive pad on which the first conductive bump is not disposed and a portion of the side surface of the first conductive bump; as well as A second conductive bump is disposed on the upper surface of the passivation layer. The second conductive bump covers the portion of the side surface of the first conductive bump that is not covered by the passivation layer, as well as the upper surface of the first conductive bump.

2. The printed circuit board according to claim 1, wherein, The insulating layer includes a photosensitive insulating material.

3. The printed circuit board according to claim 1, wherein, The surface roughness of the upper surface of the passivation layer is greater than the surface roughness of the lower surface of the passivation layer, and The second conductive bump is in contact with the upper surface of the passivation layer.

4. The printed circuit board according to claim 1, wherein, The upper surface of the conductive pad is recessed below the upper surface of the insulating layer to form a recessed space between the upper surface of the conductive pad and the upper surface of the insulating layer. The passivation layer fills a portion of the recessed space.

5. The printed circuit board according to claim 4, wherein, When the thickness from the upper surface of the conductive pad to the upper surface of the first conductive bump is represented by t1, and the thickness from the upper surface of the passivation layer to the upper surface of the first conductive bump is represented by t2, the condition (t1 × 20%) is satisfied. <t2<(t1×80%)。 6. The printed circuit board according to claim 4, wherein, When the thickness from the upper surface of the conductive pad to the upper surface of the first conductive bump is represented by t1, and the thickness from the upper surface of the conductive pad to the upper surface of the passivation layer is represented by t3, the condition (t1 × 20%) is satisfied. <t3<(t1×80%)。 7. The printed circuit board according to claim 1, wherein, The second conductive bump includes a seed layer and a pattern layer. The seed layer generally conformally and continuously covers the upper surface of the passivation layer, the portion of the side surface of the first conductive bump that is not covered by the passivation layer, and the upper surface of the first conductive bump. The pattern layer is disposed on the seed layer.

8. The printed circuit board according to claim 7, wherein, Each of the seed layer and the pattern layer comprises a single layer containing copper.

9. The printed circuit board according to claim 7, wherein, The seed layer comprises multiple layers, which sequentially include a layer containing titanium and a layer containing copper, and The patterned layer comprises a single layer containing copper.

10. The printed circuit board according to claim 1, wherein, The printed circuit board also includes: A surface treatment layer covers the upper and side surfaces of the second conductive bump.

11. The printed circuit board according to claim 10, wherein, The surface treatment layer comprises multiple layers, which sequentially include a layer containing nickel and a layer containing gold.

12. The printed circuit board according to claim 1, wherein, The passivation layer has a blind cavity. The upper surface of the passivation layer has a stepped portion due to the blind cavity, and The conductive pads, the first conductive bump, and the second conductive bump are disposed in the region overlapping with the blind cavity.

13. The printed circuit board according to claim 12, wherein, The surface roughness of the upper surface of the passivation layer in the region where the blind cavity is provided is greater than the surface roughness of the upper surface of the passivation layer in the region where the blind cavity is not provided.

14. The printed circuit board according to claim 1, further comprising: Multiple wiring layers are respectively disposed on or within the insulating layer; as well as Multiple via layers are respectively disposed in the insulating layer, and the multiple via layers connect the multiple wiring layers to each other. The uppermost wiring layer among the plurality of wiring layers is embedded in the upper side of the insulating layer. The lowest wiring layer of the plurality of wiring layers protrudes from the lower surface of the insulating layer, and The topmost wiring layer includes the conductive pads.

15. The printed circuit board according to claim 14, wherein, The printed circuit board includes multiple conductive pads, multiple first conductive bumps, and multiple second conductive bumps. The topmost wiring layer also includes multiple conductive lines. The multiple conductive lines are respectively connected to a portion of the multiple conductive pads, and In the plan view, at least a portion of each of the plurality of conductive lines is disposed between at least two of the plurality of conductive pads.

16. A printed circuit board, comprising: Conductive pads; A first conductive bump is connected to the upper surface of the conductive pad; The second conductive bump is connected to the upper end of the first conductive bump; An insulating layer is in contact with a portion of the conductive pad, the insulating layer is spaced apart from the first conductive bump and the second conductive bump, and the insulating layer comprises a photosensitive insulating material; as well as A passivation layer is disposed on the upper surface of the insulating layer, the passivation layer being in contact with the conductive pads and a portion of each of the first conductive bump and the second conductive bump. The upper end of the first conductive bump, which is connected to the second conductive bump, protrudes from the upper surface of the passivation layer.

17. The printed circuit board according to claim 16, wherein, The photosensitive insulating material includes epoxy photosensitive polymers or acrylic photosensitive polymers.

18. The printed circuit board according to claim 17, wherein, The photosensitive insulating material also includes fillers.

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