Back contact solar cell, preparation method thereof and cell module

Abstract

The invention discloses a back contact solar cell, a preparation method thereof and a cell module. The end portion, opposite to the first doped semiconductor layer, of at least part of the first polar structure in the back contact solar cell comprises a first sub-region and a second sub-region connected with the first sub-region, and the first sub-region in at least one end portion is in contact with the adjacent second polar structure in the back contact solar cell. The surface roughness of the first sub-region far away from the semiconductor substrate is greater than that of the second sub-region far away from the semiconductor substrate; or / and the depth of the first pit microstructure arranged on the surface, far away from the semiconductor substrate, of the first sub-region is greater than the depth of the second pit microstructure arranged on the surface, far away from the semiconductor substrate, of the second sub-region. The thickness of the second sub-region and the contact region of the first doped semiconductor layer contained in the first polar structure in the back contact solar cell is uniform, the passivation strength of the first passivation layer is enhanced, and the conversion efficiency, filling factors and other electrical properties of the back contact solar cell are obviously enhanced.

Description

Technical Field

[0001] This application belongs to the field of crystalline silicon solar cell technology, specifically relating to a back-contact solar cell, its fabrication method, and a cell assembly. Background Technology

[0002] Among various battery cell (BC) technologies, hybrid technology, which combines half heterojunction (HJT) passivation contact technology and half tunnel oxide passivation contact (TOPCon) passivation contact technology, and applies both passivation contact technologies to the back of the battery, forms a hybrid back contact (HBC) battery. This technology balances battery efficiency, process complexity, and production cost, and is currently a hot research topic for various research institutions and manufacturing companies.

[0003] However, hybrid HBC cells require the fabrication of a high-temperature tunneling layer and a doped polycrystalline silicon stack first, followed by a low-temperature intrinsic amorphous silicon and a doped amorphous / microcrystalline silicon stack. Before fabricating the low-temperature thin film layer, a cleaning process is necessary to remove surface contaminants. During the cleaning process, alkaline solutions etch the doped polycrystalline silicon layer, resulting in deeper corrosion pits, reduced thickness, and increased structural defects. This leads to increased damage to the tunneling layer / doped polycrystalline silicon stack during subsequent laser etching and wet etching processes, resulting in poor passivation quality of the TOPCon structure and affecting the efficiency of the hybrid back contact cell. Summary of the Invention

[0004] In view of the above problems, this application provides a back-contact solar cell, a method for fabricating the same, and a battery module containing the back-contact solar cell, to solve the technical problem that the low passivation quality of the TOPCon structure in existing hybrid back-contact solar cells leads to low photoelectric conversion efficiency.

[0005] In a first aspect, embodiments of this application provide a back-contact solar cell. The back-contact solar cell of this application includes a semiconductor substrate, a plurality of first polarity structures, and a plurality of second polarity structures; on the backlight surface of the semiconductor substrate, the first polarity structures and the second polarity structures are alternately arranged in a direction parallel to the backlight surface; The first polar structure includes a first functional layer, the first functional layer includes a first passivation layer and a first doped semiconductor layer, and the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate; In at least a portion of the first polar structure, the first doped semiconductor layer includes a first sub-region, a second sub-region, and a contact region. At least one of the first sub-regions is in contact with an adjacent second polar structure, and the second sub-region is disposed between the first sub-region and the contact region. The surface roughness of the first sub-region away from the semiconductor substrate is R. z1The surface roughness of the second sub-region away from the semiconductor substrate is R. z2 And R z1 >R z2 .

[0006] Compared with existing back-contact solar cells, the back-contact solar cell of this application features a second sub-region and contact region of the first doped semiconductor layer in the first polar structure with uniform thickness and a strong passivation performance of the first passivation layer. The uniform thickness of the second sub-region and contact region of the first doped semiconductor layer improves the overall surface quality away from the semiconductor substrate, such as reducing surface roughness and making the surface smoother. Simultaneously, it enhances the protective effect of the first doped semiconductor layer on the first passivation layer, significantly improving the structural integrity and passivation strength of the first passivation layer. This results in a significant improvement in its carrier tunneling capability and selective collection function, more effectively repelling minority carriers and reducing surface recombination rate. Consequently, it significantly improves the overall passivation performance of the first polar structure and substantially enhances the electrical performance of the back-contact solar cell, including its conversion efficiency and fill factor.

[0007] In addition, since the surface roughness of the first sub-region at the end of the first doped semiconductor layer is relatively high, the contact interface quality between the first doped semiconductor layer and the electrode structure contained in the first polar structure is improved, while ensuring that the structural integrity of the first passivation layer is significantly improved, thus improving the contact electrical performance of the interface.

[0008] Furthermore, the R z1 The R z2 (1.5~1000): 1.

[0009] Furthermore, the R z1 The range is from 1 nm to 100 nm.

[0010] Furthermore, the R z2 The range is 0.1 nm to 40 nm.

[0011] Furthermore, the surface of the first sub-region away from the semiconductor substrate is provided with a first pit microstructure, and the surface of the second sub-region away from the semiconductor substrate is provided with a second pit microstructure. The minimum distance w1 between the first pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, and the minimum distance w2 between the second pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, wherein w2 > w1.

[0012] Furthermore, w1 is 29 nm to 220 nm.

[0013] Furthermore, w2 is 49 nm to 240 nm.

[0014] Furthermore, along the direction from the first sub-region to the contact region in the first doped semiconductor layer, the length ratio of the first sub-region to the second sub-region is (0.03~15):1.

[0015] Furthermore, along the direction from the first sub-region to the contact region in the first doped semiconductor layer, the length ratio of the first sub-region to the second sub-region is (0.03~15):1.

[0016] Furthermore, the surface of the contact area away from the semiconductor substrate has a third pit microstructure and / or a protrusion microstructure.

[0017] Furthermore, the surface roughness of the contact area away from the semiconductor substrate is R. z3 And the R z3 >R z2 .

[0018] Furthermore, the surface roughness of the contact area away from the semiconductor substrate is R. z3 And the R z3 The range is 2nm to 160nm.

[0019] Furthermore, the surface of the contact area is provided with the third pit microstructure, and the minimum distance w3 between the third pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate is greater than w1.

[0020] Furthermore, the depth of the third pit microstructure is 0.1 nm to 60 nm.

[0021] Furthermore, the width of the opening of the third pit microstructure is 0.1 nm to 120 nm.

[0022] Furthermore, the height of the protruding microstructure is 1 nm to 100 nm.

[0023] Furthermore, the width of the root of the protruding microstructure is 1 nm to 100 nm.

[0024] Furthermore, the second polar structure includes a second functional layer, which extends into the adjacent first polar structure and covers the surfaces of the first sub-region and the second sub-region in the first doped semiconductor layer that are adjacent to the second polar structure and far from the semiconductor substrate.

[0025] Furthermore, the semiconductor substrate includes a passivation layer and an antireflection layer on the light-receiving side, with the passivation layer disposed between the light-receiving surface and the antireflection layer; and the light-receiving surface of the semiconductor substrate has a textured surface structure.

[0026] Secondly, embodiments of this application provide a back-contact solar cell. The back-contact solar cell of this application includes a semiconductor substrate, a plurality of first polarity structures, and a plurality of second polarity structures; on the backlight surface of the semiconductor substrate, the first polarity structures and the second polarity structures are alternately arranged in a direction parallel to the backlight surface; The first polar structure includes a first functional layer, the first functional layer includes a first passivation layer and a first doped semiconductor layer, and the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate; In at least a portion of the first polar structure, the first doped semiconductor layer includes a first sub-region, a second sub-region, and a contact region. At least one of the first sub-regions is in contact with an adjacent second polar structure, and the second sub-region is disposed between the first sub-region and the contact region. The surface of the first sub-region away from the semiconductor substrate is provided with a first pit microstructure, and the surface of the second sub-region away from the semiconductor substrate is provided with a second pit microstructure. The depth of the first pit microstructure is greater than the depth of the second pit microstructure.

[0027] Compared with existing back-contact solar cells, the back-contact solar cell of this application features a second sub-region and contact region with uniform thickness of the first doped semiconductor layer in the first polar structure, and a strong passivation performance of the first passivation layer. The uniform thickness of the second sub-region and contact region of the first doped semiconductor layer improves the overall surface quality away from the semiconductor substrate. For example, the depth of the second pit microstructure on the surface of the second sub-region is lower than the depth of the first pit microstructure on the surface of the first sub-region, which enhances the protective effect of the first doped semiconductor layer on the first passivation layer. This significantly improves the structural integrity and passivation strength of the first passivation layer, thereby significantly improving its carrier tunneling capability and selective collection function. It can more effectively repel minority carriers, reduce surface recombination rate, and thus significantly improve the overall passivation performance of the first polar structure, significantly enhancing the conversion efficiency and fill factor of the back-contact solar cell.

[0028] In addition, since the depth of the first pit microstructure provided on the surface of the first sub-region in the end of the first doped semiconductor layer is deeper than the depth of the second pit microstructure provided on the surface of the first sub-region, the contact interface quality between the first doped semiconductor layer and the electrode structure contained in the first polar structure is improved, and the contact electrical performance of the interface is improved, while ensuring that the structural integrity of the first passivation layer is significantly improved.

[0029] Furthermore, the depth ratio of the first pit microstructure to the depth of the second pit microstructure is (1.5~1000):1.

[0030] Furthermore, the depth of the first pit microstructure is 1 nm to 100 nm.

[0031] Furthermore, the depth of the second pit microstructure is 0.1 nm to 40 nm.

[0032] Furthermore, the minimum distance w1 between the first pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, and the minimum distance w2 between the second pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, wherein w2 > w1.

[0033] Furthermore, w1 is 29 nm to 220 nm.

[0034] Furthermore, w2 is 49 nm to 240 nm.

[0035] Furthermore, the surface of the contact area away from the semiconductor substrate is provided with a third pit microstructure and / or a protrusion microstructure.

[0036] Furthermore, the surface roughness of the contact area away from the semiconductor substrate is R. z3 The surface roughness of the second sub-region away from the semiconductor substrate is R. z2 And R z3 >R z2 .

[0037] Furthermore, the surface roughness of the contact area away from the semiconductor substrate is 2 nm to 160 nm.

[0038] Furthermore, the depth of the third pit microstructure is 0.1 nm to 60 nm.

[0039] Furthermore, the width of the opening of the third pit microstructure is 0.1 nm to 120 nm.

[0040] Furthermore, the height of the protruding microstructure is 1 nm to 100 nm.

[0041] Furthermore, the width of the root of the protruding microstructure is 1 nm to 100 nm.

[0042] Furthermore, the minimum distance w1 between the first pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, and the minimum distance w3 between the third pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, wherein w3 > w1.

[0043] Furthermore, w3 is 48 nm to 290 nm.

[0044] Thirdly, embodiments of this application provide a method for fabricating a back-contact solar cell. The method for fabricating a back-contact solar cell according to embodiments of this application includes the following steps: A semiconductor substrate is provided, wherein a plurality of first polar regions and a plurality of second polar regions are divided on the back surface of the semiconductor substrate, and the first polar regions and the second polar regions are alternately arranged along a direction parallel to the back surface; A patterned first functional film is fabricated on the back surface of the semiconductor substrate, such that the first functional film covers the first polar region in the back surface; wherein, the first functional film is a functional film with a tunneling oxide passivation contact structure; the first functional film includes a first passivation film and a first doped semiconductor film, and the first passivation film is disposed between the first doped semiconductor film and the semiconductor substrate. A protective film is formed on at least a portion of the surface of the first doped semiconductor film away from the semiconductor substrate, and the protective film covers the first doped semiconductor film but exposes the two end regions of the first doped semiconductor film near the second polarity region; The semiconductor substrate on which the protective film is prepared is cleaned, and the protective film is removed. A second functional film is prepared in at least the second polar region of the backlight surface.

[0045] The method for fabricating a back-contact solar cell in this application involves covering at least a portion of the main area of ​​the surface of the first doped semiconductor film of the patterned tunneling oxide passivation contact structure with a protective film, while the two end regions of the first doped semiconductor film near the second polarity region are not covered with a protective film. During the cleaning process of the semiconductor substrate with the protective film, the protective film can effectively protect the covered surface of the first doped semiconductor film, thereby mitigating the thinning of the first doped semiconductor film or the formation of deep corrosion pits caused by the etching of the surface of the main area of ​​the first doped semiconductor film during the cleaning process. At the same time, during the cleaning process, the two end regions of the first doped semiconductor film that are in contact with the adjacent second polarity region are etched. In this way, after cleaning, the thickness of the main surface area protected by the protective film in the first doped semiconductor film is relatively thicker than the thickness of the unprotected end areas, and the resulting pits are relatively shallow. This significantly improves the thickness uniformity of the main surface area of ​​the first doped semiconductor film and significantly reduces the undesirable phenomenon of localized etching or excessively thin remaining thickness in the first doped semiconductor film. Therefore, it effectively protects the integrity of the first passivation film in the first functional film of the tunnel oxide passivation contact structure during cleaning and subsequent processes, improving its passivation performance. Furthermore, it increases the process window and improves the efficiency of the fabrication method for the back contact solar cell in this embodiment.

[0046] Furthermore, the method for preparing the protective film includes at least one of laser processing and using a patterned mask.

[0047] Furthermore, the thickness of the protective film is 0.1 nm to 50 nm.

[0048] Furthermore, the material of the protective film includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] Furthermore, the method for preparing the second functional membrane includes the following steps: A continuous second functional film is prepared on the surface of the second polar region and the first doped semiconductor film after the cleaning treatment away from the semiconductor substrate; The second functional film located in the first polar region is patterned so that at least a portion of the surface of the first doped semiconductor film in the first polar region is exposed.

[0050] Furthermore, it also includes a step of texturing the light-receiving surface of the semiconductor substrate, so that the light-receiving surface is textured.

[0051] Furthermore, it also includes the step of first forming a passivation layer on the velvet surface, and then forming an antireflection layer on the surface of the passivation layer away from the velvet surface.

[0052] Fourthly, this application also provides a battery module. The battery module of this application includes a back-contact solar cell of this application or a back-contact solar cell prepared according to the back-contact solar cell preparation method of this application. Because the battery module of this application contains a back-contact solar cell, it has higher peak power and module efficiency, and higher actual power generation compared to existing battery modules containing back-contact solar cells. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a back-contact solar cell according to an embodiment of this application; Figure 2 for Figure 1 The diagram shown is an enlarged view of the layout of region A in the back-contact solar cell of this application embodiment; Figure 3 This is a schematic diagram of a fabrication method for a back-contact solar cell according to an embodiment of this application; Figure 4 This is a schematic diagram of a semiconductor substrate structure in the fabrication method of a back-contact solar cell according to an embodiment of this application; Figure 5 This is a schematic diagram of the structure in which a patterned first functional film is formed on the back surface of a semiconductor substrate in the fabrication method of a back contact solar cell according to an embodiment of this application. Figure 6 This is a schematic diagram of a structure in which a protective film is formed in the region between the two ends of the surface of the first functional film in the preparation method of the back contact solar cell of this application embodiment; Figure 7 To Figure 6 A schematic diagram of the structure after cleaning treatment; Figure 8 In order to be in Figure 7 The diagram shows a structure in which a second functional film, including a second passivation film and a second doped semiconductor film, is formed on the exposed second polar region and the surface of the first functional film. Figure 9 In order to be in Figure 8 The diagram shows a structure in which the second functional film is patterned to remove at least a portion of the surface of the first doped semiconductor film in the first functional film of the first polar region, thus exposing the surface of the first doped semiconductor film. Figure 10 This is a scanning electron microscope (SEM) image of a cross-section perpendicular to the surface of the region between the two ends of the surface of the first doped semiconductor film 22' after the cleaning treatment including alkaline treatment in step S5 of the back contact solar cell in Example 1. Figure 11 This is a scanning electron microscope (SEM) image of a cross-section perpendicular to the surface of the region between the two ends of the surface of the first doped semiconductor film 22' after the cleaning treatment including alkaline treatment in step S5 of the back contact solar cell in Example 2. Figure 12 This is a scanning electron microscope (SEM) image of a cross-section perpendicular to the surface of the region between the two ends of the surface of the first doped semiconductor film 22' after the cleaning treatment including alkaline solution treatment in step S5 of the back contact solar cell in Comparative Example 1.

[0055] The reference numerals in the detailed embodiments are as follows: R1 - First polarity region, R2 - Second polarity region; 1-Semiconductor substrate, 11-Backlight surface, 12-Light-receiving surface; 2-First polar structure, 21-First passivation layer, 22-First doped semiconductor layer, 221-First sub-region, 222-Second sub-region, 223-Contact region, 224-First pit microstructure, 225-Second pit microstructure, 226-Third pit microstructure, 227-Protrusion microstructure, 23-First conductive layer, 24-First electrode, 21'-First passivation film, 22'-First doped semiconductor film, 25-Protective film; 3-Second polar structure, 31-Second passivation layer, 32-Second doped semiconductor layer, 33-Second conductive layer, 34-Second electrode; 31'-Second passivation film, 32'-Second doped semiconductor film; 4-Isolation trench, 5-Third passivation layer, 6-Anti-reflection layer. Detailed Implementation

[0056] To make the technical problems, technical solutions, and beneficial effects of this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0057] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0058] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can both mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple.

[0059] It should be understood that in the various embodiments of this application, the order of the above processes does not imply the order of execution. Some or all steps may be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0060] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0061] The weights of the relevant components mentioned in the embodiments of this application can refer not only to the specific content of each component, but also to the proportional relationship between the weights of the components. Therefore, any scaling up or down of the content of the relevant components according to the embodiments of this application is within the scope disclosed in the embodiments of this application. Specifically, the mass described in the embodiments of this application can be a well-known unit of mass in the chemical industry, such as µg, mg, g, or kg.

[0062] The terms "first" and "second" are used for descriptive purposes only, to distinguish objects, such as substances, from one another, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. For example, without departing from the scope of the embodiments of this application, "first XX" may also be referred to as "second XX," and similarly, "second XX" may also be referred to as "first XX." Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature.

[0063] Faced with ever-increasing global energy demand, the photovoltaic industry, as a major force in renewable energy, relies on continuously improving the conversion efficiency of solar cells as its core driving force for technological development. Among various high-efficiency cell technologies, back-contact (BC) solar cells represent an important development direction for crystalline silicon cell technology. This technology integrates all metal electrodes, emitters, and back fields on the back of the cell, completely eliminating the shading of incident light by the front metal grid lines. This revolutionary structural design brings two core advantages: first, it significantly reduces carrier recombination losses on the front of the cell; second, it maximizes the absorption and utilization of incident sunlight, thereby simultaneously increasing the cell's short-circuit current and open-circuit voltage, ultimately significantly improving photoelectric conversion efficiency. Furthermore, back-contact technology is essentially a highly compatible "platform-type" technology architecture, capable of deep integration with various advanced passivation contact technologies, such as tunneling oxide passivation contact (TOPCon) technology and heterojunction (HJT) technology, continuously pushing the efficiency limits through structural innovation.

[0064] Among the various back contact technologies, a technology route known as "hybrid back contact" (HBC) has become a research focus in academia and industry due to its outstanding potential. This technology ingeniously integrates the advantages of HJT and TOPCon technologies on the same back side of the battery, aiming to achieve an optimal balance between ultimate battery efficiency, process complexity, and manufacturing cost. A typical hybrid HBC battery fabrication process requires a strict process sequence: first, a high-temperature TOPCon structure, consisting of a tunneling oxide layer and a doped polycrystalline silicon stack, is fabricated on the back surface of the semiconductor substrate; then, a crucial surface cleaning is performed; finally, a low-temperature HJT structure, consisting of an intrinsic amorphous silicon stack and a doped amorphous / microcrystalline silicon stack, is deposited.

[0065] However, this approach combining high-temperature and low-temperature processes presents an inherent challenge: to obtain a clean, ideal surface before depositing the HJT amorphous silicon layer, which is extremely sensitive to interface quality, a cleaning process must be introduced. Existing techniques typically employ a cleaning step involving alkaline treatment to effectively remove contaminants and the native oxide layer. However, this approach has a significant drawback: the alkaline solution uncontrollably etches the exposed surface of the doped polysilicon layer during the cleaning process. This etching leads to uneven polysilicon layer thickness, deep pits on the surface, and the introduction of numerous lattice defects and recombination centers.

[0066] This initial damage triggers a series of adverse reactions. The TOPCon stack, whose surface has already been damaged by the alkaline solution, suffers a decline in mechanical integrity and passivation quality. In subsequent unavoidable patterning processes such as laser delamination and wet etching, it is more prone to secondary damage such as microcracks and over-etching, leading to a severe degradation of its excellent passivation performance. Ultimately, this "invisible" damage introduced by the basic cleaning process becomes a bottleneck restricting further efficiency improvements in hybrid HBC cells and affecting their process window and yield.

[0067] To address the damage caused by alkaline cleaning, existing solutions primarily focus on the cleaning process itself, mainly by providing novel cleaning agents or developing alternative cleaning processes. However, these methods have drawbacks: firstly, their protective effect on TOPCon layers has an upper limit, and the degree of damage reduction is limited; secondly, they often lead to more complex cleaning processes, increased costs, and potential derivative risks such as insufficient cleaning effectiveness.

[0068] To effectively mitigate the damage caused by alkaline cleaning, the embodiments of this application provide the following solutions.

[0069] [Back contact solar cell] In a first aspect, embodiments of this application provide a back-contact solar cell. The back-contact solar cell of this application includes a semiconductor substrate, a plurality of first polarity structures, and a plurality of second polarity structures; on the backlight surface of the semiconductor substrate, the first polarity structures and the second polarity structures are alternately arranged in a direction parallel to the backlight surface.

[0070] In some embodiments of this application, the structure of the back contact solar cell is as follows: Figure 1 As shown, it includes a semiconductor substrate 1, a plurality of first polar structures 2 and a plurality of second polar structures 3; on the backlight surface 11 of the semiconductor substrate 1, the first polar structures 2 and the second polar structures 3 are alternately arranged in a direction parallel to the backlight surface 11.

[0071] Among them, the direction along the parallel backlight surface 11 is as follows Figure 1 In the x-axis direction, the first polar structure 2 and the second polar structure 3 are alternately arranged on the backlight surface 11 of the semiconductor substrate 1. As in the embodiment, the first polar structure 2 and the second polar structure 3 can be alternately arranged on the backlight surface 11 of the semiconductor substrate 1 to form an interdigitated array structure.

[0072] Semiconductor substrate: In the back-contact solar cell of this application embodiment, the semiconductor substrate it contains is as follows: Figure 1 As shown, it has a backlight surface 11 and a light-receiving surface 12 opposite to the backlight surface 11. During the operation of the back contact solar cell, sunlight (photons) enters the interior of the semiconductor substrate 1 from the light-receiving surface 12. When the energy of the photon is greater than or equal to the band gap of the semiconductor material in the semiconductor substrate 1, it will excite the valence band electrons of the semiconductor material to jump to the conduction band, thereby generating electron-hole pairs in the semiconductor.

[0073] like Figure 1 As shown, the backlight surface 11 of the semiconductor substrate 1 is provided with a plurality of first polarity regions R1 and a plurality of second polarity regions R2. At this time, along the parallel backlight surface... Figure 1 In the x-direction, the first polarity region R1 and the second polarity region R2 are alternately distributed. Specifically, the first polarity structure 2 is located in the first polarity region R1, and the second polarity structure 3 is located in the second polarity region R2; of course, their positions can also be interchanged, such as the first polarity structure 2 being located in the second polarity region R2, and the second polarity structure 3 being located in the first polarity region R2.

[0074] In some embodiments, such as Figure 1 As shown, the light-receiving surface 12 of the semiconductor substrate 1 can be a textured structure. This can reduce the reflectivity of sunlight on the light-receiving surface 12, increase the absorption rate of sunlight, and thus improve the short-circuit current and conversion efficiency of the back-contact solar cell.

[0075] In some embodiments, the material of the semiconductor substrate 1 may include single-crystal silicon, gallium arsenide, or other III-V compound semiconductors, or materials such as germanium. The doping type of the semiconductor substrate 1 may be N-type doped or P-type doped. Of course, the material of the semiconductor substrate 1 may also be other semiconductor materials used in the field of solar cells.

[0076] First polar structure: In the back-contact solar cell of this application embodiment, "a plurality of" in "a plurality of first polarity structures" indicates that the number of first polarity structures contained in the back-contact solar cell is one or more, generally multiple.

[0077] In one embodiment of the back-contact solar cell of this application, the first polarity structure may be a tunnel oxide passivated contact (TOPCon) structure. Setting the first polarity structure as a TOPCon structure can comprehensively improve the photoelectric conversion efficiency of the back-contact solar cell of this application from the dimensions of voltage (through excellent passivation), current (through low recombination), and fill factor (through low resistance).

[0078] In a first polar structure, a first functional layer and a first electrode structure are included, with the first functional layer disposed between a semiconductor substrate and the first electrode structure. The first functional layer includes a first passivation layer and a first doped semiconductor layer, with the first passivation layer disposed between the first doped semiconductor layer and the semiconductor substrate. In at least a portion of the first polar structure, the first doped semiconductor layer includes a first sub-region, a second sub-region, and a contact region. At least one first sub-region is in contact with an adjacent second polar structure, and the second sub-region is disposed between the first sub-region and the contact region. The surface roughness of the first sub-region away from the semiconductor substrate is R. z1 The surface roughness of the second sub-region away from the semiconductor substrate is R. z2 And R z1 >R z2 .

[0079] Based on the above connection relationship between the first sub-region, the second sub-region, and the contact region in the first doped semiconductor layer, the first sub-region and the second sub-region are located at the end of the first doped semiconductor layer, and the contact region is located at the middle of the two ends opposite to each other. The first sub-region, the second sub-region, and the contact region are arranged sequentially from the first sub-region to the contact region.

[0080] Based on the above structure of the first polar structure and the first doped semiconductor layer, as in some embodiments, the structure of the first polar structure 2 is as follows: Figure 1As shown, the first polar structure 2 includes a first functional layer and a first electrode structure, with the first functional layer disposed between the semiconductor substrate 1 and the first electrode structure. The first functional layer includes a first passivation layer 21 and a first doped semiconductor layer 22, with the first passivation layer 21 disposed between the first doped semiconductor layer 22 and the semiconductor substrate 1, i.e., in the case of... Figure 1 Along the y-axis, a semiconductor substrate 1, a first passivation layer 21, and a first doped semiconductor layer 22 are sequentially stacked. In at least a portion of the first polar structure 2, the first doped semiconductor layer 22 includes opposing ends and a contact region 223 located between the two ends. Each end includes a first sub-region 221 and a second sub-region 222. At least one end's first sub-region 221 contacts an adjacent second polar structure 3, and the second sub-region 222 is located between the first sub-region 221 and the contact region 223. The surface roughness of the first sub-region 221 away from the semiconductor substrate 1 is R. z1 The surface roughness of the second sub-region 222, which is away from the semiconductor substrate 1, is R. z2 And R z1 >R z2 .

[0081] In this way, by providing a first sub-region and a second sub-region at the middle end of at least a portion of the first doped semiconductor layer contained in the first polar structure, and controlling the surface roughness of the first sub-region and the second sub-region in the aforementioned relationship, compared with existing back contact solar cells with tunnel oxide passivation contact structures, at least the following effects are achieved: (1) It can improve the thickness uniformity of the second sub-region and the contact region of the first doped semiconductor layer in the first polar structure and enhance the passivation strength of the first passivation layer; specifically, the surface roughness of the first sub-region at the end of the first doped semiconductor layer is greater than that of the second sub-region, which can significantly improve the thickness uniformity of the first doped semiconductor layer and improve the overall surface quality of the surface away from the semiconductor substrate, such as reducing the overall surface roughness and making the surface smoother; at the same time, it can significantly improve the structural integrity of the first passivation layer. (2) The protection effect of the first doped semiconductor layer on the first passivation layer is improved, the structural integrity of the first passivation layer is significantly improved, the passivation quality of the first passivation layer is enhanced, its carrier tunneling ability and selective collection function are improved, and the loss of carriers during transport is reduced.

[0082] (3) The surface roughness of the first sub-region at the end of the first doped semiconductor layer, which is far from the semiconductor substrate, is greater than that of the second sub-region, thereby improving the contact interface quality between the first doped semiconductor layer and the first electrode structure in the first polar structure, increasing the effective contact area between the two layers, and reducing the contact resistance.

[0083] Therefore, in the back-contact solar cell of this application embodiment, the first doped semiconductor layer containing the second sub-region in the first polarity structure can effectively enhance the passivation strength of the first passivation layer, and can significantly enhance the electrical performance of the back-contact solar cell, such as the conversion efficiency and fill factor. Here, the surface roughness Rz of the first and second sub-regions at the end of the first doped semiconductor layer, away from the semiconductor substrate, refers to the vertical distance between the highest peak and the lowest valley on the surface of the first doped semiconductor layer away from the semiconductor substrate or a certain region of that surface. In other words, the roughness characterizes the extreme fluctuation range of the surface or a certain region of that surface. For example, if the roughness is R... z1 Rz refers to the extreme fluctuation range of the surface of the first sub-region away from the semiconductor substrate, that is, it characterizes the extreme fluctuation range of the surface of the first sub-region away from the semiconductor substrate. This roughness Rz can be detected using a scanning electron microscope (SEM) or an atomic force microscope (AFM).

[0084] Furthermore, the aforementioned phrase "at least in some first polar structures, the first doped semiconductor layer includes opposing ends and a contact region located between the ends, the ends including a first sub-region and a second sub-region" can be understood to mean that in all first polar structures, the first doped semiconductor layer may include the contact region and the ends containing the first and second sub-regions. Of course, it is also possible that some or a small number of first polar structures may not include the contact region and the ends may not contain the second sub-region. In actual production, generally, the first doped semiconductor layer of all first polar structures distributed in the middle region of the backlight surface of the semiconductor substrate includes the contact region and the ends containing the first and second sub-regions; while the first doped semiconductor layer of the outermost first polar structures distributed in the two end regions of the backlight surface of the semiconductor substrate does not include the contact region and the ends may not contain the second sub-region, but the ends may contain the first sub-region. For example, in some embodiments, in... Figure 1 On the backlight surface 11 of the semiconductor substrate 1 shown, along the x-axis direction, except for the first polar structures 2 at the outermost two ends, all other first polar structures 2 include contact areas 223, and their ends include first sub-regions 221 and second sub-regions 222; the first polar structures 2 at the outermost two ends do not contain contact areas 223, and their ends contain first sub-regions 221 but do not contain second sub-regions 222.

[0085] In some embodiments, such as Figure 1 The surface roughness R of the first sub-region 221 at the end of the first doped semiconductor layer 22 shown is... z1 The surface roughness R of the second sub-region 222 surface z2The ratio is (1.5~1000):1. In the examples, it can be a typical but non-restrictive ratio such as 1.5:1, 10:1, 50:1, 100:1, 300:1, 500:1, 800:1, 1000:1, or any range between two ratios.

[0086] In some embodiments, such as Figure 1 In the end of the first doped semiconductor layer 22 shown, the first sub-region 221 is far from the surface roughness R of the semiconductor substrate 1. z1 The roughness can be 1 nm to 100 nm, optionally 10 nm to 30 nm or 30 nm to 60 nm. In the example, it can be a typical but non-limiting roughness such as 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 90 nm, or 100 nm, or any range between two roughness values.

[0087] In some embodiments, such as Figure 1 In the end of the first doped semiconductor layer 22 shown, the second sub-region 222 is far from the surface roughness R of the semiconductor substrate 1. z2 The roughness can be 0.1 nm to 40 nm, optionally 0.1 nm to 10 nm or 10 nm to 20 nm. In the example, it can be a typical but non-limiting roughness such as 0.1 nm, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm, or a range between any two roughness values.

[0088] The first sub-region 221 and the second sub-region 222 having the above-mentioned roughness ratio range and / or the above-mentioned roughness range can, together with the contact region 223, improve the thickness uniformity of the second sub-region 222 and the contact region 223 of the first doped semiconductor layer 22, and improve the protection of the first passivation layer 21, and enhance the passivation strength of the first passivation layer 21; at the same time, they can also improve the ohmic contact characteristics between the first doped semiconductor layer 22 and the first electrode structure.

[0089] In some embodiments, such as Figure 1 In the end of the first doped semiconductor layer 22 shown, the surface of the first sub-region 221 away from the semiconductor substrate 1 is provided with a first pit microstructure 224, and the surface of the second sub-region 222 away from the semiconductor substrate 1 is provided with a second pit microstructure 225, as shown. Figure 2 As shown, the minimum distance w1 between the first pit microstructure 224 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, and the minimum distance w2 between the second pit microstructure 225 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, are such that w2 > w1.

[0090] By controlling the film thickness of the second sub-region 222 shown in w2 to be greater than the film thickness of the first sub-region 221 shown in w1, the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21 can be improved, the layer structure integrity of the first passivation layer 21 can be improved, and the passivation strength of the first passivation layer 21 can be enhanced. The first pit microstructure 224 and the second pit microstructure 225 refer to pits with a depth and pit diameter in the nanometer range distributed on the surfaces of the first sub-region 221 and the second sub-region 222 away from the semiconductor substrate 1, respectively.

[0091] In the embodiments, in such Figure 1 In the end of the first doped semiconductor layer 22 shown, the minimum distance w1 between the first pit microstructure 224 contained in the surface of the first sub-region 221 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1 can be 29 nm to 220 nm, optionally 50 nm to 130 nm. In the exemplary example, it can be a typical but non-limiting distance such as 20 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 220 nm, or any range between two distance values.

[0092] In the embodiments, in such Figure 1 In the end of the first doped semiconductor layer 22 shown, the minimum distance w2 between the second pit microstructure 225 contained in the second sub-region 222 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1 can be 49 nm to 240 nm, optionally 70 nm to 150 nm. In the exemplary example, it can be a typical but non-limiting distance such as 49 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 240 nm, or any range between two distance values.

[0093] The first sub-region 221 and the second sub-region 222, having the film layer ranges shown in w1 and w2 above, can work together with the contact region 223 to improve the structural integrity of the first passivation layer 21, enhance the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, and strengthen the passivation strength of the first passivation layer 21; at the same time, they can improve the quality of the contact interface between the first doped semiconductor layer 22 and the first electrode structure, and strengthen the passivation strength of the first passivation layer 21.

[0094] In the embodiments, in such Figure 1In the first doped semiconductor layer 22 shown, along the direction from its first sub-region 221 to the contact region 223, the ratio of the length d1 of the first sub-region 221 to the length d2 of the second sub-region 222 is (0.03~15):1, optionally (0.1~5):1. In the example, it can be a typical but non-limiting length ratio such as 0.03:1, 0.1:1, 0.2:1, 0.5:1, 1:1, 2:1, 5:1, 8:1, 10:1, 12:1, 15:1, or any range between two length ratios. This range of length ratios can reduce the length proportion of the first sub-region 221 in the first doped semiconductor layer 22, thereby improving the overall integrity of the first passivation layer 21 structure and protecting the passivation effect of the first passivation layer 21 on the semiconductor substrate; at the same time, it improves the contact interface performance between the first doped semiconductor layer 22 and the first electrode structure.

[0095] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, along the direction from its first sub-region 221 to the contact region 223, the ratio of the length d2 of the second sub-region 222 to the length d3 of the contact region 223 can be (0.02~2):1, optionally (0.1~1):1. In the example, it can be a typical but non-limiting length ratio such as 0.02:1, 0.1:1, 0.5:1, 1:1, 1.5:1, 2:1, or any range between two length ratios. This range of length ratios can increase the contact area between the contact region 223 and the first electrode structure, and improve the interface performance between the first doped semiconductor layer 22 and the first electrode structure.

[0096] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, along the direction from its first sub-region 221 to the contact region 223, the length d1 of the first sub-region 221 can be 3 nm to 75 nm, optionally 5 to 50 nm. In the example, it can be a typical but non-limiting length such as 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, or any range between two length values. The first sub-region 221 with this length range can, together with the second sub-region 222 and the contact region 223, improve the structural integrity of the first passivation layer 21 and protect the passivation effect of the first passivation layer 21 on the semiconductor substrate; at the same time, it can improve the contact area and ohmic contact characteristics between the first doped semiconductor layer 22 and the first electrode structure. A shorter length for the first sub-region 221 is more desirable.

[0097] In the embodiments, in such Figure 1In the first doped semiconductor layer 22 shown, along the direction from its first sub-region 221 to the contact region 223, the length d2 of the second sub-region 222 can be 5~100 nm, optionally 10~75 nm. In the example, it can be a typical but non-limiting length such as 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, or any range between two length values. The second sub-region 222 with this length range can, together with the contact region 223, improve the structural integrity of the first passivation layer 21 and protect the passivation effect of the first passivation layer 21 on the semiconductor substrate; at the same time, it can improve the ohmic contact characteristics between the first doped semiconductor layer 22 and the first electrode structure.

[0098] In some embodiments, such as Figure 1 In the first doped semiconductor layer 22 shown, the surface of its contact region 223 away from the semiconductor substrate 1 has a third pit microstructure 226 and / or a protrusion microstructure 227. The provision of the third pit microstructure 226 and / or the protrusion microstructure 227 can increase the roughness of the surface of the contact region 223 away from the semiconductor substrate 1, thereby enhancing the ohmic contact characteristics between the first doped semiconductor layer 22 and the first electrode structure. The third pit microstructure 226 refers to pits with a depth and pit diameter in the nanometer range distributed on the surface of the contact region 223 away from the semiconductor substrate 1, facing the semiconductor substrate 1. The protrusion microstructure 227 refers to protrusions with a height and width in the nanometer range distributed on the surface of the contact region 223 away from the semiconductor substrate 1, facing away from the semiconductor substrate 1.

[0099] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a third pit microstructure 226, the depth of the third pit microstructure 226 can be from 0.1 nm to 60 nm. In the example, it can be a typical but non-limiting depth such as 0.1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or 60 nm, or a range between any two depth values. The depth of the third pit microstructure 226 refers to... Figure 1 The straight-line distance from the opening of the third pit microstructure 226 to the bottom of the pit of the third pit microstructure 226 shown.

[0100] In the embodiments, in such Figure 1In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a third pit microstructure 226, the width of the opening of the third pit microstructure 226 can be 0.1 nm to 120 nm. In the example, it can be a typical but non-limiting width ratio or a range between any two width values, such as 0.1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, or 120 nm. The width of the opening of the third pit microstructure 226 refers to the width of the opening within a certain range. Figure 1 The straight-line distance between the opening side and the opposite side of the third pit microstructure 226 shown.

[0101] The third pit microstructure 226 with the aforementioned depth and opening width range can improve the surface quality of the first doped semiconductor layer 22. On the one hand, it can enhance the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, improve the structural integrity of the first passivation layer 21, and enhance the passivation strength of the first passivation layer 21; on the other hand, it enhances the ohmic contact characteristics with the first electrode structure.

[0102] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a third pit microstructure 226, the third pit microstructure 226 can be an etched pit. Here, the etched pit refers to a pit formed by an etching process. Therefore, the depth and opening width of the third pit microstructure 226 do not necessarily have to be exactly the same.

[0103] In some embodiments, such as Figure 1 In the first doped semiconductor layer 22, such as Figure 2 As shown, when the surface of the contact area 223 is provided with a third pit microstructure 226, the minimum distance w3 between the third pit microstructure 226 contained on the surface of the contact area 223 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, combined with the minimum distance w1 between the surface of the first sub-region 221 away from the semiconductor substrate 1 provided with a first pit microstructure 224 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, then w3 > w1.

[0104] In the embodiments, in such Figure 1 At the end of the first doped semiconductor layer 22, such as Figure 2As shown, the minimum distance w3 between the third pit microstructure 226 contained on the surface of the contact area 223 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1 can be 48 nm to 290 nm. It can be a typical but non-limiting distance such as 48 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 260 nm, 290 nm, or any range between two distance values.

[0105] By controlling the film thickness of the contact region 223 shown in w3 to be greater than the film thickness of the first sub-region 221 shown in w1 above, or by further controlling the film thickness of the contact region 223 shown in w3 within the above range, it is possible to improve the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, improve the layer structure integrity of the first passivation layer 21, and enhance the passivation strength of the first passivation layer 21.

[0106] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a raised microstructure 227, the raised microstructure 227 is as follows: Figure 2 The height h3 shown is 1 nm to 100 nm. In the example, it can be a typical but non-limiting height such as 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any range between two height values. The height of the protruding microstructure 227 can be as follows: Figure 1 The line L connecting the two ends of the first doped semiconductor layer 22 away from the highest point of the surface of the semiconductor substrate 1 is taken as the reference height to one side of the first electrode structure, that is, as shown in the figure. Figure 2 The height is shown in h3. The height of this protruding microstructure 227 can also be detected using scanning electron microscopy (SEM) or transmission electron microscopy (TEM).

[0107] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a raised microstructure 227, the raised microstructure 227 is as follows: Figure 2The width 'a' of the root shown is 1 nm to 100 nm, optionally 5 nm to 50 nm. In the example, it can be a typical but non-limiting height such as 1 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or any range between two height values. The width of the root of the protruding microstructure 227 refers to the maximum distance between the two edges of the protruding microstructure 227, measured along a direction parallel to the surface of the first doped semiconductor layer 22, at the root position where the protruding microstructure 227 meets the surface of the first doped semiconductor layer 22. Figure 2 The distance shown in a is as follows. When the morphology of the protruding microstructure 227 is a protruding granular structure, such as a hemispherical morphology, the width of the root of the protruding microstructure 227 can be up to the diameter of the protruding microstructure 227.

[0108] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a protruding microstructure 227, the morphology of the protruding microstructure 227 includes at least one of granular structure, blocky structure, hill-like structure, and irregular protrusion.

[0109] The protruding microstructure 227 with the above-mentioned height, root width and morphology can, together with the third pit microstructure 226 contained on the surface of the contact area 223, further improve the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, and at the same time improve the contact interface quality between the first electrode structure and the first electrode structure.

[0110] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a protruding microstructure 227, the protruding microstructure 227 can also be a protruding microstructure 227 formed during the patterning process of the second functional layer by laser ablation. Therefore, the height, root width, and morphology of the protruding microstructure 227 may not be exactly the same.

[0111] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the contact region 223 on the surface away from the semiconductor substrate 1 is provided with a third pit microstructure 226 and / or a protrusion microstructure 227, the roughness R of the surface of the contact region 223 away from the semiconductor substrate 1 is... z3 And the R z3 The surface roughness R of the second sub-region 222 at the end above is greater than that of the semiconductor substrate 1. z2 In this embodiment, the contact area 223 is located away from the surface roughness R of the semiconductor substrate 1. z3The roughness can range from 2 nm to 160 nm. In the example, it can be a typical but non-limiting roughness such as 2 nm, 5 nm, 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, 130 nm, or 160 nm, or any range between two roughness values. The surface roughness of the contact region 223 away from the semiconductor substrate 1 is controlled to be greater than the surface roughness of the second sub-region 222, and its surface roughness R is further controlled to be greater than that of the second sub-region 222. z3 Controlling the above range can, on the one hand, improve the surface quality of the first doped semiconductor layer 22, enhance the structural integrity of the first passivation layer 21, and improve the passivation strength and other properties of the first passivation layer 21; on the other hand, it can improve its ohmic contact characteristics with the first electrode structure.

[0112] In some embodiments, such as Figure 1 In the first polar structure 2 shown, the material of the first doped semiconductor layer 22 may include doped polysilicon. Of course, other doped semiconductor materials suitable for the doped semiconductor layer in the TOPCon structure may also be used. The doping type may be the same as or opposite to the doping type of the semiconductor substrate, and the thickness may be any thickness within the range of 50 to 250 nm, such as typical but non-limiting thicknesses like 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm, or any range between two thicknesses, or other thickness ranges.

[0113] In some embodiments, such as Figure 1 In the first polar structure 2 shown, the first passivation layer 21 contained therein can be directly disposed in the first polar region R1 of the semiconductor substrate 1.

[0114] In this embodiment, the surface of the semiconductor substrate 1 that is in contact with the first passivation layer 21 is a polished surface, such as the first polar region R1 that is in contact with the first passivation layer 21 being a polished surface; then the corresponding contact surface between the first passivation layer 21 and the semiconductor substrate 1 is also a polished surface, which can improve the passivation effect of the first passivation layer 21.

[0115] In the embodiments, in such Figure 1 In the first polar structure 2 shown, the material of the first passivation layer 21 contained therein may include tunneling oxide, and its thickness may be flexibly adjusted according to design needs. For example, it may be any thickness within the range of 0.5 nm to 2.5 nm, such as typical but non-limiting thicknesses such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or any range between two thicknesses, or other thickness ranges.

[0116] In some embodiments, such as Figure 1The first polar structure 2 shown includes a first conductive layer 23 and a first electrode 24. The first conductive layer 23 is disposed on the surface of the first doped semiconductor layer 22 away from the semiconductor substrate 1, and the first electrode 24 is disposed on the surface of the first conductive layer 23 away from the semiconductor substrate 1.

[0117] In the embodiments, such as Figure 1 The material of the first conductive layer 23 shown may include conductive oxide or doped conductive oxide; as in the example, the material of the first conductive layer 23 may include at least one of doped or undoped zinc oxide, indium oxide, and tin oxide. The doping element may include at least one metallic element selected from gallium (Ga), tin (Sn), titanium (Ti), zirconium (Zr), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al). Furthermore, the thickness of the second conductive layer 33 can be flexibly adjusted according to design requirements, such as any thickness within the range of 30 nm to 85 nm, including typical but non-limiting thicknesses such as 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, and 85 nm, or any range between two thicknesses, or other thickness ranges.

[0118] In the embodiments, such as Figure 1 The material of the first electrode 24 shown may include a metallic element or an alloy; for example, in the exemplary embodiment, the material of the first electrode 24 may include at least one of silver, copper, tin, etc. Furthermore, the thickness of the first electrode 24 can be flexibly adjusted according to design requirements.

[0119] Second polar structure: In the back-contact solar cell of this application embodiment, "a plurality of" in "a plurality of second polarization structures" indicates that the number of second polarization structures contained in the back-contact solar cell is one or more, generally multiple.

[0120] In the back-contact solar cell of this application embodiment, the polarity of the second polarity structure is different from the polarity of the first polarity structure mentioned above.

[0121] In the second polarity structure, the second polarity structure includes a second functional layer and a second electrode structure. The second functional layer is disposed between the semiconductor substrate and the second electrode structure. The second functional layer includes a second passivation layer and a second doped semiconductor layer, with the second passivation layer disposed between the second doped semiconductor layer and the semiconductor substrate. The second electrode structure includes a second conductive layer and a second electrode, with the second conductive layer at least partially disposed between the second doped semiconductor layer and the second electrode. That is, along the direction away from the semiconductor substrate, the second doped semiconductor layer, the semiconductor substrate, the second conductive layer, and the second electrode are sequentially arranged.

[0122] In some embodiments, the structure of the second polar structure 3 is as follows: Figure 1 As shown, the second polar structure 3 includes a second functional layer and a second electrode structure. The second functional layer is disposed between the semiconductor substrate 1 and the second electrode structure. The second functional layer includes a second passivation layer 31 and a second doped semiconductor layer 32. The second electrode structure includes a second conductive layer 33 and a second electrode 34. The second conductive layer 33 is at least partially disposed between the second doped semiconductor layer 32 and the second electrode 34; that is, along a direction away from the semiconductor substrate 1 (along such a direction). Figure 1 (Extending along the y-axis), a semiconductor substrate 1, a second passivation layer 31, a second doped semiconductor layer 32, a second conductive layer 33, and a second electrode 34 are sequentially arranged.

[0123] In some embodiments, the structure of the second polar structure 3 is as follows: Figure 1 As shown, the second functional layer contained therein extends into the first polar structure 2 above and forms an overlapping region. Specifically, the second functional layer of the second polar structure 3, containing a second passivation layer 31 and a second doped semiconductor layer 32, extends into the first polar structure 2 above and at least covers the end surface of the first doped semiconductor layer 22 in the first polar structure 2 that is away from the semiconductor substrate 1. In the embodiment, when the end of the first doped semiconductor layer 22 in the first polar structure 2 includes as follows... Figure 1 When the first sub-region 221 and the second sub-region 222 are shown, the second functional layer in the second polar structure 3, which includes the second passivation layer 31 and the second doped semiconductor layer 32, extends to the end surface of the first doped semiconductor layer 22 in the first polar structure 2 that is away from the semiconductor substrate 1, and covers the surfaces of the first sub-region 221 and the second sub-region 222. In this way, the back surface of the semiconductor substrate 1 can be fully passivated, reducing the recombination of charge carriers on the back surface and improving the electrical performance of the back contact solar cell, such as the open-circuit voltage, fill factor, and conversion efficiency.

[0124] In some embodiments, such as Figure 1 In the second polar structure 3 shown, the material of the second passivation layer 31 may include intrinsic amorphous silicon, and its thickness can be flexibly adjusted according to design needs. For example, it can be any thickness within the range of 5 nm to 15 nm, such as typical but non-limiting thicknesses like 5 nm, 8 nm, 10 nm, 13 nm, and 15 nm, or any range between two thicknesses, or even other thickness ranges. The second passivation layer 31 with this material and thickness range has good passivation performance.

[0125] In some embodiments, such as Figure 1In the second polar structure 3 shown, the material of the second doped semiconductor layer 32 may include doped amorphous silicon and / or microcrystalline silicon; moreover, the doping type of the second doped semiconductor layer 32 is opposite to the doping type of the first doped semiconductor layer 22 in the first polar structure 2 described above. For example, if the first doped semiconductor layer 22 is N-type doped, then the second doped semiconductor layer 32 may be P-type doped; conversely, if the first doped semiconductor layer 22 is P-type doped, then the second doped semiconductor layer 32 may be N-type doped. The thickness of the second doped semiconductor layer 32 can be flexibly adjusted according to design needs, such as any thickness within the range of 10 nm to 50 nm, including typical but non-limiting thicknesses such as 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm, or any range between two thicknesses, or even other thickness ranges. The second doped semiconductor layer 32 with this material and thickness range exhibits good carrier transport performance.

[0126] In some embodiments, such as Figure 1 In the second polar structure 3 shown, the material of the second conductive layer 33 contained in the second electrode structure can be the same as or different from the material of the first conductive layer 23 in the first polar structure 2 described above. Specifically, it can include conductive oxides or doped conductive oxides. For example, in the exemplary example, the material of the second conductive layer 33 can include at least one of doped or undoped zinc oxide, indium oxide, and tin oxide. The doping element can include at least one metal element selected from gallium (Ga), tin (Sn), titanium (Ti), zirconium (Zr), molybdenum (Mo), cerium (Ce), fluorine (F), tungsten (W), and aluminum (Al). In addition, the thickness of the second conductive layer 33 can be flexibly adjusted according to design needs. For example, it can be any thickness within the range of 30 nm to 85 nm, such as typical but non-limiting thicknesses like 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, and 85 nm, or any range between two thicknesses, or other thickness ranges.

[0127] In the embodiments, in such Figure 1 In the second polar structure 3 shown, the material of the second electrode 34 can be the same as or different from the material of the first electrode 24 in the first polar structure 2 described above. For example, it can include a metallic element or an alloy; in the example, the material of the second electrode 34 can include at least one of silver, copper, tin, etc. In addition, the thickness of the second electrode 34 can be flexibly adjusted according to design requirements.

[0128] Furthermore, in the back-contact solar cells of the above embodiments, an isolation groove is provided between the first electrode structure in the first polarity structure and the second electrode structure in the second polarity structure, thereby insulating the first electrode structure in the first polarity structure and the second electrode structure in the second polarity structure. As in the embodiments, in... Figure 1 In the back-contact solar cell shown, an isolation trench 4 is further provided between the first conductive layer 23 and the second conductive layer 33, so that the first electrode structure containing the first conductive layer 23 and the first electrode 24 is insulated from the second electrode structure containing the second conductive layer 33 and the second electrode 34, thereby preventing a short circuit between the first polar structure 2 and the second polar structure 3. The isolation trench 4 can also be provided above the first polar structure R1 away from the semiconductor substrate 1.

[0129] In some embodiments, such as Figure 1 As shown, in the above embodiments, the light-receiving surface 12 of the semiconductor substrate 1 of the back-contact solar cell is further provided with a third passivation layer 5 and an anti-reflection layer 6; wherein, the third passivation layer 5 is in contact with the light-receiving surface 12 of the semiconductor substrate 1, and the anti-reflection layer 6 is disposed on the surface of the third passivation layer 5 away from the semiconductor substrate 1. When the light-receiving surface 12 of the semiconductor substrate 1 has a textured structure as described above, the third passivation layer 5 is disposed on the light-receiving surface 12 of the textured structure. Adding a third passivation layer 5 to the light-receiving surface 12 of the semiconductor substrate 1, such as the textured light-receiving surface 12, can effectively saturate these dangling bonds, thereby passivating the light-receiving surface 12 and reducing the recombination probability of holes and electrons on the light-receiving surface 12. The anti-reflection layer 6 can reduce the reflectivity of sunlight and improve the utilization rate of sunlight; at the same time, it can also protect the anti-reflection layer 6, improving the long-term reliability and stability of the back-contact solar cell.

[0130] In the embodiments described above, when the light-receiving surface 12 of the semiconductor substrate 1 that is in back contact with the solar cell is further provided with a third passivation layer 5 and an antireflection layer 6, the third passivation layer 5 may include at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin-film silicon, and a composite layer of tunneling oxide and doped polycrystalline silicon. The material of the antireflection layer 6 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium fluoride, and transparent conductive oxide.

[0131] Secondly, embodiments of this application also provide another type of back-contact solar cell. The functional layer structure of the back-contact solar cell in this application embodiment can be the functional layer structure of the first type of back-contact solar cell described above. In some embodiments, the back-contact solar cell in this application embodiment includes a semiconductor substrate, a plurality of first polarity structures and a plurality of second polarity structures; on the backlight surface of the semiconductor substrate, the first polarity structures and the second polarity structures are alternately arranged in a direction parallel to the backlight surface.

[0132] In some embodiments of this application, the back-contact solar cell structure can also be as follows: Figure 1 As shown, it includes a semiconductor substrate 1, a plurality of first polar structures 2 and a plurality of second polar structures 3; on the backlight surface 11 of the semiconductor substrate 1, the first polar structures 2 and the second polar structures 3 are alternately arranged in a direction parallel to the backlight surface 11.

[0133] Among them, the direction along the parallel backlight surface 11 is as follows Figure 1 In the x-axis direction, the first polar structure 2 and the second polar structure 3 are alternately arranged on the backlight surface 11 of the semiconductor substrate 1. As in the embodiment, the first polar structure 2 and the second polar structure 3 can be alternately arranged on the backlight surface 11 of the semiconductor substrate 1 to form an interdigitated array structure.

[0134] Semiconductor substrate: In the back-contact solar cells of this application embodiment, the semiconductor substrate contained therein can be the same as the semiconductor substrate contained in the first type of back-contact solar cell of this application described above. Figure 1 As shown, it has a backlight surface 11 and a light-receiving surface 12 opposite to the backlight surface 11. The backlight surface 11 is provided with a plurality of first polarity regions R1 and a plurality of second polarity regions R2. At this time, along the parallel backlight surface, as shown... Figure 1 In the x-direction, the first polarity region R1 and the second polarity region R2 are alternately distributed. Specifically, the first polarity structure 2 is located in the first polarity region R1, and the second polarity structure 3 is located in the second polarity region R2; of course, their positions can also be interchanged, such as the first polarity structure 2 being located in the second polarity region R2, and the second polarity structure 3 being located in the first polarity region R2.

[0135] In some embodiments, such as Figure 1 As shown, the light-receiving surface 12 of the semiconductor substrate 1 can be a textured structure. This can reduce the reflectivity of sunlight on the light-receiving surface 12, increase the absorption rate of sunlight, and thus improve the short-circuit current and conversion efficiency of the back-contact solar cell.

[0136] In some embodiments, the material of the semiconductor substrate 1 may include single-crystal silicon, gallium arsenide, or other III-V compound semiconductors, or materials such as germanium. The doping type of the semiconductor substrate 1 may be N-type doping or P-type doping.

[0137] First polar structure: In the back-contact solar cell of this application embodiment, "a plurality of" in "a plurality of first polarity structures" indicates that the number of first polarity structures contained in the back-contact solar cell is one or more, generally multiple.

[0138] In one embodiment of the back-contact solar cell of this application, the first polarity structure may be a tunnel oxide passivated contact (TOPCon) structure. Setting the first polarity structure as a TOPCon structure can comprehensively improve the photoelectric conversion efficiency of the back-contact solar cell of this application from the dimensions of voltage (through excellent passivation), current (through low recombination), and fill factor (through low resistance).

[0139] like Figure 1 As shown, in the first polar structure 2 of this embodiment, the first polar structure 2 includes a first functional layer and a first electrode structure. The first functional layer is disposed between the semiconductor substrate 1 and the first electrode structure. The first functional layer includes a first passivation layer 21 and a first doped semiconductor layer 22, and the first passivation layer 21 is disposed between the first doped semiconductor layer 22 and the semiconductor substrate 1, that is, in... Figure 1 Along the y-axis, a semiconductor substrate 1, a first passivation layer 21, and a first doped semiconductor layer 22 are sequentially stacked. In at least a portion of the first polar structure 2, the first doped semiconductor layer 22 includes a first sub-region 221, a second sub-region 222, and a contact region 223. At least one first sub-region 221 contacts an adjacent second polar structure 3, and the second sub-region 222 is located between the first sub-region 221 and the contact region 223. The surface of the first sub-region 221 away from the semiconductor substrate 1 has a first pit microstructure 224, and the surface of the second sub-region 222 away from the semiconductor substrate 1 has a second pit microstructure 225. The depth of the first pit microstructure 224 is greater than the depth of the second pit microstructure 225.

[0140] In the back-contact solar cell of this application embodiment, based on the above-described connection relationship between the first sub-region 221 and the second sub-region 222 and the contact region 223 in the first doped semiconductor layer 22, the first sub-region 221 and the second sub-region 222 are located at the ends of the first doped semiconductor layer 22, and the contact region 223 is located at the middle position of the opposite ends, and the first sub-region 221, the second sub-region 222, and the contact region 223 are arranged sequentially from the first sub-region 221 to the contact region 223. The first pit microstructure 224 and the second pit microstructure 225 refer to pits with a depth and pit diameter in the nanometer range distributed on the surface of the first sub-region 221 and the second sub-region 222 away from the semiconductor substrate 1, respectively. The depth of the first pit microstructure 224 refers to the straight-line distance from the opening of the first pit microstructure 224 to the bottom of the pit; similarly, the depth of the second pit microstructure 225 refers to the straight-line distance from the opening of the second pit microstructure 225 to the bottom of the pit.

[0141] In this way, by providing a first sub-region 221 and a second sub-region 222 in at least a portion of the first doped semiconductor layer 22 contained in the first polar structure 2, and by making the depth of the first pit microstructure 224 provided on the surface of the first sub-region 221 greater than the depth of the second pit microstructure 225 provided on the surface of the second sub-region 222, compared with the existing back contact solar cells with tunneling oxide passivation contact structures, at least the following effects are achieved: (1) The second pit microstructure 225 contained in the second sub-region 222 at the end of the first doped semiconductor layer 22 is relatively shallow, which can significantly improve the thickness uniformity of the first doped semiconductor layer 22 together with the contact region 223, and improve the overall surface quality of the semiconductor substrate 1 away from it. This enhances the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, significantly improves the structural integrity of the first passivation layer 21, enhances the passivation quality of the first passivation layer 21, improves its carrier tunneling ability and selective collection function, and reduces the loss of carriers during transport.

[0142] (2) A relatively deep first pit microstructure 224 is provided at both ends of the first doped semiconductor layer 22. This increases the surface of the first sub-region 221 and the contact interface with the first electrode structure to form a strong "anchoring" structure (or ohmic contact). This significantly reduces the contact resistance of the conductive layer-semiconductor interface, ensuring that the charge carriers can be efficiently collected and discharged by the first electrode structure, thus reducing power loss at this point. A relatively shallow second pit microstructure 225 is provided at the end of the second sub-region 222 of the first doped semiconductor layer 22. This provides a moderate contact area and a relatively smooth transition in electrical characteristics. While reducing the series resistance between the first doped semiconductor layer 22 and the first electrode structure, it also reduces the defects of the first doped semiconductor layer 22 and improves the transport properties of the charge carriers.

[0143] Therefore, the first doped semiconductor layer 22 with a second sub-region contained in the first polar structure 2 of the back contact solar cell in the embodiments of this application can effectively enhance the passivation strength of the first passivation layer 21, and can significantly enhance the electrical performance of the back contact solar cell, such as conversion efficiency and fill factor.

[0144] Furthermore, the understanding of the above-mentioned "at least in a portion of the first polar structure 2, the first doped semiconductor layer 22 it contains includes oppositely disposed ends and a contact region 223 located between the two ends; the end includes a first sub-region 221 and a second sub-region 222, the first sub-region 221 in at least one end is in contact with an adjacent second polar structure 3, and the second sub-region 222 is disposed between the first sub-region 221 and the contact region 223" is the same as the explanation of the first back-contact solar cell in the above-mentioned embodiment. That is, in all the first polar structures 2, all the first doped semiconductor layers 22 contained in the first polar structure 2 may include the contact region 223 and the ends may contain the first sub-region 221 and the second sub-region 222. Of course, there may also be some or a small number of first polar structures 2 containing first doped semiconductor layers 22 that do not include the contact region 223 and the ends may not contain the second sub-region 222. In actual production, along the x-axis direction, the first doped semiconductor layer 22 contained in all the first polar structures 2 distributed in the middle region of the backlight surface 11 of the semiconductor substrate 1 generally includes the contact area 223 and the end containing the first sub-region 221 and the second sub-region 222; while the first doped semiconductor layer 22 contained in the outermost first polar structures 2 distributed in the two end regions of the backlight surface 11 of the semiconductor substrate 1 does not include the contact area 223 and the end does not contain the second sub-region 222, but the end may contain the first sub-region 221.

[0145] In some embodiments, such as Figure 1 In the end of the first doped semiconductor layer 22 shown, the depth ratio of the first pit microstructure 224 on the surface of the first sub-region 221 to the depth ratio of the second pit microstructure 225 on the surface of the second sub-region 222 is (1.5~1000):1. In the example, it can be a typical but non-limiting depth ratio such as 1.5:1, 10:1, 50:1, 100:1, 300:1, 500:1, 800:1, 1000:1, or any range between two depth ratios. The first pit microstructure 224 and the second pit microstructure 225 within this depth ratio range can simultaneously improve the layer structure integrity of the first passivation layer 21 and enhance the passivation strength of the first passivation layer 21; and improve the interface performance between the first doped semiconductor layer 22 and the first electrode structure.

[0146] In some embodiments, such as Figure 1 At the end of the first doped semiconductor layer 22 shown, as Figure 2 As shown, the depth h1 of a single first pit microstructure 224 in the first sub-region 221 can be 1 nm to 100 nm, and optionally 10 nm to 60 nm. In the example, it can be a typical but non-limiting depth such as 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, or any range between two depth values.

[0147] In some embodiments, such as Figure 1 In the end of the first doped semiconductor layer 22 shown, the width of the opening of the first pit microstructure 224 in the first sub-region 221 can be 1 nm to 200 nm, optionally 20 nm to 120 nm. In the example, it can be a typical but non-limiting width such as 1 nm, 20 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, or any range between two widths.

[0148] In some embodiments, such as Figure 1 At the end of the first doped semiconductor layer 22 shown, as Figure 2 As shown, the depth h2 of a single second pit microstructure 225 in the second sub-region 222 can be 0.1 nm to 40 nm, and optionally 1 nm to 30 nm. In the example, it can be a typical but non-limiting depth such as 0.1 nm, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, or any range between two depth values.

[0149] In some embodiments, such as Figure 1 In the end of the first doped semiconductor layer 22 shown, the width of the opening of the second pit microstructure 225 in the second sub-region 222 can be 0.1 nm to 80 nm, optionally 1 nm to 40 nm. In the example, it can be a typical but non-limiting width such as 0.1 nm, 1 nm, 5 nm, 10 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, or any range between two width values.

[0150] The first pit microstructure 224 and the second pit microstructure 225, which have the above-mentioned depth and width range, can further improve the layer structure integrity of the first passivation layer 21 and protect the passivation effect of the first passivation layer 21 on the semiconductor substrate; at the same time, they can improve the contact interface performance between the first doped semiconductor layer 22 and the first electrode structure.

[0151] The width of the opening of the first pit microstructure 224 and the second pit microstructure 225 refers to the straight-line distance from one side of the opening to the opposite side.

[0152] In some embodiments, such as Figure 2As shown, the minimum distance w1 between the first pit microstructure 224 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, and the minimum distance w2 between the second pit microstructure 225 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, are both greater than w1. By controlling the film thickness of the second sub-region 222 (as shown by w2) to be greater than the film thickness of the first sub-region 221 (as shown by w1), the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21 can be improved, the layer structure integrity of the first passivation layer 21 can be improved, and the passivation strength of the first passivation layer 21 can be enhanced.

[0153] In some embodiments, such as Figure 2 As shown, the minimum distance w1 between the first pit microstructure 224 contained on the surface of the first sub-region 221 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1 can be 29 nm to 220 nm, optionally 50 nm to 130 nm. In the example, it can be a typical but non-limiting distance such as 20 nm, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 220 nm, or any range between two distance values.

[0154] In the embodiments, such as Figure 2 As shown, the minimum distance w2 between the second pit microstructure 225 contained on the surface of the second sub-region 222 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1 can be 49 nm to 240 nm, optionally 70 nm to 150 nm. In the example, it can be a typical but non-limiting distance such as 49 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 240 nm, or any range between two distance values.

[0155] The first sub-region 221 and the second sub-region 222, having the film layer ranges shown in w1 and w2 above, can work together with the contact region 223 to improve the structural integrity of the first passivation layer 21, enhance the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, and strengthen the passivation strength of the first passivation layer 21; at the same time, they can improve the quality of the contact interface between the first doped semiconductor layer 22 and the first electrode structure, and strengthen the passivation strength of the first passivation layer 21.

[0156] In the embodiments, in such Figure 1At the end of the first doped semiconductor layer 22 shown, at least one of the first pit microstructure 224 in the first sub-region 221 and the second pit microstructure 225 in the second sub-region 222 can be formed by etching. Therefore, the depth, opening width, and morphology of each pit microstructure 224 and the second pit microstructure 225 may not be exactly the same.

[0157] In addition, in such Figure 1 Other features of the first sub-region 221 and the second sub-region 222 at the end of the first doped semiconductor layer 22 shown, such as the length ratio or other features between the first sub-region 221 and the second sub-region 222 along the X-axis, may be the same as those of the first sub-region 221 and the second sub-region 222 in the first type of back contact solar cell described above.

[0158] In some embodiments, such as Figure 1 In the first doped semiconductor layer 22 shown, the surface of its contact region 223 away from the semiconductor substrate 1 has a third pit microstructure 226 and / or a protrusion microstructure 227. The provision of the third pit microstructure 226 and / or the protrusion microstructure 227 can increase the roughness of the surface of the contact region 223 away from the semiconductor substrate 1, thereby enhancing the ohmic contact characteristics between the first doped semiconductor layer 22 and the first electrode structure.

[0159] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a third pit microstructure 226, the third pit microstructure 226 may have the same characteristics as the third pit microstructure 226 contained in the first type of back contact solar cell described above. In an embodiment, the depth of the third pit microstructure 226 may be 0.1 nm to 60 nm. In an embodiment, the width of the opening of the third pit microstructure 226 may be 0.1 nm to 120 nm. In an embodiment, the minimum distance w3 between the third pit microstructure 226 contained on the surface of the contact region 223 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, and w3 > w1 as described above.

[0160] In the embodiments, in such Figure 1 In the first doped semiconductor layer 22 shown, when the surface of its contact region 223 contains a raised microstructure 227, the raised microstructure 227 may have the characteristics of the raised microstructure 227 contained in the first type of back-contact solar cell described above. As in the embodiment, the raised microstructure 227 has the following characteristics: Figure 2 The height h3 shown is 1 nm to 100 nm. As in the embodiment, such as... Figure 2The width 'a' of the root of the raised microstructure 227 shown is 1 nm to 100 nm. In the embodiments, the morphology of the raised microstructure 227 includes at least one of granular structure, blocky structure, hill-like structure, and irregular protrusions. In the embodiments, when the surface of its contact area 223 contains the raised microstructure 227, the raised microstructure 227 can also be a raised microstructure 227 formed during the patterning process of the second functional layer by laser ablation.

[0161] In some embodiments, such as Figure 1 In the first doped semiconductor layer 22 shown, when the contact region 223 on the surface away from the semiconductor substrate 1 is provided with a third pit microstructure 226 and / or a protrusion microstructure 227, the roughness R of the surface of the contact region 223 away from the semiconductor substrate 1 is... z3 And the R z3 The surface roughness R of the second sub-region 222 is greater than that of the semiconductor substrate 1. z2 That is, R z3 >R z2 In this embodiment, the contact area 223 is located away from the surface roughness R of the semiconductor substrate 1. z3 The roughness can range from 2 nm to 160 nm. In the example, it can be a typical but non-limiting roughness such as 2 nm, 5 nm, 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, 130 nm, or 160 nm, or any range between two roughness values. The surface roughness of the contact region 223 away from the semiconductor substrate 1 is controlled to be greater than the surface roughness of the second sub-region 222, and its surface roughness R is further controlled to be greater than that of the second sub-region 222. z3 Controlling the above range can, on the one hand, improve the surface quality of the first doped semiconductor layer 22, enhance the structural integrity of the first passivation layer 21, and improve the passivation strength and other properties of the first passivation layer 21; on the other hand, it can improve its ohmic contact characteristics with the first electrode structure. The definitions of the third pit microstructure 226 and the protrusion microstructure 227 in the back-contact solar cell of this application embodiment are the same as those in the back-contact solar cell of the above-mentioned application embodiment.

[0162] In some embodiments, such as Figure 1 In the first doped semiconductor layer 22, such as Figure 2 As shown, when the surface of the contact area 223 is provided with a third pit microstructure 226, the minimum distance w3 between the third pit microstructure 226 contained on the surface of the contact area 223 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, combined with the minimum distance w1 between the surface of the first sub-region 221 away from the semiconductor substrate 1 provided with a first pit microstructure 224 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, then w3 > w1.

[0163] In the embodiments, in such Figure 1 At the end of the first doped semiconductor layer 22, such as Figure 2 As shown, the minimum distance w3 between the third pit microstructure 226 contained on the surface of the contact area 223 away from the semiconductor substrate 1 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1 can be 48 nm to 290 nm. It can be a typical but non-limiting distance such as 48 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 260 nm, 290 nm, or any range between two distance values.

[0164] By controlling the film thickness of the contact region 223 shown in w3 to be greater than the film thickness of the first sub-region 221 shown in w1 above, or by further controlling the film thickness of the contact region 223 shown in w3 within the above range, it is possible to improve the protective effect of the first doped semiconductor layer 22 on the first passivation layer 21, improve the layer structure integrity of the first passivation layer 21, and enhance the passivation strength of the first passivation layer 21.

[0165] First polar structure: In some embodiments, the second polarity structure in the back-contact solar cell of this application can be the same as the second polarity structure in the back-contact solar cell of this application described in the first aspect above. To save space, the second polarity structure in the back-contact solar cell of this application will not be described again here.

[0166] [Preparation method of back contact solar cells] Thirdly, embodiments of this application provide a method for fabricating the back-contact solar cell described in the above embodiments. In some embodiments, such as... Figure 3 As shown, the method for fabricating a back-contact solar cell according to an embodiment of this application includes the following steps: S10: Provide a semiconductor substrate, divide the backlight surface of the semiconductor substrate into several first polarity regions and several second polarity regions, and alternately arrange the first polarity regions and the second polarity regions along the direction parallel to the backlight surface; S20: A patterned first functional film is prepared on the backlight surface of a semiconductor substrate, such that the first functional film covers a first polar region in the backlight surface; wherein, the first functional film is a functional film with a tunnel oxide passivation contact structure; the first functional film includes a first passivation film and a first doped semiconductor film, and the first passivation film is disposed between the first doped semiconductor film and the semiconductor substrate. S30: A protective film is prepared on at least a portion of the surface of the first doped semiconductor film away from the semiconductor substrate, and the protective film covers the first doped semiconductor film but exposes the two end regions of the first doped semiconductor film near the second polar region; S40: The semiconductor substrate with the protective film is cleaned and the protective film is removed; S50: A second functional film is prepared at least in the second polar region of the back surface of the semiconductor substrate.

[0167] In the fabrication method of the back-contact solar cell in this application embodiment, the protective film prepared in step S30 should be understood to have the function of resisting the etching caused by the cleaning process in step S40. That is, the protective film can maintain the stability of the film structure or large-area stability during the cleaning process in step S40, so as to protect the first doped semiconductor film covered by it in the first polarity region. Preparing the protective film at least on a portion of the surface of the first doped semiconductor film away from the semiconductor substrate means that the protective film can be formed on a portion of the first doped semiconductor films contained in all the patterned first functional films, or it can be formed on all the first doped semiconductor films contained in the first functional films. In actual production, it is generally chosen to form the protective film on all the first doped semiconductor films contained in the first functional films.

[0168] Thus, the fabrication method of the back contact solar cell in this embodiment first forms a protective film on the surface of the first doped semiconductor film contained in the patterned at least partially tunneling oxide passivation contact structure, and covers the surface area of ​​the first doped semiconductor film within the first polarity region except for the area near the two ends of the second polarity region with the protective film. During the cleaning process of the semiconductor substrate with the protective film, the protective film can effectively protect the first functional film within the first polarity region, especially the first doped semiconductor film, specifically the area between the two ends of the first doped semiconductor film surface near the second polarity region. This alleviates the thinning of the first doped semiconductor film or the formation of deep corrosion pits caused by etching in this area of ​​the first doped semiconductor film during the cleaning process in step S40, thus preventing the first doped semiconductor film from becoming thinner or forming deep corrosion pits. The thickness of the protected area in the conductor film is greater than the thickness of the unprotected areas at both ends of the first doped semiconductor film, and the surface is smoother. This results in the thickness of the area between the two ends of the first doped semiconductor film after cleaning in step S40 being greater than the thickness of the area between the two ends of the first doped semiconductor film, and the resulting pits are also relatively shallow. This can significantly improve the thickness uniformity of the area between the two ends of the first doped semiconductor film, and can significantly reduce the adverse phenomena such as over-etching (e.g., being etched through) or being too thin in the first doped semiconductor film, thereby reducing the passivation performance of the first passivation film. This can effectively protect the passivation performance of the first passivation film in the first functional film of the tunnel oxide passivation contact structure and improve its passivation performance. Furthermore, it increases the process window of the fabrication method of the back contact solar cell in this application embodiment and improves the efficiency of the fabrication method.

[0169] Furthermore, since the regions at both ends of the first doped semiconductor film containing the protective film layer that contact the adjacent second polar region are not covered by the protective film, during the cleaning process in step S40, the regions at both ends of the first doped semiconductor film in the first polar region that contact the adjacent second polar region will have varying degrees of etching damage. This can increase the surface roughness at the contact edge between the first doped semiconductor film in the first polar region and the adjacent second polar region, thereby enhancing the quality of the contact interface between the first doped semiconductor film and the subsequently formed first electrode structure, such as increasing the effective contact area between the two layers.

[0170] Step S10: The semiconductor substrate provided in step S10 may have polished surfaces arranged opposite each other, one of which serves as the backlight surface. Furthermore, the material of this semiconductor substrate is the same as that of the semiconductor substrate 1 in the back-contact solar cell described above.

[0171] In some embodiments, the structure of the semiconductor substrate provided in step S10 can be as follows: Figure 4 As shown, a polished surface of the semiconductor substrate is selected as the backlight surface 11, and the backlight surface 11 is divided into several first polar regions R1 and several second polar regions R2. At this time, the other surface opposite to the backlight surface 11 can serve as the light-receiving surface. By setting the backlight surface 11 as a polished surface, when a first functional film is formed in the first polar region R1 contained in the smooth backlight surface 11 in step S20, the interface defects between the first passivation film and the semiconductor substrate 1 in the first functional film can be reduced, the passivation effect of the first passivation film can be improved, and thus the recombination probability of charge carriers at the interface between the first passivation layer and the semiconductor substrate 1 can be reduced. The light-receiving surface 12 has a textured structure, which can reduce the emissivity of sunlight occurring on the light-receiving surface 12, thereby improving the absorption rate of the back-contact solar cell.

[0172] Step S20: The structure of the patterned first functional film fabricated on the back surface 11 of the semiconductor substrate 1 is as follows: Figure 5 As shown, the first functional film covers the first polar region R1 in the backlight surface 11 of the semiconductor substrate 1, which includes a first passivation film 21' and a first doped semiconductor film 22'. The first passivation film 21' covers the first polar region R1 in the backlight surface 11 of the semiconductor substrate 1 and is disposed between the first doped semiconductor film 22' and the semiconductor substrate 1.

[0173] In some embodiments, a method for fabricating a patterned first functional film on the back surface 11 of a semiconductor substrate 1 may include the following steps: S21: A first passivation film 21', a first doped semiconductor film 22', and a pattern mask are successively fabricated on the entire backlight surface 11 of the semiconductor substrate 1; S22: The first passivation film 21' and the first doped semiconductor film 22' in step S21 are patterned to remove the first passivation film 21' and the first doped semiconductor film 22' located in the second polar region R2 of the backlight surface 11, so that the backlight surface 11 located in the second polar region R2 is exposed; at the same time, the first passivation film 21' and the first doped semiconductor film 22' located in the first polar region R1 of the backlight surface 11 are retained.

[0174] After the patterning process in step S22, a first functional layer is formed by a first passivation film 21' and a first doped semiconductor film 22' located within the first polarity region R1. Since the first polarity region R1 and the second polarity region R2 are alternately arranged on the backlight surface 11 of the semiconductor substrate 1, the first functional film patterned in step S10 is spaced apart across the entire backlight surface 11 of the semiconductor substrate 1. The spaced arrangement of the first functional layer on the backlight surface 11 of the semiconductor substrate 1 after the patterning process in step S22 is as follows: Figure 5 As shown.

[0175] In this embodiment, the patterning process in step S22 can be achieved using a chemical etching process with a chemical etching solution. The chemical etching process effectively removes the first functional film containing the first passivation film 21' and the first doped semiconductor film 22' within the second polar region R2, exposing the backlight surface within the second polar region R2. Simultaneously, the surface of the second polar region R2 in the backlight surface 11 of the semiconductor substrate 1 is also generally etched, forming a textured structure, such as... Figure 5 As shown.

[0176] In this embodiment, when the patterning process in step S22 can be achieved using a chemical etching solution, since the light-receiving surface 12 of the semiconductor substrate 1 can also directly contact the chemical etching solution, the light-receiving surface 12 of the semiconductor substrate 1 will be etched during the patterning process in step S22, thereby forming a pattern as shown in the image. Figure 5 The velvet structure shown.

[0177] Since the back-contact solar cell prepared is the back-contact solar cell of the above-described embodiment, the first functional film prepared in step S20 is a functional film of the tunnel oxide passivation contact structure. The first passivation film 21' contained in the first functional film prepared in step S20 is cleaned in step S40 to form the first passivation layer 21 contained in the first polar structure 2 of the back-contact solar cell of the above-described embodiment. Therefore, the material and thickness of the first passivation film 21' contained in the first functional film are the same as the material and thickness of the first passivation layer 21 contained in the first polar structure 2 of the back-contact solar cell of the above-described embodiment. The first doped semiconductor film 22' contained in the first functional film is cleaned in step S40 to form the first doped semiconductor layer 22 contained in the first polar structure 2 of the back-contact solar cell of the above-described embodiment. Therefore, the material of the first doped semiconductor film 22' contained in the first functional film is the same as the material of the first doped semiconductor layer 22 contained in the first polar structure 2 of the back-contact solar cell of the above-described embodiment.

[0178] Step S30: The structure for preparing a protective film on the surface of the first doped semiconductor film away from the semiconductor substrate is as follows: Figure 6 As shown, the protective film 25 covers the region between the two ends of the surface of the first doped semiconductor film 22' away from the semiconductor substrate 1, thus providing protection to that region. Meanwhile, as... Figure 6 As shown, the protective film 25 is not covered at both ends of the second polar region R2 in the backlight surface 11 of the first doped semiconductor film 22'.

[0179] In some embodiments, the method for preparing the protective film may include at least one of laser processing, forming a patterned mask from a mask material, etc.

[0180] In this embodiment, when the protective film 25 is prepared using a laser processing method, the method for preparing the protective film 25 is as follows: a pulsed laser is used to sweep across the area of ​​the backlight surface 11 of the first doped semiconductor film away from the semiconductor substrate 1, excluding the two end regions. Instantaneous high temperature forms a silicon oxide layer on this surface region of the first doped semiconductor film, covering the first doped semiconductor film 22' located within the first polar region R1. This silicon oxide layer has the ability to resist alkaline corrosion and can protect this area on the surface of the first doped semiconductor film 22' during the cleaning process in step S40, preventing severe etching damage to this area. The wavelength of the pulsed laser can be 355 nm, 325 nm, or 532 nm, etc., and the pulse width of the pulsed laser is 10 ps to 10 ns.

[0181] In this embodiment, when the protective film 25 is prepared using a patterned mask, the method for preparing the protective film 25 using a patterned mask is as follows: a mask is prepared on the surface of the first doped semiconductor film 22' away from the semiconductor substrate 1; a portion of the mask is removed using a protective or etchant ink or other material; the ink or other material is removed using a wet process, leaving only the mask covering the surface area except for the two end regions, to cover the area between the two ends of the surface of the first doped semiconductor film 22' located within the first polar region R1. This mask has the ability to resist alkaline corrosion and can protect this area of ​​the surface of the first doped semiconductor film 22' during cleaning, preventing severe etching damage to this area of ​​the surface of the first doped semiconductor film 22'. The material of the mask may include silicon nitride, silicon oxide, silicon oxynitride, etc.

[0182] These methods can all achieve, for example Figure 5 A protective film 25 is formed in the region between the two ends of the surface of the first doped semiconductor film 22' away from the semiconductor substrate, so as to protect the region.

[0183] In some embodiments, the thickness of the protective film 25 can be 0.5 nm to 50 nm, optionally 1 nm to 10 nm. In exemplary examples, it can be a typical but non-limiting thickness such as 0.5 nm, 2 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or any range between two thickness values. The protective film 25 with this thickness range can effectively protect the entire surface of the first doped semiconductor film 22' away from the semiconductor substrate.

[0184] In some embodiments, the material of the prepared protective film 25 may include silicon oxide, and of course, at least one of silicon nitride and silicon oxynitride. The protective film 25 formed by these materials maintains good stability during the cleaning process in the subsequent step S40, thereby improving the protective effect of the protective film 25 on the area between the two ends of the surface of the first doped semiconductor film 22' away from the semiconductor substrate 1.

[0185] Step S40: Currently, after fabricating the functional layer of the TOPCon structure, the semiconductor substrate containing the functional layer of the TOPCon structure is generally subjected to an etching and cleaning process, including alkaline etching, before other layer structures are fabricated. The existing cleaning process typically includes an alkaline etching process. That is, conventional cleaning processes include alkaline etching and acid washing. In the existing cleaning process, the alkaline etching is used to remove organic and particulate contaminants from the backlight surface, improving the surface cleanliness of the backlight surface and improving the passivation quality of the second passivation layer 31 on the semiconductor substrate 1 of the second polar region 2. This alkaline etching can also be an alkaline smoothing etching process to improve the surface morphology and performance of the second polar region 2 in the backlight surface 11 of the semiconductor substrate 1, or further improve the surface morphology and performance of the light-receiving surface 12.

[0186] Therefore, in step S40, the semiconductor substrate with the protective film is cleaned. Since in step 30 of the back-contact solar cell fabrication method in this embodiment, a protective film 25 covers the region between the two ends of the first doped semiconductor film 22'. Specifically, during the alkaline etching process in step S40, the region between the two ends of the first doped semiconductor film 22' is protected by the protective film 25. This results in a significantly lower degree of etching in this region compared to the ends of the first doped semiconductor film 22' without the protective film 25. Consequently, fewer and / or shallower pits are formed in the region protected by the protective film 25, and the pits are thicker than those at the ends without the protective film 25. Figure 7 As shown, this improves the flatness of the surface of the contact area away from the semiconductor substrate 1, making the contact area 223 and the second sub-region 222 of the first doped semiconductor layer 22 formed after cleaning relatively thicker than the doped semiconductor layer contained in the conventional TOPCon structure, and significantly improving the thickness uniformity. The depth of the second pit microstructure 225 and the third pit microstructure 226 formed by etching is also significantly reduced, thereby effectively protecting the first passivation layer 21 and improving the protection of the first passivation film 21', and increasing the passivation strength of the first passivation film 21'. Therefore, after the cleaning process in step S40, the region between the two ends of the first doped semiconductor film 22' forms as shown in the figure. Figure 7 The contact region 223 of the first doped semiconductor film 22' and the second sub-regions 222 at both ends, that is, as shown in Figure 1 The contact region 223 and the second sub-regions 222 at both ends of the first doped semiconductor layer 22 in the first polar structure 2 of the back contact solar cell shown in the above embodiment can protect the first passivation layer 21 and improve its passivation performance. Thus, Figure 7The surface roughness of the contact area 223 and the second sub-region 222 at both ends of the first doped semiconductor film 22' will be significantly lower than the surface roughness of the first sub-region 221 of the first doped semiconductor film 22' that is etched.

[0187] Meanwhile, since the protective film 25 is not covered near the second polar region R2 of the first doped semiconductor film 22' in step S30, during the cleaning process in step S40, specifically the alkaline etching process, the surface of the end region of the first doped semiconductor film 22' that contacts the second polar region R2 will be etched, thereby forming relatively deep pits and creating... Figure 7 The first sub-region 221 is located at the end of the first doped semiconductor film 22' that contacts the second polar region R2. At this time, the first sub-region 221 constitutes the first sub-region 221 at the end of the first doped semiconductor layer 22 contained in the first polar structure 2 of the back contact solar cell in the above-described embodiment.

[0188] Furthermore, in step S40, the cleaning process of the semiconductor substrate with the protective film is specifically an acid pickling process. This effectively removes impurities and other residues from the semiconductor substrate 1 that were generated in the previous process, improving the cleanliness of the backlight surface 11, including the second polar region R2. Moreover, this acid pickling process also removes the protective film 25 covering the surface of the first doped semiconductor film 22', such as... Figure 7 As shown.

[0189] Step S50: In some embodiments, combined with Figure 8 and Figure 9 The method for preparing the second functional film in the second polar region R2 of the backlight surface 11 of the semiconductor substrate 1 in step S50 includes the following steps: S51: A continuous second functional film is prepared on the surface of the second polar region R2 and the first doped semiconductor film 22' formed after cleaning, away from the semiconductor substrate 1; S52: The second functional film located in the first polar region R1 is patterned so that at least a portion of the surface of the first doped semiconductor film 22' in the first polar region R1 is exposed.

[0190] In step S51, the structure after the second functional film is formed on the surface of the second polar region R2 and the first doped semiconductor layer 22' away from the semiconductor substrate 1 and before it is patterned is as follows: Figure 8 As shown, a second functional film including a second passivation film 31' and a second doped semiconductor film 32' is sequentially formed on the outer surface of the first functional film formed after cleaning in the second polar region R2 and step S40. The second passivation film 31' is disposed between the second doped semiconductor film 32' and the semiconductor substrate 1.

[0191] Since the back-contact solar cell prepared is the back-contact solar cell of the above-described embodiment, the second functional film prepared in step S50 is the functional layer of the second polarity structure 3 contained in the back-contact solar cell of the above-described embodiment. The corresponding second passivation film 31', after patterning in step S52, forms the second passivation layer 31 contained in the second polarity structure 3 of the back-contact solar cell of the above-described embodiment. Therefore, the material and thickness of the second passivation film 31' are the same as those of the second passivation layer 31 contained in the second polarity structure 3 of the back-contact solar cell of the above-described embodiment. The second doped semiconductor film 32', after patterning in step S52, forms the second doped semiconductor layer 32 contained in the second polarity structure 3 of the back-contact solar cell of the above-described embodiment; the material used to form the second doped semiconductor film 32' is the same as that of the second doped semiconductor layer 32 contained in the second polarity structure 3 of the back-contact solar cell of the above-described embodiment. That is, the second functional film prepared in step S52 is as follows... Figure 1 The second functional layer contained in the second polar structure 3 of the back contact solar cell shown in the above application embodiment includes a second passivation layer 31 and a second doped semiconductor layer 32.

[0192] Thus, during the patterning process in step S52, the second functional film within the first polar region R1 is removed, exposing at least a portion of the surface of the first doped semiconductor film 22' within the first functional film of the first polar region R1. Because the patterning process of the second functional film within the first polar region R1 often results in a certain degree of pits and / or protrusions on the surface of the first doped semiconductor film 22' within the first polar region R1, formed by the resolidification of the melted second functional film, creating a... Figure 9 The structure is shown. At this time, the first doped semiconductor film 22' forms the first doped semiconductor layer 22 contained in the first polar structure 2 of the back contact solar cell in the above-described embodiment.

[0193] In some embodiments, the pattern processing method in step S52 may be wet etching and / or laser etching. In the embodiments, when laser etching is used, further processing may be performed... Figure 9 The contact area 223 of the first doped semiconductor layer 22 shown is away from the surface of the semiconductor substrate 1 and forms a third pit microstructure 226 and / or a protrusion microstructure 227.

[0194] In this embodiment, the etching process of the second functional film within the first polar region R1 in step S52 is a partial etching, exposing a portion of the surface of the first doped semiconductor film 22' within the first polar region R1. At this time, the second functional film formed in step S50 extends to the surface of the first functional film within the first polar region R1, and the two functional films form an overlapping region (including the overlapping region of the contact region 223 of the first doped semiconductor layer 22 and the second sub-region 222), such as... Figure 9 As shown.

[0195] Following step S52, step S60 is further included: forming a first functional film on the surface away from the semiconductor substrate 1, such as... Figure 1 The first electrode structure shown has a second functional film formed on the surface away from the semiconductor substrate 1, as shown. Figure 1 The second electrode structure shown is thus obtained as follows. Figure 1 The back-contact solar cell shown. The first electrode structure and the second electrode structure prepared in step S60 are insulated from each other, as shown by... Figure 1 The isolation slot 4 in the middle achieves insulation.

[0196] In some embodiments, such as Figure 4 As shown, after step S20 and before step S30, the method for fabricating a back-contact solar cell in this embodiment further includes the step of sequentially fabricating a third passivation layer 5 and an antireflection layer 6 on the light-receiving surface 12 of the semiconductor substrate. Of course, depending on adjustments to the fabrication process of the back-contact solar cell, the step of fabricating the third passivation layer 5 and the antireflection layer 6 can be performed after other steps.

[0197] The materials of the third passivation layer 5 and the antireflection layer 6 can be the same as those used in the back contact solar cell described in the previous application. The method for forming the third passivation layer 5 and the antireflection layer 6 can be prepared according to existing methods.

[0198] [Battery Components] Fourthly, embodiments of this application also provide a battery module. The battery module includes a back-contact solar cell as described in the above-described embodiments, or includes a back-contact solar cell derived from the back-contact solar cell described in the above-described embodiments. Therefore, the battery module of this application embodiment has higher peak power and module efficiency, and higher actual power generation.

[0199] [Example] The following describes embodiments of this application. The embodiments described below are exemplary and are only used to explain this application, and should not be construed as limiting this application. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Reagents or instruments used, unless otherwise specified, are all conventional products that can be obtained commercially.

[0200] Example 1: This embodiment provides a back-contact solar cell, the structure of which is as follows: Figure 1 As shown, it includes an N-type crystalline silicon semiconductor substrate 1, which has a backlight surface 11 and a light-receiving surface 12 with a textured surface; wherein, the backlight surface 11 is divided into alternating first polarity regions R1 and second polarity regions R2, and a first polarity structure 2 is provided on the backlight surface of the first polarity region R1, the first polarity structure 2 including a first polarity region R1 with alternating first polarity regions R1 and R2 with alternating first polarity regions R1 and R2. Figure 1 An ultrathin silicon oxide first passivation layer 21 and a phosphorus-doped n-type phosphorus oxide layer are sequentially stacked along the y-axis extension direction. + A first doped semiconductor layer 22 of polycrystalline silicon (the first passivation layer 21 and the first doped semiconductor layer 22 constitute a first functional layer), a first conductive layer 23 of transparent conductive oxide ITO, and a first silver electrode 24 (the first conductive layer 23 and the first electrode 24 constitute a first electrode structure); a second polar structure 3 is provided on the backlight surface of the second polar region R2, the second polar structure 3 including a first conductive layer 22 of polycrystalline silicon ITO, the ... Figure 1 An intrinsic amorphous silicon second passivation layer 31, a boron-doped p-type amorphous silicon second doped semiconductor layer 32 (the second passivation layer 31 and the second doped semiconductor layer 32 constitute a second functional layer), a transparent conductive oxide ITO second conductive layer 33, and a silver second electrode 34 (the second conductive layer 33 and the second electrode 34 constitute a second electrode structure) are sequentially stacked along the y-axis extension direction. The second functional layer extends to the space between the first doped semiconductor layer 22 and the first conductive layer 23 in the adjacent first polar structure 2, and covers the first sub-region 221 and the second sub-region 222 at the end of the first doped semiconductor layer 22, forming an overlapping region. The first sub-region 221 of the first doped semiconductor layer 22 has a first pit microstructure 224 on its surface away from the semiconductor substrate 1, with a surface roughness of R. z1 The minimum distance w1 between the first pit microstructure 224 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1; the second sub-region 222 has a second pit microstructure 225 on its surface away from the semiconductor substrate 1; and the surface roughness is R. z2 The minimum distance w2 between the second pit microstructure 225 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1, and the third pit microstructure 226 is provided on the surface of the contact area 223 away from the semiconductor substrate 1, with a surface roughness of R. z3 The minimum distance w3 between the third pit microstructure 226 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1. The light-receiving surface 12 has a textured structure, and a third passivation layer 5 and a reflective layer 6 are sequentially stacked along the direction away from the light-receiving surface 12.

[0201] The fabrication method of back contact solar cells includes the following steps: S1: Provide an N-type crystalline silicon semiconductor substrate 1 with polished surfaces on both sides; use one of the polished surfaces as a backlight surface 11, and divide the backlight surface 11 into a plurality of alternating first polarity regions R1 and second polarity regions R2; S2: Following existing methods, first fabricate the entire backlight surface 11 of the N-type crystalline silicon semiconductor substrate 1, and then... Figure 5 The ultrathin silicon oxide first passivation film 21' and phosphorus-doped n shown are shown. + A first doped semiconductor film 22' of polycrystalline silicon is formed to form a first functional film; then the first functional film is patterned according to existing methods to remove the first functional film covering the second polar region R2 in the backlight surface 11 of the N-type crystalline silicon semiconductor substrate 1, and retain the first functional film covering the first polar region R1 in the backlight surface 11 of the N-type crystalline silicon semiconductor substrate 1, so that the first functional films are spaced apart on the backlight surface 11 of the semiconductor substrate 1; at the same time, another polished surface of the N-type crystalline silicon semiconductor substrate 1 is etched to form a textured structure, which serves as the light-receiving surface 12; S3: Based on step S2, a third passivation layer 5 and a reflective layer 6 are sequentially prepared on the textured light-receiving surface 12 of the N-type crystalline silicon semiconductor substrate 1. S4: Based on step S3, the region between the two ends of the surface of the first doped semiconductor film 22' located away from the semiconductor substrate 1 within the first polar region R1 is laser-processed to form a silicon oxide layer with a thickness of 3 nm on its surface, which is then used as... Figure 6 The protective film 25 shown covers the area between the two ends of the surface of the first doped semiconductor film 22' away from the semiconductor substrate 1, that is, it does not cover the two end areas of the first doped semiconductor film 22' near the second polar region R2; wherein, the laser pulse width of the laser processing is 15ps and the laser power is 10W; S5: Based on step S4, the substrate containing the protective film 25 is subjected to a cleaning process including alkaline etching and acid cleaning. Alkaline etching is performed on the surface regions at both ends of the first doped semiconductor film 22' near the second polar region. The second polar region R2 in the backlight surface 11 of the semiconductor substrate 1 is cleaned, and the protective film 25 is removed, forming a substrate as shown in the image. Figure 7 The structure shown; S6: Based on step S5, as shown in the figure, are formed successively on the surfaces of the second polar region R2 and the first doped semiconductor film 22'. Figure 8 The intrinsic amorphous silicon second passivation layer film 31' and the boron-doped p-type amorphous silicon second doped semiconductor film 32' are shown. S7: Based on step S6, the intrinsic amorphous silicon second passivation layer film 31' and the boron-doped p-type amorphous silicon second doped semiconductor film 32' located in the contact region within the first polar region R1 are removed again using existing laser etching, and the phosphorus-doped n-type amorphous silicon second doped semiconductor film 32' located in the contact region within the first polar region R1 is removed. + The surface of the polycrystalline silicon first doped semiconductor film 22' is etched and exposed. At this time, the intrinsic amorphous silicon second passivation layer film 31' is formed, the intrinsic amorphous silicon second passivation layer 31 is formed, the boron-doped p-type amorphous silicon second doped semiconductor film 32' is formed, and the phosphorus-doped n-type amorphous silicon second doped semiconductor film 32' is formed. + The first doped semiconductor film 22' of polycrystalline silicon forms phosphorus-doped n + Polycrystalline silicon first doped semiconductor layer 22; S8: Based on step S7, in the second doped semiconductor film 32 and n of the p-type amorphous silicon... + After a continuous transparent conductive oxide ITO film is formed on the outer edge of the first doped semiconductor film 22 of polycrystalline silicon, the local transparent conductive oxide ITO film of the first polar region R1 and the second polar region R2 is etched away to form the first conductive layer 23 of the first polar structure 2 and the second conductive layer 33 of the second polar structure 3, respectively. S9: A silver metal first electrode 24 and a silver metal second electrode 34 are respectively prepared on the surfaces of the first conductive layer 23 and the second conductive layer 33 away from the semiconductor substrate 1.

[0202] Example 2: This embodiment provides a back-contact solar cell. Compared with the back-contact solar cell in Embodiment 1, the average depth and surface roughness R of the first pit microstructure 224 of the first sub-region 221 of the first doped semiconductor layer 22, which faces away from the surface of the semiconductor substrate 1, are different. z1 The minimum distance w1, the average depth of the second pit microstructure 225 of the second sub-region 222 facing away from the surface of the semiconductor substrate 1, and the surface roughness R z2 Minimum distance w2, average depth of the third pit microstructure 226 of the contact area 223 away from the surface of the semiconductor substrate 1, and surface roughness R z3 The minimum distance w3 is different from that in Example 1, but the rest are the same.

[0203] The back-contact solar cell fabrication method differs from that in Example 1 in that the thickness of the protective film in step S4 is different, specifically 6 nm. The laser pulse width for laser processing is 15 ps, and the laser power is 15 W. Example 3: This embodiment provides a back-contact solar cell. Compared with the back-contact solar cell in Embodiment 1, the average depth and surface roughness R of the first pit microstructure 224 of the first sub-region 221 of the first doped semiconductor layer 22, which faces away from the surface of the semiconductor substrate 1, are different. z1 The minimum distance w1, the average depth of the second pit microstructure 225 of the second sub-region 222 facing away from the surface of the semiconductor substrate 1, and the surface roughness R z2 Minimum distance w2, average depth of the third pit microstructure 226 of the contact area 223 away from the surface of the semiconductor substrate 1, and surface roughness R z3 The minimum distance w3 is different from that in Example 1, but the rest are the same.

[0204] The back-contact solar cell fabrication method differs from that in Example 1 in that the material of the protective film 25 in step S4 is replaced with silicon nitride.

[0205] Comparative Example 1: This comparative example provides a back-contact solar cell. Compared with the back-contact solar cell in Example 1, the average depth and surface roughness R of the first pit microstructure 224 of the first sub-region 221 of the first doped semiconductor layer 22 away from the surface of the semiconductor substrate 1 are different. z1 The minimum distance w1, the average depth of the second pit microstructure 225 of the second sub-region 222 facing away from the surface of the semiconductor substrate 1, and the surface roughness R z2 Minimum distance w2, average depth of the third pit microstructure 226 of the contact area 223 away from the surface of the semiconductor substrate 1, and surface roughness R z3 The minimum distance w3 is different from that in Example 1, but the rest are the same.

[0206] The back-contact solar cell fabrication method differs from the method in Example 1 in that steps S4 and S6 are omitted; that is, the ultrathin silicon oxide first passivation film 21' and the phosphorus-doped n-type solar cell are directly applied in step S2. + The first doped semiconductor film 22' of polycrystalline silicon is subjected to a cleaning process including alkaline treatment.

[0207] Parameter measurement and performance testing of back-contact solar cells: The back-contact solar cells in Examples 1 to 2 and Comparative Example 1 were measured according to the parameters and performance shown in Table 1 below. The detection methods for each parameter and performance are as follows, and the test results are shown in Table 1 below.

[0208] Surface roughness test method for the first doped semiconductor layer 22: SEM; Method for testing the average depth of pit microstructures on the surface of the first doped semiconductor layer 22: Using SEM, calculate the arithmetic mean of the sum of the depths of all first pit microstructures 224, second pit microstructures 225, and third pit microstructures 226 in the same unit area of ​​the surface of the first sub-region 221, second sub-region 222, and third sub-region 223 away from the semiconductor substrate 1 in each unit area, and use them as the average depths of the first pit microstructures 224, second pit microstructures 225, and third pit microstructures 226, respectively. Test method for minimum distances w1, w2, and w3 between the pit microstructure contained on the surface of the first doped semiconductor layer 22 and the surface of the first doped semiconductor layer 22 near the semiconductor substrate 1: SEM; Photovoltaic efficiency testing method for back-contact solar cells: IV electrical performance testing; Open-circuit voltage test method for back-contact solar cells: IV electrical performance test; Fill factor (FF) test method for back-contact solar cells: IV electrical performance test.

[0209] Table 1

[0210] In Examples 1 and 2, and Comparative Example 1, the scanning electron microscope (SEM) images of the cross-section perpendicular to the surface of the contact area between the two ends of the surface of the first doped semiconductor film 22' after the cleaning treatment including alkaline treatment in step S5 are shown in the following figures. Figure 10 , Figure 11 and Figure 12 As shown in the figure. In Example 1, the average depth of the corrosion pit microstructure is relatively shallow, with an average depth ≤40nm; in Example 2, the depth of the corrosion pit microstructure is further shallow, with an average depth ≤25nm; while in Comparative Example 1, the average depth of the corrosion pit microstructure reaches more than 48nm.

[0211] Furthermore, as shown in Table 1, within a certain range, the thickness of the protective film increases with the increase of laser processing power, correspondingly improving the surface quality of the first doped semiconductor film 22'. The photoelectric conversion efficiency of the back-contact solar cell initially increases and then plateaus. For example, the photoelectric conversion efficiency of the back-contact solar cell in Example 2 is relatively the highest, and it is 0.1% higher than that of the back-contact solar cell in Example 1. abs .

[0212] As can be seen from Table 1 and the SEM images, in Examples 1 to 3, before cleaning the first doped semiconductor film 22' used to form the first functional layer in the first polar structure, a protective film 25 was used for protection. After cleaning, the depth of the pit microstructure in the region between the two ends of the surface of the first doped semiconductor layer 22 away from the semiconductor substrate 1 was significantly shallower than in Comparative Example 1, the surface roughness was significantly smaller than in Comparative Example 1, and the film thickness uniformity was significantly improved compared to Comparative Example 1. In each of Examples 1 to 2, the first doped semiconductor layer 22 can be divided into three regions: a first sub-region 221, a second sub-region 222, and a contact region 223, and the surface roughness R of the second sub-region 222 is... z2 The surface roughness R of the contact area 223 z3 The surface roughness R of both is less than that of the first sub-region 221. z1 Furthermore, the depths of the second pit microstructure on the surface of the second sub-region 222 and the third pit microstructure on the surface of the contact region 223 are both less than the depth of the first pit microstructure on the surface of the first sub-region 221. However, in each embodiment, the surface roughness and pit microstructure depth of the corresponding areas of the second sub-region 222 and the contact region 223 of the first doped semiconductor layer 22 are significantly less than those of the corresponding areas of the second sub-region 222 and the contact region 223 of the first doped semiconductor layer 22 in Comparative Example 1.

[0213] Therefore, in the back contact solar cell of this application embodiment, the structure of the first doped semiconductor layer in the first polar structure of the tunneling oxide passivation contact structure is more complete, and the passivation strength of the first passivation layer is improved, which can significantly enhance the electrical performance of the back contact solar cell, such as conversion efficiency and fill factor.

[0214] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back-contact solar cell, characterized in that: It includes a semiconductor substrate, a plurality of first polar structures and a plurality of second polar structures; on the backlight surface of the semiconductor substrate, the first polar structures and the second polar structures are alternately arranged in a direction parallel to the backlight surface; The first polar structure includes a first functional layer, the first functional layer includes a first passivation layer and a first doped semiconductor layer, and the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate; In at least a portion of the first polar structure, the first doped semiconductor layer includes a first sub-region, a second sub-region, and a contact region. At least one of the first sub-regions is in contact with an adjacent second polar structure, and the second sub-region is disposed between the first sub-region and the contact region. The surface roughness of the first sub-region away from the semiconductor substrate is R. z1 The surface roughness of the second sub-region away from the semiconductor substrate is R. z2 And R z1 >R z2 .

2. The back-contact solar cell as described in claim 1, characterized in that: The R z1 The R z2 (1.5~1000): 1; And / or, the R z1 The range is from 1 nm to 100 nm; And / or, the R z2 The range is 0.1 nm to 40 nm.

3. The back-contact solar cell as described in claim 1 or 2, characterized in that: The surface of the first sub-region away from the semiconductor substrate has a first pit microstructure, and the surface of the second sub-region away from the semiconductor substrate has a second pit microstructure. The minimum distance w1 between the first pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate is the same as the minimum distance w2 between the second pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, wherein w2 > w1.

4. The back-contact solar cell as described in claim 3, characterized in that: The w1 is 29 nm to 220 nm; And / or, w2 is 49 nm to 240 nm.

5. The back-contact solar cell as described in claim 1 or 2, characterized in that: Along the direction from the first sub-region to the contact region in the first doped semiconductor layer, the length ratio of the first sub-region to the second sub-region is (0.03~15):

1.

6. The back-contact solar cell according to any one of claims 1, 2, and 4, characterized in that, The surface of the contact area away from the semiconductor substrate is provided with a third pit microstructure and / or a protrusion microstructure.

7. The back-contact solar cell as described in claim 6, characterized in that, The contact area satisfies at least one of the following (1) to (3): (1) The surface roughness of the contact area away from the semiconductor substrate is R. z3 And the R z3 >R z2 ; (2) The surface roughness of the contact area away from the semiconductor substrate is R. z3 And the R z3 The range is from 2 nm to 160 nm; (3) The surface of the contact area is provided with the third pit microstructure, and the minimum distance w3 between the third pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate is greater than w1.

8. The back-contact solar cell as described in claim 6, characterized in that, The third pit microstructure satisfies at least one of the following (1) to (2): (1) The depth of the third pit microstructure is 0.1 nm to 60 nm; (2) The width of the opening of the third pit microstructure is 0.1 nm to 120 nm.

9. The back-contact solar cell as described in claim 6, characterized in that, The protruding microstructure satisfies at least one of the following (1) to (2): (1) The height of the protruding microstructure is 1 nm to 100 nm; (2) The width of the root of the protruding microstructure is 1 nm to 100 nm.

10. The back-contact solar cell according to any one of claims 1, 2, 7 to 9, characterized in that: The second polar structure includes a second functional layer that extends into the adjacent first polar structure and covers the surfaces of the first sub-region and the second sub-region in the first doped semiconductor layer that are adjacent to the second polar structure and far from the semiconductor substrate.

11. The back-contact solar cell according to any one of claims 1, 2, 7 to 9, characterized in that: The semiconductor substrate further includes a passivation layer and an antireflection layer on the light-receiving side, and the passivation layer is disposed between the light-receiving surface and the antireflection layer; The light-receiving surface of the semiconductor substrate has a textured surface.

12. A back-contact solar cell, characterized in that: It includes a semiconductor substrate, a plurality of first polar structures and a plurality of second polar structures; on the backlight surface of the semiconductor substrate, the first polar structures and the second polar structures are alternately arranged in a direction parallel to the backlight surface; The first polar structure includes a first functional layer, the first functional layer includes a first passivation layer and a first doped semiconductor layer, and the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate; In at least a portion of the first polar structure, the first doped semiconductor layer includes a first sub-region, a second sub-region, and a contact region. The first sub-region at at least one of the ends is in contact with an adjacent second polar structure, and the second sub-region is disposed between the first sub-region and the contact region. The surface of the first sub-region away from the semiconductor substrate is provided with a first pit microstructure, and the surface of the second sub-region away from the semiconductor substrate is provided with a second pit microstructure. The depth of the first pit microstructure is greater than the depth of the second pit microstructure.

13. The back-contact solar cell as described in claim 12, characterized in that: The depth ratio of the first pit microstructure to the depth of the second pit microstructure is (1.5~1000):1; And / or, the depth of the first pit microstructure is 1 nm to 100 nm; And / or, the depth of the second pit microstructure is 0.1 nm to 40 nm.

14. The back-contact solar cell as described in claim 12 or 13, characterized in that: The minimum distance w1 between the first pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, and the minimum distance w2 between the second pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, wherein w2 > w1.

15. The back-contact solar cell as described in claim 14, characterized in that: The w1 is 29 nm to 220 nm; And / or, w2 is 49 nm to 240 nm.

16. The back-contact solar cell as described in claims 12, 13, and 15, characterized in that: The surface of the contact area away from the semiconductor substrate is provided with a third pit microstructure and / or a protrusion microstructure.

17. The back-contact solar cell as claimed in claim 16, characterized in that, The contact area satisfies at least one of the following (1) to (2): (1) The surface roughness of the contact area away from the semiconductor substrate is R. z3 The surface roughness of the second sub-region away from the semiconductor substrate is R. z2 And R z3 >R z2 ; (2) The surface roughness of the contact area away from the semiconductor substrate is R. z3 And the R z3 The range is from 2 nm to 160 nm.

18. The back-contact solar cell as claimed in claim 16, characterized in that, The third pit microstructure satisfies at least one of the following (1) to (2): (1) The depth of the third pit microstructure is 0.1 nm to 60 nm; (2) The width of the opening of the third pit microstructure is 0.1 nm to 120 nm.

19. The back-contact solar cell as claimed in claim 16, characterized in that, The protruding microstructure satisfies at least one of the following (1) to (2): (1) The height of the protruding microstructure is 1 nm to 100 nm; (2) The width of the root of the protruding microstructure is 1 nm to 100 nm.

20. The back-contact solar cell as claimed in claim 16, characterized in that: The minimum distance w1 between the first pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, the minimum distance w3 between the third pit microstructure and the surface of the first doped semiconductor layer near the semiconductor substrate, wherein w3 > w1.

21. The back-contact solar cell as claimed in claim 20, characterized in that: The w3 is 48 nm to 290 nm.

22. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: A semiconductor substrate is provided, and the back surface of the semiconductor substrate is divided into a plurality of first polar regions and a plurality of second polar regions, and the first polar regions and the second polar regions are alternately arranged along a direction parallel to the back surface; A patterned first functional film is fabricated on the back surface of the semiconductor substrate, such that the first functional film covers the first polar region in the back surface; wherein, the first functional film is a functional film with a tunneling oxide passivation contact structure; the first functional film includes a first passivation film and a first doped semiconductor film, and the first passivation film is disposed between the first doped semiconductor film and the semiconductor substrate. A protective film is formed on at least a portion of the surface of the first doped semiconductor film away from the semiconductor substrate, and the protective film covers the first doped semiconductor film but exposes the two end regions of the first doped semiconductor film near the second polarity region; The semiconductor substrate on which the protective film is prepared is cleaned, and the protective film is removed. A second functional film is prepared at least within the second polar region of the backlight surface.

23. The preparation method according to claim 22, characterized in that: The method for preparing the protective film includes at least one of laser processing and using a patterned mask; and / or The protective film satisfies at least one of the following (1) to (2): (1) The thickness of the protective film is 0.1 nm to 50 nm; (2) The material of the protective film includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

24. The preparation method according to claim 22 or 23, characterized in that, The method for preparing the second functional membrane includes the following steps: A continuous second functional film is prepared on the surface of the second polar region and the first doped semiconductor film after the cleaning treatment away from the semiconductor substrate; The second functional film located in the first polar region is patterned so that at least part of the surface of the first doped semiconductor film in the first polar region is exposed.

25. The preparation method according to claim 22 or 23, characterized in that: It also includes a step of texturing the light-receiving surface of the semiconductor substrate, so that the light-receiving surface is texturized.

26. The preparation method according to claim 25, characterized in that: It also includes the steps of first forming a passivation layer on the velvet surface, and then forming an antireflection layer on the surface of the passivation layer away from the velvet surface.

27. A battery assembly, characterized in that, It includes the back-contact solar cell according to any one of claims 1 to 11 or the back-contact solar cell according to any one of claims 12 to 21.

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