Instruction information management system and method, chip and electronic equipment

Abstract

The invention discloses an instruction information management system and method, a chip and electronic equipment, and belongs to the field of processors. The system comprises an acquisition component, a read-write component, a first storage space and a second storage space, the first storage space is used for storing instruction information of a plurality of thread bundles, and the second storage space is used for storing reference addresses of the plurality of thread bundles. The reference address of any one of the plurality of thread bundles is used for determining the position of the instruction information of the thread bundle in the first storage space; the acquisition component is used for acquiring a read-write instruction, and the read-write instruction is used for indicating to read and write instruction information of the first thread; the acquisition component is further used for reading first information from the second storage space according to the read-write instruction, and the first information is a reference address of a thread bundle to which the first thread belongs; and the read-write component is used for reading and writing instruction information of the first thread in the first storage space based on the first information. The first storage space is shared by the plurality of thread bundles, so that the utilization rate of the first storage space is improved.

Description

Technical Field

[0001] This application relates to the field of processors, and in particular to an instruction information management system, method, chip, and electronic device. Background Technology

[0002] A multithreaded processor is a processor that supports the concurrent execution of instructions by multiple threads, thereby improving instruction processing efficiency. A multithreaded processor consists of multiple thread bundles, each containing multiple threads, and the instruction information of each thread bundle can be managed by an instruction information management system.

[0003] In related technologies, the instruction information management system includes a read / write component and a storage space corresponding to each thread bundle. For any thread bundle, when it is necessary to read or write the instruction information of a certain thread within the thread bundle, the read / write component performs the read / write operation in the storage space corresponding to the thread bundle.

[0004] However, the processor has inactive thread bundles. The instruction information management system does not read or write instruction information to these thread bundles. Since each thread bundle corresponds to a storage space, there is idle storage space, which wastes storage resources. Summary of the Invention

[0005] This application provides an instruction information management system, method, chip, and electronic device, which can improve the utilization rate of storage space and save storage resources. The technical solution includes the following contents.

[0006] On the one hand, an instruction information management system is provided. The system includes an acquisition component, a read / write component, a first storage space, and a second storage space. The first storage space is used to store instruction information of multiple thread bundles, and the second storage space is used to store reference addresses of the multiple thread bundles. The reference address of any one of the multiple thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space.

[0007] The acquisition component is used to acquire read and write instructions, which are used to instruct the reading and writing of the first thread's instruction information.

[0008] The acquisition component is further configured to read first information from the second storage space according to the read / write instruction, wherein the first information is the reference address of the thread bundle to which the first thread belongs;

[0009] The read / write component is used to read and write the instruction information of the first thread in the first storage space based on the first information.

[0010] On the other hand, an instruction information management method is provided, the method being executed by an electronic device including a first storage space and a second storage space, wherein the first storage space is used to store instruction information of a plurality of thread bundles, and the second storage space is used to store reference addresses of the plurality of thread bundles, wherein the reference address of any one of the plurality of thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space, the method comprising:

[0011] Obtain read / write instructions, which are used to instruct the first thread to read or write instruction information;

[0012] According to the read / write instructions, first information is read from the second storage space, where the first information is the reference address of the thread bundle to which the first thread belongs;

[0013] Based on the first information, read and write the instruction information of the first thread in the first storage space.

[0014] On the other hand, an instruction information management device is provided, which is applied to an electronic device including a first storage space and a second storage space. The first storage space is used to store instruction information of a plurality of thread bundles, and the second storage space is used to store reference addresses of the plurality of thread bundles. The reference address of any one of the plurality of thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space. The device includes:

[0015] The acquisition module is used to acquire read and write instructions, which are used to instruct the reading and writing of the first thread.

[0016] The reading module is used to read first information from the second storage space according to the read / write instruction, wherein the first information is the reference address of the thread bundle to which the first thread belongs;

[0017] The read / write module is used to read and write the instruction information of the first thread in the first storage space based on the first information.

[0018] In one possible implementation, the read / write instruction carries identification information of the thread bundle to which the first thread belongs;

[0019] The acquisition module is used to read the first information from the second storage space according to the identification information.

[0020] In one possible implementation, the read / write instruction includes a write instruction, and the first storage space includes a plurality of first storage units;

[0021] The read / write module is used to determine an idle unit from the plurality of first storage units that does not store instruction information; write the instruction information of the first thread into the idle unit; and write the first information into the idle unit.

[0022] In one possible implementation, the first storage unit is further configured to store a validity identifier, which indicates whether the first storage unit stores instruction information.

[0023] The read / write module is used to determine a free unit from the plurality of first storage units based on the validity identifier stored in the plurality of first storage units.

[0024] In one possible implementation, the read / write instruction includes a read instruction, and the first storage space includes a plurality of first storage units;

[0025] The read / write module is used to determine an information unit from the plurality of first storage units based on the first information, wherein the information unit stores instruction information of the first thread; and to read the instruction information stored in the information unit.

[0026] In one possible implementation, the device further includes:

[0027] The determining module is used to determine the second information, which is the address storing the instruction information of the thread bundle to which the first thread belongs;

[0028] An update module is used to update the first information to the second information in the second storage space.

[0029] In one possible implementation, the read / write instruction includes a write instruction, the first storage space includes a plurality of first storage units, and the second information is the address of the first storage unit for writing instruction information of the first thread.

[0030] In one possible implementation, the read / write instruction includes a read instruction, and the first storage space includes a plurality of first storage units, the plurality of first storage units including an information unit storing instruction information of the first thread;

[0031] The determining module is configured to determine that the second information is the address of the relevant unit when the information unit still stores the address of the relevant unit, wherein the relevant unit is a first storage unit that stores instruction information of the thread bundle to which the first thread belongs; and to determine that the second information is blank when the information unit does not store the address of the relevant unit.

[0032] In one possible implementation, the second storage space includes a plurality of second storage units, each corresponding to one of the plurality of thread bundles, and the second storage unit is used to store the reference address of the corresponding thread bundle.

[0033] On the other hand, a chip is provided that includes the aforementioned instruction information management system.

[0034] On the other hand, an electronic device is provided, which includes the aforementioned chip.

[0035] On the other hand, a computer-readable storage medium is also provided, wherein at least one computer program is stored in the computer-readable storage medium, and the at least one computer program is loaded and executed by a processor to enable an electronic device to implement the above-described instruction information management method.

[0036] On the other hand, a computer program is also provided, wherein the computer program is at least one, and the at least one computer program is loaded and executed by a processor to enable the electronic device to implement the above-described instruction information management method.

[0037] On the other hand, a computer program product is also provided, which stores at least one computer program, which is loaded and executed by a processor to enable an electronic device to implement the above-described instruction information management method.

[0038] The technical solution provided in this application brings at least the following beneficial effects:

[0039] In the technical solution provided in this application, the first storage space is used to store the instruction information of each thread bundle, and the second storage space is used to store the reference address of each thread bundle. When the acquisition component obtains the read / write instruction of the first thread, it can read the reference address of the thread bundle to which the first thread belongs from the second storage space. Since this reference address indicates the location of the instruction information of the thread bundle to which the first thread belongs in the first storage space, the read / write component can read and write the instruction information of the first thread in the first storage space based on this reference address. This realizes the storage of the instruction information of each thread bundle through the first storage space, and the management of the instruction information of each thread bundle through the acquisition component, the read / write component, the first storage space, and the second storage space.

[0040] Furthermore, since multiple thread bundles share the first storage space, even if there are inactive thread bundles among them, the first storage space will still store the instruction information of the active thread bundles, thereby improving the utilization rate of the first storage space and reducing the waste of storage resources. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram illustrating the writing of instruction information according to an embodiment of this application;

[0044] Figure 3 This is a schematic diagram illustrating the reading of instruction information provided in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of an instruction information management system provided in an embodiment of this application;

[0046] Figure 5 This is a schematic diagram of a thread bundle and stack structure provided by related technologies;

[0047] Figure 6 This is a schematic diagram of a first storage unit provided in an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of another instruction information management system provided in an embodiment of this application;

[0049] Figure 8 This is a schematic diagram illustrating a method for writing instruction information according to an embodiment of this application;

[0050] Figure 9 This is a schematic diagram illustrating a method for reading instruction information provided in an embodiment of this application;

[0051] Figure 10 This is a schematic diagram of an instruction information management method provided in an embodiment of this application;

[0052] Figure 11 This is a framework diagram of an instruction information management system provided in an embodiment of this application;

[0053] Figure 12 This is a flowchart of another instruction information management method provided in the embodiments of this application;

[0054] Figure 13 This is a schematic diagram of the structure of an instruction information management device provided in an embodiment of this application;

[0055] Figure 14 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application;

[0056] Figure 15 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0059] First, the abbreviations and key terms involved in the embodiments of this application are defined.

[0060] A multiplexer (MUX) is a circuit component used to select one input signal from multiple input signals as the output signal. Typically, a multiplexer receives a control signal and determines which input signal to use as the output signal based on that signal.

[0061] De-Multiplexer (DEMUX): A circuit component used to send input data to any one of multiple output terminals. Typically, a de-multiplexer receives control signals and determines which output terminal to send the input signal to.

[0062] Leading One Detector (LOD): A circuit component used to determine the most significant bit of binary data and its position in a binary sequence. The most significant bit of binary data is also called the leading one. Optionally, the leading one refers to the first specified bit of binary data in the binary sequence, which can be either 0 or 1.

[0063] For multi-threaded processors, instruction information for each thread bundle can be managed by an instruction information management system (IPMS). This IMS includes read / write components and memory spaces corresponding to each thread bundle. When it's necessary to read or write instruction information for a specific thread within a given thread bundle, the read / write components perform the read / write operation in the memory space corresponding to that thread bundle. However, processors may have inactive thread bundles. The IMS will not read or write instruction information for these thread bundles, and since each thread bundle corresponds to a separate memory space, there is idle memory space, resulting in wasted storage resources.

[0064] In response, this application provides an instruction information management system that allows multiple threads to share a first storage space, thereby improving the utilization of the first storage space and saving storage resources.

[0065] like Figure 1 As shown, Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application. The computer system includes a terminal device 002 and a server 001. The terminal device 002 has a client installed and running, and the server 001 provides background services to the client.

[0066] In one possible implementation, server 001 undertakes the primary computational work, while terminal device 002 undertakes the secondary computational work. Alternatively, server 001 undertakes the secondary computational work, while terminal device 002 undertakes the primary computational work. Or, terminal device 002 and server 001 collaborate on computation using a distributed computing architecture.

[0067] Optionally, terminal device 002 can be any electronic device product capable of human-computer interaction with a user through one or more methods such as a keyboard, touchpad, remote control, voice interaction, or handwriting device. For example, terminal device 002 can be a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, PC (Personal Computer), mobile phone, PDA (Personal Digital Assistant), wearable device, PPC (Pocket PC), smart car system, smart TV, etc.

[0068] Terminal device 002 can refer to one of multiple terminal devices, and this embodiment only uses terminal device 002 as an example. Those skilled in the art will know that the number of terminal devices 002 can be more or less. For example, there may be only one terminal device 002, or there may be dozens or hundreds of terminal devices 002, or even more. This application embodiment does not limit the number or type of terminal devices 002.

[0069] Server 001 can be a single server, a server cluster consisting of multiple servers, or any of the following: a cloud computing platform or a virtualization center. This application embodiment does not limit this. Server 001 communicates directly or indirectly with terminal device 002 via a wired or wireless network. Server 001 has data receiving, data processing, and data sending functions. Of course, server 001 may also have other functions, which are not limited in this application embodiment.

[0070] Those skilled in the art should understand that the terminal device 002 and server 001 described above are merely illustrative examples. Other existing or future terminal devices or servers that are applicable to this application should also be included within the scope of protection of this application, and are hereby incorporated by reference.

[0071] In practical applications, the instruction information management system provided in this application embodiment can be located in terminal device 002 or server 001. For example... Figure 2 and Figure 3 As shown, the instruction information management system includes an acquisition component 10, a read / write component 20, a first storage space 30, a second storage space 40, and an update component 50. The instruction information management system can, according to... Figure 2 The process shown can be used to write instruction information, which can be done according to... Figure 3 The process shown is for reading instruction information. The following sections describe the process of writing and reading instruction information in sequence.

[0072] (i) When any thread within an arbitrary thread bundle needs to write instruction information, it can send a write instruction to the instruction information management system. The write instruction carries instruction information and the identifier of the thread bundle to which the thread belongs. For example, if a write instruction carries instruction information 0 and the thread bundle identifier w0, then... Figure 2 As shown, after receiving a write command, the instruction information management system can perform the following steps:

[0073] Step 1: Acquire the identification information w0 of the thread bundle using component 10. Specifically, the thread sends a write command to component 10, which carries the identification information w0.

[0074] Step 2: Based on the identification information w0, component 10 reads address 1 in the second storage space 40.

[0075] Assuming there are m thread bundles (m is a positive integer), the second storage space 40 includes m second storage units 400, each corresponding to one of the m thread bundles. The identifiers of the m thread bundles are w0, w1, w2, ... . The first storage space 30 includes n first storage units 300 (n is a positive integer), each capable of storing the instruction information of one thread. A second storage unit 400 can store the address of a first storage unit 300, and this first storage unit 300 stores the instruction information of a specific thread within the thread bundle corresponding to that second storage unit 400. For example, assuming the first storage unit 300 corresponding to address 1 stores the instruction information of a thread within the thread bundle indicated by identifier w0, then the second storage unit 400 corresponding to identifier w0 can store address 1. Similarly, assuming the first storage unit 300 corresponding to address 3 stores the instruction information of a thread within the thread bundle indicated by identifier w1, then the second storage unit 400 corresponding to identifier w1 can store address 3. And so on, without going into detail here.

[0076] In this example, such as Figure 2 As shown, assuming that the second storage unit 400 corresponding to the identification information w0 stores address 1, after the acquisition component 10 obtains the identification information w0, it can read the stored address 1 in the second storage unit 400 corresponding to the identification information w0 in the second storage space 40.

[0077] Step 3: Get component 10 to send address 1 to read / write component 20.

[0078] Step 4: Read / write component 20 receives instruction information 0 from thread 0. Optionally, thread 0 can directly send instruction information 0 to read / write component 20, or it can send a write instruction to read / write component 20, with the write instruction carrying instruction information 0.

[0079] Step 5: Read / write component 20 determines address 0 based on the first storage space 30.

[0080] The first storage space 30 includes n (n is a positive integer) first storage units 300. Each first storage unit 300 includes a first storage subunit 301, a second storage subunit 302, and a third storage subunit 303. The first storage subunit 301 stores instruction information for a specific thread. The second storage subunit 302 stores the address of another first storage unit 300, and this first storage unit 300 stores another instruction information for the thread bundle to which the thread belongs. The third storage subunit 303 stores a validity flag. If the first storage subunit 301 stores instruction information, the validity flag indicates validity; if the first storage subunit 301 does not store instruction information, the validity flag indicates invalidity.

[0081] For example, in the first storage unit 300 corresponding to address 0, if the first storage subunit 301 does not store instruction information, then the third storage subunit 303 stores a validity flag indicating invalidity. In the first storage unit 300 corresponding to address 1, if the first storage subunit 301 stores instruction information, then the third storage subunit 303 stores a validity flag indicating validity. And so on, without further elaboration.

[0082] Furthermore, assuming that in the first storage unit 300 corresponding to address 1, the first storage subunit 301 stores instruction information 1, and instruction information 1 belongs to the thread bundle indicated by the identification information w0, then: the second storage subunit 302 stores address 2, and the first storage unit 300 corresponding to address 2 stores another instruction information of the thread bundle indicated by the identification information w0, that is, instruction information 2 also belongs to the thread bundle indicated by the identification information w0. Similarly, in the first storage unit 300 corresponding to address 2, the second storage subunit 302 stores address 7, and the first storage unit 300 corresponding to address 7 stores another instruction information of the thread bundle indicated by the identification information w0.

[0083] In this example, the read / write component 20 can obtain the address corresponding to the invalid validity identifier based on the validity identifier stored in each third storage sub-unit 303. For example, if the third storage sub-unit 303 corresponding to address 0 stores the invalid validity identifier, then the read / write component 20 can obtain address 0.

[0084] Step 6: Based on address 0, read / write component 20 writes instruction information 0 and address 1 into the first storage space 30. Read / write component 20 can determine the first storage unit 300 corresponding to address 0 in the first storage space 30, write instruction information 0 into the first storage sub-unit 301 of the first storage unit 300, and write address 1 into the second storage sub-unit 302 of the first storage unit 300. Furthermore, after writing instruction information 0 and address 1, the invalidity indicated by the validity flag can be changed to validity in the third storage sub-unit 303 of the first storage unit 300.

[0085] Step 7: Read / write component 20 sends address 0 to update component 50.

[0086] Step 8: Update component 50 updates address 1 in the second storage space 40 to address 0. Update component 50 can determine the second storage unit 400 corresponding to the identification information w0 in the second storage space 40, and replace address 1 in the second storage unit 400 with address 0.

[0087] (II) When any thread within an arbitrary thread bundle needs to read instruction information, it can send a read instruction to the instruction information management system. The read instruction carries the identifier information of the thread bundle to which the thread belongs. Taking a read instruction carrying the thread bundle identifier w0 as an example... Figure 3 As shown, after receiving a read command, the instruction information management system can perform the following steps:

[0088] Step 1: Acquire the identification information w0 of the thread bundle using component 10. Specifically, the thread sends a read command to component 10, which carries the identification information w0.

[0089] Step 2: Based on the identification information w0, component 10 reads address 1 in the second storage space 40.

[0090] Step 3: Get component 10 to send address 1 to read / write component 20.

[0091] The implementation details of steps 2 and 3 can be found in the description of steps 2 and 3 in the instruction information writing process. The implementation principles of the two are similar, and will not be repeated here.

[0092] Step 4: The read / write component 20 reads instruction information 1 and address 2 from the first storage space 30 based on address 1. The read / write component 20 can determine the first storage unit 300 corresponding to address 1 in the first storage space 300, read the stored instruction information 1 from the first storage sub-unit 301 in the first storage unit 300, and read the stored address 2 from the second storage sub-unit 302 in the first storage unit 300. Furthermore, after reading instruction information 1 and address 2, the component can release the instruction information 1 stored in the first storage sub-unit 301 and the address 2 stored in the second storage sub-unit 302 in the first storage unit 300, and in the third storage sub-unit 303, replace the valid execution flag with invalid.

[0093] Step 5: Read / write component 20 sends instruction information 1 to the thread.

[0094] Step 6: Read / write component 20 sends address 2 to update component 50.

[0095] Step 7: Update component 50 updates address 1 in the second storage space 40 to address 2. Update component 50 can determine the second storage unit 400 corresponding to the identification information w0 in the second storage space 40, and replace address 1 in the second storage unit 400 with address 2.

[0096] This application provides an instruction information management system, which can be deployed in terminal device 002 or server 001 within the aforementioned computer system. For ease of description, terminal device 002 or server 001 is collectively referred to as an electronic device. The electronic device includes a chip, which includes a multi-threaded processor responsible for executing programs. During program execution, the multi-threaded processor can generate instructions, execute instructions, and perform read / write instructions. The type of chip is not limited here; for example, the chip can be a central processing unit chip, a graphics processing unit chip, an artificial intelligence chip, etc. The chip includes an instruction information management system, which reads and writes instructions for each thread.

[0097] like Figure 4 As shown, the instruction information management system includes an acquisition component 10, a read / write component 20, a first storage space 30, and a second storage space 40. The acquisition component 10 is connected to the second storage space 40 and the read / write component 20, and the read / write component 20 is connected to the first storage space 30. The instruction information management system is an internal circuit of the chip. The acquisition component 10 is a sub-circuit within this circuit, and its structure is not limited here; any sub-circuit capable of acquiring read / write instructions and reading first information can serve as the acquisition component 10. Similarly, the read / write component 20 is a sub-circuit, and its structure is also not limited; any sub-circuit capable of reading and writing instruction information can serve as the read / write component 20. The first storage space 30 and the second storage space 40 are different memories within the circuit, or the first storage space 30 and the second storage space 40 are different storage areas of the same memory within the circuit.

[0098] The first storage space 30 is used to store instruction information of multiple thread bundles, and the second storage space 40 is used to store reference addresses of multiple thread bundles. The reference address of any one of the multiple thread bundles is used to determine the location of the instruction information of the thread bundle in the first storage space 30.

[0099] A multithreaded processor consists of multiple warps, the number of which is denoted as warp_num (a positive integer). A warp is the basic unit of execution in a processor architecture, and each warp contains multiple threads. The number of threads in a warp is denoted as thread_num (a positive integer), optionally, thread_num = 32, meaning a warp contains 32 threads. A thread is the smallest unit of computation that the operating system can schedule; each thread represents an execution flow within a program.

[0100] For single-threaded processors, branch prediction is typically used to handle branch instructions. Branch prediction is an important technique in processors used to predict the execution path of branch instructions in a program. A branch instruction is a control flow instruction used to execute different program paths based on conditions; branch instructions include, but are not limited to, conditional jumps, loops, and function calls.

[0101] When the processor encounters a branch instruction, it doesn't know whether a jump to that branch instruction is necessary. Therefore, the processor first predicts an execution path and continues executing the instructions along that predicted path. If the prediction is correct, the processor will execute instructions continuously without pause. If the prediction is incorrect, the processor needs to discard the instructions executed on the incorrect path and roll back to the correct path to re-execute the instructions. Based on this, the processor needs to record the jump information of historical branch instructions, including whether a jump occurred and the jump address. By storing the jump information of historical branch instructions, it is possible to predict whether a jump is needed for the current instruction based on this information.

[0102] For multithreaded processors, because multiple threads can execute in parallel, different threads may execute different branch instructions. For example, some threads may execute jump branch instructions (jumping to another memory location to execute instructions in that memory location), while others may execute non-jump branch instructions (not jumping to another memory location and continuing to execute instructions in the current memory location). Therefore, branch prediction for single-threaded processors is no longer applicable to multithreaded processors.

[0103] Typically, multithreaded processors can execute two branch instructions sequentially, for example, executing a non-jump branch instruction first, followed by a jump branch instruction. Because the two branch instructions are executed sequentially, it's necessary to record the jump information of the later-executed branch instruction so that it can be executed after the earlier branch instruction has finished. Taking the example of executing a non-jump branch instruction first, followed by a jump branch instruction, the jump information of the jump branch instruction needs to be saved. After the non-jump branch instruction finishes executing, the jump branch instruction is executed based on its jump information. Because this jump information needs to be stored, multithreaded processors require memory to store this information.

[0104] In related technologies, each thread bundle needs to maintain a stack, and the stack depth needs to meet certain conditions to ensure that stack overflow does not occur. For example... Figure 5As shown, assume the number of thread bundles 501 is warp_num, and each thread bundle includes thread_num threads. In related technologies, each thread bundle 501 needs to maintain a stack 502. To prevent stack overflow, the stack depth needs to be equal to the number of threads in the thread bundle 501, that is, the stack includes stack space from 0 to thread_num. Assuming that each thread bundle 501 includes the same number of threads, the multithreaded processor needs to provide warp_num × thread_num stack space. Since the processor has inactive thread bundles, and each thread bundle corresponds to a stack, there are idle stacks, resulting in low stack utilization and wasted storage resources.

[0105] In this example, at least two thread bundles in the multithreaded processor share a first storage space 30. Optionally, all thread bundles in the multithreaded processor share a first storage space 30. By assigning multiple thread bundles to a single first storage space 30, the utilization rate of the first storage space 30 is improved, and the consumption of storage resources is reduced.

[0106] The first storage space 30 is used to store instruction information for multiple thread bundles. Instruction information refers to branch instruction information, including but not limited to branch instruction jump information, branch instruction masking information, and branch instruction instruction type. It should be noted that each thread in a thread bundle can generate instruction information, and since a thread bundle includes multiple threads, each thread bundle corresponds to at least one instruction information.

[0107] In this example, at least two thread bundles in the multithreaded processor jointly maintain a second storage space 40. Optionally, all thread bundles in the multithreaded processor jointly maintain a second storage space 40. The second storage space 40 stores the reference addresses of each thread bundle, and the reference addresses of the thread bundles can indicate the location of the instruction information of the thread bundle in the first storage space 30. Optionally, the first storage space 30 can be regarded as a stack of multiple thread bundles, and the thread bundle stack stores the instruction information of the thread bundles in a last-in-last-out manner. Therefore, the reference address of the thread bundle can be the top address of the thread bundle's stack.

[0108] In an exemplary embodiment, the acquisition component 10 is used to acquire read / write instructions, which are used to instruct the reading and writing of instruction information of the first thread.

[0109] Read and write instructions include either read instructions or write instructions. The first thread can be any thread in the multi-threaded processor. The first thread can send a read instruction to the acquisition component 10, which includes the first thread's instruction information and is used to instruct the reading of the first thread's instruction information. The first thread can also send a write instruction to the acquisition component 10, which includes the first thread's instruction information and is used to instruct the writing of the first thread's instruction information.

[0110] The acquisition component 10 is also used to read first information from the second storage space 40 according to read / write instructions. The first information is the reference address of the thread bundle to which the first thread belongs.

[0111] Since the second storage space 40 can store the reference addresses of each thread bundle, when the acquisition component 10 receives a read instruction or write instruction from the first thread, it can read the reference address of the thread bundle to which the first thread belongs from the second storage space 40, that is, read the first information.

[0112] Optionally, the second storage space includes multiple second storage units, each corresponding to a multiple thread bundle. The i-th second storage unit is used to store the reference address of the i-th thread bundle, where i is an integer.

[0113] In other words, assuming a multithreaded processor includes `warp_num` thread bundles, the second storage space includes `warp_num` second storage spaces, each corresponding one-to-one with one of the `warp_num` thread bundles. Each thread bundle has unique identification information, which includes at least one of the following: numbers, letters, symbols, etc. For example, the identification information for the i-th thread bundle is `warpi` or `wi`. The unique identification information identifies the corresponding thread bundle, allowing for precise identification of each thread bundle. The number of identification information is `warp_num`. Since `warp_num` identification information corresponds one-to-one with one of the `warp_num` thread bundles, `warp_num` identification information also corresponds one-to-one with one of the `warp_num` second storage spaces. Figure 2 and Figure 3 As shown, the second storage space 40 includes multiple second storage units 400. The i-th second storage unit 400 corresponds to the identification information wi of the i-th thread bundle, thereby realizing the correspondence between the i-th second storage unit 400 and the i-th thread bundle and the identification information of the i-th thread bundle.

[0114] In addition to storing the reference address of the corresponding thread bundle, the second storage unit can also store other information about the corresponding thread bundle, such as its identification information. That is, the second storage unit can include two sub-units: one sub-unit stores the identification information of the corresponding thread bundle, and the other sub-unit stores the reference address of the corresponding thread bundle. By storing the reference addresses of the corresponding thread bundles in the second storage unit, which corresponds one-to-one with multiple thread bundles, the acquisition component 10 can accurately obtain the reference address of the thread bundle to which the first thread belongs. This allows it to read and write the instruction information of the first thread based on the reference address, thus enabling instruction information management.

[0115] Understandably, the second storage space is a structure used to store data, and it can take various forms, such as a queue, a data pool, or a table. A table is a storage architecture used to store data. In this example, the second storage space can be represented as a table, which includes `warp_num` entries. Each entry is a row of cells in the table, and each entry is a representation of a second storage unit. Entries are used to store the reference address of the corresponding thread bundle, and can also be used to store other information about the corresponding thread bundle.

[0116] In an exemplary embodiment, the acquisition component 10 includes a first acquisition unit and a second acquisition unit, wherein the first acquisition unit and the second acquisition unit are connected, and the second acquisition unit is connected to the second storage space 40. The first acquisition unit is used to acquire read / write instructions, which carry identification information of the thread bundle to which the first thread belongs; the second acquisition unit is used to read first information from the second storage space 40 according to the identification information.

[0117] The first thread can send read / write instructions to the first acquisition unit. After receiving the read / write instructions, the first acquisition unit can directly send read / write instructions to the second acquisition unit, or it can extract identification information from the read / write instructions and send the identification information to the second acquisition unit. The first acquisition unit can be any of the following: a sub-circuit, a component, or a transistor. For example, the read / write instructions include a read instruction and a write instruction. The first acquisition unit is a multiplexer with two inputs, used to receive the read and write instructions sent by the thread, respectively. The multiplexer has one output, used to select which instruction to send to the second acquisition unit. In other words, the multiplexer is used to send either a read instruction or a write instruction to the second acquisition unit.

[0118] Since the second storage space 40 can store the reference addresses of each thread bundle, the second acquisition unit can read the reference address of the thread bundle corresponding to the identification information from the second storage space 40 to obtain the first information. Optionally, the second storage space 40 includes warp_num second storage units. The second acquisition unit can determine the second storage unit corresponding to the identification information from the warp_num second storage units, read the reference address from it, and obtain the first information. Figure 2 As shown, assuming the read / write instruction carries identification information w0, the second acquisition unit can determine the first second storage unit 400 from warp_num second storage units 400 and read the first information "address 1" from it.

[0119] The second acquisition unit can be any of the following: a sub-circuit, a component, or a transistor. For example, the second acquisition unit is a multiplexer. The multiplexer has `warp_num` inputs, each corresponding to one of the `warp_num` second storage units, used to receive the reference address stored in the corresponding second storage unit. The multiplexer has one output, used to select and output a single reference address, which is the first information.

[0120] In practical applications, there might be situations where the second storage space 40 does not store the reference address of the thread bundle corresponding to the identification information. For example, Figure 2 The first second storage unit 400 does not store any information. In this case, the second acquisition unit cannot read the first information; that is, the second acquisition unit reads blank information based on the identification information.

[0121] In other words, if the reference address of the thread bundle corresponding to the identification information is stored in the second storage space 40, the second acquisition unit reads the first information from the second storage space 40. If the reference address of the thread bundle corresponding to the identification information is not stored in the second storage space 40, the second acquisition unit reads blank information from the second storage space 40.

[0122] For the first thread, the reference address of the thread bundle to which the first thread belongs can be accurately read from the second storage space through the identification information, thereby improving the accuracy of the reference address. This allows subsequent read and write instructions of the first thread to be accurately performed in the first storage space based on the reference address, thus improving the system's management performance.

[0123] The read / write component 20 is used to read and write instruction information of the first thread in the first storage space 30 based on the first information.

[0124] If the acquisition component 10 acquires a read instruction, the read-write component 20 can read the instruction information of the first thread stored in the first storage space 30 based on the first information; if the acquisition component 10 acquires a write instruction, the read-write component 20 can write the instruction information of the first thread into the first storage space 30 based on the first information.

[0125] In practical applications, there are differences between the way the read / write component 20 reads instruction information and the way the read / write component 20 writes instruction information. These two methods are described in implementation method A and implementation method B respectively.

[0126] In implementation A, the read / write instruction includes a write instruction, the first storage space 30 includes multiple first storage units, and the read / write component 20 includes a determining unit and a writing unit. The determining unit is connected to the writing unit and the first storage space 30, and the writing unit is connected to the acquiring component 10 and the first storage space 30. The determining unit is used to determine a free unit from the multiple first storage units that does not store instruction information; the writing unit is used to write the instruction information of the first thread into the free unit; the writing unit is also used to write first information into the free unit.

[0127] The first storage space 30 includes M (M is a positive integer) first storage units, each of which is used to store one instruction message. If a first storage unit has stored instruction information, it can be considered a valid first storage unit (referred to as a valid unit) or a first storage unit storing information (referred to as an information unit); if a first storage unit has not stored instruction information, it can be considered an invalid first storage unit (referred to as an invalid unit) or a free first storage unit (referred to as a free unit).

[0128] Understandably, the first storage space is a structure used to store data, and it can take various forms, such as a queue, a data pool, or a table. Optionally, the first storage space can be represented as a table, which includes multiple entries (i.e., a row of cells in the table). Each entry is a representation of a first storage unit. Entries are used to store thread instruction information, and can also be used to store other information about the corresponding thread.

[0129] In this example, the first thread or acquisition component 10 can send a write command to the determined unit. After receiving the write command, the determined unit traverses each first storage unit to identify a free unit. Optionally, after traversing each first storage unit, if the first storage unit is free, the traversal process ends; if the first storage unit is valid, the next first storage unit is traversed. This process continues until the first free unit is found.

[0130] Optionally, the first storage unit is further configured to store a validity identifier, which indicates whether the first storage unit stores instruction information; the determining unit is configured to determine a free unit from the multiple first storage units based on the validity identifiers stored in the multiple first storage units.

[0131] The first storage unit stores a validity flag, the value of which reflects whether the first storage unit stores instruction information. If the validity flag is a first value, the first storage unit stores instruction information; if the validity flag is a second value, the first storage unit does not store instruction information. The first value and the second value are different values; for example, the first value is 1 and the second value is 0.

[0132] The determination unit can iterate through the validity identifiers of each first storage unit to determine the second value, thereby identifying the free unit corresponding to the second value. Optionally, after iterating through the validity identifiers of each first storage unit, if the first storage unit is determined to be a free unit based on the validity identifier, the iteration process ends; if the first storage unit is determined to be a valid unit based on the validity identifier, the validity identifiers of the next first storage unit are iterated through. This process continues until the first free unit is found.

[0133] Optionally, the first value is 1 and the second value is 0, and the determining unit is a leading 1 detector. The leading 1 detector can arrange the validity identifiers of each first memory unit in sequence to form a binary sequence, and detect the first second value (i.e., 0) in the binary sequence to determine the free unit corresponding to the second value.

[0134] By using a validity flag to indicate whether the first storage unit stores instruction information, the system can quickly and accurately identify free units based on the validity flag, so that instruction information and first information can be written into the free units subsequently, thus improving the writing efficiency of instruction information.

[0135] Understandably, once the determining unit identifies a free unit, it obtains the address of that free unit. The determining unit then sends the address of the free unit to the writing unit. Based on the address of the free unit, the writing unit can locate the free unit in the first storage space 30 and write the instruction information and first information of the first thread into the free unit.

[0136] Optionally, the first storage unit includes a first storage sub-unit, a second storage sub-unit, and a third storage sub-unit. The first storage sub-unit is used to store the instruction information of the thread. The second storage sub-unit is used to store the address of another second storage unit (hereinafter referred to as the related unit) related to the first storage unit, and the related unit stores another instruction information of the thread bundle to which the thread belongs. The third storage sub-unit is used to store a validity identifier. Optionally, the first storage unit is an entry, including a row of cells in a table. The first storage sub-unit, the second storage sub-unit, and the third storage sub-unit can be represented as different cells in an entry.

[0137] Based on this, after locating an idle unit, the write unit can write the instruction information of the first thread in the first storage sub-unit of the idle unit, write the first information in the second storage sub-unit of the idle unit, and change the validity flag from indicating that the instruction information has not been stored to indicating that the instruction information has been stored in the third storage sub-unit of the idle unit.

[0138] Understandably, if the acquisition component 10 reads blank information based on the identification information, the write unit, after locating the free unit, writes the instruction information of the first thread into the first storage sub-unit of the free unit, and changes the validity flag from indicating that the instruction information is not stored to indicating that the instruction information is stored in the third storage sub-unit of the free unit.

[0139] like Figure 6 As shown in (2), the first storage space 30 is represented in the form of a table. The table includes multiple entries, each entry being a row cell in the table, and each entry corresponds to a first storage unit 300. Therefore, the first storage space 30 includes multiple first storage units 300. Each entry corresponds to a branch_info field, a pre_index field, and a valid field. The cell in the branch_info field corresponds to the first storage subunit 301, which is used to store the instruction information of the thread. The cell in the pre_index field corresponds to the second storage subunit 302, which is used to store the address of the relevant unit. The cell in the valid field corresponds to the third storage subunit 303, which is used to store the validity identifier.

[0140] For the first storage unit, since the first storage subunit stores the instruction information of the thread, the second storage subunit stores the address of the related unit, and the related unit stores another instruction information of the thread bundle to which the thread belongs, the first storage unit can indicate two instruction information of the thread bundle. Optionally, the instruction information stored in the related unit is the previous instruction information of the instruction information stored in the first storage subunit generated by the same thread bundle, and two adjacent instruction information generated by the thread bundle can be indicated through one first storage unit. Assuming that the thread bundle generates N (N is a positive integer) instruction information in sequence, the embodiments of this application can store the N instruction information in N first storage units in a first-generate-first-store manner. The N first storage units can reflect the storage order of the N instruction information, so that the N first storage units can be regarded as the stack of the thread bundle, and the N first storage units can be discretely distributed.

[0141] like Figure 6 As shown in (1), Figure 6 (1) is a schematic diagram of stack storage of instruction information in related technologies. Assuming that the thread bundle generates instruction information a, instruction information b and instruction information c in sequence, then: the stack first receives instruction information a and stores instruction information a at the top of the stack, and the state of the stack at this time is shown as 601; then the stack receives instruction information b and stores instruction information b at the top of the stack shown in 601, and the state of the stack at this time is shown as 602; then the stack receives instruction information c and stores instruction information c at the top of the stack shown in 602, and the state of the stack at this time is shown as 603.

[0142] In this example, such as Figure 6 As shown in (2), assuming that the thread bundle generates instruction information a, instruction information b, and instruction information c in sequence, then: First, instruction information a can be obtained. The determining unit determines a free unit from the first storage space 30, and the address of the free unit is address 3. The writing unit writes instruction information a into the first storage sub-unit 301. Since instruction information a does not have a previous instruction information, the second storage sub-unit 302 does not store any information. "NULL" is used to represent that no information is stored. In addition, the writing unit changes the validity flag from 0 (indicating that no instruction information is stored) to 1 (indicating that instruction information is stored). Next, instruction information b can be obtained. Assuming that before obtaining instruction information b, the first storage space 30 corresponding to addresses 2 and 1 has already stored instruction information of other thread bundles, in this case, the determining unit can determine a free unit from the first storage space 30, and the address of the free unit is address 0. The writing unit writes instruction information b into the first storage sub-unit 301. Since instruction information a is the preceding instruction information b, address 3 is the address of the relevant unit. The second storage subunit 302 stores address 3. Furthermore, the write unit changes the validity flag from 0 to 1. Afterwards, instruction information c can be obtained. Assuming that the first storage space 30 corresponding to address 1 did not store instruction information before obtaining instruction information c, the determining unit can determine a free unit from the first storage space 30. The address of this free unit is address 1. The write unit writes instruction information c into the first storage subunit 301. Since instruction information b is the preceding instruction information c, address 0 is the address of the relevant unit. The second storage subunit 302 stores address 0. Furthermore, the write unit changes the validity flag from 0 to 1. Finally, the following can be obtained: Figure 6 The first storage space 30 is shown in (2) of the diagram.

[0143] Depend on Figure 6 As can be seen from (2) above, each first storage unit belonging to the same thread bundle can be determined through the first storage subunit 301 and the second storage subunit 302, and these first storage units can constitute the stack of the thread bundle. The first storage space 30 includes the stack of at least one thread bundle. For example, the first storage unit corresponding to address 1, the first storage unit corresponding to address 0, and the first storage unit corresponding to address 3 can constitute the stack of the thread bundle. Figure 6 The stack corresponding to label 603 shown in (1) is shown.

[0144] It is understandable that before the system writes the instruction information of the first thread, the second storage space stores the reference address of the thread bundle to which the first thread belongs. When the system writes the instruction information of the first thread, it needs to write the reference address into the second storage sub-unit 302. Therefore, the reference address can be understood as the stack top address of the stack corresponding to the thread bundle.

[0145] like Figure 6 As shown in (2), before writing instruction information a to the first storage unit 300 corresponding to address 3, the second storage space does not store a reference address, which means that when writing instruction information a to the first storage sub-unit 301, it is impossible to write information to the second storage sub-unit 302. Before writing instruction information b to the first storage unit 300 corresponding to address 0, the second storage space stores the reference address "address 3". As can be seen from the stack shown by label 601, the address storing instruction information a is the top address of the stack, that is, "address 3" is the top address of the stack, which means that when writing instruction information b to the first storage sub-unit 301, address 3 can be written to the second storage sub-unit 302. Before writing instruction information c to the first storage unit 300 corresponding to address 1, the second storage space stores the reference address "address 0". As can be seen from the stack shown by label 602, the address storing instruction information b is the top address of the stack, that is, "address 0" is the top address of the stack, which means that when writing instruction information c to the first storage sub-unit 301, address 0 can be written to the second storage sub-unit 302.

[0146] By determining a free unit from the first storage space through the determination unit, and writing the instruction information and first information of the first thread into the free unit through the write unit, the instruction information of the same thread bundle is associated and stored, thereby improving the management performance of the system.

[0147] Optionally, if the acquisition component 10 reads blank information from the second storage space 40 according to the read / write instruction, that is, the second storage space 40 does not store the reference address of the thread bundle to which the first thread belongs, then: the determination unit can determine the free unit, and the write unit directly writes the instruction information of the first thread into the free unit.

[0148] In implementation B, the read / write instruction includes a read instruction, the first storage space 30 includes multiple first storage units, and the read / write component 10 includes a read unit. The read unit is connected to the first storage space 30 and the acquisition component 10. The read unit is used to determine an information unit from the multiple first storage units based on first information. The information unit stores instruction information of the first thread. The read unit is also used to read the instruction information stored in the information unit.

[0149] In this example, the first information is the address of a first storage unit, which the read unit can directly determine. Since this first storage unit stores the instruction information of the first thread, it is an information unit. The read unit can directly read the instruction information stored in the information unit and send the instruction information to the first thread.

[0150] Optionally, the first storage unit includes a first storage sub-unit, a second storage sub-unit, and a third storage sub-unit. The read unit can directly read the instruction information stored in the first storage sub-unit and send the instruction information to the first thread.

[0151] By locating the information unit using the first information, the reading unit can read accurate instruction information, thus improving the efficiency of instruction information reading.

[0152] Understandably, if the acquisition component 10 fails to read information from the second storage space 40 according to the read instruction, the acquisition component 10 or the read unit can send a prompt signal to the first thread to indicate that the instruction information reading failed.

[0153] In an exemplary embodiment, such as Figure 7 As shown, the instruction information management system of this application embodiment further includes an update component 50, wherein the update component 50 is connected to the read / write component 20 and the second storage space 40. The read / write component 20 is used to determine second information, which is the address storing instruction information of the thread bundle to which the first thread belongs; the update component 20 is used to update the first information to the second information in the second storage space 40.

[0154] Regardless of whether the read / write component 20 receives a read instruction or a write instruction, it will determine the second information. The read / write component 20 sends the second information to the update component 50, so that the update component 50 updates the first information in the second storage space 40 with the second information. Optionally, the read / write component 20 sends the second information and the identification information of the thread bundle to which the first thread belongs to the update component 50. The update component 50 determines the second storage unit based on the identification information and updates the first information in the second storage unit with the second information.

[0155] The instruction information management system is an internal circuit of the chip, and the update component 50 is a sub-circuit within this circuit. The structure of the sub-circuit is not limited here; any sub-circuit capable of updating information can serve as the update component 50. For example, the update component 50 includes a multiplexer and a multiplexer. The multiplexer has two inputs, receiving the second information of a read instruction and the second information of a write instruction, respectively. The multiplexer has one output, used to output the second information. The multiplexer has one input, used to receive the second information output by the multiplexer. The multiplexer has `warp_num` outputs, each corresponding one-to-one with `warp_num` second storage units, used to allocate the second information to one output for output, so that the first information is replaced with the second information in the corresponding second storage unit of that output.

[0156] In practical applications, read instructions and write instructions correspond to different second information. The two methods are described in implementation method C and implementation method D respectively.

[0157] In implementation C, the read / write instructions include write instructions, the first storage space 30 includes multiple first storage units, and the second information is the address of the first storage unit for the instruction information to be written to the first thread.

[0158] Since the determining unit writes the instruction information and first information of the first thread into the idle unit after determining the idle unit, the second information is the address of this idle unit. The determining unit or the writing unit in the read / write component 20 can send the second information to the update component 50 so that the update component replaces the first information with the second information.

[0159] By updating the first information in the second storage space 40 to the address of the first storage unit for writing instruction information, the foundation for the next instruction information of the thread bundle is laid, which is beneficial for reading and writing the next instruction information and improves the management performance of the system.

[0160] The following section describes the process of writing instruction information using implementation methods A and C. Figure 8 As shown. In this example, both the first storage space 30 and the second storage space 40 exist in the form of a table. The first storage space 30 includes entries (i.e., first storage units) corresponding to each address. Each entry includes a cell of the branch_info field (i.e., a first storage sub-unit), a cell of the pre_index field (i.e., a second storage sub-unit), and a cell of the valid field (i.e., a third storage sub-unit). The second storage space 40 includes entries (i.e., second storage units) corresponding to each thread number.

[0161] In the initial state, neither the first storage space 30 nor the second storage space 40 stores instruction information. Therefore, the value of each valid field (i.e., the validity flag) in the first storage space 30 is 0, indicating that no instruction information is stored in any entry in the first storage space 30. Similarly, "NULL" is used to indicate that no address is stored in any entry in the second storage space 40.

[0162] Suppose that a thread in thread bundle 2 needs to write instruction information 'a'. In this case, the acquisition component 10 first determines the entry corresponding to the identification information w2 of thread bundle 2 from the second storage space 40. At this time, the entry has no stored address. Next, the determination unit determines an address with a valid value of 0, which is the address of a free entry. For example, the determination unit determines address 0. The write unit can determine the entry 802 corresponding to address 0, write the instruction information 'a' into the branch_info field of entry 802, and set the valid field of entry 802 from 0 to 1. The valid = 1 indicates that entry 802 stores instruction information. Afterwards, the update component 50 writes address 0 into the entry corresponding to the identification information w2, obtaining entry 801. Here, address 0 is equivalent to the stack top address of the stack corresponding to thread bundle 2.

[0163] Suppose another thread in thread bundle 2 needs to write instruction information b. In this case, the acquisition component 10 first determines the entry corresponding to the identification information w2 of thread bundle 2 from the second storage space 40, that is, determines entry 801. At this time, entry 801 is stored at address 0. The acquisition component 10 can send address 0 to the write unit. Next, the determination unit determines an address with a valid value of 0, which is the address of a free entry. For example, the determination unit determines address 1. The write unit can determine the entry 804 corresponding to address 1, write instruction information b in the branch_info field of entry 804, write address 0 in the pre_index field of entry 804, and set the valid field of entry 804 from 0 to 1. The valid = 1 indicates that entry 804 stores instruction information. Afterwards, the update component 50 replaces address 0 with address 1 in entry 801 to obtain entry 803. Here, address 1 is equivalent to the stack top address of the stack corresponding to thread bundle 2. And so on.

[0164] In implementation method D, the read / write instruction includes a read instruction, and the first storage space 30 includes multiple first storage units, each of which includes an information unit that stores instruction information of the first thread.

[0165] The read / write component 20 is used to determine that the second information is the address of the relevant unit when the information unit still stores the address of the relevant unit, and to determine that the second information is blank information when the information unit does not store the address of the relevant unit. The relevant unit is the first storage unit that stores the instruction information of the thread bundle to which the first thread belongs.

[0166] As mentioned above, when the read unit in the read / write component 20 determines an information unit, the second storage subunit in the information unit can store the address of the relevant unit. In this case, the read unit can read the address of the relevant unit from the second storage subunit in the information unit, and this address is the second information. Alternatively, the second storage subunit in the information unit may not store any information. In this case, the read unit can use blank information as the second information. The read unit can send the second information to the update component 50 so that the update component replaces the first information with the second information.

[0167] Furthermore, if the information unit stores second information, the read unit, after reading the instruction information and second information from the information unit, can release the stored instruction information and second information, and change the validity flag from indicating that instruction information is stored to indicating that instruction information is not stored. Similarly, if the information unit does not store second information, the read unit, after reading the instruction information from the information unit, can release the stored instruction information, and change the validity flag from indicating that instruction information is stored to indicating that instruction information is not stored.

[0168] By updating the first information in the second storage space 40 to blank information or the second information stored in the information unit, and the second information can be used to determine the first storage unit of the previous instruction information of the storage thread bundle, the subsequent thread bundle can read and write instruction information based on the second information, thereby improving the management performance of the system.

[0169] The following section describes the process of reading instruction information using implementation methods B and D. Figure 9 As shown. In this example, both the first storage space 30 and the second storage space 40 exist in the form of a table. The first storage space 30 includes entries (i.e., first storage units) corresponding to each address. Each entry includes a cell of the branch_info field (i.e., a first storage sub-unit), a cell of the pre_index field (i.e., a second storage sub-unit), and a cell of the valid field (i.e., a third storage sub-unit). The second storage space 40 includes entries (i.e., second storage units) corresponding to each thread bundle.

[0170] Assume the identifiers for thread bundles 0 to 3 are w0 to w3 respectively. For the first storage space 30, in the entry corresponding to address 0, the cell in the `branch_info` field stores the instruction information `c` for thread bundle 1, and `valid = 1`; in the entry corresponding to address 1, `valid = 0`; in the entry corresponding to address 2, the cell in the `branch_info` field stores the instruction information `b` for thread bundle 2, and the cell in the `pre_index` field stores address 3, and `valid = 1`; in the entry corresponding to address 3, the cell in the `branch_info` field stores the instruction information `a` for thread bundle 2, and `valid = 1`. From the first storage space 30, we know that the stack top address of thread bundle 1 is address 0, and the stack top address of thread bundle 2 is address 2. Based on this, for the second storage space 40, the entry corresponding to thread bundle 1 stores address 0, and the entry corresponding to thread bundle 2 stores address 2.

[0171] Suppose that a thread in thread bundle 2 needs to read instruction information. In this case, the acquisition component 10 first determines the entry corresponding to the identification information w2 of thread bundle 2 from the second storage space 40, that is, determines entry 901. At this time, entry 901 is stored at address 2. The acquisition component 10 can send address 2 to the read unit. Next, the read unit can determine the entry corresponding to address 2, read instruction information b from the branch_info field of the entry, read address 3 from the pre_index field of the entry, send instruction information b to the thread, and send address 3 to the update component. In addition, the instruction information and address in the entry corresponding to address 2 are deleted, and the valid field is set from 1 to 0. The valid=0 indicates that the entry does not store instruction information. Finally, the entry corresponding to address 2 is shown as label 902. After that, the update component 50 replaces address 2 with address 3 in the entry corresponding to w2, and finally obtains the entry shown as label 901. At this time, address 3 in the first storage space 30 is equivalent to the stack top address of the stack corresponding to thread bundle 2. And so on.

[0172] By updating the first information in the second storage space 40 to the second information, the foundation for the next instruction information of the thread bundle to which the first thread belongs is laid, which facilitates the reading and writing of the next instruction information and improves the management performance of the system.

[0173] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant regions. For example, the instruction information and addresses involved in this application were obtained with full authorization.

[0174] In the above system, the first storage space is used to store the instruction information of each thread bundle, and the second storage space is used to store the reference address of each thread bundle. When the acquisition component obtains the read / write instruction of the first thread, it can read the reference address of the thread bundle to which the first thread belongs from the second storage space. Since this reference address indicates the location of the instruction information of the thread bundle to which the first thread belongs in the first storage space, the read / write component can read and write the instruction information of the first thread in the first storage space based on this reference address. This realizes the storage of instruction information of each thread bundle in the first storage space, and the management of instruction information of each thread bundle through the acquisition component, the read / write component, the first storage space, and the second storage space.

[0175] Furthermore, since multiple thread bundles share the first storage space, even if there are inactive thread bundles among them, the first storage space will still store the instruction information of the active thread bundles, which not only improves the utilization of the first storage space but also reduces the waste of storage resources.

[0176] The following section systematically explains the process of managing instruction information through the aforementioned instruction information management system. For example... Figure 10 As shown, the process includes the following steps:

[0177] Step 1001: Obtain the component acquisition instruction, and read the first information from the second storage space according to the identification information in the instruction.

[0178] like Figure 11 As shown, the acquisition component includes multiplexer 101 and multiplexer 102. Multiplexer 101 can receive write commands and read commands, both of which carry identification information. Multiplexer 101 sends the identification information to multiplexer 102, and multiplexer 102 reads the corresponding stored first information from the second storage space 40 based on the identification information. For example, if the identification information is w0, multiplexer 102 can determine the entry corresponding to w0 from the second storage space 40, read address 1 from that entry, and address 1 is the first information.

[0179] Step 1002: Determine if the instruction is a write instruction. If the instruction is a write instruction, proceed to steps 1003 to 1004. If the instruction is a read instruction, proceed to step 1005.

[0180] Step 1003: Determine the address of the free unit from the first storage space and set the address as the second information.

[0181] like Figure 11As shown, the determining unit is the preamble detector 201. The first storage space 30 includes entries for each address, and each entry can store a validity flag indicating whether it is valid or invalid. If an entry stores instruction information, the validity flag indicates validity; if an entry does not store instruction information, the validity flag indicates invalidity. The preamble detector 501 can traverse each validity flag to obtain a validity flag indicating invalidity and determine the address corresponding to that flag. For example, the preamble detector 501 determines address 0. Address 0 is the second information.

[0182] Step 1004: The write unit writes the instruction information and the first information into the first storage space according to the address of the free unit.

[0183] like Figure 11 As shown, the write unit 202 can receive instruction information, first information, and second information. It determines a free unit based on the second information, for example, determining the entry corresponding to address 0 in the first storage space 30. The write unit 202 writes the instruction information and the first information into the entry and changes the validity flag from indicating invalid to indicating valid.

[0184] Step 1005: The reading unit determines the information unit corresponding to the first information from the first storage space, and reads the instruction information and the second information from the information unit.

[0185] like Figure 11 As shown, the read unit is a multiplexer 203. The multiplexer 203 can receive first information and determine the entry corresponding to the first information in the first storage space 30. For example, it can determine the entry corresponding to address 1 in the first storage space 30; this entry is the information unit. The information unit stores instruction information and second information. The second information is the address of an entry storing another instruction information of the thread bundle corresponding to the instruction information. For example, if instruction information 1 and instruction information 2 correspond to the same thread bundle, then the entry at address 1 can store address 2 corresponding to instruction information 2. The read unit can read the instruction information and second information stored in the information unit. For example, if the information unit is the entry corresponding to address 1, then the read unit can read instruction information 1 and address 2; address 2 is the second information.

[0186] Step 1006: The updating component updates the first information to the second information in the second storage space.

[0187] like Figure 11As shown, the updating components include a multiplexer 501 and a multiplexer 502. The multiplexer 501 can receive the second information from both write and read instructions, and select one of the second information to output. For example, for a write instruction, the second information is address 0; for a read instruction, the second information is address 2, and the multiplexer 501 can output either address 0 or address 2. The multiplexer 502 can receive the second information sent by the multiplexer 501 and replace the first information with the second information. For example, for a write instruction, the multiplexer 502 can replace address 1 with address 0; for a read instruction, the multiplexer 502 can replace address 1 with address 2.

[0188] It should be noted that the first storage space 30 can be viewed as the stack of each thread bundle, and the entries in the stack can be discretely distributed. Each address in the second storage space 40 can be viewed as a pointer to each thread bundle, and the thread bundle stack is managed through these pointers. Since each thread bundle shares the first storage space 30, and multi-threaded processors typically have inactive thread bundles, a smaller first storage space 30 can be configured. For example, if a multi-threaded processor corresponds to `warp_num` thread bundles, and each thread bundle includes `thread_num` threads, then the first storage space 30 can include (`warp_num` × `thread_num`) × 0.5 entries. This configuration of the first storage space 30 can generally meet the needs of various scenarios and can reduce chip area.

[0189] like Figure 12 As shown, Figure 12 This is a flowchart illustrating an instruction information management method provided in an embodiment of this application. This method can be applied to the aforementioned instruction information management system and is executed by an electronic device including a first storage space and a second storage space. The electronic device includes a terminal device or a server. The first storage space stores instruction information for multiple thread bundles, and the second storage space stores reference addresses for the multiple thread bundles. The reference address of any one of the multiple thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space. Figure 12 As shown, the instruction information management method of this application embodiment includes the following steps.

[0190] Step 1201: Obtain read / write instructions. Read / write instructions are used to instruct the first thread to read or write instructions.

[0191] Step 1202: According to the read / write instruction, read the first information from the second storage space. The first information is the reference address of the thread bundle to which the first thread belongs.

[0192] Step 1203: Based on the first information, read and write the instruction information of the first thread in the first storage space;

[0193] The first storage space is used to store instruction information for multiple thread bundles, and the second storage space is used to store reference addresses for multiple thread bundles. The reference addresses are used to determine the location of the instruction information for the corresponding thread bundle in the first storage space.

[0194] In one possible implementation, the read / write instruction carries identification information of the thread bundle to which the first thread belongs; step 1202 includes: reading the first information from the second storage space according to the identification information.

[0195] In one possible implementation, the read / write instruction includes a write instruction, and the first storage space includes a plurality of first storage units; step 1203 includes: determining a free unit from the plurality of first storage units that does not store instruction information; writing instruction information of the first thread into the free unit; and writing first information into the free unit.

[0196] In one possible implementation, the first storage unit is further used to store a validity identifier, which indicates whether the first storage unit stores instruction information; determining a free unit that does not store instruction information from a plurality of first storage units includes: determining a free unit from a plurality of first storage units based on the validity identifiers stored in the plurality of first storage units.

[0197] In one possible implementation, the read / write instruction includes a read instruction, and the first storage space includes multiple first storage units; step 1203 includes: determining an information unit from the multiple first storage units based on first information, the information unit storing instruction information of the first thread; and reading the instruction information stored in the information unit.

[0198] In one possible implementation, the method also includes:

[0199] Determine the second information, which is the address of the instruction information of the thread bundle to which the first thread belongs; update the first information to the second information in the second storage space.

[0200] In one possible implementation, the read / write instruction includes a write instruction, the first storage space includes multiple first storage units, and the second information is the address of the first storage unit containing the instruction information to be written to the first thread.

[0201] In one possible implementation, the read / write instruction includes a read instruction; the first storage space includes multiple first storage units, and the multiple first storage units include information units storing instruction information of the first thread; determining the second information includes:

[0202] If the information unit still stores the address of the relevant unit, it is determined that the second information is the address of the relevant unit, and the relevant unit is the first storage unit that stores the instruction information of the thread bundle to which the first thread belongs; if the information unit does not store the address of the relevant unit, it is determined that the second information is blank information.

[0203] In one possible implementation, the second storage space includes multiple second storage units, each corresponding to a different thread bundle, and the second storage unit is used to store the reference address of the corresponding thread bundle.

[0204] In the above method, the first storage space is used to store the instruction information of each thread bundle, and the second storage space is used to store the reference address of each thread bundle. When a read / write instruction for the first thread is obtained, the reference address of the thread bundle to which the first thread belongs can be read from the second storage space. Since this reference address indicates the location of the instruction information of the thread bundle to which the first thread belongs in the first storage space, the instruction information of the first thread can be read and written in the first storage space based on this reference address. This achieves the storage of instruction information of each thread bundle through the first storage space and the management of instruction information of each thread bundle through the first and second storage spaces.

[0205] Furthermore, since multiple thread bundles share the first storage space, even if there are inactive thread bundles among them, the first storage space will still store the instruction information of the active thread bundles, which not only improves the utilization of the first storage space but also reduces the waste of storage resources.

[0206] Figure 13 The diagram shows a schematic representation of an instruction information management device according to an embodiment of this application. This device is applied to an electronic device including a first storage space and a second storage space. The first storage space stores instruction information for multiple thread bundles, and the second storage space stores reference addresses for the multiple thread bundles. The reference address of any one of the multiple thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space. Figure 13 As shown, the device includes:

[0207] The acquisition module is used to acquire read and write instructions, which are used to instruct the first thread to read or write instructions.

[0208] The read module is used to read the first information from the second storage space according to the read and write instructions. The first information is the reference address of the thread bundle to which the first thread belongs.

[0209] The read / write module is used to read and write instruction information of the first thread in the first storage space based on the first information.

[0210] In one possible implementation, the read / write instruction carries the identification information of the thread bundle to which the first thread belongs;

[0211] The acquisition module is used to read the first information from the second storage space based on the identification information.

[0212] In one possible implementation, the read / write instruction includes a write instruction, and the first storage space includes a plurality of first storage units;

[0213] The read / write module is used to determine a free unit from multiple first storage units that does not store instruction information; write the instruction information of the first thread into the free unit; and write first information into the free unit.

[0214] In one possible implementation, the first storage unit is also used to store a validity flag, which indicates whether the first storage unit stores instruction information.

[0215] The read / write module is used to determine a free unit from multiple first storage units based on the validity identifiers stored in multiple first storage units.

[0216] In one possible implementation, the read / write instruction includes a read instruction, and the first storage space includes a plurality of first storage units;

[0217] The read / write module is used to determine an information unit from multiple first storage units based on first information, where the information unit stores instruction information of the first thread; and to read the instruction information stored in the information unit.

[0218] In one possible implementation, the device further includes:

[0219] The determination module is used to determine the second information, which is the address of the instruction information of the thread bundle to which the first thread belongs;

[0220] The update module is used to update the first information to the second information in the second storage space.

[0221] In one possible implementation, the read / write instruction includes a write instruction, the first storage space includes multiple first storage units, and the second information is the address of the first storage unit containing the instruction information to be written to the first thread.

[0222] In one possible implementation, the read / write instruction includes a read instruction, and the first storage space includes multiple first storage units, each of which includes an information unit that stores instruction information of the first thread.

[0223] The determination module is used to determine that the second information is the address of the relevant unit when the information unit still stores the address of the relevant unit, and the relevant unit is the first storage unit that stores the instruction information of the thread bundle to which the first thread belongs; and to determine that the second information is blank when the information unit does not store the address of the relevant unit.

[0224] In one possible implementation, the second storage space includes multiple second storage units, each corresponding to a different thread bundle, and the second storage unit is used to store the reference address of the corresponding thread bundle.

[0225] In the aforementioned device, the first storage space is used to store the instruction information of each thread bundle, and the second storage space is used to store the reference address of each thread bundle. When a read / write instruction for the first thread is received, the reference address of the thread bundle to which the first thread belongs can be read from the second storage space. Since this reference address indicates the location of the instruction information of the thread bundle to which the first thread belongs in the first storage space, the instruction information of the first thread can be read and written in the first storage space based on this reference address. This achieves the storage of instruction information of each thread bundle through the first storage space and the management of instruction information of each thread bundle through the first and second storage spaces.

[0226] Furthermore, since multiple thread bundles share the first storage space, even if there are inactive thread bundles among them, the first storage space will still store the instruction information of the active thread bundles, which not only improves the utilization of the first storage space but also reduces the waste of storage resources.

[0227] It should be understood that the above Figure 13 The provided device, in implementing its functions, is only illustrated by the division of the above-described functional modules. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, and will not be repeated here.

[0228] Figure 14 This diagram illustrates a structural block diagram of a terminal device 1400 provided in an exemplary embodiment of this application. The terminal device 1400 includes a processor 1401 and a memory 1402. The processor 1401 includes an instruction information management system, which is used to execute an instruction information management method.

[0229] Processor 1401 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1401 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1401 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1401 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1401 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0230] The memory 1402 may include one or more computer-readable storage media, which may be non-transitory. The memory 1402 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1402 are used to store at least one computer program, which is executed by the processor 1401 to implement the instruction information management method provided in the method embodiments of this application.

[0231] In some embodiments, the terminal device 1400 may also optionally include a peripheral device interface 1403 and at least one peripheral device. The processor 1401, memory 1402, and peripheral device interface 1403 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1403 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: a radio frequency circuit 1404, a display screen 1405, a camera assembly 1406, an audio circuit 1407, and a power supply 1408.

[0232] Peripheral device interface 1403 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1401 and memory 1402. In some embodiments, processor 1401, memory 1402 and peripheral device interface 1403 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1401, memory 1402 and peripheral device interface 1403 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0233] The radio frequency (RF) circuit 1404 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1404 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1404 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1404 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, etc. The RF circuit 1404 can communicate with other terminals through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1404 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0234] Display screen 1405 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1405 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1401 for processing. In this case, display screen 1405 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1405, disposed on the front panel of terminal device 1400; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal device 1400 or in a folded design; in still other embodiments, display screen 1405 may be a flexible display screen, disposed on a curved or folded surface of terminal device 1400. Furthermore, display screen 1405 may also be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1405 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0235] The camera assembly 1406 is used to acquire images or videos. Optionally, the camera assembly 1406 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1406 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0236] The audio circuit 1407 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1401 for processing, or input to the radio frequency circuit 1404 to achieve voice communication. For stereo sound acquisition or noise reduction purposes, there may be multiple microphones, each located at a different part of the terminal device 1400. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1401 or the radio frequency circuit 1404 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1407 may also include a headphone jack.

[0237] Power supply 1408 is used to power the various components in terminal device 1400. Power supply 1408 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1408 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, and a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0238] In some embodiments, the terminal device 1400 further includes one or more sensors 1409. The one or more sensors 1409 include, but are not limited to: an accelerometer 1411, a gyroscope 1412, a pressure sensor 1413, an optical sensor 1414, and a proximity sensor 1415.

[0239] Accelerometer 1411 can detect the magnitude of acceleration along the three coordinate axes of a coordinate system established by terminal device 1400. For example, accelerometer 1411 can be used to detect the components of gravitational acceleration along the three coordinate axes. Processor 1401 can control display screen 1405 to display the user interface in either a landscape or portrait view based on the gravitational acceleration signal acquired by accelerometer 1411. Accelerometer 1411 can also be used for games or for acquiring user motion data.

[0240] The gyroscope sensor 1412 can detect the orientation and rotation angle of the terminal device 1400. The gyroscope sensor 1412 can work in conjunction with the accelerometer sensor 1411 to collect 3D motion data from the user on the terminal device 1400. Based on the data collected by the gyroscope sensor 1412, the processor 1401 can perform the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0241] The pressure sensor 1413 can be disposed on the side bezel of the terminal device 1400 and / or on the lower layer of the display screen 1405. When the pressure sensor 1413 is disposed on the side bezel of the terminal device 1400, it can detect the user's grip signal on the terminal device 1400, and the processor 1401 can perform left / right hand recognition or quick operation based on the grip signal collected by the pressure sensor 1413. When the pressure sensor 1413 is disposed on the lower layer of the display screen 1405, the processor 1401 can control the operable controls on the UI interface based on the user's pressure operation on the display screen 1405. The operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0242] Optical sensor 1414 is used to collect ambient light intensity. In one embodiment, processor 1401 can control the display brightness of display screen 1405 based on the ambient light intensity collected by optical sensor 1414. Specifically, when the ambient light intensity is high, the display brightness of display screen 1405 is increased; when the ambient light intensity is low, the display brightness of display screen 1405 is decreased. In another embodiment, processor 1401 can also dynamically adjust the shooting parameters of camera assembly 1406 based on the ambient light intensity collected by optical sensor 1414.

[0243] The proximity sensor 1415, also known as a distance sensor, is typically located on the front panel of the terminal device 1400. The proximity sensor 1415 is used to detect the distance between the user and the front of the terminal device 1400. In one embodiment, when the proximity sensor 1415 detects that the distance between the user and the front of the terminal device 1400 is gradually decreasing, the processor 1401 controls the display screen 1405 to switch from a screen-on state to a screen-off state; when the proximity sensor 1415 detects that the distance between the user and the front of the terminal device 1400 is gradually increasing, the processor 1401 controls the display screen 1405 to switch from a screen-off state to a screen-on state.

[0244] Those skilled in the art will understand that Figure 14 The structure shown does not constitute a limitation on the terminal device 1400, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0245] Figure 15This is a schematic diagram of the server structure provided in the embodiments of this application. The server 1500 can vary considerably due to different configurations or performance. It may include one or more processors 1501 and one or more memories 1502. The processor 1501 includes an instruction information management system, which is used to execute instruction information management methods. Optionally, the one or more memories 1502 store at least one computer program, which is loaded and executed by the one or more processors 1501 to implement the instruction information management methods provided in the above-described method embodiments. For example, the processor 1501 is a CPU. Of course, the server 1500 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server 1500 may also include other components for implementing device functions, which will not be elaborated here.

[0246] In an exemplary embodiment, a chip is provided, the chip including any of the above-described instruction information management systems, the instruction information management system being used to execute any of the above-described instruction information management methods.

[0247] In an exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer program that is loaded and executed by a processor to enable an electronic device to implement any of the above-described instruction information management methods.

[0248] Optionally, the aforementioned computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0249] In an exemplary embodiment, a computer program is also provided, which is at least one such computer program, loaded and executed by a processor to enable an electronic device to implement any of the above-described instruction information management methods.

[0250] In an exemplary embodiment, a computer program product is also provided, which stores at least one computer program that is loaded and executed by a processor to enable an electronic device to implement any of the above-described instruction information management methods.

[0251] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0252] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0253] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. An instruction information management system, characterized in that, The system includes an acquisition component, a read / write component, a first storage space, and a second storage space. The first storage space is used to store instruction information of multiple thread bundles, and the second storage space is used to store reference addresses of the multiple thread bundles. The reference address of any one of the multiple thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space. The acquisition component is used to acquire read and write instructions, which are used to instruct the reading and writing of the first thread's instruction information. The acquisition component is further configured to read first information from the second storage space according to the read / write instruction, wherein the first information is the reference address of the thread bundle to which the first thread belongs; The read / write component is used to read and write the instruction information of the first thread in the first storage space based on the first information.

2. The system according to claim 1, characterized in that, The acquisition component includes a first acquisition unit and a second acquisition unit; The first acquisition unit is used to acquire a read / write instruction, wherein the read / write instruction carries the identification information of the thread bundle to which the first thread belongs; The second acquisition unit is used to read the first information from the second storage space according to the identification information.

3. The system according to claim 1 or 2, characterized in that, The read / write instructions include write instructions, the first storage space includes a plurality of first storage units, and the read / write component includes a determination unit and a write unit; The determining unit is used to determine, from the plurality of first storage units, an idle unit that does not store instruction information; The write unit is used to write the instruction information of the first thread into the idle unit; The write unit is also used to write the first information into the idle unit.

4. The system according to claim 3, characterized in that, The first storage unit is also used to store a validity identifier, which is used to indicate whether the first storage unit stores instruction information; The determining unit is used to determine a free unit from the plurality of first storage units based on the validity identifier stored in the plurality of first storage units.

5. The system according to claim 1 or 2, characterized in that, The read / write instructions include read instructions, the first storage space includes a plurality of first storage units, and the read / write component includes a read unit; The read unit is used to determine an information unit from the plurality of first storage units based on the first information, wherein the information unit stores instruction information of the first thread; The read unit is also used to read instruction information stored in the information unit.

6. The system according to claim 1 or 2, characterized in that, The system also includes an update component; The read / write component is used to determine the second information, which is the address where the instruction information of the thread bundle to which the first thread belongs is stored; The updating component is used to update the first information to the second information in the second storage space.

7. The system according to claim 6, characterized in that, The read / write instructions include write instructions, the first storage space includes multiple first storage units, and the second information is the address of the first storage unit for writing instruction information of the first thread.

8. The system according to claim 6, characterized in that, The read / write instructions include read instructions, and the first storage space includes a plurality of first storage units, the plurality of first storage units including information units that store instruction information of the first thread; The read / write component is used to determine that the second information is the address of the relevant unit when the information unit still stores the address of the relevant unit, and to determine that the second information is blank information when the information unit does not store the address of the relevant unit. The relevant unit is a first storage unit that stores instruction information of the thread bundle to which the first thread belongs.

9. The system according to claim 1 or 2, characterized in that, The second storage space includes multiple second storage units, each corresponding to one of the multiple thread bundles. The i-th second storage unit is used to store the reference address of the i-th thread bundle, where i is an integer.

10. A method for managing instruction information, characterized in that, The method is executed by an electronic device including a first storage space and a second storage space. The first storage space is used to store instruction information of a plurality of thread bundles, and the second storage space is used to store reference addresses of the plurality of thread bundles. The reference address of any one of the plurality of thread bundles is used to determine the location of the instruction information of that thread bundle in the first storage space. The method includes: Obtain read / write instructions, which are used to instruct the first thread to read or write instruction information; According to the read / write instructions, first information is read from the second storage space, where the first information is the reference address of the thread bundle to which the first thread belongs; Based on the first information, read and write the instruction information of the first thread in the first storage space.

11. The method according to claim 10, characterized in that, The read / write instruction carries the identification information of the thread bundle to which the first thread belongs; The step of reading the first information from the second storage space according to the read / write instruction includes: Based on the identification information, the first information is read from the second storage space.

12. The method according to claim 10 or 11, characterized in that, The read / write instructions include write instructions. The first storage space includes multiple first storage units. The step of reading and writing the instruction information of the first thread in the first storage space based on the first information includes: Identify free cells that do not store instruction information from the plurality of first storage cells; The instruction information of the first thread is written into the idle unit; The first information is written into the idle unit.

13. The method according to claim 12, characterized in that, The first storage unit is also used to store a validity identifier, which is used to indicate whether the first storage unit stores instruction information; The step of determining the free cell from the plurality of first storage cells that does not store instruction information includes: Based on the validity identifier stored in the plurality of first storage units, a free unit is determined from the plurality of first storage units.

14. The method according to claim 10 or 11, characterized in that, The read / write instructions include read instructions, and the first storage space includes multiple first storage units; the step of reading and writing the instruction information of the first thread in the first storage space based on the first information includes: Based on the first information, an information unit is determined from the plurality of first storage units, and the information unit stores the instruction information of the first thread; Read the instruction information stored in the information unit.

15. The method according to claim 10 or 11, characterized in that, The method further includes: Determine the second piece of information, which is the address where the instruction information of the thread bundle to which the first thread belongs is stored; In the second storage space, the first information is updated to the second information.

16. The method according to claim 15, characterized in that, The read / write instructions include write instructions, the first storage space includes multiple first storage units, and the second information is the address of the first storage unit for writing instruction information of the first thread.

17. The method according to claim 15, characterized in that, The read / write instructions include read instructions, and the first storage space includes a plurality of first storage units, the plurality of first storage units including information units that store instruction information of the first thread; The determination of the second information includes: If the information unit also stores the address of a related unit, it is determined that the second information is the address of the related unit, and the related unit is a first storage unit that stores instruction information of the thread bundle to which the first thread belongs; If the information unit does not store the address of the related unit, it is determined that the second information is blank.

18. The method according to claim 10 or 11, characterized in that, The second storage space includes a plurality of second storage units, each of which corresponds one-to-one with the plurality of thread bundles. The second storage unit is used to store the reference address of the corresponding thread bundle.

19. A chip, characterized in that, The chip includes the instruction information management system as described in any one of claims 1 to 9.

20. An electronic device, characterized in that, The electronic device includes the chip of claim 19.

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