FPGA dynamic reconfiguration method, reconfiguration controller, and FPGA dynamic reconfiguration system

Abstract

This application provides an FPGA dynamic reconfiguration method, a reconfiguration controller, and an FPGA dynamic reconfiguration system. The method is applied to a reconfiguration controller in an FPGA module, which includes a configuration memory area. The reconfiguration controller includes a fine-grained reconfiguration unit. The method includes: in fine-grained reconfiguration mode, the fine-grained reconfiguration unit reads configuration information of the logic unit to be configured from the configuration memory area and writes it to on-chip memory; during the process of writing the read configuration information to the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written to the on-chip memory; after all the configuration information of the logic unit to be configured has been written to the on-chip memory and the configuration information in the on-chip memory has been modified, the modified configuration information in the on-chip memory is written back to the configuration memory area. The above method can achieve efficient FPGA reconfiguration at the basic logic unit level.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an FPGA dynamic reconfiguration method, a reconfiguration controller, and an FPGA dynamic reconfiguration system. Background Technology

[0002] With the rapid development of embedded systems and reconfigurable computing technologies, FPGAs (Field Programmable Gate Arrays) are widely used in real-time systems, communications, image processing, and security encryption due to their reconfigurability and parallel processing capabilities. Partial reconfiguration (PR) technology allows for dynamic modification of a portion of the FPGA's logic function at runtime without interrupting the overall system operation, thereby significantly improving system flexibility and resource utilization.

[0003] A common FPGA dynamic reconfiguration scheme involves the host writing reconfiguration information to the FPGA's configuration memory via the FPGA's Internal Configuration Access Port (ICAP). However, this scheme only allows for module-level reconfiguration of the FPGA and cannot achieve fine-grained dynamic modification of basic logic units, thus limiting its application in high-frequency, fine-grained reconfiguration scenarios. Summary of the Invention

[0004] Based on the above-mentioned technical problems, this application provides an FPGA dynamic reconfiguration method, a reconfiguration controller, and an FPGA dynamic reconfiguration system, which can achieve efficient FPGA reconfiguration at the basic logic unit level.

[0005] The first aspect of this application provides an FPGA dynamic reconfiguration method, applied to a reconfiguration controller in an FPGA module. The FPGA module further includes a configuration storage area for storing FPGA configuration information. The reconfiguration controller includes a fine-grained reconfiguration unit. The method includes: In fine-grained reconfiguration mode, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory; wherein, the fine-grained reconfiguration mode is used to reconfigure the basic logic units of the FPGA; the on-chip memory includes at least two data ports that support bidirectional read and write operations; During the process of reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written into the on-chip memory. After writing all the configuration information of the logic unit to be configured into the on-chip memory and modifying the configuration information in the on-chip memory, the fine-grained reconfiguration unit writes the modified configuration information in the on-chip memory back to the configuration storage area.

[0006] In some implementations, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory, including: The fine-grained reconfiguration unit sequentially reads each configuration data frame of the logic unit to be configured from the configuration storage area, and writes the read configuration data frame to the position of the write pointer of the sliding window of the on-chip memory. Whenever a configuration data frame is written to the sliding window, the write pointer moves backward by one step. When it reaches the end of the sliding window, the write pointer automatically jumps to the beginning of the sliding window. The storage space of the sliding window of the on-chip memory is equal to the total number of configuration data frames of the logic unit to be configured, and the step size is the same as the length of one configuration data frame.

[0007] In some implementations, during the process of reading configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written into the on-chip memory, including: During the process of reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the fine-grained reconfiguration unit reads the configuration data frames sequentially from the beginning of the on-chip memory, modifies the read configuration data frames, and writes them back to the on-chip memory.

[0008] In some implementations, a valid flag bit and a modified flag bit are set at the storage location of each configuration data frame in the on-chip memory. After the fine-grained reconfiguration unit writes a configuration data frame completely into the on-chip memory, it sets the valid flag bit of the storage location where the configuration data frame is located to a valid state. Furthermore, after the fine-grained reconfiguration unit modifies a configuration data frame in the on-chip memory, it sets the modification flag bit of the storage location where the configuration data frame is located to an active state. After writing all the configuration information of the logic unit to be configured into the on-chip memory and modifying the configuration information in the on-chip memory, the fine-grained reconfiguration unit writes the modified configuration information in the on-chip memory back to the configuration storage area, including: When the valid flag and modified flag of each storage location within the same sliding window of the on-chip memory are both valid, the fine-grained reconfiguration unit writes all configuration data frames stored in the sliding window back to the configuration storage area.

[0009] In some implementations, the reconfiguration controller further includes a data cache unit and a memory configuration access port. The data cache unit and the fine-grained reconfiguration unit are respectively connected to the configuration storage area through the memory configuration access port. The data cache unit and the fine-grained reconfiguration unit are connected to the host through an XDMA channel and a PCIe link. The data caching unit is used to receive and cache module reconfiguration information sent by the host in module-level reconfiguration mode, and send the cached module reconfiguration information to the configuration storage area; the module-level reconfiguration mode is used to reconfigure the functional modules of the FPGA, and the functional modules include multiple basic logic units.

[0010] In some implementations, the reconfiguration controller further includes a task mode arbitration controller, used to determine whether the current reconfiguration mode is a fine-grained reconfiguration mode or a module-level reconfiguration mode based on the reconfiguration information sent by the host.

[0011] In some implementations, the reconfiguration controller further includes a clock management module for providing a clock signal for the memory configuration access port.

[0012] The task mode arbitration controller is also used for: If it is determined that the current reconfiguration mode is fine-grained reconfiguration mode, the clock management module is controlled to provide a clock signal of the first frequency to the memory configuration access port; or, If it is determined that the current reconfiguration mode is a module-level reconfiguration mode, the clock management module is controlled to provide a second frequency clock signal to the memory configuration access port; The second frequency is greater than the first frequency.

[0013] In some implementations, the task mode arbitration controller is further configured to: When it is detected that the reconfiguration mode has switched from the fine-grained reconfiguration mode to the module-level reconfiguration mode, or from the module-level reconfiguration mode to the fine-grained reconfiguration mode, the memory configuration access port is controlled to suspend data transmission operations, and the clock management module is controlled to switch to the clock frequency provided by the memory configuration access port. Upon receiving the clock latch signal output by the clock management module, the current reconfiguration mode is determined, and the memory configuration access port is controlled to perform data transmission operations; the clock latch signal indicates that the clock management module has completed clock frequency switching and can stably output clock signals.

[0014] In some implementations, the task mode arbitration controller determines whether the current reconfiguration mode is a fine-grained reconfiguration mode or a module-level reconfiguration mode based on the reconfiguration information sent by the host, including: The task mode arbitration controller determines whether the current reconfiguration mode is fine-grained reconfiguration mode or module-level reconfiguration mode based on the reconfiguration identifier written by the host to the reconfiguration controller. The value of the reconfiguration identifier is a first value, which indicates fine-grained reconfiguration mode, and the value of the reconfiguration identifier is a second value, which indicates module-level reconfiguration mode. or, The task mode arbitration controller determines the current reconfiguration mode as a module-level reconfiguration mode when it receives module reconfiguration information sent by the host through the AXI-Stream interface, or determines the current reconfiguration mode as a fine-grained reconfiguration mode when it receives a logic unit reconfiguration instruction sent by the host through the AXI-Lite interface.

[0015] A second aspect of this application provides a reconfiguration controller configured to implement the above-described FPGA dynamic reconfiguration method.

[0016] A third aspect of this application provides an FPGA dynamic reconfiguration system, the FPGA dynamic reconfiguration system including a host and an FPGA module, the FPGA module including a configuration storage area and the aforementioned reconfiguration controller.

[0017] The FPGA dynamic reconfiguration method provided in this application sets up a fine-grained reconfiguration unit in the reconfiguration controller, and the fine-grained reconfiguration unit has an on-chip memory inside. In fine-grained reconfiguration mode, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the FPGA's configuration memory area and writes the read configuration information into the on-chip memory. During the process of writing the configuration information into the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written into the on-chip memory. Finally, after all the configuration information of the logic unit to be configured has been written into the on-chip memory and the configuration information in the on-chip memory has been modified, the fine-grained reconfiguration unit writes the modified configuration information in the on-chip memory back to the configuration memory area.

[0018] In the above scheme, the fine-grained reconfiguration unit uses on-chip memory to read, modify, and write back the configuration information of the FPGA basic logic units stored in the FPGA configuration storage area, thereby realizing fine-grained dynamic modification of the FPGA basic logic units.

[0019] Furthermore, in the above scheme, the fine-grained reconfiguration unit modifies the configuration information while reading the configuration information of the logic unit to be configured from the configuration storage area into the on-chip memory. This processing method can improve the efficiency of fine-grained reconfiguration compared with the serial processing method of "read-modify-write back". Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of an FPGA dynamic reconfiguration system provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of another FPGA dynamic reconfiguration system provided in an embodiment of this application.

[0023] Figure 3 This is a flowchart illustrating an FPGA dynamic reconfiguration method provided in an embodiment of this application. Detailed Implementation

[0024] With the rapid development of embedded systems and reconfigurable computing technologies, FPGAs (Field Programmable Gate Arrays) are widely used in real-time systems, communications, image processing, and security encryption due to their reconfigurability and parallel processing capabilities. Partial reconfiguration (PR) technology allows for dynamic modification of a portion of the FPGA's logic function at runtime without interrupting the overall system operation, thereby significantly improving system flexibility and resource utilization.

[0025] Traditional FPGA dynamic reconfiguration schemes involve the host writing reconfiguration information to the FPGA's configuration memory via the FPGA's Internal Configuration Access Port (ICAP). This traditional reconfiguration method typically uses low-speed external memory (such as Flash) to store the reconfiguration information; that is, the reconfiguration information is written from the low-speed external memory to the FPGA's configuration memory via ICAP. However, the read speed of the low-speed external memory is much lower than the bandwidth of ICAP, resulting in a reconfiguration rate that is much lower than the theoretical bandwidth of ICAP, leading to low reconfiguration efficiency.

[0026] To address these issues, traditional solutions necessitate introducing an "intermediary"—preloading the reconfiguration bitstream from Flash into high-speed memory (such as DDR or BRAM). However, this immediately introduces new problems: the reconfiguration process is no longer instantaneous; it requires additional preparation time and necessitates allocating valuable DDR or BRAM space for the bitstream, with larger bitstreams requiring more space. Furthermore, in the aforementioned traditional reconfiguration scheme, data occupies the bus multiple times, from the Flash controller to DDR, from DDR to the reconfigured controller, and then to the ICAP port, severely impacting bus bandwidth.

[0027] Furthermore, the aforementioned reconfiguration scheme can only achieve module-level reconfiguration of the FPGA, and cannot achieve fine-grained dynamic modification of basic logic units, which limits its application in high-frequency, fine-grained reconfiguration scenarios.

[0028] Therefore, in FPGA dynamic reconfiguration scenarios, a reconfiguration scheme that can achieve both module-level reconfiguration and fine-grained reconfiguration is needed, and a faster configuration rate is required during module-level reconfiguration.

[0029] To address the aforementioned technical problems, this application provides a dynamic reconfiguration method for FPGAs. This method first enables fine-grained dynamic reconfiguration of basic logic units, and achieves more efficient fine-grained dynamic reconfiguration. Furthermore, the method provided in this application can also achieve faster and more efficient module-level dynamic reconfiguration.

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] This application first provides a reconfiguration controller that can be applied to an FPGA module to control the dynamic reconfiguration of the FPGA module.

[0032] Figure 1 A schematic diagram of an FPGA dynamic reconfiguration system is shown.

[0033] See Figure 1 As shown, the FPGA dynamic reconfiguration system includes a host and an FPGA module. The FPGA module includes a reconfiguration controller and a configuration storage area as provided in this embodiment. The configuration storage area stores the FPGA's configuration information. By modifying or reconfiguring the configuration information stored in this storage area, the FPGA can be reconfigured. The host is the one used to reconfigure the FPGA module; specifically, it can be a configuration server, such as an x86 server or a computer host.

[0034] exist Figure 2 The diagram shown illustrates the structure of the reconfiguration controller provided in the embodiment of the application within the FPGA dynamic reconfiguration system.

[0035] See Figure 2 As shown, the reconfiguration controller provided in this embodiment includes a fine-grained reconfiguration unit for reconfiguring basic logic units in an FPGA. Furthermore, this fine-grained reconfiguration unit is equipped with an on-chip memory for storing configuration information of the logic units. In this embodiment, the on-chip memory is a multi-port memory, and at least two data ports support bidirectional read / write operations, thereby enabling simultaneous read and write operations through different ports. For example, the on-chip memory can be a dual-port BRAM (Block RAM).

[0036] Based on the aforementioned reconfiguration controller, this application provides an FPGA dynamic reconfiguration method, see [link to relevant documentation]. Figure 3 As shown, the method includes: S101. In fine-grained reconfiguration mode, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory.

[0037] The fine-grained reconfiguration mode described above is a mode for reconfiguring the basic logic units of an FPGA. In this mode, reconfiguration of the basic logic units is achieved by modifying their truth lookup tables. Each logic unit's truth lookup table contains 64 bits of data, distributed across four adjacent configuration frames, approximately 404 bytes per frame, with only 16 bits in each frame related to the logic unit to be configured. Therefore, in fine-grained configuration mode, it is necessary to modify four consecutive configuration frames storing the configuration information of the logic unit to be configured in the configuration memory area.

[0038] The activation of the fine-grained configuration mode described above can be controlled by the host. For example, the host sends a logic unit reconfiguration command to the reconfiguration controller, carrying the physical location parameters to be configured and the opcode in the command. When the reconfiguration controller receives the logic unit reconfiguration command, it can activate the fine-grained configuration mode and control the fine-grained reconfiguration unit to start working.

[0039] When the fine-grained reconfiguration unit reconfigures the logic unit to be configured in fine-grained reconfiguration mode, it first reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory.

[0040] As described in the above embodiments, the configuration information corresponding to a logic unit is stored in four adjacent configuration frames. Therefore, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory. This can be done by sequentially reading each configuration frame storing the configuration information of the logic unit to be configured from the configuration storage area and sequentially writing the read configuration frames into the on-chip memory area.

[0041] In another embodiment, it is disclosed that the on-chip memory in the fine-grained reconfiguration unit adopts a sliding window data read / write method. The storage space of one sliding window is equal to the total number of configuration data frames of the logic unit to be configured, that is, the capacity of one sliding window is 4 configuration frames. Furthermore, multiple sliding windows can be set in the on-chip memory.

[0042] In each sliding window, data is written by sliding the write pointer. Initially, the write pointer is located at the beginning of the sliding window. When writing data to this sliding window, writing begins from the position of the write pointer. Each time a configuration data frame is written to the sliding window, the write pointer moves forward by one step. When it reaches the end of the sliding window, the write pointer automatically jumps back to the beginning of the sliding window. This one step is the same as the length of a configuration data frame for the logic unit to be configured.

[0043] In the manner described above, the fine-grained reconfiguration unit can sequentially read each configuration data frame of the logic unit to be configured from the configuration storage area and write the read configuration data frames to the position of the write pointer of the sliding window of the on-chip memory. As configuration data frames are continuously written and the write pointer is continuously shifted, when the fine-grained reconfiguration unit has finished reading all the configuration data frames of the logic unit to be configured, these data frames will also fill one sliding window of the on-chip memory.

[0044] S102. During the process of reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written into the on-chip memory.

[0045] During the process of the fine-grained reconfiguration unit reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the modification engine in the fine-grained reconfiguration unit simultaneously modifies the configuration information written into the on-chip memory.

[0046] For example, whenever the fine-grained reconfiguration unit finishes writing a configuration data frame to the on-chip memory, the modification engine has already begun modifying the configuration data frame that has been written according to the logic unit reconfiguration instructions during the process of reading and writing the next configuration data frame.

[0047] In this way, the fine-grained reconfiguration unit can perform configuration information modification operations on the configuration logic unit to be configured while reading the configuration information of the first configuration logic unit from the configuration storage area and writing it into the on-chip memory, so that the configuration data frame reading and modification operations are performed synchronously, realizing "reading and modifying simultaneously".

[0048] In another embodiment, it is disclosed that during the process of the fine-grained reconfiguration unit reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the modification engine in the fine-grained reconfiguration unit reads the configuration data frames sequentially from the beginning of the on-chip memory, modifies the read configuration data frames, and then writes them back to the on-chip memory.

[0049] The aforementioned modification engine is a functional unit located within the fine-grained reconfiguration unit, specifically designed to modify the configuration data frames of the logic units written to the on-chip memory.

[0050] In another embodiment, a valid flag and a dirty flag are set at the storage location of each configuration data frame in the on-chip memory. After the fine-grained reconfiguration unit writes a configuration data frame completely into the on-chip memory, it sets the valid flag bit of the storage location where the configuration data frame is located to a valid state. For example, setting the value of valid to 1 indicates that the configuration data frame has been written completely.

[0051] Furthermore, after the fine-grained reconfiguration unit completes the modification of a configuration data frame in the on-chip memory, it sets the modification flag "dirty" at the storage location of the configuration data frame to an active state, for example, by setting the value of "dirty" to 1, indicating that the modification of the configuration data frame has been completed.

[0052] The above method can accurately record the read and modification status of each configuration data frame of the logic unit to be configured.

[0053] S103. After writing all the configuration information of the logic unit to be configured into the on-chip memory and modifying the configuration information in the on-chip memory, the fine-grained reconfiguration unit writes the modified configuration information in the on-chip memory back to the configuration storage area.

[0054] Specifically, after the fine-grained reconfiguration unit writes all four consecutive configuration data frames containing the configuration information of the logic unit to be configured into the on-chip memory, and after the fine-grained reconfiguration unit completes the modification of the four configuration data frames, the fine-grained reconfiguration unit writes the modified four configuration data frames back into the configuration storage area of ​​the FPGA module, thereby completing the reconfiguration of the logic unit to be configured.

[0055] The fine-grained reconfiguration unit interacts with the configuration storage area of ​​the FPGA module through ICAP for data read and write.

[0056] Before writing the four modified configuration data frames back to the configuration storage area, according to the ICAP protocol requirements, a virtual frame needs to be inserted before the valid data frames to serve as the start of the write session. Therefore, when the fine-grained reconfiguration unit writes the four modified configuration data frames back to the configuration storage area, it is actually writing back one virtual frame and the four modified configuration data frames.

[0057] In some embodiments, a valid flag and a dirty flag are set at the storage location of each configuration data frame in the on-chip memory. After the fine-grained reconfiguration unit writes a configuration data frame completely into the on-chip memory, it sets the valid flag bit of the storage location where the configuration data frame is located to a valid state. For example, setting the value of valid to 1 indicates that the configuration data frame has been written completely.

[0058] Furthermore, after the fine-grained reconfiguration unit completes the modification of a configuration data frame in the on-chip memory, it sets the modification flag "dirty" at the storage location of the configuration data frame to an active state, for example, by setting the value of "dirty" to 1, indicating that the modification of the configuration data frame has been completed.

[0059] When the fine-grained reconfiguration unit detects that the valid flag and modification flag of each storage location in the same sliding window of the on-chip memory are both valid, it can determine that the modification operation of the four configuration data frames of the logic unit to be configured has been completed. At this time, the fine-grained reconfiguration unit writes all the configuration data frames stored in the sliding window back to the configuration storage area.

[0060] As described in the above embodiments, the FPGA dynamic reconfiguration method provided in this application includes a fine-grained reconfiguration unit within the reconfiguration controller, which contains an on-chip memory. In fine-grained reconfiguration mode, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the FPGA's configuration memory and writes the read configuration information into the on-chip memory. During the writing process, the fine-grained reconfiguration unit modifies the configuration information written to the on-chip memory. Finally, after all the configuration information of the logic unit to be configured has been written into the on-chip memory and the configuration information in the on-chip memory has been modified, the fine-grained reconfiguration unit writes the modified configuration information from the on-chip memory back to the configuration memory.

[0061] In the above scheme, the fine-grained reconfiguration unit uses on-chip memory to read, modify, and write back the configuration information of the FPGA basic logic units stored in the FPGA configuration storage area, thereby realizing fine-grained dynamic modification of the FPGA basic logic units.

[0062] Furthermore, in the above scheme, the fine-grained reconfiguration unit modifies the configuration information while reading the configuration information of the logic unit to be configured from the configuration storage area into the on-chip memory. This processing method can improve the efficiency of fine-grained reconfiguration compared with the serial processing method of "read-modify-write back".

[0063] Specifically, since the read and write operations on the configuration storage area of the FPGA are generally implemented through the ICAP port, and the ICAP port only supports a single read or write operation at any given time and cannot perform read and write operations in parallel. Moreover, according to the requirements of the ICAP protocol, a virtual frame needs to be inserted as the start of the write session before writing a data frame to the configuration storage area of the FPGA. According to the traditional fine-grained reconfiguration operation method, it is necessary to sequentially execute the sequential operations of "read 4 frames - modify - write 5 frames" through the ICAP port, and the reconfiguration time for a single logic unit takes approximately the transmission time of 9 data frames + the modification time.

[0064] However, by using the reconfiguration method provided in the embodiments of the present application, the modification operation of the configuration data frame can be performed during the process of reading the configuration data frame. Therefore, the time consumed for reading the configuration data frame overlaps with the time consumed for modifying the configuration data frame, which can save the total reconfiguration time.

[0065] Assume that the time consumed in the stage of reading the configuration data frame is T_read = N × T_frame, where T_frame is the transmission time of a single configuration data frame; the time consumed in the stage of writing back the configuration data frame is T_write = (N + 1) × T_frame, where the "+1" is due to the virtual frame requirement; the time consumed for modifying the configuration data frame is denoted as T_mod. Since the modification of the configuration frame can be parallel with the reading of the configuration frame, the total reconfiguration time for 4 configuration data frames within a sliding window is: T_window = max(T_read, T_mod) + T_write When only a single logic unit needs to be reconfigured, T_mod << T_read, and its overall time consumption is equivalent to the time consumption of traditional serial reconfiguration (about 9 frame read / write times). However, when there are modification requirements for multiple adjacent logic units within the same sliding window, the fine-grained reconfiguration unit can perform multiple modifications before a single write-back, but only needs to perform one read operation and one write operation, thereby significantly reducing the number of repeated read / write sessions. Compared with the traditional serial method of independently performing "4-frame read + 5-frame write" for each logic unit, for the modification of multiple adjacent logic units (multiple logic units whose configuration information is recorded on the same configuration frame). The solution of the embodiments of the present application can concentrate the modification of the configuration information of K logic units into one session, and the time consumption is approximately max(T_read, T_mod) + T_write, while the traditional serial reconfiguration scheme requires a time consumption of K × (T_read + T_write). When K is relatively large, an acceleration of several orders of magnitude can be obtained.

[0066] Continue to refer to Figure 2As shown, the reconfiguration controller also includes a data cache unit and a memory configuration access port (ICAP). The data cache unit and the fine-grained reconfiguration unit are connected to the configuration storage area via the ICAP. Furthermore, the data cache unit and the fine-grained reconfiguration unit are connected to the host via an XDMA (Xilinx DMA for PCI Express, an proprietary core provided by Xilinx that connects to the PCIe hard core on one end and user logic on the other. It implements complex PCIe endpoint functions and integrates a high-performance direct memory access engine responsible for directly transferring data between host memory and memory or user logic on the FPGA) channel and a PCIe link.

[0067] Based on the above-described reconfiguration controller structure, another embodiment discloses that the data cache unit in the reconfiguration controller can perform module-level reconfiguration operations on the FPGA.

[0068] In this embodiment, under the module-level reconfiguration mode, the data caching unit receives and caches the module reconfiguration information sent by the host, and sends the cached module reconfiguration information to the configuration storage area.

[0069] The module-level reconfiguration mode described above refers to the mode of reconfiguring the functional modules of an FPGA. A functional module of an FPGA can include multiple basic logic units. In module-level reconfiguration mode, since a functional module includes numerous basic logic units, the reconfiguration information of a module is typically written directly into the FPGA's configuration storage area, overwriting the original configuration information of that module. Therefore, this method involves a large amount of data transmission and requires a high reconfiguration data transmission rate.

[0070] The aforementioned data buffer unit employs an asynchronous FIFO data buffer structure. Its input is directly connected via an XDMA channel and a PCIe link, operating in the XDMA clock domain. Its output is connected to the configuration memory area of ​​the FPGA module via an ICAP port, operating in the ICAP clock domain. This data buffer unit serves as a buffer and rate adapter during cross-clock domain transmission, ensuring that data continuously written to the host side can be safely read on demand at the ICAP end.

[0071] Based on the reconfiguration controller structure provided in this embodiment, the host can directly write module-level reconfiguration data into the configuration storage area of ​​the FPGA module through the data buffer unit inside the reconfiguration controller via a high-speed PCIe interface. This is not limited by the read / write rate of external memory, nor does it require additional memory space or bus bandwidth, thereby improving the module-level reconfiguration rate and efficiency.

[0072] In another embodiment, such as Figure 2 As shown, a task-mode arbitration controller is also included within the reconfiguration controller. This controller determines whether the current reconfiguration mode is fine-grained or module-level based on the reconfiguration information sent by the host. Furthermore, the task-mode arbitration controller can trigger corresponding functional units to perform the appropriate reconfiguration operations based on the current reconfiguration mode. When the task-mode arbitration controller determines that the current reconfiguration mode is fine-grained, it triggers the fine-grained reconfiguration unit to start working to perform fine-grained reconfiguration of the FPGA. When the task-mode arbitration controller determines that the current reconfiguration mode is module-level, it triggers the data buffer unit to start working to perform module-level reconfiguration of the FPGA.

[0073] In some embodiments, the task mode arbitration controller determines whether the current reconfiguration mode is a fine-grained reconfiguration mode or a module-level reconfiguration mode based on the reconfiguration identifier written by the host to the reconfiguration controller. The value of the reconfiguration identifier is a first value, which indicates a fine-grained reconfiguration mode, and the value of the reconfiguration identifier is a second value, which indicates a module-level reconfiguration mode.

[0074] Specifically, the reconfiguration controller has registers that can be used to store reconfiguration identifiers written by the host.

[0075] When the host writes a reconfiguration flag start to the reconfiguration controller and it is 0, it indicates module-level reconfiguration mode. When the host writes a reconfiguration flag start to the reconfiguration controller and it is 1, it indicates fine-grained reconfiguration mode.

[0076] In other embodiments, the task mode arbitration controller determines the current reconfiguration mode as a module-level reconfiguration mode upon receiving module reconfiguration information sent by the host through the AXI-Stream interface, or determines the current reconfiguration mode as a fine-grained reconfiguration mode upon receiving a logic unit reconfiguration instruction sent by the host through the AXI-Lite interface.

[0077] Specifically, when the host sends module reconfiguration information to the reconfiguration controller, it sends it through the XDMA AXI-Stream interface. When the task mode arbitration controller recognizes that there is data being sent through the AXI-Stream interface, it can determine that it is currently in module-level reconfiguration mode.

[0078] When the host needs to reconfigure some basic logic units of the FPGA, it sends a logic unit reconfiguration command to the reconfiguration controller through the XDMA AXI-Lite interface. The logic unit reconfiguration command carries the configuration parameters and opcode of the logic unit to be configured.

[0079] When the task mode arbitration controller detects that data is being sent through the AXI-Lite interface, it can determine that it is currently in fine-grained reconfiguration mode.

[0080] See also Figure 2 As shown, a clock management module is also set up inside the reconfiguration controller to provide clock signals for the memory configuration access port ICAP.

[0081] In another embodiment, the task mode arbitration controller is further configured to control the clock management module to provide a clock signal of a first frequency to the memory configuration access port when it is determined that the current reconfiguration mode is a fine-grained reconfiguration mode. or, If the current reconfiguration mode is determined to be module-level reconfiguration mode, the control clock management module provides a second frequency clock signal to the memory configuration access port; The second frequency is greater than the first frequency.

[0082] In this embodiment, the task mode arbitration controller can control the clock management module to provide different frequency clock signals to the memory configuration access port according to different reconfiguration modes. Specifically, when the reconfiguration mode is a module-level reconfiguration mode, the clock management module provides a high-frequency clock signal to the memory configuration access port; when the reconfiguration mode is a fine-grained reconfiguration mode, the clock management module provides a low-frequency clock signal to the memory configuration access port. This clock frequency control method ensures that the clock signal frequency of the memory configuration access port matches the actual reconfiguration task mode, guarantees that the data transmission rate of the memory configuration access port matches the task requirements, and reduces clock power consumption.

[0083] The aforementioned clock management module includes a clock management unit and a configuration port. The task mode arbitration controller writes the clock frequency configuration information to be output to the clock management module through the configuration port, while the clock management unit adjusts and outputs the clock signal to the memory configuration access port based on the clock frequency configuration information received by the configuration port.

[0084] In another embodiment, when the task mode arbitration controller detects that it is currently in a certain reconfiguration mode, it sends a control signal to the clock management module to cause the clock management module to output a clock signal that matches the current reconfiguration mode. When the clock management module adjusts the frequency of the output clock signal according to the control signal sent by the task mode arbitration controller and the output clock signal frequency is stable, it outputs a clock latch signal to the task mode arbitration controller to inform the task mode arbitration controller that the clock signal frequency adjustment has been completed. At this point, the task mode arbitration controller truly determines the current reconfiguration mode and controls the corresponding functional units to perform the corresponding reconfiguration operations.

[0085] For example, when the task mode arbitration controller detects that it is currently in fine-grained reconfiguration mode, it sends a control signal to the clock management module to cause the clock management module to output a clock signal that matches the fine-grained reconfiguration mode. When the clock management module adjusts the frequency of the output clock signal according to the control signal sent by the task mode arbitration controller and the output clock signal frequency is stable, it outputs a clock latch signal to the task mode arbitration controller to inform it that the clock signal frequency adjustment has been completed. At this point, the task mode arbitration controller truly determines that it has entered the fine-grained reconfiguration mode and controls the fine-grained reconfiguration unit to perform the reconfiguration operation on the basic logic unit.

[0086] In other embodiments, it is disclosed that when the task mode arbitration controller detects a switch from module-level reconfiguration mode to fine-grained reconfiguration mode, it controls the memory configuration access port (ICAP) to suspend data transmission operations. Simultaneously, it controls the clock management module to switch to the clock frequency provided by the memory configuration access port; specifically, it controls the clock management module to reduce the clock frequency to meet the clock frequency requirements of fine-grained reconfiguration. Upon receiving a clock latch signal from the clock management module, the task mode arbitration controller determines that the current reconfiguration mode has successfully switched to fine-grained reconfiguration mode and controls the memory configuration access port to perform data transmission operations.

[0087] Specifically, under normal circumstances, the reconfiguration controller is in module-level reconfiguration mode by default. In this mode, the task mode arbitration controller controls the clock management module to provide a high-frequency clock signal (such as 300MHz-600MHz) to the memory configuration access port to meet the extreme throughput requirements.

[0088] If the task mode arbitration controller determines that the current reconfiguration mode has switched to fine-grained reconfiguration mode, it sends a low-frequency configuration command to the clock management module, causing the clock management module to downclock to a safe clock frequency, such as 100MHz, to ensure the timing reliability of the read-modify-write process.

[0089] During the above configuration process, the task mode arbitration controller first completes a handshake with the ICAP controller: notifying ICAP to pause the data path, and ICAP pulls the tready signal of the AXI-Stream interface low, causing the data buffer unit to stop outputting new data to ICAP, thereby freezing the data stream before the clock domain switch and ensuring that the existing data in the data buffer unit remains intact.

[0090] After a safe pause in the data path, the task-mode arbitration controller initiates a reconfiguration process for the clock management module, writing new frequency parameters to its internal configuration register via the module's configuration port. Once reconfigured and relocked, the clock management unit outputs a clock latch signal, indicating that the new frequency is stable and available. Subsequently, the clock management module provides the new clock signal to the ICAP port to ensure no clock glitches or missampling occur during the switching process. After the clock frequency switch is complete, the task-mode arbitration controller controls the ICAP memory configuration access port to resume data transmission, at which point fine-grained reconfiguration operations on the FPGA configuration memory area can be performed via ICAP.

[0091] Similarly, when the task mode arbitration controller detects a switch from fine-grained reconfiguration mode to module-level reconfiguration mode, it first controls the memory configuration access port (ICAP) to pause data transmission. Simultaneously, it controls the clock management module to switch to the clock frequency provided by the memory configuration access port; specifically, it controls the clock management module to increase the clock frequency to meet the clock frequency requirements of module-level reconfiguration. Upon receiving the clock latch signal from the clock management module, the task mode arbitration controller determines that the current reconfiguration mode has successfully switched to module-level reconfiguration mode and controls the memory configuration access port to execute data transmission operations. For a detailed explanation of this switching process, please refer to the above-described process for switching from module-level reconfiguration mode to fine-grained reconfiguration mode.

[0092] In other embodiments, when the reconfiguration mode switches from module-level reconfiguration mode to fine-grained reconfiguration mode, the module reconfiguration process stops only when ICAP detects a valid frame boundary flag, i.e., at the completion node of a data frame transmission. At this time, ICAP pulls the tready signal of the AXI-Stream interface low and stops the data buffer unit from outputting new data to ICAP. When the reconfiguration mode switches from fine-grained reconfiguration mode to module-level reconfiguration mode, the fine-grained reconfiguration mode stops only when both the fine-grained reconfiguration end flag and the clock latch signal are valid.

[0093] Another embodiment of this application also provides a reconfiguration controller, which can be used to control the reconfiguration process of an FPGA, for example... Figure 2 As shown, the reconfiguration controller can be set on the FPGA module and placed on the link between the host and the configuration storage area of ​​the FPGA module. This allows the reconfiguration controller to configure the configuration storage area of ​​the FPGA module based on the instructions and data sent by the host.

[0094] The structure of the reconfiguration controller provided in this embodiment can be found in [reference needed]. Figure 2The structure of the reconfiguration controller shown is not repeated here. This reconfiguration controller is configured to execute the FPGA dynamic reconfiguration method described in any of the above embodiments, and possesses the beneficial effects of executing the FPGA dynamic reconfiguration method described above.

[0095] The specific structure of the reconfiguration controller, the functions of each part, and the specific processing of the reconfiguration controller executing the FPGA dynamic reconfiguration method described in the above embodiments can all be found in the description of the above embodiments.

[0096] Based on the reconfiguration controller described above, another embodiment of this application provides an FPGA dynamic reconfiguration system, the structure of which can be found in [reference needed]. Figure 1 and Figure 2 As shown, the FPGA dynamic reconfiguration system includes a host and an FPGA module. The FPGA module is equipped with a configuration storage area and a reconfiguration controller provided in the above embodiment.

[0097] In the FPGA dynamic reconfiguration system provided in this embodiment, the FPGA dynamic reconfiguration method provided in any of the above embodiments of this application can be executed through the reconfiguration controller included therein, and it has the beneficial effect of executing the above FPGA dynamic reconfiguration method. For the specific processing of executing the above FPGA dynamic reconfiguration method in this system, please refer to the corresponding description of the above embodiments.

[0098] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0099] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0100] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0101] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0102] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0103] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0104] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0105] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0106] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0107] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0108] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for dynamic reconfiguration of an FPGA, characterized in that, The reconfiguration controller is applied to an FPGA module, and the FPGA module is further provided with a configuration storage area for storing configuration information of the FPGA; the reconfiguration controller comprises a fine-grained reconfiguration unit; The method comprises: In the fine-grained reconfiguration mode, the fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory; wherein the fine-grained reconfiguration mode is used to reconfigure the basic logic unit of the FPGA; and the on-chip memory comprises at least two data ports supporting bidirectional read and write operations; In the process of reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written into the on-chip memory; After the configuration information of the logic unit to be configured is completely written into the on-chip memory and the modification of the configuration information in the on-chip memory is completed, the fine-grained reconfiguration unit writes the modified configuration information in the on-chip memory back to the configuration storage area.

2. The method of claim 1, wherein, The fine-grained reconfiguration unit reads the configuration information of the logic unit to be configured from the configuration storage area and writes the read configuration information into the on-chip memory, comprising: The fine-grained reconfiguration unit sequentially reads each configuration data frame of the logic unit to be configured from the configuration storage area and writes the read configuration data frame into the position where the write pointer of the sliding window of the on-chip memory is located; Wherein, each time a configuration data frame is written into the sliding window, the write pointer is shifted backward by one step, and when it is shifted to the tail end of the sliding window, the write pointer automatically jumps to the starting end of the sliding window; the storage space of the sliding window of the on-chip memory is equal to the total number of configuration data frames of the logic unit to be configured, and the step length is equal to the length of one configuration data frame.

3. The method of claim 2, wherein, In the process of reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on-chip memory, the fine-grained reconfiguration unit modifies the configuration information written into the on-chip memory, comprising: In the process of reading the configuration information of the logic unit to be configured from the configuration storage area and writing the read configuration information into the on- chip memory, the fine-grained reconfiguration unit reads the configuration data frame from the starting end of the on-chip memory, modifies the read configuration data frame, and writes it back to the on-chip memory.

4. The method of claim 3, wherein, An effective flag bit and a modification flag bit are respectively arranged at the storage position of each configuration data frame in the on-chip memory; After the fine-grained reconfiguration unit writes a configuration data frame into the on-chip memory completely, the effective flag bit of the storage position of the configuration data frame is set to an effective state; And after the fine-grained reconfiguration unit modifies a configuration data frame in the on-chip memory completely, the modification flag bit of the storage position of the configuration data frame is set to an effective state; After the configuration information of the logic units to be configured is written into the on-chip memory completely and the modification of the configuration information in the on-chip memory is completed, the fine-grained reconfiguration unit writes the modified configuration information in the on-chip memory back to the configuration storage area, including: In the case where the valid flag and the modification flag of each storage location in the same sliding window of the on-chip memory are both in the valid state, the fine-grained reconfiguration unit writes all the configuration data frames stored in the sliding window back to the configuration storage area.

5. The method according to any one of claims 1 to 4, characterized in that, The reconfiguration controller further comprises a data cache unit and a memory configuration access port, the data cache unit and the fine-grained reconfiguration unit are connected with the configuration storage area through the memory configuration access port, and the data cache unit and the fine-grained reconfiguration unit are connected with the host through an XDMA channel and a PCIe link. The data cache unit is configured to, in a module-level reconfiguration mode, receive and cache module reconfiguration information sent by the host, and send the cached module reconfiguration information to the configuration storage area; the module-level reconfiguration mode is used for reconfiguring functional modules of the FPGA, and the functional modules comprise a plurality of basic logic units.

6. The method of claim 5, wherein, The reconfiguration controller further comprises a task mode arbitration controller configured to determine, based on the reconfiguration information sent by the host, whether the current reconfiguration mode is the fine-grained reconfiguration mode or the module-level reconfiguration mode.

7. The method of claim 6, wherein, The reconfiguration controller further comprises a clock management module configured to provide a clock signal for the memory configuration access port. The task mode arbitration controller is further configured to: In the case where it is determined that the current reconfiguration mode is the fine-grained reconfiguration mode, control the clock management module to provide a clock signal of a first frequency for the memory configuration access port. Or, In the case where it is determined that the current reconfiguration mode is the module-level reconfiguration mode, control the clock management module to provide a clock signal of a second frequency for the memory configuration access port. The second frequency is greater than the first frequency.

8. The method of claim 7, wherein, The task mode arbitration controller is further configured to: In the case where it is detected that the reconfiguration mode is switched from the fine-grained reconfiguration mode to the module-level reconfiguration mode or from the module-level reconfiguration mode to the fine-grained reconfiguration mode, control the memory configuration access port to suspend the data transmission operation and control the clock management module to switch the clock frequency provided for the memory configuration access port; In the case where a clock latch signal output by the clock management module is received, determine the current reconfiguration mode and control the memory configuration access port to perform the data transmission operation; the clock latch signal indicates that the clock management module completes the clock frequency switching and can stably output the clock signal.

9. The method of claim 6, wherein, The task mode arbitration controller determines, based on the reconfiguration information sent by the host, whether the current reconfiguration mode is the fine-grained reconfiguration mode or the module-level reconfiguration mode, including: The task mode arbitration controller determines whether the current reconfiguration mode is fine-grained reconfiguration mode or module-level reconfiguration mode based on the reconfiguration identifier written by the host to the reconfiguration controller. The value of the reconfiguration identifier is a first value, which indicates fine-grained reconfiguration mode, and the value of the reconfiguration identifier is a second value, which indicates module-level reconfiguration mode. or, The task mode arbitration controller determines the current reconfiguration mode as a module-level reconfiguration mode when it receives module reconfiguration information sent by the host through the AXI-Stream interface, or determines the current reconfiguration mode as a fine-grained reconfiguration mode when it receives a logic unit reconfiguration instruction sent by the host through the AXI-Lite interface.

10. A reconfiguration controller, characterized by The reconfiguration controller is configured to implement the FPGA dynamic reconfiguration method as described in any one of claims 1 to 9.

11. An FPGA dynamic reconfiguration system, the FPGA dynamic reconfiguration system comprising a host and an FPGA module, the FPGA module comprising a configuration storage area and a reconfiguration controller as described in claim 10.

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