Overcurrent protection circuit for testing power device

Abstract

The invention discloses an overcurrent protection circuit for power device testing, which belongs to the technical field of power device testing, is integrally mounted in a testing main loop between a testing power supply and a tested device, and comprises a current detection circuit, a desaturation voltage detection circuit and a logic judgment and driving circuit which are connected in sequence, the current detection circuit and the desaturation voltage detection circuit are connected in series through an MOS switch tube Q1; after the current detection circuit executes, the desaturation voltage detection circuit is started; and the desaturation voltage detection circuit and the logic judgment and driving circuit are connected in series through an AND gate chip AND1, and are used for changing the output of the logic judgment and driving circuit after execution of the desaturation voltage detection circuit. According to the invention, a triple cooperative overcurrent protection architecture is constructed, and the system safety and the test efficiency of the electrical test of the power device are comprehensively improved.

Description

Technical Field

[0001] This invention belongs to the field of power device testing technology, and specifically relates to an overcurrent protection circuit for power device testing. Background Technology

[0002] Electrical testing is a crucial part of all performance testing for power devices. It primarily examines key parameters such as the device's blocking, conducting, and switching characteristics. During testing, the Device Under Test (DUT) is subjected to large current surges, making it prone to overcurrent faults. If the test equipment fails to provide timely protection, it can lead to DUT burnout, equipment damage, invalid test data, and even personal injury accidents. Therefore, overcurrent protection is one of the core technologies for ensuring test safety and valid test data in power device electrical testing equipment.

[0003] Currently, overcurrent protection technologies used in the industry for electrical testing of power devices generally adopt a single protection method. Common protection technology solutions are as follows:

[0004] Option 1: Current Detection and Protection Scheme. This scheme uses a sampling resistor or Hall effect current sensor connected in series in the test circuit to monitor the test current in real time. The sampled current signal is transmitted to the protection circuit, which has a preset overcurrent protection limit. By comparing the sampled current signal with the preset limit, when the sampled current exceeds the preset limit, the protection action is triggered, cutting off the control signal of the device under test, thus achieving overcurrent protection.

[0005] Option 2: Protection scheme based on desaturation detection. This type of scheme detects the collector-emitter voltage (V) of the device under test (e.g., IGBT device). CE The change in V indicates whether the IGBT device is in an overcurrent state; when an overcurrent fault occurs, the IGBT enters a desaturation state, and V... CE The voltage will rise sharply, and the protection circuit will detect V. CE When the preset desaturation limit is exceeded, protection is immediately triggered to shut down the device under test and prevent overcurrent damage.

[0006] The two existing overcurrent protection schemes mentioned above have the following obvious defects and shortcomings in practical applications: they are prone to protection failure or false triggering, and are difficult to meet the high reliability testing requirements of devices:

[0007] When using Scheme 1 (current detection protection), ordinary sampling resistors have high bandwidth, but they are prone to interference and drift during signal transmission. Hall current sensors have limited measurement bandwidth and are also prone to interference and drift, resulting in sampling delay and insufficient accuracy. This leads to delayed protection response and inability to block rapid overcurrent faults in a timely manner.

[0008] When using Scheme 2 (desaturation protection), the high-frequency switching action during electrical testing will generate a large number of interference signals, which may lead to false detection by the protection circuit and false triggering of protection, interrupting the normal test process and affecting test efficiency. In addition, desaturation detection requires setting a blanking time, which will also prolong the protection action time and may damage the device.

[0009] In addition, both existing solutions use the method of shutting off the control signal of the device under test to achieve protection. However, in the case of overcurrent, although the rapid shutdown of the power device avoids overcurrent failure, it is very easy to cause secondary breakdown failure of the device, which weakens the effectiveness of the protection circuit. Summary of the Invention

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0011] An overcurrent protection circuit for power device testing is integrated into the main test circuit between the test power supply and the device under test. It includes a current detection circuit, a desaturation voltage detection circuit, and a logic determination and drive circuit connected in sequence. The current detection circuit and the desaturation voltage detection circuit are connected in series via a MOS switch Q1. The desaturation voltage detection circuit is activated after the current detection circuit is executed. The desaturation voltage detection circuit and the logic determination and drive circuit are connected in series via an AND gate chip AND1, which is used to change the output of the logic determination and drive circuit after the desaturation voltage detection circuit is executed.

[0012] The present invention has the following beneficial effects:

[0013] This invention constructs a triple-coordinated overcurrent protection architecture by combining a dual judgment mechanism of current detection and desaturation voltage detection, and linking it with the fast cut-off unit (logic judgment and drive circuit) of the main power circuit. This not only effectively improves the effect of current detection and increases the sampling bandwidth and accuracy, but also effectively filters out false triggering of desaturation detection caused by high-frequency interference, achieving highly accurate microsecond-level response. Furthermore, it eliminates secondary shutdown failure of the device under test at the physical level, thereby comprehensively improving the system safety and testing efficiency of power device electrical testing. Attached Figure Description

[0014] Figure 1 This is a functional schematic diagram of an overcurrent protection circuit for power device testing provided in an embodiment of the present invention, wherein AA node and BB node are shown.

[0015] Figure 2 The structural diagram of the overcurrent protection circuit for power device testing provided in the embodiment of the present invention includes nodes AA, BB, CC, and DD.

[0016] Figure 3This is a structural diagram of the current detection circuit provided in an embodiment of the present invention, wherein AA node, BB node, and CC node are shown.

[0017] Figure 4 This is a structural diagram of the desaturation voltage detection circuit provided in an embodiment of the present invention, wherein AA node, BB node, CC node, and DD node are shown.

[0018] Figure 5 The diagram shows the structure of the logic determination and driving circuit provided in the embodiment of the present invention, wherein there are nodes AA, BB, and DD. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0020] This invention addresses the shortcomings of existing overcurrent protection methods, such as their simplistic approach, susceptibility to misjudgment, significant response delays, and high risk of shutdown failure. It proposes a novel overcurrent protection circuit for power device testing. This circuit achieves more accurate and faster overcurrent protection by combining a triple protection mechanism of current detection, desaturation detection, and rapid main circuit disconnection, thereby improving the safety and efficiency of electrical testing.

[0021] To achieve the above objectives, this invention introduces an overcurrent protection circuit integrating a broadband pulse current transformer (CT) into the electrical test circuit. This circuit is connected in series in the main test circuit and triggers protection through a dual mechanism combining current detection and desaturation voltage detection. This invention reduces false triggering due to simple current threshold judgment. By combining desaturation detection logic, it ensures that protection action is only initiated after double confirmation of overcurrent and desaturation of the switching device. Moreover, unlike traditional protection schemes that shut down the device under test, the protection action of this invention directly cuts off the test circuit, which can significantly reduce the risk of overcurrent and overvoltage failure of the device under test.

[0022] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0023] like Figure 1 As shown, the overcurrent protection circuit for power device testing in this embodiment of the invention is integrated into the main test circuit between the test power supply and the device under test, and includes a current detection circuit, a desaturation voltage detection circuit, a logic determination and driving circuit connected in sequence. Figure 1As shown, the current detection circuit and the desaturation voltage detection circuit are connected in series through the MOS switch Q1. After the current detection circuit is executed, the desaturation voltage detection circuit is started. The desaturation voltage detection circuit and the logic determination and driving circuit are connected in series through the AND gate chip AND1, which is used to change the output of the logic determination and driving circuit after the desaturation voltage detection circuit is executed.

[0024] Unlike existing methods that simply use sampling resistors or Rogowski coils, the current detection circuit of this invention uses a broadband pulse current transformer (CT) for sampling, resulting in higher bandwidth, less waveform drift, and no impact on the main circuit. The subsequent circuit consists of a unique sequential structure of a voltage follower-comparator-D latch, which can be reused in this circuit or other circuits. Unlike existing desaturation circuits, the desaturation voltage detection circuit of this invention does not require an external power supply or blanking capacitor, simplifying the circuit and accelerating the detection time. The logic determination and driving circuit of this invention works in conjunction with the current detection circuit and the desaturation voltage detection circuit, forming a triple-coordinated overcurrent protection architecture. This effectively improves the current detection performance, increases sampling bandwidth and accuracy, and effectively filters out false triggering of desaturation detection caused by high-frequency interference.

[0025] Overcurrent protection circuit for power device testing, such as Figure 2 As shown, it includes a broadband pulse current transformer CT, first to eleventh resistors R0 to R10, first TVS Zener diode Z1, second TVS Zener diode Z2, diode D1, MOS switch Q1, first high-speed operational amplifier Amp1, second high-speed operational amplifier Amp2, first high-speed comparator Cmp1, second high-speed comparator Cmp2, first D-type latch DL1, second D-type latch DL2, AND gate chip AND1, driver chip U1, main switch T1, and first reference voltage source Vcmp1 and second reference voltage source Vcmp2.

[0026] The working principle of the overcurrent protection circuit for power device testing is as follows: the broadband pulse current transformer (CT) acquires and tests the main circuit current I in real time. C The sampled signal, after attenuation and voltage regulation, is buffered by the first high-speed operational amplifier Amp1, and then compared with the first reference voltage source Vcmp1 by the first high-speed comparator Cmp1. The first TVS regulator Z1 is used to maintain the input voltage of Amp1 between ±10V to prevent damage to the first high-speed operational amplifier Amp1 due to excessive voltage. When the test main circuit current exceeds the preset overcurrent threshold, the first high-speed comparator Cmp1 outputs a high level, the first D-type latch DL1 latches the trigger signal and outputs a low level signal, which drives the MOS switch Q1 to turn off through R4, thereby controlling the collector-emitter voltage Vcmp1 of the main switch T1. CE The sampling point is clamped; at this time, the voltage divider network of the sixth resistor R5 and the seventh resistor R6 begins to clamp V.CE Sampling is performed, and the sampled voltage is buffered by the second high-speed operational amplifier Amp2 and then compared with the second reference voltage source Vcmp2 by the second high-speed comparator Cmp2. Simultaneously, if the main circuit current exceeds the preset overcurrent threshold, and Vcmp2... CE When the desaturation threshold is exceeded, the second high-speed comparator Cmp2 outputs a high level, the second D-type latch DL2 latches the confirmation signal and outputs an inverted low level, and the AND gate chip AND1 outputs a low-level turn-off signal. This signal, via the driver chip U1 and the eleventh resistor R10, drives the main switch T1 to turn off rapidly, cutting off the main power path between the test main circuit and the device under test (DUT). This achieves nanosecond-level protection for both the DUT and the main switch T1 driven by this protection circuit, independent of the protection circuit (simultaneously protecting both devices to prevent test failure or switch malfunction). The second TVS regulator Z2 is used to maintain the drive signal between ±20V. Only overcurrent is detected, and V... CE When the desaturation threshold is not exceeded, the AND gate chip AND1 does not output a shutdown signal, and the driver chip U1 maintains normal driving state, which is regarded as noise interference and does not trigger the protection action, effectively avoiding false triggering.

[0027] like Figure 3 As shown, the current detection circuit in this embodiment includes a sampling and attenuation voltage regulation network, a first-stage voltage follower network, an overcurrent voltage comparison network, and a first latch network connected in sequence, used to collect the test main circuit current and perform preliminary overcurrent judgment.

[0028] The sampling and attenuation voltage regulation network includes a broadband pulse current transformer (CT), a first TVS diode (Z1), and a first resistor (R0). The first terminal of the first TVS diode (Z1) is connected to the positive terminal of the broadband pulse current transformer (CT), and the second terminal is connected to the negative terminal of the broadband pulse current transformer (CT). The first TVS diode (Z1) and the first resistor (R0) are connected in parallel, and the negative terminal of the broadband pulse current transformer (CT) is grounded.

[0029] The first-stage voltage follower network includes a first high-speed operational amplifier Amp1, a second resistor R1, and a third resistor R2. The first terminal of the second resistor R1 is connected to the non-inverting input of the first high-speed operational amplifier Amp1, and the second terminal is connected to the first terminal of the first resistor R0. The first terminal of the third resistor R2 is connected to the output of the first high-speed operational amplifier Amp1, and the second terminal is connected to the inverting input of the first high-speed operational amplifier Amp1, with R1 = R2. This first-stage voltage follower network acts as a voltage follower, achieving impedance matching, eliminating the load effect of subsequent circuits, enabling distortion-free signal buffered transmission, suppressing interference coupling, and improving the circuit's anti-interference capability.

[0030] The overcurrent voltage comparison network includes a first high-speed comparator Cmp1, a first reference voltage source Vcmp1, and a fourth resistor R3. The first terminal of the fourth resistor R3 is connected to the non-inverting input of the first high-speed comparator Cmp1, and the second terminal is connected to the output of the first high-speed operational amplifier Amp1. The inverting input of the first high-speed comparator Cmp1 is connected to the first reference voltage source Vcmp1.

[0031] The first latch network includes a first D-type latch DL1, and the clock / enable terminal CLK of the first D-type latch DL1 is connected to the output terminal of the first high-speed comparator Cmp1.

[0032] The working principle of the current detection circuit is as follows: The broadband pulse current transformer CT connected in series in the main test circuit first converts the large current on the bus into a small-range sampling current. The sampling resistor in the sampling and attenuation voltage regulation network: The first resistor R0 linearly converts the sampling current into a voltage signal U1. The first TVS voltage regulator Z1 connected in parallel with the first resistor R0 simultaneously regulates and limits the voltage signal U1, suppresses transient spike interference, and outputs a stable sampling voltage U2. The sampling voltage U2 is input to the first-stage voltage follower network to achieve impedance matching with high input impedance and low output impedance, and outputs a buffered sampling voltage. The buffered sampling voltage is current-limited by the fourth resistor R3 and then sent to the first high-speed comparator Cmp1 of the overcurrent voltage comparison network. It is compared in real time with the overcurrent threshold reference voltage provided by the first reference voltage source Vcmp1 preset at the inverting input terminal of the first high-speed comparator Cmp1, thus completing the conversion of the analog voltage signal to a digital high and low level signal. When the main circuit current is overcurrent, a high-level trigger signal is output; when the current is normal, a low-level standby signal is output. The output high-level trigger signal or low-level standby signal is finally input to the first D-type latch DL1 of the first latch network. Its clock / enable terminal CLK is connected to the output terminal of the first high-speed comparator Cmp1. When a high-level trigger signal is detected, the first D-type latch DL1 latches the signal and continuously outputs an inverted low-level trigger signal, providing a stable low-level trigger signal for the subsequent desaturation voltage detection circuit. At the same time, it effectively avoids signal loss caused by transient interference and ensures the reliability of the overcurrent trigger signal.

[0033] like Figure 4 As shown, the desaturation voltage detection circuit in this embodiment includes a switch and voltage divider sampling network, a second-stage voltage follower network, a desaturation voltage comparison network, and a second latch network connected in sequence. It is used to acquire the collector-emitter voltage V of the main switch transistor T1 after current detection triggering. CE And perform a desaturation determination.

[0034] The switching and voltage divider sampling network includes a fifth resistor R4, a sixth resistor R5, a seventh resistor R6, a MOS switch Q1, and a main switch T1. The first terminal of the fifth resistor R4 is connected to the inverted code output terminal of the first D-type latch DL1, and the second terminal is connected to the gate of the MOS switch Q1; the first terminal of the sixth resistor R5 is connected to the collector of the main switch T1, and the second terminal is connected to the drain of the MOS switch Q1; the two terminals of the seventh resistor R6 are connected to the drain and source of the MOS switch Q1, respectively, and the source of the MOS switch Q1 is connected to the emitter of the main switch T1.

[0035] The second-stage voltage follower network includes diode D1, eighth resistor R7, ninth resistor R8, and second high-speed operational amplifier Amp2. Diode D1's first terminal is connected to the drain of MOSFET Q1, and its second terminal is connected to the first terminal of eighth resistor R7. The second terminal of eighth resistor R7 is connected to the non-inverting input of second high-speed operational amplifier Amp2. Ninth resistor R8 connects the inverting input and output of second high-speed operational amplifier Amp2, and R7 = R8.

[0036] The desaturation voltage comparator network includes a second high-speed comparator Cmp2, a second reference voltage source Vcmp2, ​​and a tenth resistor R9. The first terminal of the tenth resistor R9 is connected to the non-inverting input of the second high-speed comparator Cmp2, and the second terminal is connected to the output of the second high-speed operational amplifier Amp2. The inverting input of the second high-speed comparator Cmp2 is connected to the second reference voltage source Vcmp2.

[0037] The second latch network includes a second D-type latch DL2, whose clock / enable terminal CLK is connected to the output of the second high-speed comparator Cmp2.

[0038] The desaturation voltage detection circuit works as follows: During normal testing, the first D-type latch DL1 outputs a high level, turning on the MOS switch Q1 and pulling down the voltage divider sampling point potential to avoid false sampling; when the current detection circuit determines overcurrent, the first D-type latch DL1 outputs a low level, causing the MOS switch Q1 to quickly turn off, and then activates the voltage divider network formed by the sixth resistor R5 and the seventh resistor R6 to reduce the collector-emitter voltage V of the main switch T1. CE The low-voltage sampling signal is converted to a fixed ratio to adapt to the second-stage voltage follower network. Diode D1 simultaneously provides unidirectional limiting protection for this low-voltage sampling signal; the collector-emitter voltage V... CE After the low-voltage sampling signal is input into the second-stage voltage follower network, it achieves equal-amplitude, in-phase, distortion-free buffered transmission of the signal, and outputs a stable V. CEThe buffered sampling voltage is current-limited by the tenth resistor R9 and then fed into the desaturation voltage comparison network. The second high-speed comparator Cmp2 compares it with the preset desaturation threshold reference voltage provided by the second reference voltage source Vcmp2 at the inverting input terminal in real time, completing the conversion of the analog voltage signal to a digital high and low level signal. If Vcmp2 is the reference voltage, the signal is converted to a digital high and low level signal. CE If the sampled voltage exceeds the preset desaturation threshold reference voltage, it is determined that the main switch T1 has desaturated overcurrent, and the second high-speed comparator Cmp2 outputs a high-level signal. If it does not exceed the preset desaturation threshold reference voltage, it is determined to be an interference signal and outputs a low-level signal. The level signal output by the second high-speed comparator Cmp2 is finally input to the second D-type latch DL2 of the second latch network. The second D-type latch DL2 latches the valid high-level desaturation confirmation signal and continuously outputs an inverted low-level trigger signal. If the inverted output terminal of the second D-type latch DL2 is high, it means that there is no latch signal output and subsequent protection actions are not triggered.

[0039] like Figure 5 As shown, the logic determination and driving circuit of this embodiment includes an interconnected logic determination network and a driving enable signal output network, which is used to ensure that the original driving logic remains unchanged when the second latch network does not output a low-level trigger signal, and to constantly output a low-level driving signal when the second latch network outputs a low-level trigger signal, thereby turning off the main switch T1.

[0040] The logic decision network includes an AND gate chip AND1 and a drive signal source. The first input terminal of the AND gate chip AND1 is connected to the inverse code output terminal of the second D-type latch DL2, and the second input terminal is connected to the drive signal source.

[0041] The drive enable signal output network includes a driver chip U1, an eleventh resistor R10, and a second TVS regulator Z2. The enable pin of the driver chip U1 is connected to the output of the AND gate chip AND1. The output of the driver chip U1 is connected to the first terminal of the eleventh resistor R10, and the second terminal of the eleventh resistor R10 is connected to the gate of the main switch T1. The first terminal of the second TVS regulator Z2 is connected to the second terminal of R10, and the second terminal is connected to the emitter of the main switch T1. When the driver chip U1 receives the trigger signal from the previous stage, it issues a turn-off signal to turn off the main switch T1.

[0042] The working principle of the logic judgment and drive circuit is as follows: When the current stage circuit does not detect an overcurrent signal, the second D-type latch DL2 continuously outputs a high-level signal. At this time, the AND gate chip AND1 outputs a signal that completely follows the initial drive signal to achieve normal drive control. When the current stage circuit detects an overcurrent signal, the second D-type latch DL2 starts to output a low-level signal. At this time, regardless of whether the original drive signal is high or low, a low-level signal is output, thereby turning off the main switch T1, cutting off the electrical connection between the power supply and the device under test on the main circuit of the bus, and realizing the overcurrent protection function.

[0043] Figures 1 to 5 Nodes A, B, C, and D in the diagram are auxiliary markers describing the circuit connections. Identical nodes in different diagrams are connected together, and further details will not be elaborated here.

[0044] In this embodiment of the invention, the Chinese definitions of the devices are as follows: MOS - Metal-Oxide-Semiconductor Field-Effect Transistor; IGBT - Insulated Gate Bipolar Transistor; TVS - Transient Voltage Suppressor Diode; D-type latch is a basic storage unit of digital logic circuit, where D represents data. It is used to latch and hold the instantaneous data value at the input terminal to the output terminal under the control of a clock or enable signal until the next control signal arrives. It is often used for temporary data storage and synchronization; CT - Current Transformer.

[0045] The above description is merely an embodiment of the present invention and does not limit the scope of the invention. Any equivalent structural or procedural transformations made based on the description and drawings of this invention, or direct or indirect applications in other related system fields, are similarly included within the protection scope of this invention. Contents not described in detail in this specification are prior art known to those skilled in the art.

Claims

1. An overcurrent protection circuit for testing power devices, characterized in that, Integrated into the main test circuit between the test power supply and the device under test, it includes a current detection circuit, a desaturation voltage detection circuit, and a logic determination and drive circuit connected in sequence. The current detection circuit and the desaturation voltage detection circuit are connected in series through a MOS switch Q1. The desaturation voltage detection circuit is started after the current detection circuit is executed. The desaturation voltage detection circuit and the logic determination and drive circuit are connected in series through an AND gate chip AND1, which is used to change the output of the logic determination and drive circuit after the desaturation voltage detection circuit is executed.

2. The overcurrent protection circuit for power device testing according to claim 1, characterized in that, The current detection circuit includes a sampling and attenuation voltage regulation network, a first-stage voltage follower network, an overcurrent voltage comparison network, and a first latch network connected in sequence, which are used to collect the test main circuit current and make a preliminary overcurrent judgment.

3. The overcurrent protection circuit for power device testing according to claim 2, characterized in that, The sampling and attenuation voltage regulation network includes a broadband pulse current transformer CT, a first TVS Zener diode Z1, and a first resistor R0. The first terminal of the first TVS Zener diode Z1 is connected to the positive terminal of the broadband pulse current transformer CT, and the second terminal is connected to the negative terminal of the broadband pulse current transformer CT. The first TVS Zener diode Z1 and the first resistor R0 are connected in parallel, and the negative terminal of the broadband pulse current transformer CT is grounded. The first-stage voltage follower network includes a first high-speed operational amplifier Amp1, a second resistor R1, and a third resistor R2. The first terminal of the second resistor R1 is connected to the non-inverting input terminal of the first high-speed operational amplifier Amp1, and the second terminal is connected to the first terminal of the first resistor R0. The first terminal of the third resistor R2 is connected to the output terminal of the first high-speed operational amplifier Amp1, and the second terminal is connected to the inverting input terminal of the first high-speed operational amplifier Amp1. The first-stage voltage follower network is used as a voltage follower. The overcurrent voltage comparison network includes a first high-speed comparator Cmp1, a first reference voltage source Vcmp1, and a fourth resistor R3; the first end of the fourth resistor R3 is connected to the non-inverting input of the first high-speed comparator Cmp1, the second end is connected to the output of the first high-speed operational amplifier Amp1, and the inverting input of the first high-speed comparator Cmp1 is connected to the first reference voltage source Vcmp1. The first latch network includes a first D-type latch DL1, and the clock / enable terminal CLK of the first D-type latch DL1 is connected to the output terminal of the first high-speed comparator Cmp1.

4. The overcurrent protection circuit for power device testing according to claim 3, characterized in that, R1=R2.

5. The overcurrent protection circuit for power device testing according to claim 1, characterized in that, The desaturation voltage detection circuit includes a switch and voltage divider sampling network, a second-stage voltage follower network, a desaturation voltage comparison network, and a second latch network connected in sequence. It is used to acquire the collector-emitter voltage V of the main switch transistor T1 after current detection triggering. CE And perform a desaturation determination.

6. The overcurrent protection circuit for power device testing according to claim 5, characterized in that, The switching and voltage divider sampling network includes a fifth resistor R4, a sixth resistor R5, a seventh resistor R6, a MOS switch Q1, and a main switch T1. The first end of the fifth resistor R4 is connected to the inverted code output terminal of the first D-type latch DL1, and the second end is connected to the gate of the MOS switch Q1. The first end of the sixth resistor R5 is connected to the collector of the main switch T1, and the second end is connected to the drain of the MOS switch Q1. The two ends of the seventh resistor R6 are connected to the drain and source of the MOS switch Q1, respectively, and the source of the MOS switch Q1 is connected to the emitter of the main switch T1. The second-stage voltage follower network includes diode D1, eighth resistor R7, ninth resistor R8, and second high-speed operational amplifier Amp2; the first terminal of diode D1 is connected to the drain of MOS switch Q1, and the second terminal is connected to the first terminal of eighth resistor R7. The second terminal of eighth resistor R7 is connected to the non-inverting input terminal of second high-speed operational amplifier Amp2. Ninth resistor R8 is connected to the inverting input terminal and the output terminal of second high-speed operational amplifier Amp2. The desaturation voltage comparison network includes a second high-speed comparator Cmp2, a second reference voltage source Vcmp2, ​​and a tenth resistor R9; the first terminal of the tenth resistor R9 is connected to the non-inverting input terminal of the second high-speed comparator Cmp2, the second terminal is connected to the output terminal of the second high-speed operational amplifier Amp2, and the inverting input terminal of the second high-speed comparator Cmp2 is connected to the second reference voltage source Vcmp2. The second latch network includes a second D-type latch DL2, whose clock / enable terminal CLK is connected to the output of the second high-speed comparator Cmp2.

7. The overcurrent protection circuit for power device testing according to claim 6, characterized in that, R7=R8.

8. The overcurrent protection circuit for power device testing according to claim 1, characterized in that, The logic determination and driving circuit includes an interconnected logic determination network and a driving enable signal output network, which are used to ensure that the original driving logic remains unchanged when the second latch network does not output a low-level trigger signal, and to output a low-level driving signal constantly when the second latch network outputs a low-level trigger signal, thereby turning off the main switch T1.

9. The overcurrent protection circuit for power device testing according to claim 8, characterized in that, The logic decision network includes an AND gate chip AND1 and a drive signal source. The first input terminal of the AND gate chip AND1 is connected to the inverse code output terminal of the second D-type latch DL2, and the second input terminal is connected to the drive signal source.

10. The overcurrent protection circuit for power device testing according to claim 9, characterized in that, The drive enable signal output network includes a driver chip U1, an eleventh resistor R10, and a second TVS regulator Z2. The enable pin of the driver chip U1 is connected to the output of the AND gate chip AND1. The output of the driver chip U1 is connected to the first end of the eleventh resistor R10. The second end of the eleventh resistor R10 is connected to the gate of the main switch T1. The first end of the second TVS regulator Z2 is connected to the second end of R10, and the second end is connected to the emitter of the main switch T1. When the driver chip U1 receives the trigger signal from the previous stage, it issues a shutdown signal to turn off the main switch T1.

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