Display devices and electronic devices

Abstract

A display device and an electronic device including the display device are provided, the display device being able to improve image quality by minimizing or reducing the visibility of blemishes. According to one or more embodiments of this disclosure, the display device includes: a substrate; a reflective electrode on the substrate; a pixel defining film on the reflective electrode; a first electrode on the pixel defining film; a light-emitting stack on the first electrode; a second electrode on the light-emitting stack; and a via penetrating the pixel defining film between the reflective electrode and the first electrode to connect the reflective electrode and the first electrode, wherein the via is arranged at different locations in corresponding pixels among a plurality of pixels.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0169616, filed on November 25, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to a display device, for example, to a display device capable of improving image quality by minimizing or reducing the visibility of blemishes, and to an electronic device including the display device. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to focus an image at close range in front of the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays magnify images displayed on a small display device using multiple lenses and then display the magnified image to the user. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), as high-resolution small organic light-emitting display devices, can be used as display devices for head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are arranged on a semiconductor silicon wafer substrate, and complementary metal-oxide-semiconductor (CMOS) circuitry is arranged on the semiconductor silicon wafer substrate. Summary of the Invention

[0005] One or more aspects of embodiments of this disclosure relate to a display device capable of improving image quality by minimizing or reducing the visibility of blemishes, and an electronic device including the display device. Further aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0006] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a reflective electrode on the substrate; a pixel defining film on the reflective electrode; a first electrode on the pixel defining film; a light-emitting stack on the first electrode; a second electrode on the light-emitting stack; and a via penetrating the pixel defining film between the reflective electrode and the first electrode to connect the reflective electrode and the first electrode, wherein the via is arranged at different locations for each pixel (e.g., arranged at different locations in corresponding pixels among a plurality of pixels).

[0007] According to one or more embodiments of the present disclosure, an electronic device includes: a display device including (e.g., provided) a screen, wherein the display device includes: a substrate; a reflective electrode on the substrate; a pixel defining film on the reflective electrode; a first electrode on the pixel defining film; a light-emitting stack on the first electrode; a second electrode on the light-emitting stack; and a via penetrating the pixel defining film between the reflective electrode and the first electrode to connect the reflective electrode and the first electrode, wherein the via is arranged at different locations for each pixel (e.g., arranged at different locations in corresponding pixels among a plurality of pixels).

[0008] According to one or more embodiments of this disclosure, the visibility of blemishes can be minimized or reduced, thereby improving image quality. For example, by randomly (or irregularly) arranging vias that may cause blemishes for each pixel, the visually identifiable blemishes around the vias are minimized or reduced, thereby improving the image quality of the display device.

[0009] For example, a display device and an electronic device are provided, both including a substrate, a reflective electrode on the substrate, a pixel defining film on the reflective electrode, a first electrode on the pixel defining film, a light-emitting stack on the first electrode, a second electrode on the light-emitting stack, and a via penetrating the pixel defining film to connect the reflective electrode and the first electrode. For each pixel (among multiple pixels), the vias are arranged at different locations to minimize or reduce the visibility of blemishes, thereby improving image quality.

[0010] The effects and aspects of this disclosure are not limited to those described above, and other effects and aspects not described herein will become apparent to those skilled in the art from the following description. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The above and other aspects and features of this disclosure will become more apparent and readily understood from the following description of exemplary embodiments of the disclosure with reference to the accompanying drawings, in which: Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure; Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure; Figure 3 This is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure; Figure 4 This is a layout diagram illustrating examples of display panels according to one or more embodiments of the present disclosure; Figure 5 This illustrates one or more embodiments according to the present disclosure. Figure 4 An example layout diagram of the display area; Figure 6 This illustrates one or more embodiments according to the present disclosure. Figure 4 An example layout diagram of the display area; Figure 7 This illustrates one or more embodiments according to the present disclosure. Figure 5 A cross-sectional view of an example display panel, taken by line I1-I1'; Figure 8 A more detailed description of one or more embodiments according to this disclosure is provided. Figure 7 A sectional view of region A1; Figure 9 This is a plan view of a display device according to one or more embodiments of the present disclosure; Figure 10 This is a schematic diagram illustrating the location of vias for each pixel according to one or more embodiments of the present disclosure; Figure 11 This is a perspective view showing a head-mounted display according to one or more embodiments of the present disclosure; Figure 12 This illustrates one or more embodiments according to the present disclosure. Figure 11 An exploded perspective view of an example of a head-mounted display; Figure 13 This is a perspective view showing a head-mounted display according to one or more embodiments of the present disclosure; Figure 14 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure; and Figure 15 , Figure 16 and Figure 17 These are schematic diagrams illustrating electronic devices according to one or more embodiments of the present disclosure. Detailed Implementation

[0012] This disclosure will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0013] It will also be understood that if a layer is referred to as "on" another layer or substrate (e.g., when a layer is referred to as "on" another layer or substrate), the layer may be directly on said other layer or substrate, or one or more intervening layers may exist between them. Conversely, "directly on" may mean that there is no additional intervening element or layer between an element or layer and another element or layer. Furthermore, in one or more embodiments of this disclosure, if an element is referred to as being arranged "on" another element (e.g., when an element is referred to as being arranged "on" another element), the element may be arranged "above" said other element or arranged "below" or "under" said other element. Throughout this disclosure, the same or similar reference numerals denote the same or similar components. In the figures, the thickness of layers and / or regions may be exaggerated for clarity.

[0014] Although the terms “first” and / or “second” etc. may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Thus, without departing from the teachings of one or more embodiments, the first element in discussion may be referred to as the second element. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. In one or more embodiments, the terms “first” and / or “second” etc. may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first” and / or “second” etc. may respectively refer to “first category (or first group)” and / or “second category (or second group)” etc.

[0015] Features of one or more suitable embodiments of this disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, one or more suitable interactions and operations are technically possible. The various embodiments may be practiced individually or in combination.

[0016] In the following description, one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0017] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0018] Reference Figure 1 and Figure 2The display device 10 according to one or more embodiments is a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. In one or more embodiments, the display device 10 can be applied to smartwatches, smartwatch phones, and / or head-mounted displays (HMDs) for implementing virtual reality and / or augmented reality.

[0019] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0020] In one or more embodiments, the display panel 100 may have a planar shape, for example, similar to a quadrilateral. For instance, the display panel 100 may have a planar shape similar to a quadrilateral having a short side on a first direction DR1 and a long side on a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side on the first direction DR1 and the long side on the second direction DR2 intersect may be a right angle or rounded with a set or predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0021] The display panel 100 includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), multiple data lines (DL), a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 2 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0022] Multiple pixels PX can be arranged in the display area DAA. In one or more embodiments, the multiple pixels PX can be arranged in a matrix in a first direction DR1 and a second direction DR2. Multiple scan lines SL and multiple emission control lines EL can extend in the first direction DR1 and be arranged in the second direction DR2. Multiple data lines DL can extend in the second direction DR2 and be arranged relative to each other in the first direction DR1.

[0023] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0024] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. Each of the multiple sub-pixels SP1, SP2, and SP3 can include, for example: Figure 3 The multiple pixel transistors shown can be formed and arranged on a semiconductor substrate SSUB using semiconductor processes (see...). Figure 7 For example, in one or more embodiments, the pixel transistors of the plurality of sub-pixels SP1, SP2 and SP3 may be formed of complementary metal-oxide semiconductor (CMOS), but embodiments of this disclosure are not limited thereto.

[0025] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL selected from a plurality of write scan lines GWL (e.g., any one), a control scan line GCL selected from a plurality of control scan lines GCL (e.g., any one), a bias scan line GBL selected from a plurality of bias scan lines GBL (e.g., any one), a first emission control line EL1 selected from a plurality of first emission control lines EL1 (e.g., any one), a second emission control line EL2 selected from a plurality of second emission control lines EL2 (e.g., any one), and a data line DL selected from a plurality of data lines DL (e.g., any one). Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0026] In one or more embodiments, the scan driver 610, the transmit driver 620, and the data driver 700 may all be arranged in the non-display area NDA.

[0027] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor diagram]). Figure 7 For example, in one or more embodiments, the plurality of scanning transistors and the plurality of light-emitting transistors may be formed by CMOS, but the embodiments of this disclosure are not limited thereto.

[0028] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0029] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and output them sequentially to the first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and output them sequentially to the second transmit control line EL2.

[0030] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 For example, in one or more embodiments, multiple data transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto.

[0031] Data driver 700 can receive digital video data DATA and data timing control signal DCS from timing control circuit 400. Data driver 700 converts the digital video data DATA into analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to data line DL. In this regard, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of scan driver 610, and data voltage (e.g., analog data voltage) can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0032] The heat dissipation layer 200 can be stacked on the display panel 100 in a third-direction DR3, where DR3 is the thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on a surface (e.g., a surface) of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a graphite or metal layer (such as silver (Ag), copper (Cu), and / or aluminum (Al)) with high thermal conductivity.

[0033] Circuit board 300 can be electrically connected to the first pad (or "soldering pad") portion of display panel 100 PDA1 (see [link to PDA1]) using conductive adhesive components (such as anisotropic conductive film). Figure 4 Multiple first pads PD1 (see) Figure 4 In one or more embodiments, circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Although circuit board 300 in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this respect, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion PDA1 of the display panel 100 (see [reference]) using conductive adhesive members. Figure 4 Multiple first pads PD1 (see) Figure 4 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0034] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0035] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, in one or more embodiments, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later in conjunction with... Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0036] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this regard, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0037] In one or more embodiments, similar to scan driver 610, transmit driver 620, and data driver 700, each of timing control circuitry 400 and power supply circuitry 500 may be arranged in the non-display area NDA of display panel 100. In these embodiments, timing control circuitry 400 may include a plurality of timing transistors, and power supply circuitry 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (see [link to semiconductor diagram]) using semiconductor processes. Figure 7 On. For example, in one or more embodiments, the plurality of timing transistors and the plurality of power transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto. In one or more embodiments, each of the timing control circuitry 400 and the power supply circuitry 500 may be arranged on the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0038] Figure 3 This is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure.

[0039] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. For example, in one or more embodiments, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. In these embodiments, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0040] In one or more embodiments, the first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0041] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount (e.g., emission intensity) of the light-emitting element LE can be proportional to the drive current (Ids). The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. In one or more embodiments, the light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in these embodiments, the light-emitting element LE can be a miniature light-emitting diode.

[0042] The first transistor T1 may be a driving transistor that controls the source-drain current (Ids) (hereinafter referred to as the "driving current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0043] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal to write scan line GWL, thereby connecting one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0044] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal controlling the scan line GCL, thereby connecting the first node N1 to the second node N2. For this purpose, if the gate and drain electrodes of the first transistor T1 are connected (e.g., when the gate and drain electrodes of the first transistor T1 are connected), the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0045] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1, thereby connecting the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0046] A fifth transistor T5 can be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line GBL, connecting the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0047] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal via the second emitter control line EL2, thereby connecting the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0048] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0049] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0050] The first node N1 is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0051] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, in one or more embodiments, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. In one or more embodiments, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0052] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0053] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can both be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are not repeated in this disclosure.

[0054] Figure 4 This is a layout diagram illustrating an example of a display panel according to one or more embodiments of the present disclosure.

[0055] Reference Figure 4The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0056] The scan driver 610 can be arranged on a first side of the display area DAA, and the transmit driver 620 can be arranged on a second side of the display area DAA. For example, in one or more embodiments, the scan driver 610 can be arranged on one side of the display area DAA in a first direction DR1, and the transmit driver 620 can be arranged on the other side of the display area DAA in the first direction DR1. For example, as Figure 4 As shown, the scan driver 610 may be arranged on the left side of the display area DAA, and the transmit driver 620 may be arranged on the right side of the display area DAA. However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, both the scan driver 610 and the transmit driver 620 may be arranged (e.g., simultaneously) on the first side or the second side of the display area DAA (i.e., opposite to the first side).

[0057] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by conductive adhesive members. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, in one or more embodiments, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed on the outside of the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0058] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to fixtures or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0059] The second pad portion PDA2 can be disposed on the fourth side of the display area DAA. For example, in one or more embodiments, the second pad portion PDA2 can be disposed on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be disposed outside the second distribution circuit 720 in the second direction DR2. For example, the second pad portion PDA2 can be disposed closer to the edge of the display panel 100 than the second distribution circuit 720.

[0060] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, in one or more embodiments, the first distribution circuit 710 can distribute the data voltage applied through one of the first pads PD1 in the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of multiple first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be arranged on the lower side of the display area DAA.

[0061] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be arranged on the upper side of the display area DAA.

[0062] In the context of this disclosure, unless otherwise specified, "one side of the display area DAA in the second direction DR2" refers to the specified side of the display area along the direction marked DR2. For example, if DR2 represents the vertical direction, it could indicate the bottom side of the display area. Conversely, "the other side of the display area DAA in the second direction DR2" refers to the opposite side of the display area along the same direction DR2, and continuing the previous example, it could indicate the top side of the display area. These phrases are used to describe components such as distribution circuitry located on opposite sides of the display area along the specified direction DR2.

[0063] Figure 5 and Figure 6 All are shown according to one or more embodiments Figure 4 An example layout diagram of the display area.

[0064] Reference Figure 5and Figure 6 Each pixel PX includes a first emission region EA1 as the emission region of a first sub-pixel SP1, a second emission region EA2 as the emission region of a second sub-pixel SP2, and a third emission region EA3 as the emission region of a third sub-pixel SP3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be surrounded by a trench TRC. (See below for further details.) Figure 7 A more detailed description of the trench TRC's structure.

[0065] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape in the plan view.

[0066] In one or more embodiments, the maximum length of the first transmission region EA1 in the first direction DR1 may be less than the maximum length of the second transmission region EA2 in the first direction DR1 and the maximum length of the third transmission region EA3 in the first direction DR1. The maximum lengths of the second transmission region EA2 and the third transmission region EA3 in the first direction DR1 may be substantially the same.

[0067] In one or more embodiments, the maximum length of the first transmission region EA1 in the second direction DR2 may be greater than the maximum length of the second transmission region EA2 in the second direction DR2 and the maximum length of the third transmission region EA3 in the second direction DR2. The maximum length of the second transmission region EA2 in the second direction DR2 may be less than the maximum length of the third transmission region EA3 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 may be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0068] In one or more embodiments, the first transmission region EA1, the second transmission region EA2, and the third transmission region EA3 can all have the following characteristics in a plan view: Figure 6 The hexagonal shape formed by six straight lines shown is illustrated, but the embodiments of this disclosure are not limited thereto. In one or more embodiments, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may each independently have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape other than a hexagon in a plan view.

[0069] like Figure 5As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0070] In one or more embodiments, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 can be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction orthogonal (e.g., perpendicular) to the first diagonal direction DD1.

[0071] The first sub-pixel SP1 can be used to emit light emitted from the first emission region EA1 that has already passed through the first color filter CF1 (see...). Figure 7 The first light, the second sub-pixel SP2, can be used to emit light that has passed through the second color filter CF2 from the second emission region EA2 (see...). Figure 7 The second light, and the third sub-pixel SP3 can be used to emit light that has passed through the third color filter CF3 from the third emission region EA3 (see...). Figure 7 The third light is light in the blue band. In one or more embodiments, the first light may be light in the blue band, the second light may be light in the green band, and the third light may be light in the red band. For example, the blue band may be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green band may be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band may be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0072] exist Figure 5 and Figure 6 The illustration shows that each of a plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, each of the plurality of pixels PX may include four emission regions.

[0073] Furthermore, the layout of the emission regions of multiple pixel PXs is not limited to Figure 5 and Figure 6 The layout shown is illustrated. For example, in one or more embodiments, the emission regions of a plurality of pixels PX can be arranged as a strip structure in which the emission regions are arranged along a first direction DR1, or as a PenTile in which the emission regions are arranged in a diamond shape. ® The structure, or the emission region within it that has a hexagonal shape in a planar view, such as Figure 6 The hexagonal structure arranged as shown in the image. (PenTile) ® It is an officially registered trademark of Samsung Display Co., Ltd.

[0074] Figure 7 It is shown that along one or more embodiments Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'. Figure 8 A more detailed description is provided based on one or more embodiments. Figure 7 A sectional view of region A1.

[0075] Reference Figure 7 and Figure 8 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0076] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1, SINS2, and SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may include (for example, may be) reference... Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0077] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type (type) of impurity. Multiple well regions WA can be arranged in the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type (type) of impurity. The second type (type) of impurity can be different from the aforementioned first type (type) of impurity. For example, in one or more embodiments, if the first type (type) of impurity is a P-type (type) impurity (e.g., when the first type (type) of impurity is a P-type (type) impurity), the second type (type) of impurity can be an N-type (type) impurity. In one or more embodiments, if the first type (type) of impurity is an N-type (type) impurity (e.g., when the first type (type) of impurity is an N-type (type) impurity), the second type (type) of impurity can be a P-type (type) impurity.

[0078] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to its drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0079] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0080] Each of the source region SA and the drain region DA can be a region doped with a first type (species) impurity. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can be stacked with the gate electrode GE on the third direction DR3. The source region SA can be arranged on one side of the gate electrode GE, and the drain region DA can be arranged on the other side of the gate electrode GE.

[0081] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may occur due to short channels.

[0082] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. In one or more embodiments, the first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN)-type inorganic film or silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0083] A second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. In one or more embodiments, the second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0084] Multiple contact terminals (CTEs) can be arranged on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). All of the multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound comprising any one of them.

[0085] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). In one or more embodiments, the third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0086] In one or more embodiments, the semiconductor substrate SSUB can be replaced with a glass substrate or a polymeric resin substrate (such as polyimide). In these embodiments, the thin-film transistor can be disposed on the glass substrate or the polymeric resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymeric resin substrate can be a flexible substrate that can be bent or folded.

[0087] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. Additionally, the backplane (EBP) includes multiple insulating films INS1 to INS9 disposed between the first conductive layer ML1 to the eighth conductive layer ML8.

[0088] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry of the first sub-pixel SP1 is shown. For example, in one or more embodiments, the first transistors T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection between the first transistors T1 to the sixth transistor T6, the first capacitor CP1, and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0089] A first insulating film INS1 may be disposed on a semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0090] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can connect to the second via VA2.

[0091] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and connect to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 and can connect to the third via VA3.

[0092] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can connect to the fourth via VA4.

[0093] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can connect to the fifth via VA5.

[0094] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can connect to the sixth via VA6.

[0095] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can connect to the seventh via VA7.

[0096] The eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can connect to the eighth via VA8.

[0097] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. In one or more embodiments, the first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can all be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound thereof. The first insulating films INS1 to INS8 can be made of substantially the same material. The first insulating films INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0098] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, in one or more embodiments, the thickness of the first conductive layer ML1 can be approximately 1360 angstroms (Å) (i.e., 10...). -10 The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately 1440 Å. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be approximately 1150 Å.

[0099] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, in one or more embodiments, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 4000 Å to 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 6000 Å to 7000 Å.

[0100] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. In one or more embodiments, the ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0101] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). In one or more embodiments, the thickness of the ninth via VA9 can be approximately 6000 Å to 7000 Å.

[0102] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include multiple connection electrodes (ANC), multiple reflective electrodes (RL), a planarization film (PNS), a pixel defining film (PDL), multiple first electrodes (AND), a light-emitting stack (IL), a second electrode (CAT), and multiple trenches (TRC).

[0103] Furthermore, the display element layer EML may include a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3. Each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 may be a region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked. Each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 may be a region in which a light-emitting element LE, including the first electrode AND, the light-emitting stack IL, and the second electrode CAT, is disposed. Each of the first emitting region EA1 and the second emitting region EA2 may be separated by a first pixel defining film PDL1. In one or more embodiments, the third emitting region EA3 may be defined as the entire region of the first electrode AND that is superimposed on the third emitting region EA3. For example, the third emitting region EA3 may be defined as the entire region of the first electrode AND of the third sub-pixel SP3.

[0104] The ninth insulating film INS9 may include a first region AA1 stacked with a plurality of connecting electrodes ANC and a second region AA2 arranged around each of the first region AA1.

[0105] Multiple connection electrodes ANC can be disposed on a first region AA1 of the ninth insulating film INS9. Each of the multiple connection electrodes ANC can be disposed on a corresponding first region AA1. In one or more embodiments, the multiple connection electrodes ANC can be formed of titanium nitride (TiN) or a transparent conductive oxide. For example, the transparent conductive oxide can be indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto. The thickness of each of the multiple connection electrodes ANC can be approximately 600 Å.

[0106] Multiple reflective electrodes RL can be arranged on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be arranged on its corresponding connecting electrode ANC. The multiple reflective electrodes RL can be formed of any one or an alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, in one or more embodiments, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity. The thickness of each of the multiple reflective electrodes RL may be approximately 12,000 Å.

[0107] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0108] The first electrode AND of each of the light-emitting elements LE can be disposed on its corresponding reflective electrode RL. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the reflective electrode RL, the connecting electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any alloy or compound selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or formed of a transparent conductive oxide. For example, in one or more embodiments, the first electrode AND of each of the light-emitting elements LE may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiments disclosed herein are not limited thereto.

[0109] The thickness of the first electrode AND in each of the light-emitting elements LE can be approximately 100 Å or less. For example, in one or more embodiments, the thickness of the first electrode AND in each of the light-emitting elements LE can be approximately 70 Å to 80 Å.

[0110] In the first sub-pixel SP1 and the second sub-pixel SP2, the connecting electrode ANC, the reflective electrode RL, and the first electrode AND can be stacked sequentially. Since the connecting electrode ANC, the reflective electrode RL, and the first electrode AND are patterned at once using a single mask, the side surfaces of the connecting electrode ANC, the reflective electrode RL, and the first electrode AND can be aligned with each other. Furthermore, since multiple connecting electrodes ANC, multiple reflective electrodes RL, and multiple first electrodes AND are formed simultaneously, the number of mask processes can be reduced compared to the case where each of the multiple first electrodes AND is connected to a reflective electrode RL exposed through a contact hole penetrating the insulating film, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0111] A pixel-defined film (PDL) can be disposed on the first electrode AND of each of the light-emitting elements LE of the first sub-pixel SP1 and the second sub-pixel SP2, and a portion of the first electrode AND can be exposed. The PDL can separate a first emission region EA1 and a second emission region EA2. The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light.

[0112] The pixel-limiting film (PDL) may include a first pixel-limiting film (PDL1), a second pixel-limiting film (PDL2), and a third pixel-limiting film (PDL3).

[0113] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the light-emitting elements LE of the first sub-pixel SP1 and the second sub-pixel SP2. The first electrode AND of each of the first sub-pixel SP1 and the second sub-pixel SP2 can be partially exposed and not completely covered by the first pixel defining film PDL1.

[0114] A planarization film PNS is a film used to planarize the steps caused by multiple connecting electrodes ANC, multiple reflecting electrodes RL, and multiple first electrodes AND. The planarization film PNS can be disposed between adjacent connecting electrodes ANC in a first direction DR1 or a second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL in the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed on a first pixel defining film PDL1, which is disposed on a second region AA2 of a ninth insulating film INS9 (e.g., disposed overlapping with the second region AA2 of the ninth insulating film INS9).

[0115] The second pixel defining film PDL2 can be disposed on the first pixel defining film PDL1 and the planarization film PNS, and the third pixel defining film PDL3 can be disposed on the second pixel defining film PDL2. In one or more embodiments, both the first pixel defining film PDL1 and the third pixel defining film PDL3 can be formed as silicon nitride (SiN). x Inorganic films of this type, and both the second pixel defining film PDL2 and the planarization film PNS can be formed as silicon oxide (SiO2). x ( ) type inorganic film. The first pixel defining film PDL1 is formed of a material different from that of the planarization film PNS, and therefore can be used as a stopper in the chemical mechanical polishing process used for the planarization film PNS.

[0116] In one or more embodiments, the thickness of the first pixel defining film PDL1 and the thickness of the second pixel defining film PDL2 may both be approximately 500 Å, but the embodiments of this disclosure are not limited thereto. In one or more embodiments, the thickness of the third pixel defining film PDL3 may be approximately 700 Å, but the embodiments of this disclosure are not limited thereto.

[0117] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 form a single pixel defining film, the height of this single pixel defining film increases, making it possible for the second electrode CAT and the first encapsulating inorganic film TFE1 to be cut due to step coverage. Step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which it is coated on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0118] To reduce or prevent the possibility of the second electrode CAT and the first encapsulating inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can collectively have a cross-sectional structure with stepped portions. For example, a portion of the first pixel defining film PDL1 can be exposed and not covered by the second pixel defining film PDL2, and a portion of the second pixel defining film PDL2 can be exposed and not covered by the third pixel defining film PDL3. The exposed portion of the first pixel defining film PDL1 can be an edge of the first pixel defining film PDL1, and the exposed portion of the second pixel defining film PDL2 can be an edge of the second pixel defining film PDL2.

[0119] Furthermore, the width of the first pixel-defining film PDL1 can be greater than the width of the second pixel-defining film PDL2 and the width of the third pixel-defining film PDL3, and the width of the second pixel-defining film PDL2 can be greater than the width of the third pixel-defining film PDL3. The width of the first pixel-defining film PDL1 refers to the horizontal length of the first pixel-defining film PDL1 defined in the first direction DR1 or the second direction DR2.

[0120] The first electrode AND of the third sub-pixel SP3 can be disposed on the third pixel defining film PDL3. Between the reflective electrode RL of the third sub-pixel SP3 and the first electrode AND of the third sub-pixel SP3, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can be disposed. The pixel defining film PDL between the first electrode AND of the third sub-pixel SP3 and the reflective electrode RL of the third sub-pixel SP3 can serve as a resonant layer. Due to the resonant layer of the third sub-pixel SP3, the first electrode AND of the third sub-pixel SP3 can be disposed higher than the first electrodes AND of other sub-pixels SP1 and SP2 on the third-direction DR3. Therefore, the third sub-pixel SP3 can have a different resonant distance than other sub-pixels SP1 and SP2. For example, in one or more embodiments, the distance between the first electrode AND of the third sub-pixel SP3 and the reflective electrode RL of the third sub-pixel SP3 can be greater than the distance between the first electrode AND of the first sub-pixel SP1 (or the second sub-pixel SP2) and the reflective electrode RL of the first sub-pixel SP1 (or the second sub-pixel SP2).

[0121] The first electrode AND of the third sub-pixel SP3 can be connected to the reflective electrode RL of the third sub-pixel SP3 through the tenth via VA10 that penetrates the first pixel limiting film PDL1, the second pixel limiting film PDL2 and the third pixel limiting film PDL3.

[0122] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the planarization film PNS, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. Furthermore, the ninth insulating film INS9 can be partially recessed at each of the multiple trench TRCs.

[0123] At least one trench TRC can be arranged between adjacent emission areas EA1, EA2, and EA3. Although Figure 7 and Figure 8 Two trench TRCs are shown arranged between adjacent emission regions EA1, EA2 and EA3, but the embodiments disclosed herein are not limited thereto.

[0124] The light-emitting stack IL can include multiple stacked layers IL1, IL2 and IL3. Figure 7 and Figure 8The illustration shows a light-emitting stack IL having a triple-tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3; however, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting stack IL may have a double-tandem structure including two stacked layers.

[0125] In a three-tiered structure, in one or more embodiments, the light-emitting stack IL may have a tiered structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 configured to emit a first light, a second stacked layer IL2 configured to emit a second light, and a third stacked layer IL3 configured to emit a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially (e.g., in the order stated).

[0126] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting a first light, and a first electron transport layer are stacked sequentially (e.g., in the order stated). The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting a second light, and a second electron transport layer are stacked sequentially (e.g., in the order stated). The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting a third light, and a third electron transport layer are stacked sequentially (e.g., in the order stated).

[0127] In one or more embodiments, a first charge-generating layer for supplying charge (e.g., holes) to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type charge-generating layer that supplies holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0128] A second charge generation layer for supplying charge (e.g., holes) to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0129] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL. A residual film RIL made of the same material as the first stacked layer IL1 can be disposed on the bottom surface of each of the trench TRCs. Due to the trench TRCs, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRCs, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be disposed in each trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRCs and can be disposed to cover the second stacked layer IL2 in each of the trench TRCs.

[0130] In a three-series structure, since current can flow through the first and second charge generation layers between adjacent sub-pixels SP1, SP2, and SP3, each of the plurality of trench TRCs can be a structure for cutting off the first and second charge generation layers of the display element layer EML. In one or more embodiments, in a two-series structure, since current can flow through the charge generation layers, each of the plurality of trench TRCs can be a structure for cutting off the charge generation layers disposed between the lower and upper stacked layers.

[0131] To stably cut off the first and second charge generation layers of the display element layer EML between adjacent emission regions EA1, EA2, and EA3, the height of each of the plurality of trench TRCs can be greater than the sum of the thicknesses of the first pixel defining film PDL1, the second pixel defining film PDL2, the third pixel defining film PDL3, and the planarization film PNS. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3.

[0132] To cut off the first and second charge generation layers of the display element layer EML between adjacent emission regions EA1, EA2, and EA3, an alternative structure can be used instead of the trench TRC. For example, in one or more embodiments, instead of the trench TRC, inverted conical partition walls can be arranged on the pixel defining film PDL.

[0133] The second electrode CAT can be disposed on the light-emitting stack IL. The second electrode CAT can also be disposed on a third stacked layer IL3 on each of the plurality of trench TRCs. In one or more embodiments, the second electrode CAT can be formed of a transparent conductive material (TCO) or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In these embodiments, the luminous efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be increased due to the microcavity effect.

[0134] To utilize the microcavity, the first resonant distance between the first organic light-emitting layer of the first stacked layer IL1 and the reflective electrode RL can be set by considering the dominant peak wavelength of the first light. Furthermore, the second resonant distance between the second organic light-emitting layer of the second stacked layer IL2 and the reflective electrode RL can be set by considering the dominant peak wavelength of the second light. Finally, the third resonant distance between the third organic light-emitting layer of the third stacked layer IL3 and the reflective electrode RL can be set by considering the dominant peak wavelength of the third light.

[0135] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one of an encapsulation inorganic film TFE1 and an encapsulation inorganic film TFE2 to reduce or prevent oxygen and / or moisture from penetrating into the display element layer EML. For example, in one or more embodiments, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0136] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is formed. x ), silicon oxynitride (SiON) and silicon oxide (SiO) x A multilayer of one or more inorganic films selected from the group, stacked alternately. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0137] The second encapsulating inorganic film TFE2 can be disposed on the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x The second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0138] Organic film APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. Organic film APL can be an organic film such as one formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0139] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can all be arranged on the organic film APL.

[0140] The first color filter CF1 can be stacked with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can be used to transmit first light (e.g., light in the blue band). Therefore, the first color filter CF1 can be used to transmit the first light emitted from the light-emitting stack IL of the first emission region EA1.

[0141] The second color filter CF2 can be stacked with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can be used to transmit a second light (e.g., light in the green band). Therefore, the second color filter CF2 can be used to transmit a second light from the light emitted by the light-emitting stack IL of the second emission region EA2.

[0142] The third color filter CF3 can be stacked with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can be used to transmit third light (e.g., light in the red band). Therefore, the third color filter CF3 can be used to transmit third light from the light emitted by the light-emitting stack IL of the third emission region EA3.

[0143] Multiple lenses LNS can be arranged on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed toward the front of the display device 10. Although each of the lenses LNS is shown as having an upwardly convex cross-sectional shape, the embodiments of this disclosure are not limited thereto.

[0144] The filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer (FIL) can have a set or predetermined refractive index such that light travels in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens lenses (LNS). Furthermore, the filler layer (FIL) can also be a planarization layer. The filler layer (FIL) can be an organic film, such as one formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0145] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. In one or more embodiments, when the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In these embodiments, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. In one or more embodiments, when the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0146] The polarizing plate (POL) can be disposed on the surface (e.g., a surface) of the CVL cover layer. The polarizing plate (POL) can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. For example, in one or more embodiments, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. However, if the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3 (e.g., when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3), the polarizing plate (POL) may not be required.

[0147] In one or more embodiments, the first electrode AND of the first sub-pixel SP1 may have a groove GR recessed toward the reflective electrode RL at the center of the first electrode AND of the first sub-pixel SP1. For example, in one or more embodiments, the first electrode AND of the first sub-pixel SP1 may have a groove GR at its center other than the edge overlapping with the first pixel defining film PDL1. For example, the first electrode AND of the first sub-pixel SP1 may have a groove GR in a region not overlapping with the first pixel defining film PDL1. Due to the groove GR, the thickness of the first electrode AND of the first sub-pixel SP1 at the center may be less than the thickness at the edge. Therefore, the proportion of light emitted from the first organic light-emitting layer of the first stacked layer IL1 that resonates between the first electrode AND and the second electrode CAT of the first sub-pixel SP1 can be increased. Similarly, the proportion of light emitted from the second organic light-emitting layer of the second stacked layer IL2 that resonates between the first electrode AND and the second electrode CAT of the first sub-pixel SP1, and the proportion of light emitted from the third organic light-emitting layer of the third stacked layer IL3 that resonates between the first electrode AND and the second electrode CAT of the first sub-pixel SP1 can also be increased. Therefore, the proportion of light emitted due to the optical microcavity between the first electrode AND and the second electrode CAT of the first sub-pixel SP1 can be increased. Thus, the luminous efficiency of the first emitting region EA1 can be improved.

[0148] Similarly, the first electrode AND of the second sub-pixel SP2 can have a groove recessed towards the reflective electrode RL at the center of the first electrode AND of the second sub-pixel SP2. Therefore, the luminous efficiency of the second emitting region EA2 can be improved.

[0149] According to one or more embodiments, the first electrode of the first sub-pixel (or the second sub-pixel) can be directly connected to (or in direct contact with) the reflective electrode of the first sub-pixel (or the second sub-pixel). However, the first electrode of the third sub-pixel can be connected to the reflective electrode of the third sub-pixel through a tenth via VA10. Since the tenth via VA10 overlaps with the first electrode of the third sub-pixel and the third emission region, the periphery of the tenth via VA10 may be visually perceived as a blemish. To address this image quality defect, it is preferable that the tenth vias VA10 in the third emission region are randomly arranged. Reference will be made below. Figure 9 One or more embodiments thereof are described in more detail.

[0150] Figure 9 This is a plan view of a display device according to one or more embodiments of the present disclosure.

[0151] like Figure 9 As shown, in one or more embodiments, each of pixels PX1, PX2, PX3, and PX4 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. In these embodiments, the tenth via VA10 arranged in the third sub-pixel SP3 of the first pixel PX1, the tenth via VA10 arranged in the third sub-pixel SP3 of the second pixel PX2, the tenth via VA10 arranged in the third sub-pixel SP3 of the third pixel PX3, and the tenth via VA10 arranged in the third sub-pixel SP3 of the fourth pixel PX4 may be arranged in different regions of the respective sub-pixels.

[0152] For example, in one or more embodiments, if the first electrode AND of the third sub-pixel SP3 of the first pixel PX1 is defined as the first anode electrode AND1, the first electrode AND of the third sub-pixel SP3 of the second pixel PX2 is defined as the second anode electrode AND2, the first electrode AND of the third sub-pixel SP3 of the third pixel PX3 is defined as the third anode electrode AND3, and the first electrode AND of the third sub-pixel SP3 of the fourth pixel PX4 is defined as the fourth anode electrode AND4 (for example, when the first electrode AND of the third sub-pixel SP3 of the first pixel PX1 is defined as the first anode electrode AND1, the first electrode AND of the third sub-pixel SP3 of the second pixel PX2 is defined as the second anode electrode AND2, the first electrode AND of the third sub-pixel SP3 of the third pixel PX3 is defined as the third anode electrode AND3, and the first electrode AND of the third sub-pixel SP3 of the fourth pixel PX4 is defined as the fourth anode electrode AND4) When the first electrode AND of pixel SP3 is defined as the third anode electrode AND3, and the first electrode AND of the third sub-pixel SP3 of the fourth pixel PX4 is defined as the fourth anode electrode AND4, the tenth via VA10 of the third sub-pixel SP3 of the first pixel PX1 can be placed near the 5 o'clock position of the first anode electrode AND1, the tenth via VA10 of the third sub-pixel SP3 of the second pixel PX2 can be placed near the 2 o'clock position of the second anode electrode AND2, the tenth via VA10 of the third sub-pixel SP3 of the third pixel PX3 can be placed near the 6 o'clock position of the third anode electrode AND3, and the tenth via VA10 of the third sub-pixel SP3 of the fourth pixel PX4 can be placed near the 12 o'clock position of the fourth anode electrode AND4. However, Figure 9 The placement of the tenth via VA10 in the example is merely an example, and the tenth via VA10 can be placed randomly and is not limited to this. Figure 9 The arrangement is shown in the figure.

[0153] Figure 10 This is a schematic diagram illustrating the location of vias for each pixel according to one or more embodiments of the present disclosure.

[0154] Figure 10 An example is shown in which eight adjacent pixels PX1, PX2, PX3, PX4, PX5, PX6, PX7, and PX8 are arranged. However, for the sake of simplicity, Figure 10 The first electrode AND is shown in the third sub-pixel arranged in each pixel PX1, PX2, PX3, PX4, PX5, PX6, PX7, PX8.

[0155] like Figure 10In the example shown, the tenth via VA10 in the third sub-pixel of the first pixel PX1 can be positioned at the 5 o'clock position of the first electrode AND; the tenth via VA10 in the third sub-pixel of the second pixel PX2 can be positioned at the 2 o'clock position of the first electrode AND; the tenth via VA10 in the third sub-pixel of the third pixel PX3 can be positioned at the 6 o'clock position of the first electrode AND; the tenth via VA10 in the third sub-pixel of the fourth pixel PX4 can be positioned at the 2 o'clock position of the first electrode AND; and the tenth via VA10 in the third sub-pixel of the fifth pixel PX5 can be positioned at the 7 o'clock position of the first electrode AND. Furthermore, the tenth via VA10 in the third sub-pixel of the sixth pixel PX6 can be positioned at the 12 o'clock position of the first electrode AND; the tenth via VA10 in the third sub-pixel of the seventh pixel PX7 can be positioned at the 5 o'clock position of the first electrode AND; and the tenth via VA10 in the third sub-pixel of the eighth pixel PX8 can be positioned at the 2 o'clock position of the first electrode AND. For example, the tenth via VA10 in the third sub-pixel of each pixel (PX1 to PX8) is arranged at different positions on the first electrode. Specifically, the positions are as follows: PX1 at 5 o'clock, PX2 at 2 o'clock, PX3 at 6 o'clock, PX4 at 2 o'clock, PX5 at 7 o'clock, PX6 at 12 o'clock, PX7 at 5 o'clock, and PX8 at 2 o'clock.

[0156] Since the tenth via VA10 is arranged randomly (or irregularly) for each pixel, the phenomenon of visually identifiable blemishes can be minimized or reduced, thereby improving the image quality of the display device.

[0157] Figure 11 This is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure. Figure 12 It is shown Figure 11 An exploded perspective view of an example of a head-mounted display. For example, Figure 11 and Figure 12 An example of a head-mounted display as an optical device is shown.

[0158] Reference Figure 11 and Figure 12 A head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0159] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figures 1 to 10 The display devices 10 described are substantially the same, so no description of the first display device 10_1 and the second display device 10_2 will be provided.

[0160] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0161] The intermediate frame 1400 can be arranged between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0162] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert the image source input from the outside into digital video data DATA, and send the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0163] In one or more embodiments, the control circuit board 1600 can be used to send digital video data DATA corresponding to a left-eye image that is improved or optimized for the user's left eye to a first display device 10_1, and can be used to send digital video data DATA corresponding to a right-eye image that is improved or optimized for the user's right eye to a second display device 10_2. In one or more embodiments, the control circuit board 1600 can be used to send the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0164] The display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, an intermediate frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for viewing through the user's left eye and a second eyepiece 1220 for viewing through the user's right eye. Figure 11 and Figure 12 The first eyepiece 1210 and the second eyepiece 1220 are shown arranged separately, but embodiments of this disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0165] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0166] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. In one or more embodiments, when the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display 1000 can be as follows: Figure 13 The setup shown is an eyeglass frame, not a headband 1300.

[0167] In one or more embodiments, the head-mounted display 1000 may further include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0168] Figure 13 This is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure. For example, Figure 13 An example of an optical device is shown: a head-mounted display in the form of eyeglasses.

[0169] Reference Figure 13 The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path changing component 1070, and a display device housing 1200_1.

[0170] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0171] Figure 13 The illustration shows the display device housing 1200_1 positioned at the right end of the support frame 1030, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in these embodiments, the image on the display device 10_3 may be provided to the user's left eye. In one or more embodiments, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030 (e.g., simultaneously at both the left and right ends of the support frame 1030), and in these embodiments, the user may view the image displayed on the display device 10_3 through both the left and right eyes (e.g., simultaneously through both the left and right eyes).

[0172] The display device 10 according to one or more embodiments can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments may include the above-described display device 10, and may also include modules or devices with other additional functions in addition to the display device 10.

[0173] Figure 14 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure. (See also...) Figure 14 The electronic device 50 according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14. In one or more embodiments, the electronic device 50 may also include an input module 15, an output module 16, and / or a communication module 17.

[0174] Electronic device 50 can output one or more suitable pieces of information in the form of images via display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user via display module 11. Power module 14 may include a power module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power module to generate the desired or required power for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Output module 16 can be used to receive information other than images sent from processor 12, such as sound, touch, and / or light, and provide it to the user. Communication module 17 is responsible for sending and receiving information between electronic device 50 and external devices, and may include a receiver and a transmitter.

[0175] At least one of the components of the electronic device 50 described above may be included in the display device according to one or more of the above embodiments. In one or more embodiments, some of the modules that are functionally included in a single module may be included in the display device, while some other modules may be provided separately from the display device. For example, in one or more embodiments, the display device may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided in the form of other devices in the electronic device 50 besides the display device.

[0176] Figure 15 , Figure 16 and Figure 17 These are all schematic diagrams illustrating electronic devices according to various embodiments of the present disclosure. Figures 15 to 17 Examples of display devices 10 applied thereto to one or more suitable electronic devices according to one or more embodiments are shown.

[0177] Figure 15 Examples of electronic devices are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0178] In addition to the display module 11, the smartphone 10_1a may also include a communication module and / or an input module such as a touch sensor. The smartphone 10_1a can process information received through the communication module or the input module and display the processed information through the display module of the display device.

[0179] Similar to the smartphone 10_1a, each of the tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e may include a display module and an input module, and in some cases may also include a communication module.

[0180] Figure 16 An embodiment of an electronic device including a display module applied to a wearable electronic device is shown. The wearable electronic device may be smart glasses 10_2a, a head-mounted display 10_2b, and / or a smartwatch 10_2c, etc.

[0181] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that outputs an image and a reflector that reflects the output image and provides it to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0182] The smartwatch 10_2c may include a biometric sensor as an input device and may provide the user with biometric information identified by the biometric sensor through a display module.

[0183] Figure 17 An embodiment of an electronic device including a display module applied to a vehicle is shown. For example, the electronic device 10_4 can be applied to the vehicle's dashboard or central dashboard, or to a central information display (CID) placed in the vehicle's dashboard or an interior mirror display that replaces the side mirrors.

[0184] In this disclosure, it will be understood that the terms "comprising," "including," or "having," and variations thereof, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms "comprising," "including," "having," or other similar terms include or support the terms "consisting of" and "substantially consisting of," indicating the presence of the stated features, integrals, steps, operations, elements, and / or components, while other features, integrals, steps, operations, elements, components, and / or groups thereof are absent or substantially absent.

[0185] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” “an,” and “the” are intended to include the plural forms as well. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0186] In this disclosure, when expressions such as “at least one of…”, “one of…”, and “selected from…” follow a list of elements, they modify the entire list of elements rather than individual elements within that list. For example, “at least one of a, b, and c”, “at least one selected from a, b, and c”, “at least one selected from a to c”, etc., can indicate only a, only b, only c, both a and b (e.g., both a and b at the same time), both a and c (e.g., both a and c at the same time), both b and c (e.g., both b and c at the same time), all of a, b, and c, or variations thereof.

[0187] In the context of this application, unless otherwise specified, the term “use” and its variations may be considered synonymous with the term “utilize” and its variations, respectively.

[0188] As used herein, the terms “substantially,” “about,” “approximately,” or similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. “About” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” could mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0189] Any numerical range described herein is intended to include all subranges of the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and includes both the described minimum value of 1.0 and the described maximum value of 10.0), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, while any minimum numerical limit described in this disclosure is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this disclosure (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0190] The light-emitting elements, display modules, display devices, electronic devices / electronic devices, device manufacturing equipment, or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or on separate IC chips. Furthermore, various components of the device can be implemented on flexible printed circuit films, tape-on-a-carrier packages (TCPs), printed circuit boards (PCBs), or formed on a substrate. Additionally, various components of the device can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0191] It will be understood by those skilled in the art that, in view of the overall content of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or combined with each other in part or in whole, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0192] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the presented embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes. It will be understood that the scope of this disclosure is defined by the appended claims and their equivalents, not by the foregoing detailed description, and all modifications and variations derived from the claims and their equivalents fall within the scope of this disclosure.

Claims

1. A display device, the display device comprising: Base; Reflective electrodes are located on the substrate. A pixel-defining film is placed on the reflective electrode; The first electrode is on the pixel defining film; A light-emitting stack on the first electrode; The second electrode is on the light-emitting stack; as well as Multiple vias penetrate the pixel defining film between the reflective electrode and the first electrode to connect the reflective electrode and the first electrode. Each of the plurality of vias is arranged at a different position in a corresponding pixel among the plurality of pixels of the display device.

2. The display device according to claim 1, wherein, The plurality of pixels includes a first pixel and a second pixel. The first pixel includes a first sub-pixel and a second sub-pixel. The second pixel includes a third sub-pixel corresponding to the first sub-pixel and a fourth sub-pixel corresponding to the second sub-pixel. The vias are located in each of the first sub-pixels of the first pixel and the third sub-pixels of the second pixel, and The position of the via in the first sub-pixel is different from the position of the via in the third sub-pixel.

3. The display device according to claim 2, wherein, The via of the first sub-pixel penetrates the pixel defining film to connect the first electrode of the first sub-pixel and the reflective electrode of the first sub-pixel to each other.

4. The display device according to claim 2, wherein, The via of the third sub-pixel penetrates the pixel defining film to connect the first electrode of the third sub-pixel and the reflective electrode of the third sub-pixel to each other.

5. The display device according to claim 2, wherein, The edge of the first electrode of the second sub-pixel of the first pixel is superimposed on the pixel defining film.

6. The display device according to claim 5, wherein, The center of the first electrode of the second sub-pixel has a groove recessed toward the reflective electrode of the second sub-pixel.

7. The display device according to claim 2, wherein, The edge of the first electrode of the fourth sub-pixel of the second pixel is superimposed on the pixel defining film.

8. The display device according to claim 7, wherein, The center of the first electrode of the fourth sub-pixel has a groove recessed toward the reflective electrode of the fourth sub-pixel.

9. The display device according to claim 2, wherein, The distance between the first electrode of the first sub-pixel and the reflective electrode of the first sub-pixel is greater than the distance between the first electrode of the second sub-pixel and the reflective electrode of the second sub-pixel.

10. The display device according to claim 2, wherein, The distance between the first electrode of the third sub-pixel and the reflective electrode of the third sub-pixel is greater than the distance between the first electrode of the fourth sub-pixel and the reflective electrode of the fourth sub-pixel.

11. The display device according to claim 1, wherein, Each of the plurality of vias is superimposed on the first electrode in the emission region of each of the plurality of pixels.

12. The display device according to claim 1, wherein, The pixel-defining film includes: First pixel limiting film; A second pixel defining film is disposed on the first pixel defining film; and The third pixel defining film is on the second pixel defining film.

13. An electronic device, the electronic device comprising: Display device, having a screen, The display device includes: Base; Reflective electrodes are located on the substrate. A pixel-defining film is placed on the reflective electrode; The first electrode is on the pixel defining film; A light-emitting stack on the first electrode; The second electrode is on the light-emitting stack; and Multiple vias penetrate the pixel defining film between the reflective electrode and the first electrode to connect the reflective electrode and the first electrode. Each of the plurality of vias is arranged at a different position in a corresponding pixel among the plurality of pixels of the display device.

14. The electronic device according to claim 13, wherein, The plurality of pixels includes a first pixel and a second pixel. The first pixel includes a first sub-pixel and a second sub-pixel. The second pixel includes a third sub-pixel corresponding to the first sub-pixel and a fourth sub-pixel corresponding to the second sub-pixel. The vias are located in each of the first sub-pixels of the first pixel and the third sub-pixels of the second pixel, and The position of the via in the first sub-pixel is different from the position of the via in the third sub-pixel.

15. The electronic device according to claim 14, wherein, The via of the first sub-pixel penetrates the pixel defining film to connect the first electrode of the first sub-pixel and the reflective electrode of the first sub-pixel to each other.

16. The electronic device according to claim 14, wherein, The via of the third sub-pixel penetrates the pixel defining film to connect the first electrode of the third sub-pixel and the reflective electrode of the third sub-pixel to each other.

17. The electronic device according to claim 14, wherein, The edge of the first electrode of the second sub-pixel of the first pixel is superimposed on the pixel defining film.

18. The electronic device according to claim 17, wherein, The center of the first electrode of the second sub-pixel has a groove recessed toward the reflective electrode of the second sub-pixel.

19. The electronic device according to claim 14, wherein, The edge of the first electrode of the fourth sub-pixel of the second pixel is superimposed on the pixel defining film.

20. The electronic device according to claim 19, wherein, The center of the first electrode of the fourth sub-pixel has a groove recessed toward the reflective electrode of the fourth sub-pixel.

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