A chip packaging process and structure with a magnetic-mechanical composite positioning mechanism

Abstract

This invention discloses a chip packaging process and structure with a magnetic-mechanical composite positioning mechanism, comprising a substrate layer, a chip layer, a temporary reinforcement layer, and a packaging layer. The substrate layer has an annular positioning step on its surface, within which an annular magnetic pad is located. Signal pads are arranged on the outer side of the magnetic pad, and an insulating layer separates the two. The chip layer has a matching annular boss on its bottom surface corresponding to the positioning step. A magnetic adsorption layer corresponding to the magnetic pad is integrated inside the boss, and the chip's functional areas are arranged correspondingly to the signal pads. The temporary reinforcement layer surrounds the outside of the positioning step for temporary fixation of the chip to the substrate. The packaging layer covers the chip-substrate connection area. This invention achieves high-precision self-alignment during the mounting stage and stable positioning during the molding stage, reducing reliance on expensive precision equipment, decreasing production costs, and improving packaging yield and long-term product reliability.

Description

Technical Field

[0001] This invention belongs to the field of advanced semiconductor packaging technology, and relates to a chip packaging process and structure with a magnetic-mechanical composite positioning mechanism. Background Technology

[0002] In chip packaging, die bonding and molding are the core processes that determine product yield. With increasing packaging density and miniaturized chip size, traditional processes face two major challenges: Insufficient chip placement positioning accuracy: When transferring chips in batches on a large-area substrate, mechanical errors of the placement equipment can easily cause the chips to shift or deflect. Subsequent compensation methods require expensive precision equipment or multiple equipment working together, which significantly increases production costs.

[0003] Chip displacement during molding: The impact force generated by the resin flow during molding can easily cause the mounted chip to shift, affecting the reliability of circuit interconnection. This problem is more prominent in high-density stacked packaging and can lead to product failure in severe cases. Summary of the Invention

[0004] The purpose of this invention is to provide a chip packaging process and structure with a magnetic-mechanical composite positioning mechanism, which enables high-precision self-alignment during the mounting stage and stable positioning during the molding stage, reduces reliance on expensive precision equipment, reduces production costs, and improves packaging yield and long-term product reliability.

[0005] The objective of this invention is achieved through the following technical solution: A chip packaging structure with a magnetic-mechanical composite positioning mechanism includes: The substrate layer has an annular positioning step on its substrate surface, an annular magnetic pad is disposed inside the positioning step, a signal pad is arranged outside the magnetic pad, and an insulating layer is disposed between the magnetic pad and the signal pad. The chip layer has a matching annular protrusion on the bottom surface of the chip corresponding to the positioning step. A magnetic adsorption layer is integrated inside the annular protrusion. The magnetic adsorption layer corresponds to the magnetic pad. The chip functional area is laid out in correspondence with the signal pad. A temporary reinforcement layer is provided around the outside of the positioning step to temporarily fix the chip to the substrate; The encapsulation layer covers the area where the chip connects to the substrate, and the positioning step, magnetic pad, annular boss, magnetic adsorption layer and temporary reinforcement layer are all embedded in the encapsulation layer.

[0006] As a further improvement of the present invention, the fitting gap between the positioning step and the annular boss is 0.5-1μm, and the magnetic attraction force between the magnetic pad and the magnetic adsorption layer is 0.8-1.2N.

[0007] As a further improvement of the present invention, the materials of the magnetic pad and the magnetic adsorption layer are selected from one or a combination of two of cobalt-nickel alloy and nickel-iron alloy, and the thickness is 5-10μm.

[0008] As a further improvement of the present invention, the insulating isolation layer is made of SiO2 or silicon nitride, has a thickness of 2-3 μm, and an insulation resistance ≥10¹²Ω.

[0009] As a further improvement of the present invention, the sidewall inclination angle of the annular boss is 5-10°, and the temporary reinforcement layer is a low-temperature curing adhesive with a shrinkage rate ≤0.5%.

[0010] A chip packaging process with a magnetic-mechanical composite positioning mechanism includes the following steps: S1. Substrate prefabrication process: An annular positioning step is fabricated on the substrate surface using LDI direct imaging technology, followed by deposition of annular magnetic pads and completion of the fabrication of insulating isolation layer and signal pads. S2. Chip pretreatment process: An annular protrusion is made at the corresponding position on the bottom surface of the chip. A magnetic adsorption layer is deposited on the inner side of the annular protrusion and then annealed. S3, Composite positioning and mounting process: The chip is initially placed in the positioning area of ​​the substrate, and automatic alignment is achieved by the opposite polarity adsorption of the magnetic pad and the magnetic adsorption layer. The annular boss and the positioning step are fitted together to form a mechanical limit. S4. Temporary reinforcement process: Apply low-temperature curing adhesive to the outside of the positioning step and cure at 120℃ for 30 minutes to form a temporary reinforcement layer; S5. Molding process: Inject molding resin, pour under gradient pressure and then cure at high temperature. The composite positioning structure composed of the annular boss and the positioning step resists the impact of resin flow. S6. Subsequent processes: sequentially perform rewiring fabrication, substrate thinning, cutting and separation, and complete the packaging.

[0011] As a further improvement of the present invention, the positioning step in step S1 is fabricated by LDI direct imaging technology with a concentricity error ≤ ±0.3μm; the magnetic pad is deposited by magnetron sputtering at a deposition temperature of 150-200℃.

[0012] As a further improvement of the present invention, the annular boss in step S2 is fabricated by DRIE etching, the etching gas is a mixture of SF6 / O2, and the etching rate is 1-2 μm / min.

[0013] As a further improvement of the present invention, the casting pressure of the molding resin in step S5 is 0.8-1.2 MPa, the curing temperature is 150°C, and the curing time is 60 min.

[0014] The above technical solution has the following beneficial effects: 1. Through the innovative composite structure design of "magnetic self-alignment + mechanical interlocking" and the phased optimization of process parameters, the alignment accuracy of chip mounting can be controlled within ±1.5μm. During the molding process, the displacement of the chip can be controlled below 0.5μm, which is far superior to traditional processes (usually exceeding 2μm), ensuring the reliability of high-density interconnects.

[0015] 2. It is compatible with existing mature processes such as LDI exposure and magnetron sputtering, which is expected to reduce production costs by more than 30% and reduce dependence on high-priced precision placement equipment.

[0016] 3. The packaging yield has been increased from 85-90% in traditional processes to over 98%, significantly reducing scrap losses caused by misalignment and molding displacement.

[0017] 4. No need to introduce complex external magnetic field equipment; the built-in magnetic structure and signal area isolation design avoid electromagnetic interference.

[0018] 5. The composite positioning structure enhances the connection strength between the chip and the substrate, with an interlayer shear strength of ≥25MPa. After 1000 hours of high temperature and high humidity (85℃ / 85%RH) reliability testing, the resistance change rate is ≤3%, and the overall product reliability is improved by more than 40%. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0020] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0021] Figure 1 This is a partial three-dimensional schematic diagram of the chip packaging structure provided by the present invention.

[0022] Figure 2 This is a schematic diagram of the chip packaging structure provided by the present invention.

[0023] Figure 3 This is a schematic flowchart of the preparation method provided by the present invention.

[0024] In the picture: 1. Substrate; 11. Positioning step; 12. Signal pad; 13. Magnetic pad; 2. Chip; 21. Annular boss; 22. Magnetic adsorption layer; 3. Temporary reinforcement layer; 4. Encapsulation layer. Detailed Implementation

[0025] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0026] like Figures 1-3 As shown, a chip packaging structure with a magnetic-mechanical composite positioning mechanism mainly includes a substrate layer, a chip layer, a temporary reinforcement layer 3, and a packaging layer 4. The structures of each layer work together to achieve precise positioning, stable connection, and reliable packaging of the chip and the substrate. The specific structure is as follows: In the substrate layer, an annular positioning step 11 is integrally formed on the surface of substrate 1. The cross-sectional shape of the positioning step 11 can be set to a rectangular, trapezoidal, or similar form according to actual assembly requirements, and its size is adapted to the annular boss 21 of the chip layer. An annular magnetic pad 13 is fixedly disposed on the inner side of the positioning step 11. Signal pads 12 are evenly distributed on the outer side of the magnetic pads 13. The signal pads 12 are used to realize the electrical signal transmission between the chip and the substrate. An insulating isolation layer is provided between the magnetic pads 13 and the signal pads 12 to avoid signal interference or short circuit between them.

[0027] On the bottom surface of chip 2 of the chip layer, a matching annular boss 21 is integrally formed corresponding to the positioning step 11. The annular boss 21 and the positioning step 11 achieve mechanical positioning through concave-convex cooperation, and the cooperation gap can be reasonably set according to the packaging accuracy requirements. A magnetic adsorption layer 22 is integrated inside the annular boss 21. The magnetic adsorption layer 22 and the magnetic pad 13 are precisely aligned, and the two assist in positioning through magnetic adsorption to ensure that the chip functional area and the signal pad 12 are accurately aligned.

[0028] A temporary reinforcement layer 3 is arranged around the outside of the positioning step 11 to temporarily fix the chip 2 and the substrate 1 during the assembly process, preventing the chip from shifting during assembly. The encapsulation layer 4 covers the entire connection area between the chip 2 and the substrate 1. The positioning step, magnetic pad, annular boss, magnetic adsorption layer and temporary reinforcement layer 3 are all embedded in the encapsulation layer 4 to achieve sealing protection of the overall structure and improve the reliability and stability of the encapsulation structure.

[0029] In this packaging structure, the positioning step 11 and the annular boss 21 adopt a precise concave-convex fit design, with a fit clearance set at 0.5-1μm. This clearance dimension can be finely adjusted within the same precision range according to the actual packaging precision requirements, ensuring the accuracy of mechanical positioning while reserving assembly allowance. The sidewall tilt angle of the annular boss 21 is 5-10°. The tilt angle can be designed within the same angle range according to the assembly guidance requirements, facilitating rapid alignment and assembly of the chip layer and the substrate layer.

[0030] Furthermore, the materials of the magnetic pad 13 and the magnetic adsorption layer 22 are selected from one or a combination of cobalt-nickel alloy and nickel-iron alloy. The thickness of both is 5-10μm, and the thickness can be adjusted to match the magnetic attraction force requirements. The magnetic attraction force between the two is controlled at 0.8-1.2N. This magnetic attraction force range can effectively assist mechanical positioning, avoid assembly misalignment, and at the same time, will not cause stress damage to the chip and substrate.

[0031] Furthermore, the insulating layer between the magnetic pad 13 and the signal pad 12 is made of a material that... Alternatively, silicon nitride, with a thickness of 2-3 μm, has an insulation resistance ≥10¹²Ω, which can effectively block electrical signal interference between the two and prevent short circuit risk.

[0032] Furthermore, the temporary reinforcement layer 3 uses a low-temperature curing adhesive with a shrinkage rate of ≤0.5%, which can reliably fix the chip during the chip assembly process. After curing, the chip will not shift due to shrinkage deformation, thus ensuring the stability of the overall packaging structure.

[0033] A chip packaging process with a magnetic-mechanical composite positioning mechanism, such as Figure 3 As shown, it includes the following steps: S1. Substrate Prefabrication Process: An annular positioning step 11 is fabricated on the surface of substrate 1 using LDI direct imaging technology, with its concentricity error controlled within ≤±0.3μm to ensure subsequent positioning accuracy. Subsequently, annular magnetic pads 13 are deposited inside the positioning step 11 using magnetron sputtering, with the deposition temperature controlled at 150-200℃ to ensure a strong bond to the magnetic pads 13. After the magnetic pads 13 are fabricated, an insulating layer and signal pads 12 are fabricated sequentially. The fabrication order of these two layers can be adjusted according to actual production needs to ensure reliable insulation and signal transmission functions.

[0034] S2. Chip Pre-processing: An annular protrusion 21 is fabricated on the bottom surface of chip 2 at the position corresponding to the substrate positioning step 11. This is achieved using the DRIE etching process, with an SF6 / O2 mixed gas used for etching. The etching rate is controlled at 1-2 μm / min to ensure precise protrusion dimensions. A magnetic adsorption layer 22 is deposited inside the annular protrusion 21. The deposition process can employ the same magnetron sputtering method as the magnetic pad 13. After deposition, chip 2 undergoes annealing. Annealing parameters can be appropriately adapted according to material characteristics to improve the magnetic properties and bonding stability of the magnetic adsorption layer 22, laying the foundation for subsequent magneto-mechanical composite positioning.

[0035] S3, Composite Positioning and Mounting Process: The pre-treated chip 2 is initially placed in the preset positioning area of ​​the substrate 1. Automatic and precise alignment is achieved by the opposite polarity adsorption of the magnetic pad 13 and the magnetic adsorption layer 22, ensuring alignment accuracy. At the same time, the annular protrusion 21 on the bottom of the chip 2 precisely engages with the positioning step 11 of the substrate 1, forming a reliable mechanical limit and effectively preventing horizontal displacement of the chip after mounting.

[0036] S4. Temporary reinforcement process: A low-temperature curing adhesive is uniformly coated on the outside of the positioning step 11. After curing at 120°C for 30 minutes, a temporary reinforcement layer 3 is formed. The curing parameters can be finely adjusted within a reasonable range according to the characteristics of the adhesive to achieve temporary fixation of the chip 2 and the substrate 1, and to prevent the chip from shifting during the subsequent molding process.

[0037] S5. Molding Process: Molding resin is injected into the encapsulation area using a gradient pressure casting method, with the casting pressure controlled between 0.8-1.2 MPa. It is then cured at 150℃ for 60 minutes. The composite positioning structure composed of the annular boss 21 and the positioning step 11 effectively resists the impact force generated by resin flow, ensuring that positioning accuracy is not affected. The encapsulation layer 4 formed after curing provides sealing protection for the internal structure, improving overall encapsulation reliability. Example

[0038] The substrate is made of BT resin organic carrier board with a thickness of 0.2mm; the inner diameter of the annular positioning step is 1.2mm, the outer diameter is 1.4mm, and the height is 8μm; the magnetic pad is made of cobalt-nickel alloy with a thickness of 8μm; the insulating layer is made of SiO2 with a thickness of 2μm; and the signal pad is made of copper with a diameter of 0.08mm.

[0039] The chip specifications are as follows: dimensions 1mm×1mm×0.1mm; inner diameter of the annular boss is 1.2mm, outer diameter is 1.4mm, height is 7μm, and sidewall tilt angle is 8°; the magnetic adsorption layer is made of nickel-iron alloy with a thickness of 8μm; the diameter of the chip functional area electrode is 0.08mm.

[0040] Process parameters: LDI exposure accuracy ±0.3μm; magnetron sputtering power 100-150W, deposition rate 0.5-1nm / s; magnetic adsorption force 1.0N; low-temperature curing adhesive is epoxy resin with viscosity 1000-1500mPa·s; molding resin is low-flow impact epoxy molding compound with casting pressure 1.0MPa and curing temperature 150℃ / 60min.

[0041] The detailed implementation steps are as follows: 1. Substrate Preparation: A BT resin substrate was selected and ultrasonically cleaned (40 kHz, 10 min) to remove oil, followed by copper plating (1 μm thickness). A ring-shaped positioning step was fabricated using LDI technology. A cobalt-nickel alloy magnetic pad was deposited within the step (deposition temperature 180℃). A SiO2 insulating layer was deposited using PECVD, and the pads were exposed through windows. Electrical testing was performed to ensure an insulation resistance ≥ 10 Ω·cm. 12 Ω.

[0042] 2. Chip pretreatment: A ring-shaped bump is fabricated on the bottom surface of the silicon chip by DRIE etching (the etching gas is a mixture of SF6 / O2, and the etching rate is 1-2 μm / min); a nickel-iron alloy magnetic adsorption layer is deposited on the inner side of the bump by magnetron sputtering; after deposition, it is annealed at 200℃ for 30 min to enhance adhesion; insulation and dimensional inspection are performed to ensure that the dimensional error of the bump is ≤ ±0.1 μm.

[0043] 3. Composite positioning and mounting: Using conventional chip mounting equipment, the chip is initially placed in the positioning area of ​​the substrate (initial positioning error within ±5μm); the magnetic pad and the adsorption layer are attracted by opposite poles, which drives the chip to automatically correct and align, with a positioning accuracy of ±1.0μm; the annular boss and the positioning step are engaged to form a mechanical limit; the positioning accuracy is verified by optical inspection equipment.

[0044] 4. Temporary reinforcement: Apply a ring-shaped low-temperature curing adhesive (0.4 mm wide and 5 μm thick) to the outside of the positioning step using a dispensing process; place the component in an oven and cure at 120°C for 30 minutes to form a temporary fixing structure; check the integrity of the reinforcement layer.

[0045] 5. Molding: Place the component into the molding mold and preheat to 80℃ for 30 minutes; inject epoxy molding compound (pouring speed 0.5-1mm / s, pouring pressure 1.0MPa); cure at 150℃ for 60 minutes, and monitor temperature uniformity by infrared thermal imaging; after molding, detect the chip displacement to ensure ≤0.4μm.

[0046] 6. Subsequent processes: After molding, the back of the substrate is ground to thin it to 0.15mm; rewiring is fabricated through photolithography and electroplating; laser cutting is used for separation (cutting speed 50-100mm / s); electrical and reliability tests are performed, and the substrate is packaged and shipped after passing the tests.

[0047] The product prepared in Example 1 was tested, and its performance results are as follows: Positioning accuracy: Chip mounting alignment accuracy ±1.0μm, chip offset after molding ≤0.4μm.

[0048] Electrical performance: chip-to-substrate connection resistance ≤5mΩ, insulation resistance ≥10^12Ω, signal transmission attenuation ≤0.1dB (1GHz).

[0049] Mechanical properties: interlaminar shear strength 28MPa, after 1000 thermal shocks (-40℃~125℃, 30min per cycle), the chip showed no detachment or displacement.

[0050] Reliability: After 1000 hours of high temperature and high humidity testing (85℃ / 85%RH), the resistance change rate is ≤2%, and the packaging yield reaches 98.5%, which is 12% higher than that of traditional processes.

[0051] Therefore, this invention, through its innovative composite structure design of "magnetic self-alignment + mechanical interlocking" and phased process parameter optimization, can control the alignment accuracy of chip mounting within ±1.5μm, and the chip displacement during molding can be controlled below 0.5μm, which is far superior to traditional processes (usually exceeding 2μm). This achieves high-precision self-alignment in the mounting stage and stable positioning in the molding stage, improving packaging yield and long-term product reliability.

[0052] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0053] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip packaging structure with a magneto-mechanical composite positioning mechanism, characterized in that, include: The substrate layer has an annular positioning step on its substrate surface, an annular magnetic pad is disposed inside the positioning step, a signal pad is arranged outside the magnetic pad, and an insulating layer is disposed between the magnetic pad and the signal pad. The chip layer has a matching annular protrusion on the bottom surface of the chip corresponding to the positioning step. A magnetic adsorption layer is integrated inside the annular protrusion. The magnetic adsorption layer corresponds to the magnetic pad. The chip functional area is laid out in correspondence with the signal pad. A temporary reinforcement layer is provided around the outside of the positioning step to temporarily fix the chip to the substrate; The encapsulation layer covers the area where the chip connects to the substrate, and the positioning step, magnetic pad, annular boss, magnetic adsorption layer and temporary reinforcement layer are all embedded in the encapsulation layer.

2. The chip packaging structure according to claim 1, characterized in that, The gap between the positioning step and the annular boss is 0.5-1μm, and the magnetic attraction between the magnetic pad and the magnetic adsorption layer is 0.8-1.2N.

3. The chip packaging structure according to claim 1, characterized in that, The materials of the magnetic pad and the magnetic adsorption layer are selected from one or a combination of two of cobalt-nickel alloy and nickel-iron alloy, and the thickness is 5-10μm.

4. The chip packaging structure according to claim 1, characterized in that, The insulating layer is made of SiO2 or silicon nitride, with a thickness of 2-3 μm and an insulation resistance ≥10 Ω·cm. 12 Ω.

5. The chip packaging structure according to claim 1, characterized in that, The sidewall inclination angle of the annular boss is 5-10°, and the temporary reinforcement layer is a low-temperature curing adhesive with a shrinkage rate of ≤0.5%.

6. A chip packaging process as described in claim 1, characterized in that, Includes the following steps: S1. Substrate prefabrication process: An annular positioning step is fabricated on the substrate surface using LDI direct imaging technology, followed by deposition of annular magnetic pads and completion of the fabrication of insulating isolation layer and signal pads. S2. Chip pretreatment process: An annular protrusion is made at the corresponding position on the bottom surface of the chip. A magnetic adsorption layer is deposited on the inner side of the annular protrusion and then annealed. S3, Composite positioning and mounting process: The chip is initially placed in the positioning area of ​​the substrate, and automatic alignment is achieved by the opposite polarity adsorption of the magnetic pad and the magnetic adsorption layer. The annular boss and the positioning step are fitted together to form a mechanical limit. S4. Temporary reinforcement process: Apply low-temperature curing adhesive to the outside of the positioning step and cure at 120℃ for 30 minutes to form a temporary reinforcement layer; S5. Molding process: Inject molding resin, pour under gradient pressure and then cure at high temperature. The composite positioning structure composed of the annular boss and the positioning step resists the impact of resin flow. S6. Subsequent processes: sequentially perform rewiring fabrication, substrate thinning, cutting and separation, and complete the packaging.

7. The chip packaging process according to claim 6, wherein the positioning step in step S1 is fabricated by LDI direct imaging technology with a concentricity error ≤ ±0.3μm; the magnetic pad is deposited by magnetron sputtering at a deposition temperature of 150-200℃.

8. The chip packaging process according to claim 6, wherein the annular protrusion in step S2 is fabricated by DRIE etching, the etching gas is an SF6 / O2 mixture, and the etching rate is 1-2 μm / min.

9. The chip packaging process according to claim 6, wherein the casting pressure of the molding resin in step S5 is 0.8-1.2 MPa, the curing temperature is 150°C, and the curing time is 60 min.

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