Time measurement unit dynamic frequency multiplication method and apparatus

Abstract

The application relates to a time measurement unit dynamic frequency multiplication method and device. The method comprises the following steps: acquiring an input clock domain frequency, and determining a frequency multiplication coefficient and a frequency division coefficient based on the input clock domain frequency; determining a current sampling clock frequency based on the frequency multiplication coefficient and the frequency division coefficient; under the condition that a phase difference between a to-be-measured signal and the current sampling clock is cyclic, adjusting the frequency division coefficient, and re-determining the current sampling clock frequency based on the frequency multiplication coefficient and the adjusted frequency division coefficient until the target frequency division coefficient is obtained under the condition that the phase difference between the to-be-measured signal and the current sampling clock is not cyclic. The method avoids phase difference cycle overlap, and thus does not need to restart services multiple times.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a dynamic frequency multiplication method and apparatus for a time measurement unit. Background Technology

[0002] The clock used by the TMU module of a digital board is often coupled with the domain clock (test machine master clock) of other services. TMU jitter measurement relies on Carry8 calibration of the code density algorithm, but this calibration method itself has certain defects, resulting in inaccurate delays in the first 16 taps of the carry chain. Therefore, when the test signal output by the chip under test falls in the first 16 taps of the carry chain, it affects the jitter measurement accuracy of the TMU module. Generally, dynamic phase locking is used to change the position of the test signal falling in the carry chain (i.e., change the phase of the test signal). The TmuClk sampling clock waveform and the test signal waveform are from the same source, both derived from the domain clock, which makes it more likely that the test signal will fall in the first 16 taps of the carry chain. In addition, the frequent cyclic overlap of phase differences between the test signal waveform and the sampling clock waveform will lead to inaccurate TMU module jitter measurement accuracy.

[0003] In existing technologies, changing the phase of the signal under test by repeatedly restarting the sub-board service clock can reduce the probability that the signal under test falls within the first 16 taps of the carry chain, but it does not completely solve the problem of jitter measurement accuracy and has poor usability.

[0004] Therefore, there is an urgent need for a method to solve the problem of frequent cyclic overlap between the phase of the waveform of the signal under test and the sampling clock waveform. Summary of the Invention

[0005] Therefore, it is necessary to provide a dynamic frequency multiplication method and apparatus for a time measurement unit that can avoid phase difference cyclic overlap in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a dynamic frequency multiplication method for a time measurement unit, comprising:

[0007] Obtain the input clock domain frequency, and determine the multiplication factor and division factor based on the input clock domain frequency;

[0008] The current sampling clock frequency is determined based on the frequency multiplication factor and frequency division factor.

[0009] When the phase difference between the signal under test and the current sampling clock is cyclic, the frequency division coefficient is adjusted, and the current sampling clock frequency is re-determined based on the frequency multiplication coefficient and the adjusted frequency division coefficient, until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target frequency division coefficient.

[0010] In one embodiment, the method further includes:

[0011] Based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test, detect whether the phase difference between the signal under test and the current sampling clock is cyclic.

[0012] In one embodiment, detecting whether the phase difference between the signal under test and the current sampling clock is cyclic, based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test, includes:

[0013] Determine the ratio of the current sampling clock frequency to the frequency of the signal under test output by the chip under test;

[0014] Based on the ratio and the number of cycles for each error phase difference, it is determined whether the phase difference between the signal under test and the current sampling clock is cyclic.

[0015] In one embodiment, detecting whether the phase difference between the signal under test and the current sampling clock is cyclic based on the ratio and the number of cycles of each error phase difference includes:

[0016] Based on the ratio and the number of cycles for each error phase difference, the offsets of the current sampling clock are obtained.

[0017] If at least one offset satisfies a preset condition, it is determined that the phase difference between the signal under test and the current sampling clock has a cycle; otherwise, it is determined that the phase difference between the signal under test and the current sampling clock does not have a cycle.

[0018] In one embodiment, obtaining the offsets of the current sampling clock based on the ratio and the number of cycles for each error phase difference includes:

[0019] The ratios are multiplied by the number of cycles for each error phase difference to obtain the detection data.

[0020] Extract the fractional part of each of the detection data as the offset of the current sampling clock;

[0021] If at least one offset satisfies a preset condition, the phase difference between the signal under test and the current sampling clock is determined to be cyclic, including:

[0022] If the offset is less than the first threshold or greater than the second threshold, it is determined that there is a cycle in the phase difference between the signal under test and the current sampling clock, the second threshold is greater than the first threshold, and both the second threshold and the first threshold are greater than or equal to 0 and less than 1.

[0023] In one embodiment, prior to obtaining the input clock domain frequency, the process includes:

[0024] Receive configuration parameter values;

[0025] Based on the configuration parameter values, the corresponding jitter measurement dynamic frequency multiplication rule is determined. If the jitter measurement mode is determined based on the configuration parameter values, the step of obtaining the input clock domain frequency continues.

[0026] In one embodiment, the method further includes:

[0027] If, based on the configuration parameter values, it is determined that the mode is neither jitter measurement mode nor cross-daughterboard synchronous trigger mode, the input clock domain frequency is obtained;

[0028] The multiplication factor and division factor are determined based on the input clock domain frequency.

[0029] In one embodiment, determining the multiplication factor and division factor based on the input clock domain frequency includes:

[0030] The multiplication factor is determined based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager;

[0031] The frequency multiplication factor and the input clock domain frequency are used to obtain the frequency multiplication factor;

[0032] The frequency division coefficient is obtained based on the frequency multiplication and the expected time measurement sampling clock frequency.

[0033] In one embodiment, determining the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager includes:

[0034] In jitter measurement mode, candidate values ​​for the multiplication factor are obtained based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; a reference candidate value is obtained based on the candidate values ​​for the multiplication factor; and the multiplication factor is obtained based on the reference candidate value.

[0035] If, based on the configuration parameter values, it is determined that the mode is neither a jitter measurement mode nor a cross-subboard synchronous trigger mode, candidate values ​​for the multiplication factor are obtained based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; a reference candidate value is obtained as the multiplication factor based on the candidate values ​​for the multiplication factor.

[0036] Secondly, this application also provides a dynamic frequency multiplication method for a time measurement unit, applied to an FPGA, comprising:

[0037] Receive the frequency multiplication coefficient and frequency division coefficient determined based on the above-described time measurement unit dynamic frequency multiplication method;

[0038] The sampling clock waveform corresponding to the time measurement unit is generated based on the frequency multiplication factor and the frequency division factor.

[0039] Thirdly, this application also provides a dynamic frequency multiplication device for a time measurement unit, comprising:

[0040] The first coefficient determination module is used to obtain the input clock domain frequency and determine the multiplication coefficient and division coefficient based on the input clock domain frequency.

[0041] The current sampling clock frequency determination module is used to determine the current sampling clock frequency based on the frequency multiplication factor and the frequency division factor;

[0042] The second coefficient determination module is used to adjust the frequency division coefficient when the phase difference between the signal under test and the current sampling clock is cyclic, and to redetermine the current sampling clock frequency based on the multiplication coefficient and the adjusted frequency division coefficient, until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target frequency division coefficient.

[0043] Fourthly, this application also provides a dynamic frequency multiplication device for a time measurement unit, applied to an FPGA, the device comprising:

[0044] The receiving module is used to receive the frequency multiplication coefficient and frequency division coefficient determined by the dynamic frequency multiplication device of the time measurement unit as described in any of the above embodiments;

[0045] The sampling clock waveform generation module is used to generate the sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication coefficient and the frequency division coefficient.

[0046] The aforementioned dynamic frequency multiplication method and apparatus for time measurement units acquires the input clock domain frequency and determines the frequency multiplication coefficient and frequency division coefficient based on the input clock domain frequency; determines the current sampling clock frequency based on the frequency multiplication coefficient and frequency division coefficient; adjusts the frequency division coefficient when the phase difference between the signal under test and the current sampling clock is cyclic, and redetermines the current sampling clock frequency based on the frequency multiplication coefficient and the adjusted frequency division coefficient, until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target frequency division coefficient. This avoids the problem of cyclic overlap of phase differences, thereby eliminating the need for multiple service restarts. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1This is an application environment diagram of the dynamic frequency multiplication method of the time measurement unit in one embodiment; Figure 2 This is a schematic diagram of the dynamic frequency multiplication of the jitter measurement mode in one embodiment; Figure 3 This is a flowchart of a dynamic frequency multiplication method under jitter measurement mode in one embodiment; Figure 4 This is a schematic diagram of dynamic frequency multiplication in one embodiment; Figure 5 This is a schematic diagram of a dynamic frequency doubling method in one embodiment; Figure 6 This is a flowchart illustrating the dynamic frequency multiplication method of the time measurement unit in another embodiment; Figure 7 This is a schematic diagram of dynamic frequency multiplication across the same digital board card or across different digital board cards in one embodiment; Figure 8 Here is a flowchart of the coefficient determination step in one embodiment; Figure 9 This is a flowchart illustrating the dynamic frequency multiplication method of the time measurement unit in another embodiment; Figure 10 This is an overall flowchart of the dynamic frequency multiplication method in one embodiment; Figure 11 This is a structural block diagram of the dynamic frequency multiplication device of the time measurement unit in one embodiment; Figure 12 This is a structural block diagram of the dynamic frequency multiplication device of the time measurement unit in another embodiment; Figure 13 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0051] The clock used by the TMU module of a digital board is often coupled with the DomainClk (test machine master clock) of other services. In actual chip testing, there are many complex problems such as DomainClk being changed, TMU measurements across digital boards not being able to be triggered synchronously, and the TmuClk sampling clock waveform and the waveform of the signal under test being from the same source, resulting in a fixed signal phase.

[0052] Combination Figure 1 As shown, Figure 1 This is an environmental diagram illustrating a dynamic frequency multiplication method for a time measurement unit in an example. In this embodiment, the terminal can configure parameters via an API, drive the execution of the corresponding dynamic frequency multiplication rule based on the configured parameters, obtain the frequency multiplication coefficient and the frequency division coefficient, and send the frequency multiplication coefficient and the frequency division coefficient to the FPGA so that the FPGA can use the frequency multiplication coefficient and the frequency division coefficient to generate the sampling clock waveform corresponding to the time measurement unit.

[0053] In some optional embodiments, the method includes: receiving configuration parameter values; and determining a corresponding frequency multiplication rule based on the configuration parameter values. The frequency multiplication rules include cross-subboard synchronous triggering frequency multiplication rules, jitter measurement dynamic frequency multiplication rules, and conventional dynamic frequency multiplication rules. The cross-subboard synchronous triggering frequency multiplication rule corresponds to a cross-subboard synchronous triggering mode, the jitter measurement dynamic frequency multiplication rule corresponds to a jitter measurement mode, and the conventional dynamic frequency multiplication rule corresponds to a mode that is neither a jitter measurement mode nor a cross-subboard synchronous triggering mode.

[0054] Specifically, the driver can receive configuration parameters sent by the terminal via API. These configuration parameters can include information such as Pinlist and MeasureMode. Pinlist is the board identifier and channel identifier. Each pin can correspond to multiple channels, for example, pin1 represents slot1CH1 and slot1CH3. MeasureMode is the measurement mode.

[0055] After receiving the Pinlist and MeasureMode, the driver stores them in the driver cache and parses them to determine whether it is a jitter measurement mode or whether cross-daughterboard synchronous triggering of TMU measurement is required. It then generates JitterFlag and SyncFlag. If it is a jitter measurement mode, JitterFlag is set to true. If cross-daughterboard synchronous triggering of measurement mode is required (MeasureMode is inter-channel delay measurement and Pinlist information includes two channels of the same site on different Fe boards (i.e., daughter boards), SyncFlag is set to true. In other scenarios, both Flags are set to false.

[0056] This allows the system to determine the corresponding measurement mode based on JitterFlag and SyncFlag, and then execute the corresponding dynamic frequency doubling rules. For details on the limitations of each dynamic frequency doubling rule, please refer to the following text.

[0057] In one embodiment, combined with Figure 2 As shown, Figure 2 This is a schematic diagram of dynamic frequency multiplication in a jitter measurement mode in one embodiment. The Hybrid Clock Manager (MMCM) multiplies and then divides the received input clock domain (DomainClk) waveform to obtain the TmuClk sampling clock waveform. The TMU module receives the waveform of the signal under test and the TmuClk sampling clock waveform. Other services also receive the DomainClk waveform and output a service clock pattern as a reference clock for the chip under test. Figure 2 This indicates that the waveform of the signal under test output by the chip under test and the TmuClk sampling clock waveform are from the same source. Existing technology changes the phase of the signal under test by repeatedly restarting the daughterboard service clock pattern. Although this can reduce the probability that the signal under test falls in the first 16 tap intervals of the carry chain, it does not completely solve the problem of jitter measurement accuracy and has poor usability.

[0058] For example, a situation where the phase difference between the signal under test (SUT) and the sampling clock is cyclic can easily occur. The first time the phase difference between the rising edge of the sampling clock and the rising edge of the SUT is 100ps, and the second time the phase difference is 100ps, this is recorded as one phase difference cycle. Near a certain rising edge of the sampling clock, there is a rising edge of the SUT, which means two phases overlap (or rising edges overlap). The relationship between the sampling clock and the carry chain is that every one sampling clock cycle, the result of the SUT is collected once from the carry chain. When the SUT and the sampling clock are from the same source, the edge of the SUT is likely to fall into the first 16 tap intervals of the carry chain. If such a phase relationship occurs repeatedly in the 4096 edges of the SUT, this phenomenon is called phase difference cyclic overlap.

[0059] This application proposes a dynamic frequency multiplication method under jitter measurement mode, starting from the perspective of frequent cyclic overlap of phase difference between the waveform under test and the sampling clock waveform, to solve the problem of frequent cyclic overlap of phase difference between the waveform under test and the sampling clock waveform, thereby solving the problem of inaccurate jitter measurement accuracy of TMU module.

[0060] This application introduces a dynamic frequency multiplication method under jitter measurement mode. In some optional embodiments, when the frequency multiplication rule determined based on configuration parameters is a dynamic frequency multiplication rule for jitter measurement, the multiplication coefficient and division coefficient are obtained based on the dynamic frequency multiplication rule for jitter measurement, and then combined with... Figure 3 As shown, Figure 3 This is a flowchart of a dynamic frequency multiplication method under jitter measurement mode in one embodiment, the dynamic frequency multiplication method further includes:

[0061] S302: Obtain the input clock domain frequency and determine the multiplication factor and division factor based on the input clock domain frequency.

[0062] For details on the specific limitations of determining the jitter measurement mode based on the configuration parameter values, please refer to the above text.

[0063] The input clock domain frequency is the current input clock domain frequency, Frequency_Domain. In this application, the multiplication factor and division factor can be determined based on the input clock domain frequency. For example, the multiplication factor can be determined based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager. The division factor is obtained based on the multiplication factor, the input clock domain frequency, and the expected multiplication frequency of the hybrid clock manager. Specific limitations are detailed below.

[0064] S304: Determine the current sampling clock frequency based on the multiplication factor and division factor.

[0065] The current sampling clock frequency is determined based on the calculated multiplication and division coefficients and the input clock domain frequency, as shown in the following formula:

[0066] Frequency_TmuClkTemp=Frequency_Domain*MulitFreqData / DemulitFreqData;

[0067] Where Frequency_TmuClkTemp is the current sampling clock frequency, MulitFreqData is the multiplication factor, DemulitFreqDat is the division factor, and Frequency_Domain is the current input clock domain frequency.

[0068] S306: When the phase difference between the signal under test and the current sampling clock is cyclic, adjust the frequency division coefficient, and based on the frequency multiplication coefficient and the adjusted frequency division coefficient, redetermine the current sampling clock frequency until the phase difference between the signal under test and the current sampling clock is no longer cyclic, and obtain the target frequency division coefficient.

[0069] This application can detect whether there is a cycle in the phase difference between the signal under test (SUT) and the current output clock based on the frequency of the SUT signal (Frequency_Signal) and the current sampling clock frequency (Frequency_TmuClkTemp). The specific detection method can be found below.

[0070] If the phase difference between the signal under test and the current sampling clock is cyclic, the current sampling clock frequency needs to be adjusted, for example, by adjusting the frequency division coefficient, to regenerate the current sampling clock frequency until the phase difference between the signal under test and the current sampling clock is no longer cyclic.

[0071] In this application, "cycle" is a degree term, meaning that if the phase difference between the signal under test and the current sampling clock is not easily cycled, then the phase difference between the signal under test and the current sampling clock is determined to be non-cycled; if the phase difference between the signal under test and the current sampling clock is easily cycled, then the phase difference between the signal under test and the current sampling clock is determined to be cycled.

[0072] The aforementioned dynamic frequency multiplication method for time measurement units obtains the input clock domain frequency and determines the multiplication coefficient and division coefficient based on the input clock domain frequency; based on the multiplication coefficient and division coefficient, the current sampling clock frequency is determined; when the phase difference between the signal under test and the current sampling clock is cyclic, the division coefficient is adjusted, and based on the multiplication coefficient and the adjusted division coefficient, the current sampling clock frequency is re-determined until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target division coefficient. This avoids the problem of easy cyclic overlap of phase differences, and therefore eliminates the need to restart the service clock multiple times.

[0073] In some optional embodiments, the method further includes: detecting whether the phase difference between the signal under test and the current sampling clock is cyclic, based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test.

[0074] The phase difference cyclic relationship between the signal under test and the current sampling clock is related to the frequencies of the signal under test and the current sampling clock.

[0075] In some optional embodiments, detecting whether the phase difference between the signal under test and the current output clock is cyclic, based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test, includes: determining the ratio of the current sampling clock frequency to the frequency of the signal under test output by the chip under test; and detecting whether the phase difference between the signal under test and the current sampling clock is cyclic based on the ratio and the number of cycles of each error phase difference.

[0076] The ratio of the current sampling clock frequency to the frequency of the signal under test output by the chip under test is determined by the following formula:

[0077] DataTemp= Frequency_TmuClkTemp / Frequency_Signal

[0078] In this application, during carry chain calibration, if a certain interval is inaccurate and more than x (empirical value x=1000) edges fall within this interval, it will significantly affect the jitter measurement accuracy. However, if the number of phase difference cycle periods m of the signal under test is more than 5, then at most 4096 (FPGA acquisition depth, fixed value) / 5=819 edges will fall within this area. In this case, the carry chain calibration data has a smaller impact on the jitter measurement accuracy. Since 1≤number of cycle periods m≤N, where N is a positive integer, N≤4096 / x, where x is 1000, and N≤4.1, the number of error phase difference cycle periods in this application includes 1, 2, 3, and 4. In this embodiment, when the number of error phase difference cycle periods is 1-4, that is, when the number of phase difference cycle periods of the signal under test is 1-4, the carry chain calibration has a significant impact on the jitter measurement accuracy, and the phase difference between the signal under test and the sampling clock waveform is prone to cycling. In other embodiments, the number of cycles for each error phase difference may include other values, which can be set as needed by those skilled in the art.

[0079] Based on the ratio and the number of cycles of each error phase difference, it is possible to detect whether the phase difference between the signal under test and the current sampling clock is cyclic. This can be done by determining whether the phase difference between the signal under test and the current sampling clock is cyclic based on the number of cycles of the error phase difference.

[0080] In some optional embodiments, detecting whether the phase difference between the signal under test and the current sampling clock is cyclic based on the ratio and the number of cycles of each error phase difference includes: obtaining each offset of the current sampling clock based on the ratio and the number of cycles of each error phase difference; if at least one offset satisfies a preset condition, it is determined that the phase difference between the signal under test and the current sampling clock is cyclic, otherwise it is determined that the phase difference between the signal under test and the current sampling clock is not cyclic.

[0081] In this application, the offset of the current sampling clock can be obtained based on the number of cycles of each error phase difference and the ratio of the ratio. The phase difference between the signal under test and the current sampling clock can be determined based on the offset. The preset conditions here may include less than a first threshold or greater than a second threshold. Specific limitations can be found below.

[0082] In some optional embodiments, the offsets of the current output clock are obtained based on the ratio and the number of cycles of each error phase difference, including: multiplying the ratio and the number of cycles of each error phase difference to obtain detection data; extracting the fractional part of each detection data as the offsets of the current sampling clock; and determining that the phase difference between the signal under test and the current sampling clock is cyclic when at least one offset satisfies a preset condition, including: determining that the phase difference between the signal under test and the current sampling clock is cyclic when the offset is less than a first threshold or greater than a second threshold, wherein the second threshold is greater than the first threshold, and both the second threshold and the first threshold are greater than or equal to 0 and less than 1.

[0083] The specific detection data for the current output clock are as follows:

[0084] JudgeData1 = DataTemp * 1

[0085] JudgeData2 = DataTemp * 2

[0086] JudgeData3 = DataTemp * 3

[0087] JudgeData4 = DataTemp * 4

[0088] Calculate the decimal part of the four detection data points JudgeData to obtain four offsets IntegerJudgeData, as shown in the following formula:

[0089] IntegerJudgeData1 = fabs(JudgeData1 - floor(JudgeData1))

[0090] IntegerJudgeData2 = fabs(JudgeData2 - floor(JudgeData2))

[0091] IntegerJudgeData3 = fabs(JudgeData3 - floor(JudgeData3))

[0092] IntegerJudgeData4 = fabs(JudgeData4 - floor(JudgeData4))

[0093] For example: JudgeData1=11.123, floor(JudgeData1)=11, (JudgeData1 - floor(JudgeData1)=0.123, IntegerFlag1=0.123, where floor means taking the evidence downwards, and fabs means taking the absolute value.

[0094] If the decimal part of the detected data is redundant, and after several cycles they approach an integer multiple again, it indicates that the phase difference between the signal under test and the current sampling clock is cyclic. Therefore, this application uses an offset to determine whether the phase difference between the signal under test and the current sampling clock is cyclic. The first threshold can be 0.1, and the second threshold can be 0.9. In other embodiments, these can be other values. In this application, if the offset is less than the first threshold or greater than the second threshold, it is determined that the phase difference between the signal under test and the current sampling clock is cyclic. The second threshold is greater than the first threshold, and both the second threshold and the first threshold are greater than or equal to 0 and less than 1.

[0095] For example, if any IntegerJudgeData is greater than 0.9 or less than 0.1, it is determined that the phase difference between the signal under test and the current sampling clock is cyclic.

[0096] In this application, when the phase difference between the signal under test and the current sampling clock cycles, the frequency division coefficient is adjusted, for example, by adding 0.125 to the frequency division coefficient, i.e., DemulitFreqData = DemulitFreqData+0.125, until the phase difference between the signal under test and the current sampling clock cycles, thus obtaining the final target frequency division coefficient.

[0097] Finally Frequency_TmuClk= Frequency_Domain *MulitFreqData / DemulitFreqData

[0098] Period_TmuClk = 1 / Frequency_TmuClk

[0099] Where Frequency_TmuClk is the current sampling clock frequency, Period_TmuClk is the current output clock period, Frequency_Domain is the input clock domain frequency, MulitFreqData is the multiplication factor, and DemulitFreqDat is the target division factor.

[0100] In some of these alternative embodiments, combined with Figure 4 As shown, Figure 4This is a schematic diagram of dynamic frequency multiplication in one embodiment. Since the clock of the digital board originates from the DomainClk of the communication board, and DomainClk changes according to user service requirements, the traditional method of fixing the configuration of the frequency multiplication module used to generate the TMU clock is unworkable. Therefore, a method is needed that can generate a TmuClk of approximately 400MHz regardless of how DomainClk changes, suitable for single-board measurement scenarios where DomainClk is variable. To this end, this application proposes a dynamic frequency multiplication method. When the trigger mode is determined based on configuration parameter values ​​to be neither a cross-subboard synchronous trigger mode nor a jitter measurement mode, this conventional dynamic frequency multiplication rule is adopted, combined with… Figure 5 As shown, Figure 5 This is a schematic diagram of a dynamic frequency doubling method in one embodiment, the method including:

[0101] S502: Obtain the input clock domain frequency when the non-jitter measurement mode is determined based on the configuration parameter value and it is not a multi-board synchronous trigger mode.

[0102] The input clock domain frequency, Frequency_Domain, is a fixed frequency determined based on the service input.

[0103] S504: Determines the multiplication factor and division factor based on the input clock domain frequency.

[0104] The frequency multiplication factor is determined based on the input clock domain frequency and the maximum frequency multiplication factor of the hybrid clock manager, while the frequency division factor is determined based on the frequency multiplication factor, the input clock domain frequency, and the expected time measurement sampling clock frequency.

[0105] In some optional embodiments, determining the multiplication factor and division factor based on the input clock domain frequency includes: determining the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; obtaining the multiplication frequency based on the multiplication factor and the input clock domain frequency; and obtaining the division factor based on the multiplication frequency and the expected time measurement sampling clock frequency.

[0106] It should be noted that, Figure 2 , Figure 4 and Figure 7 In the process, the hybrid clock manager (MMCM) first multiplies the frequency and then divides it to output the TmuClk sampling clock waveform. The hybrid clock manager is located inside the FPGA, and the TmuClk sampling clock waveform output by the MMCM is different from the expected time measurement sampling clock frequency.

[0107] In cases where the mode is neither jitter measurement nor cross-subboard synchronous triggering, the calculation method for the frequency multiplication coefficient using the conventional dynamic frequency multiplication rule in this application is as follows:

[0108] MulitFreqDataTemp = 1.4GHz / Frequency_Domain

[0109] MulitFreqData = 0.125 * (rounded down (MulitFreqDataTemp / 0.125))

[0110] The maximum multiplication frequency of the Hybrid Clock Manager (MMCM) is 1.4 GHz, but it can be other values ​​in other embodiments. Frequency_Domain is the input clock domain frequency, MultiFreqDataTemp is a candidate value for the multiplication factor, MultiFreqData is the multiplication factor (in the conventional dynamic multiplication rule, it is used as a reference candidate value as the multiplication factor), and 0.125 is the minimum configuration unit of the MMCM multiplication unit.

[0111] The method for calculating the harmonic frequency is as follows:

[0112] Frequency_Mulit = MulitFreqData * Frequency_Domain

[0113] DemulitFreqDataTemp = Frequency_Mulit / 400MHz

[0114] DemulitFreqData = 0.125 * (Round up (DemulitFreqDataTemp / 0.125))

[0115] Where Frequency_Mulit is the harmonic frequency, DemulitFreqDataTemp is the median value of the division coefficient, and DemulitFreqData is the division coefficient.

[0116] In some optional embodiments, determining the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager includes: in jitter measurement mode, obtaining candidate values ​​for the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; obtaining a reference candidate value based on the candidate values ​​for the multiplication factor; and obtaining the multiplication factor based on the reference candidate value; in cases where it is determined based on configuration parameter values ​​that it is neither a jitter measurement mode nor a cross-daughterboard synchronous triggering mode, obtaining candidate values ​​for the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; and obtaining a reference candidate value based on the candidate values ​​for the multiplication factor as the multiplication factor.

[0117] In jitter measurement mode, when calculating the frequency multiplication factor using the dynamic frequency multiplication rule, to avoid multiplying the frequency to the expected time for measuring the sampling clock frequency, i.e., 400MHz, the candidate value of the frequency multiplication factor is calculated as follows:

[0118] MulitFreqDataTemp = 1.4GHZ / Frequency_Domain

[0119] MulitFreqDataOrg = 0.125 * (rounded down (MulitFreqDataTemp / 0.125))

[0120] The maximum multiplication frequency of MMCM is 1.4GHz, but it can be other values ​​in other embodiments. Frequency_Domain is the input clock domain frequency, MultiFreqDataTemp is a candidate value for the multiplication factor, MultiFreqDataOrg is a reference candidate value, and 0.125 is the minimum configuration unit of the MMCM multiplication unit.

[0121] Multiplier MulitFreqData = MulitFreqDataOrg - 0.125. Subtracting 0.125 ensures that the multiplier in MMCM will not multiply to 400MHz.

[0122] In one exemplary embodiment, such as Figure 6 As shown, a dynamic frequency multiplication method for a time measurement unit is provided, which is applied to... Figure 1 Taking the driver in the example of a digital board driver, the explanation includes the following steps 602 to 604. Wherein:

[0123] S602: Determines the input clock domain range and the maximum multiplication frequency of the hybrid clock manager.

[0124] In this embodiment, the input clock domain range DomainClk is [Frequency_DomainMin, Frequency_DomainMax], which is also the input clock domain frequency range. This is because when crossing the same digital board or different digital board sub-boards, it is necessary to know the multiplication factor and division factor corresponding to each segment of the input clock domain frequency. The input clock domain range is calculated by the FPGA according to the user configuration before the TMU runs and stored in the driver cache.

[0125] The maximum multiplier frequency of the hybrid clock manager is the maximum multiplier frequency supported by the MMCM, such as Frequency_MmcmMax. Optionally, Frequency_MmcmMax = 1.4GHz, and in other embodiments, it can be other values.

[0126] S604: Based on the input clock domain range and the maximum multiplication frequency of the hybrid clock manager, and under the constraint that the multiplication coefficient, division coefficient and overall multiplication coefficient of the hybrid clock manager are all integers, determine the multiplication coefficient and division coefficient, as well as the segment information corresponding to each multiplication coefficient and division coefficient. The multiplication coefficient and division coefficient are used to generate the sampling clock waveform of the time measurement unit.

[0127] In another embodiment, the clock used by the TMU module of the digital board is often coupled with the DomainClk (test machine master clock) of other services. In traditional technology, the TMU sampling clock waveform is obtained by multiplying the DomainClk by the MMCM (Mixed-Mode Clock Manager). If the overall multiplication factor of the MMCM is a decimal, it may cause the TMU on the two daughter boards to not trigger the measurement simultaneously when performing delay measurement between daughter board channels across digital boards. This will result in the delay measurement being different from the expected one TMU sampling clock waveform cycle. Figure 7 As shown, Figure 7 This is a schematic diagram of dynamic frequency multiplication across sub-boards of the same digital board or across sub-boards of different digital boards in one embodiment. Board 1 and Board 2 are two sub-boards. Board 1 and Board 2 may or may not be on the same digital board. In this embodiment, the TmuClk sampling clock waveform of each sub-board is obtained by multiplying the input clock domain DomainClk waveform by MMCM. When measuring across sub-boards, the TMU needs to be triggered synchronously. For this reason, this application sets the constraint that the multiplication factor, division factor and overall multiplication factor of the hybrid clock manager are all integers.

[0128] Segmentation information is obtained by dividing the input clock domain into segments. For example, if the input clock domain range DomainClk is divided into Range1...RangeN, then the segmentation information is Range1...RangeN. It's important to note that segmentation involves dividing the input clock domain range [Frequency_DomainMin, Frequency_DomainMax] into continuous, non-overlapping segments.

[0129] The multiplication factor, division factor, and overall multiplication factor are all integers, which can ensure synchronous triggering across sub-boards. Therefore, the constraint of setting segmentation information in this application is to ensure that the multiplication factor, division factor, and overall multiplication factor are all integers. The overall multiplication factor is the ratio of the multiplication factor to the division factor, i.e., overall multiplication factor = multiplication factor / division factor.

[0130] The maximum multiplication frequency of the hybrid clock manager is used to limit the multiplication factor. That is, the multiplication frequency of the hybrid clock manager is less than or equal to the maximum multiplication frequency Frequency_MmcmMax. The maximum multiplication frequency of the hybrid clock manager can be represented by the input clock domain and the multiplication factor, that is, DomainClk * multiplication factor ≤ Frequency_MmcmMax.

[0131] In this application, segmentation information can be determined based on the sampling clock frequency measured at the expected time.

[0132] Once the segmentation information is determined, corresponding multiplication coefficients and division coefficients can be generated for each segment. Specifically, based on the segmentation information and the maximum multiplication frequency, the multiplication coefficients and division coefficients can be determined while ensuring that the multiplication coefficient, division coefficient, and overall multiplication coefficient are all integers.

[0133] After obtaining the frequency multiplication factor and frequency division factor, the driver sends the frequency multiplication factor and frequency division factor to the FPGA. The FPGA can generate the sampling clock waveform of the time measurement unit based on the frequency multiplication factor and frequency division factor. The sampling clock waveform is used to acquire the test signal output by the chip under test.

[0134] The aforementioned dynamic frequency multiplication method for the time measurement unit determines the input clock domain range and the maximum multiplication frequency of the hybrid clock manager. Based on the input clock domain range and the maximum multiplication frequency of the hybrid clock manager, and under the constraint that the multiplication coefficient, division coefficient, and overall multiplication coefficient of the hybrid clock manager are all integers, the multiplication coefficient and division coefficient, as well as the segment information corresponding to each multiplication coefficient and division coefficient, are determined. The multiplication coefficient and division coefficient are used to generate the sampling clock waveform of the time measurement unit. Since the multiplication coefficient, division coefficient, and overall multiplication coefficient of the hybrid clock manager are all integers, the problem of cross-subboard TMU measurement being unable to synchronously trigger measurement is solved.

[0135] In some optional embodiments, the segmentation information of the input clock domain is determined based on the input clock domain range and the maximum multiplication frequency of the hybrid clock manager, and under the constraint that the multiplication factor, division factor, and overall multiplication factor of the hybrid clock manager are all integers. This includes: determining the expected time measurement sampling clock frequency range, under the constraint that the multiplication factor, division factor, and overall multiplication factor of the hybrid clock manager are all integers, and the multiplication frequency of the hybrid clock manager is less than or equal to the maximum multiplication frequency, and under the constraint of maximizing the multiplication factor, determining the multiplication factor and division factor, and the segmentation information corresponding to each multiplication factor and division factor, based on the expected time measurement sampling clock frequency range and the input clock domain range.

[0136] The expected time measurement sampling clock frequency range is obtained by user configuration or FPGA hardware limitation and is a known value. In this application, [200MHz, 400MHz] is used as an example.

[0137] In order to obtain accurate segmentation information, this application also adds constraints to maximize the overall frequency multiplication factor and maximize the frequency multiplication factor. The constraint to maximize the overall frequency multiplication factor is to improve the accuracy of the TMU in testing the signal under test, and the constraint to maximize the frequency multiplication factor is to ensure that the clock jitter of the TMU in measuring the signal under test is smaller.

[0138] The constraint of maximizing the overall harmonic coefficient is to improve accuracy. This can be achieved by first determining the minimum and maximum values ​​of the overall harmonic coefficient, thereby determining the range of values ​​for the overall harmonic coefficient and laying the foundation for determining the subsequent segmentation information.

[0139] In this application, the expected time measurement sampling clock frequency range is determined. Under the constraints of maximizing the overall multiplication factor and maximizing the multiplication factor, as well as the constraints that the multiplication factor, division factor, and overall multiplication factor of the hybrid clock manager are all integers, and the constraint that the multiplication frequency of the hybrid clock manager is less than or equal to the maximum multiplication frequency, the above parameters are adjusted to simultaneously satisfy the above constraints, thereby determining the segmented information of the input clock domain range. Then, the multiplication factor, division factor, TMU sampling clock frequency range, and overall multiplication factor corresponding to each segment are calculated, ensuring the synchronous triggering of cross-subboard measurements.

[0140] In some alternative embodiments, combined with Figure 8 , Figure 8 This is a flowchart of a coefficient determination step in one embodiment. This step involves determining the multiplication factor and division factor, as well as the segmentation information corresponding to each multiplication factor and division factor, based on the expected time measurement sampling clock frequency range and the input clock domain range. The steps include:

[0141] S802: Based on the expected time, measure the maximum value of the sampling clock frequency range and the minimum value of the input clock domain range, and determine the range of values ​​for the overall multiplication factor under the constraint that the overall multiplication factor is an integer.

[0142] The minimum value of the overall frequency multiplication factor can be determined based on the Quinest sampling theorem, the frequency of the signal under test output by the chip under test, and the minimum value of the input clock domain range. The maximum value of the overall frequency multiplication factor can be determined based on the maximum value of the expected time measurement sampling clock frequency range and the minimum value of the input clock domain range. When the minimum and maximum values ​​of the overall frequency multiplication factor are determined, the range of values ​​for the overall frequency multiplication factor is determined under the constraint that the overall frequency multiplication factor is an integer.

[0143] In some optional embodiments, the range of values ​​for the overall frequency multiplication factor is determined based on the maximum value of the expected time-measured sampling clock frequency range and the minimum value of the input clock domain range, under the constraint that the overall frequency multiplication factor is an integer. This includes: determining the maximum value of the overall frequency multiplication factor based on the maximum value of the expected time-measured sampling clock frequency range and the minimum value of the input clock domain range; determining the minimum value of the overall frequency multiplication factor based on the Quinest sampling theorem, the frequency of the signal under test output by the chip under test, and the minimum value of the input clock domain range; and determining the range of values ​​for the overall frequency multiplication factor based on the maximum and minimum values ​​of the overall frequency multiplication factor. The maximum value of the overall frequency multiplication factor is determined based on the maximum value of the expected time-measured sampling clock frequency range and the minimum value of the input clock domain range. For example, the maximum value of the overall frequency multiplication factor is equal to the ratio of the maximum value of the expected time-measured sampling clock frequency range to the minimum value of the input clock domain range. For example, if the maximum value of the expected time-measured sampling clock frequency range is 400MHz and the minimum value of the input clock domain range is 100MHz, then the maximum value of the overall frequency multiplication factor is 4.

[0144] The calculation process for the minimum value of the overall multiplication factor is as follows: Based on the Nyquist sampling theorem, the time measurement sampling clock frequency is twice the frequency of the signal under test. Since the signal under test can support frequencies up to 100MHz, the time measurement sampling clock frequency TmuClk is 200 MHz. The minimum value of the input clock frequency range DomainClk is 100MHz. Using the formula TmuClk = DomainClk * overall multiplication factor, the minimum value of the overall multiplication factor is 2. Since the overall multiplication factor is an integer, its value range is 2, 3, and 4. This is just an example; the overall multiplication factor can also have other range values.

[0145] S804: For each overall multiplication factor within the range of overall multiplication factor values, segment information is determined based on the expected time measurement sampling clock frequency range.

[0146] In this application, segmentation information can be determined for each overall multiplication factor. Optionally, for each overall multiplication factor within the value range of the overall multiplication factor, segmentation information is determined based on the expected time measurement sampling clock frequency range, including: for each overall multiplication factor within the value range of the overall multiplication factor, segmentation information is determined based on the quotient of the expected time measurement sampling clock frequency range and the overall multiplication factor.

[0147] When the overall multiplication factor is 4, the expected time measurement sampling clock frequency is 400MHz, so the segmented information can be determined to be 100MHz; when the overall multiplication factor is 3, the segmented information is 400MHz / 3=133.3333MHz, so the segmented information is (100MHz, 133.3333MHz); when the overall multiplication factor is 2, the segmented information is 400MHz / 2=200MHz, so the segmented information is (133.3333MHz, 200MHz).

[0148] S806: Based on the maximum multiplication frequency and segmentation information, determine the range of values ​​for the multiplication coefficient under the constraint that the multiplication frequency of the hybrid clock manager is less than or equal to the maximum multiplication frequency.

[0149] Once the segmentation information is known, the range of values ​​for the multiplication factor can be determined based on the maximum multiplication frequency, under the constraint that the multiplication frequency of the hybrid clock manager is less than or equal to the maximum multiplication frequency. For example, if the segmentation information is 100MHz and the maximum multiplication frequency is 1.4GHz, then the range of values ​​for the corresponding multiplication factor is ≤1.4GHz / 100MHz, or ≤14.

[0150] S808: Based on the range of values ​​for the multiplication factor and the overall multiplication factor, the multiplication factor and the division factor are determined under the constraint that the multiplication factor and the division factor of the hybrid clock manager are both integers and the multiplication factor is maximized.

[0151] In some optional embodiments, based on the range of values ​​of the multiplication factor and the overall multiplication factor, and under the constraint that the multiplication factor and the division factor of the hybrid clock manager are both integers and the multiplication factor is maximized, the multiplication factor and the division factor are determined, including: determining the maximum multiplication factor that is divisible by the overall multiplication factor, wherein the maximum multiplication factor is an integer and the maximum multiplication factor is less than or equal to the maximum value of the range of values ​​of the multiplication factor; and determining the division factor based on the maximum multiplication factor and the overall multiplication factor.

[0152] Since both the multiplication factor and the division factor are integers, and the multiplication factor is maximized, the maximum value of the multiplication factor is 12 when the overall multiplication factor is 4 and the multiplication factor is ≤14. Therefore, the division factor is 12 / 4=3. Thus, the multiplication factor and the division factor are determined.

[0153] Specifically, for example, the expected time measurement sampling clock frequency range = DomainClk * (multiplier / divider) = DomainClk * overall multiplier. The expected time measurement sampling clock frequency range is [200MHz, 400MHz], and the input clock domain range DomainClk is [100MHz, 200MHz]. Step 1: The maximum value of the expected time measurement sampling clock frequency range (400MHz) and the minimum value of DomainClk (100MHz) determine the maximum value of the overall multiplier to be 4, while the minimum value is 2. Therefore, the overall multiplier can be 4, 3, or 2.

[0154] The second step involves determining the segment information for an overall multiplication factor of 4 as 400MHz / 4 = 100MHz. Using the maximum multiplication frequency of 1.4GHz and DomainClk, and taking the minimum of 100MHz, we determine that the multiplication factor is ≤14. Therefore, the maximum multiplication factor can be 12, resulting in an overall multiplication factor of 4. Consequently, the division factor is 3. Therefore, for an overall multiplication factor of 4, the corresponding segment information is 100MHz, the multiplication factor is 12, and the division factor is 3. Step 3: Try setting the overall multiplication factor to 3. Based on the expected time measurement sampling clock frequency range of 399.9999MHz, the calculated DomainClk is 133.3333MHz. To ensure the continuity of DomainClk segments, the second segment of DomainClk will have a range of (100MHz, 133.3333MHz). Using the maximum multiplication frequency of 1.4GHz and DomainClk of 133.3333MHz, the multiplication factor is determined to be ≤10.5. The maximum value of the multiplication factor after rounding is 9, and the division factor is 3. Thus, the expected time measurement sampling clock frequency range for the second segment is determined to be (300MHz, 399.9999MHz), corresponding to a segment information of (100MHz, 133.3333MHz), with a multiplication factor of 9 and a division factor of 3. Step 4: Try setting the overall multiplication factor to 3 again. With a frequency multiplier of 2 and an expected time measurement sampling clock frequency range of 400MHz, DomainClk is calculated to be 200MHz. To ensure the continuity of DomainClk segments, the second segment of DomainClk is set to (133.3333MHz, 200MHz). Using the maximum multiplication frequency of 1.4GHz and DomainClk set to 200MHz, the multiplication multiplier is determined to be ≤7, with a maximum value of 6. The division multiplier is set to 3, thus confirming the third segment of DomainClk as (133.3333MHz, 200MHz). Consequently, the expected time measurement sampling clock frequency range for the third segment is determined to be (266.6666MHz, 400MHz), with the corresponding segment information being (133.3333MHz, 200MHz), a multiplication multiplier of 6, and a division multiplier of 3.

[0155] Table 1 is provided for ease of understanding. Table 1 shows the harmonic coefficients and frequency division coefficients corresponding to each segment information. The number of segments N is 3.

[0156] Table 1

[0157]

[0158] In the above embodiments, the multiplication factor, division factor, and overall multiplication factor of the hybrid clock manager are all integers, and the multiplication frequency of the hybrid clock manager is less than or equal to the maximum multiplication frequency. Under the constraint of maximizing the multiplication factor, the multiplication factor and division factor, as well as the segment information corresponding to each multiplication factor and division factor, are determined based on the expected time measurement sampling clock frequency range and the input clock domain range. Since the multiplication factor, division factor, and overall multiplication factor of the hybrid clock manager are all integers, the problem of cross-subboard TMU measurement being unable to synchronously trigger measurement is solved.

[0159] In some optional embodiments, the method further includes: determining the maximum sampling period of the time measurement unit based on segmentation information, wherein the maximum sampling period is used to instruct the FPGA to set the total delay of the carry chain to be greater than the maximum sampling period.

[0160] In this application, after determining the frequency multiplication factor, frequency division factor, expected time measurement sampling clock frequency range and overall frequency multiplication factor corresponding to each segment information, the minimum sampling clock frequency of the expected time measurement sampling clock range TMU, Frequency_TmuClkMin, can also be determined, thereby obtaining the maximum TMU sampling period Period_TmuClkMax=1 / Frequency_TmuClkMin.

[0161] In this way, the total delay of the carry chain can be determined based on the maximum TMU sampling period. For example, the number of taps in the FPGA extended precision measurement unit (carry chain) requires the total delay of the carry chain to be greater than Period_TmuClkMax.

[0162] In some optional embodiments, the method further includes: obtaining the current input clock domain range; and determining the target multiplication factor and target division factor corresponding to the current input clock domain range based on the current input clock domain range and pre-generated segmentation information.

[0163] In practical applications, after obtaining the current input clock domain frequency (Frequency_Domain), the corresponding target multiplication factor and target division factor are obtained by querying the table based on the current input clock domain frequency (Frequency_Domain) and sent to the FPGA. For example, based on the current input clock domain frequency (Frequency_Domain), the input clock domain frequency range (DomainClk) to which it belongs is determined by querying Table 1 above. Then, based on the determined input clock domain frequency range, the target multiplication factor and target division factor are determined.

[0164] The above embodiments solve the problem that cross-subboard TMU measurements cannot be synchronously triggered.

[0165] In one exemplary embodiment, such as Figure 9 As shown, a dynamic frequency multiplication method for a time measurement unit is provided, which is applied to... Figure 1 Taking the FPGA as an example, the explanation includes steps 902 to 904. Wherein:

[0166] S902: Receive the frequency multiplication coefficient and frequency division coefficient determined by the time measurement unit dynamic frequency multiplication method based on any of the above embodiments.

[0167] S904: Generates the sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication factor and frequency division factor.

[0168] The FPGA can receive the multiplication and division coefficients determined by the driver and calculate the sampling clock waveform corresponding to the time measurement unit.

[0169] For ease of understanding, the following is combined Figure 10 As shown, Figure 10 The following is an overall flowchart of a dynamic frequency multiplication method in one embodiment, in which the terminal sends the configuration parameter values ​​corresponding to the hybrid clock manager to the driver via API. These configuration parameter values ​​include the board identifier, the channel identifier (Pinlist), and the measurement mode (MeasureMode).

[0170] The driver's parameter receiving and processing module receives the board identifier, channel identifier (Pinlist), and measurement mode (MeasureMode). Based on these identifiers, it parses the board identifier, channel identifier (Pinlist), and measurement mode (MeasureMode) to generate algorithm selection identifiers (JitterFlag and SyncFlag). The JitterFlag and SyncFlag are then sent to the driver's dynamic frequency multiplication module. The dynamic frequency multiplication module determines whether the mode is multi-board synchronous trigger measurement mode, jitter measurement mode, or other modes based on the JitterFlag and SyncFlag.

[0171] When SyncFlag is set to true, the dynamic frequency multiplication module is determined to be in cross-daughterboard synchronous trigger measurement mode. The frequency multiplication coefficient and frequency division coefficient are then calculated according to the dynamic frequency multiplication rules in the cross-daughterboard synchronous trigger measurement mode. Specifically, the current input clock frequency range is first determined, and then the frequency multiplication coefficient and frequency division coefficient are obtained by looking up a table. The table stores the frequency multiplication coefficient and frequency division coefficient corresponding to each segment of information. The specific generation method of the frequency multiplication coefficient and frequency division coefficient corresponding to each segment of information can be found above and will not be repeated here.

[0172] When the Jitter setting is true, the dynamic frequency multiplication module is identified as being in jitter measurement mode. The multiplication factor and division factor are then calculated according to the dynamic frequency multiplication rules for jitter measurement mode. Specifically, the division factor and multiplication factor are first determined based on the input clock domain frequency (note that the multiplication factor setting here differs from that in other modes and the jitter measurement mode). Then, the current sampling clock frequency is determined based on the multiplication factor and division factor. Next, it is checked whether the phase difference between the current sampling clock and the signal under test is cyclical. If it is cyclical, the division factor is adjusted until the phase difference between the current sampling clock and the signal under test is no longer cyclical, thus determining the final target division factor.

[0173] When the dynamic frequency multiplication module is set to false (JitterFlag and SyncFlag are both set to false), it is determined to be in other modes. The frequency multiplication coefficient and the frequency division coefficient are calculated according to the conventional dynamic frequency multiplication rules. Specifically, in this method, the frequency multiplication coefficient is first determined based on the input clock domain frequency and the maximum frequency multiplication frequency of the hybrid clock manager. Then, the frequency division coefficient is determined based on the frequency multiplication coefficient, the input clock domain frequency, and the expected frequency multiplication frequency of the hybrid clock manager.

[0174] After the frequency multiplication and division coefficients are generated by the driver, they are output to the FPGA. The FPGA then calculates the sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication and division coefficients. For details, please refer to [link to documentation]. Figure 9 .

[0175] In the above embodiments, the problem of cross-subboard TMU measurement not being able to be synchronously triggered is solved by cross-subboard synchronous triggering frequency multiplication rule, the problem of signal phase easy cyclic overlap caused by input and output being from the same source is solved by jitter measurement dynamic frequency multiplication rule, and the problem of TMU sampling clock frequency not being fixed when the Domain clock is changed is solved by conventional dynamic frequency multiplication rule.

[0176] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0177] Based on the same inventive concept, this application also provides a dynamic frequency multiplication device for a time measurement unit to implement the dynamic frequency multiplication method for a time measurement unit as described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more embodiments of the dynamic frequency multiplication device for a time measurement unit provided below can be found in the limitations of the dynamic frequency multiplication method for a time measurement unit described above, and will not be repeated here.

[0178] In one exemplary embodiment, such as Figure 11 As shown, a dynamic frequency multiplication device for a time measurement unit is provided, comprising: a first coefficient determination module 1101, a current sampling clock frequency determination module 1102, and a second coefficient determination module 1103, wherein:

[0179] The first coefficient determination module 1101 is used to obtain the input clock domain frequency and determine the multiplication coefficient and division coefficient based on the input clock domain frequency;

[0180] The current sampling clock frequency determination module 1102 is used to determine the current sampling clock frequency based on the multiplication factor and the division factor;

[0181] The second coefficient determination module 1103 is used to adjust the frequency division coefficient when the phase difference between the signal under test and the current sampling clock is cyclic, and to redetermine the current sampling clock frequency based on the multiplication coefficient and the adjusted frequency division coefficient, until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target frequency division coefficient.

[0182] In some optional embodiments, the above apparatus further includes: a detection module, configured to detect whether the phase difference between the signal under test and the current sampling clock is cyclic, based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test.

[0183] In some optional embodiments, the detection module is further configured to determine the ratio of the current sampling clock frequency to the frequency of the signal under test output by the chip under test; and based on the ratio and the number of cycles of each error phase difference, to detect whether the phase difference between the signal under test and the current sampling clock is cyclic.

[0184] In some optional embodiments, the detection module is further configured to obtain each offset of the current sampling clock based on the ratio and the number of cycles of each error phase difference; if at least one offset satisfies a preset condition, it is determined that there is a cycle in the phase difference between the signal under test and the current sampling clock, otherwise it is determined that there is no cycle in the phase difference between the signal under test and the current sampling clock.

[0185] In some optional embodiments, the detection module is further configured to multiply the ratio by the number of cycles of each error phase difference to obtain each detection data; extract the fractional part of each detection data as each offset of the current sampling clock; and determine that the phase difference between the signal under test and the current sampling clock is cyclic if at least one offset satisfies a preset condition, including: determining that the phase difference between the signal under test and the current sampling clock is cyclic when the offset is less than a first threshold or greater than a second threshold, wherein the second threshold is greater than the first threshold, and both the second threshold and the first threshold are greater than or equal to 0 and less than 1.

[0186] In some optional embodiments, the above apparatus further includes: a configuration module for receiving configuration parameter values; determining a corresponding jitter measurement dynamic frequency multiplication rule based on the configuration parameter values, wherein if the jitter measurement mode is determined based on the configuration parameter values, the step of obtaining the input clock domain frequency continues to be performed.

[0187] In some optional embodiments, the above apparatus further includes: a third coefficient determination module, configured to acquire the input clock domain frequency when it is determined, based on configuration parameter values, that it is neither a jitter measurement mode nor a cross-subboard synchronous triggering mode; and to determine the multiplication factor and division factor based on the input clock domain frequency.

[0188] In some optional embodiments, the third coefficient determination module is further configured to determine the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; obtain the multiplication frequency based on the multiplication factor and the input clock domain frequency; and obtain the division factor based on the multiplication frequency and the expected time measurement sampling clock frequency.

[0189] In some optional embodiments, the third coefficient determination module is further configured to, in jitter measurement mode, obtain candidate values ​​for the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; obtain a reference candidate value based on the candidate values ​​for the multiplication factor; and obtain the multiplication factor based on the reference candidate value; and, in the case where it is determined based on configuration parameter values ​​that it is neither a jitter measurement mode nor a cross-daughterboard synchronous triggering mode, obtain candidate values ​​for the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; and obtain a reference candidate value as the multiplication factor based on the candidate values ​​for the multiplication factor. In an exemplary embodiment, such as Figure 12 As shown, a dynamic frequency multiplication device for a time measurement unit is provided, comprising: a receiving module 1201 and a sampling clock waveform generation module 1202, wherein:

[0190] The receiving module 1201 is used to receive the frequency multiplication coefficient and frequency division coefficient determined by the dynamic frequency multiplication device of the time measurement unit based on any of the above embodiments.

[0191] The sampling clock waveform generation module 1202 is used to generate the sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication coefficient and the frequency division coefficient.

[0192] Each module in the aforementioned dynamic frequency multiplication device for time measurement can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0193] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 13As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a dynamic frequency multiplication method for a time measurement unit. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0194] Those skilled in the art will understand that Figure 13 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0195] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0196] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0197] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0198] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0199] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0200] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A dynamic frequency multiplication method for a time measurement unit, characterized in that, include: Obtain the input clock domain frequency, and determine the multiplication factor and division factor based on the input clock domain frequency; The current sampling clock frequency is determined based on the frequency multiplication factor and frequency division factor. When the phase difference between the signal under test and the current sampling clock is cyclic, the frequency division coefficient is adjusted, and the current sampling clock frequency is re-determined based on the frequency multiplication coefficient and the adjusted frequency division coefficient, until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target frequency division coefficient.

2. The method according to claim 1, characterized in that, The method further includes: Based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test, detect whether the phase difference between the signal under test and the current sampling clock is cyclic.

3. The method according to claim 2, characterized in that, The step of detecting whether the phase difference between the signal under test and the current sampling clock is cyclic, based on the current sampling clock frequency and the frequency of the signal under test output by the chip under test, includes: Determine the ratio of the current sampling clock frequency to the frequency of the signal under test output by the chip under test; Based on the ratio and the number of cycles for each error phase difference, it is determined whether the phase difference between the signal under test and the current sampling clock is cyclic.

4. The method according to claim 3, characterized in that, The step of detecting whether the phase difference between the signal under test and the current sampling clock is cyclic based on the ratio and the number of cycles of each error phase difference includes: Based on the ratio and the number of cycles for each error phase difference, the offsets of the current sampling clock are obtained. If at least one offset satisfies a preset condition, it is determined that the phase difference between the signal under test and the current sampling clock has a cycle; otherwise, it is determined that the phase difference between the signal under test and the current sampling clock does not have a cycle.

5. The method according to claim 4, characterized in that, The method of obtaining each offset of the current sampling clock based on the ratio and the number of cycles of each error phase difference includes: The ratios are multiplied by the number of cycles for each error phase difference to obtain the detection data. Extract the fractional part of each of the detection data as the offset of the current sampling clock; If at least one offset satisfies a preset condition, the phase difference between the signal under test and the current sampling clock is determined to be cyclic, including: If the offset is less than the first threshold or greater than the second threshold, it is determined that there is a cycle in the phase difference between the signal under test and the current sampling clock, the second threshold is greater than the first threshold, and both the second threshold and the first threshold are greater than or equal to 0 and less than 1.

6. The method according to claim 1, characterized in that, Before obtaining the input clock domain frequency, the following steps are included: Receive configuration parameter values; Based on the configuration parameter values, the corresponding jitter measurement dynamic frequency multiplication rule is determined. If the jitter measurement mode is determined based on the configuration parameter values, the step of obtaining the input clock domain frequency continues.

7. The method according to claim 6, characterized in that, The method further includes: If, based on the configuration parameter values, it is determined that the mode is neither jitter measurement mode nor cross-daughterboard synchronous trigger mode, the input clock domain frequency is obtained; The multiplication factor and division factor are determined based on the input clock domain frequency.

8. The method according to claim 1 or 7, characterized in that, The determination of the multiplication factor and division factor based on the input clock domain frequency includes: The multiplication factor is determined based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; The frequency multiplication factor and the input clock domain frequency are used to obtain the frequency multiplication factor; The frequency division coefficient is obtained based on the frequency multiplication and the expected time measurement sampling clock frequency.

9. The method according to claim 8, characterized in that, The determination of the multiplication factor based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager includes: In jitter measurement mode, candidate values ​​for the multiplication factor are obtained based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; a reference candidate value is obtained based on the candidate values ​​for the multiplication factor; and the multiplication factor is obtained based on the reference candidate value. If, based on the configuration parameter values, it is determined that the mode is neither a jitter measurement mode nor a cross-subboard synchronous trigger mode, candidate values ​​for the multiplication factor are obtained based on the input clock domain frequency and the maximum multiplication frequency of the hybrid clock manager; a reference candidate value is obtained as the multiplication factor based on the candidate values ​​for the multiplication factor.

10. A dynamic frequency multiplication method for a time measurement unit, characterized in that, Applied to FPGAs, including: Receive the frequency multiplication coefficient and frequency division coefficient determined based on the dynamic frequency multiplication method of the time measurement unit according to any one of claims 1 to 9; The sampling clock waveform corresponding to the time measurement unit is generated based on the frequency multiplication factor and the frequency division factor.

11. A dynamic frequency multiplication device for a time measurement unit, characterized in that, include: The first coefficient determination module is used to obtain the input clock domain frequency and determine the multiplication coefficient and division coefficient based on the input clock domain frequency. The current sampling clock frequency determination module is used to determine the current sampling clock frequency based on the frequency multiplication factor and the frequency division factor; The second coefficient determination module is used to adjust the frequency division coefficient when the phase difference between the signal under test and the current sampling clock is cyclic, and to redetermine the current sampling clock frequency based on the frequency multiplication coefficient and the adjusted frequency division coefficient, until the phase difference between the signal under test and the current sampling clock is no longer cyclic, thus obtaining the target frequency division coefficient.

12. A dynamic frequency multiplication device for a time measurement unit, characterized in that, Applied to FPGAs, including: The receiving module is configured to receive the frequency multiplication coefficient and frequency division coefficient determined based on the dynamic frequency multiplication device of the time measurement unit as described in claim 11; The sampling clock waveform generation module is used to generate the sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication coefficient and the frequency division coefficient.

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