Data storage method and electronic device

Abstract

The application provides a data storage method and an electronic device, and relates to the technical field of storage. The electronic device comprises a first memory and a second memory, and the first memory comprises a resident area. The method comprises the following steps: the electronic device receives a write instruction comprising first label information and a logical address of to-be-stored data, and the to-be-stored data; the first label information is used for indicating the attribute of the to-be-stored data. Then, the electronic device stores the to-be-stored data into the second memory. In the case that the first label information indicates that the attribute of the to-be-stored data is a first attribute, i.e. the to-be-stored data is data with higher importance, the electronic device stores the table item information of the to-be-stored data into the resident area of the first memory, so that the physical address of the data with the first attribute can be quickly found from the resident area of the first memory in the future, and then the data is acquired from the second memory based on the found physical address. The method can improve the data reading efficiency.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data storage method and electronic device. Background Technology

[0002] Currently, to improve the reliability and performance of storage media, electronic devices typically maintain a mapping table between Logical Block Addresses (LBAs) and Physical Block Addresses (PBAs). When an electronic device reads data from memory, it needs to query the mapping table to obtain the physical block address corresponding to the data being queried, and then retrieve the stored data based on the physical block address.

[0003] In electronic devices, memory can be volatile or non-volatile. Volatile memory has higher table lookup efficiency, while non-volatile memory has lower table lookup efficiency. When the storage space of volatile memory in an electronic device is limited, the mapping table between LBA and PBA may be stored (or cached) in non-volatile memory. That is, the mapping table between LBA and PBA may be stored in both volatile memory and non-volatile memory of the electronic device.

[0004] If the mapping table between LBA and PBA corresponding to the data to be queried is not cached in volatile memory, then the mapping table between LBA and PBA needs to be read from non-volatile memory to obtain the physical block address corresponding to the data to be queried. The table lookup efficiency is low, which affects the performance of electronic devices. Summary of the Invention

[0005] The application provides a data storage method and electronic device that can improve data reading efficiency.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a data storage method is provided for an electronic device, comprising a first memory and a second memory. The access efficiency of the first memory is higher than that of the second memory. The first memory includes a resident area for storing table entry information of data with a first attribute and table entry information that does not support storing data with a second attribute. The importance of the data with the first attribute is higher than that of the data with the second attribute. The method includes: the electronic device receiving a write instruction and data to be stored; wherein the write instruction includes first tag information and the logical address of the data to be stored, and the first tag information is used to indicate the attribute of the data to be stored. Then, the electronic device stores the data to be stored in the second memory. The second memory is generally a non-volatile memory. After receiving the write instruction, the electronic device first writes the data to disk in the second memory, enabling long-term data storage. When the first tag information indicates that the attribute of the data to be stored is the first attribute, the electronic device stores the table entry information of the data to be stored in the resident area of ​​the first memory, wherein the table entry information of the data to be stored is used to indicate the correspondence between the logical address and the physical address of the data to be stored.

[0008] By adopting the above technical solution, the electronic device stores the table entry information corresponding to the data of the first attribute in the resident area of ​​the first memory. Subsequently, when reading the data, it only needs to retrieve the corresponding table entry information from the first memory, and based on the correspondence between the logical address and physical address indicated by the table entry information, it can read the data corresponding to the table entry information from the second memory. That is, this data reading only requires a single read operation from the second memory, improving the performance of the electronic device.

[0009] In one possible implementation of the first aspect, the first memory includes a write cache table. Before storing the table entry information of the data to be stored in the resident area of ​​the first memory, the method further includes: in response to the data to be stored being stored in the second memory, the electronic device generates table entry information of the data to be stored. Then, the electronic device stores the table entry information of the data to be stored in the write cache table and flushes the table entry information of the data to be stored in the write cache table to the second memory. Subsequently, before the write cache table flushes the table entry information to the second memory, if a read data instruction is received, the table entry information of the data can be directly read from the write cache table. Furthermore, both the first memory and the second memory of the electronic device store the table entry information of the first data. If the table entry information in the first memory is subsequently refreshed, overwritten, or deleted, the table entry information of the first data can be downloaded again from the second memory.

[0010] In one possible implementation of the first aspect, the first memory further includes a read cache table, with a resident area included in the read cache table. Storing the table entry information of the data to be stored into the resident area of ​​the first memory includes: the electronic device determining the table entry information of the data of the first attribute in the table entry information of the data to be stored, and updating the table entry information of the data of the first attribute in the read cache table to the resident area of ​​the read cache table. Subsequently, even if other areas in the first memory storing table entry information of the data of the first attribute are updated, the electronic device can still directly read the table entry information of the data of the first attribute from the resident area of ​​the read cache table, improving data reading efficiency.

[0011] In one possible implementation of the first aspect, storing the table entry information of the data of the first attribute in a write cache table includes: in response to the first tag information indicating that the attribute of the data to be stored is the first attribute, storing the table entry information of the data to be stored and the second tag information correspondingly in the write cache table, wherein the second tag information is used to indicate that the table entry information of the data to be stored is the table entry information of the data of the first attribute. The table entry information stored in the write cache table may carry tag information indicating the attribute of the data corresponding to the table entry information. When the table entry information of the data to be stored is subsequently flushed to the second memory, it also carries the tag information to indicate the attribute of the data corresponding to the table entry information in the second memory.

[0012] Specifically, determining the table entry information for the data with the first attribute in the table entry information of the data to be stored includes: determining the table entry information in the read cache table that corresponds to the second tag information as the data with the first attribute. Both the tag information indicating the attribute of the first data and the tag information indicating the table entry information of the data with the first attribute can be represented by flag bits.

[0013] In one possible implementation of the first aspect, updating the table entry information of the data of the first attribute in the read cache table to the resident area of ​​the read cache table includes: generating a first-level mapping table, a second-level mapping table, and a third-level mapping table based on the table entry information of the data of the first attribute. The table entries of the first-level mapping table include indexes of the table entries of the second-level mapping table, the table entries of the second-level mapping table include indexes of the table entries of the third-level mapping table, and the table entries of the third-level mapping table are used to indicate the physical address of the data of the first attribute; updating the third-level mapping table to the resident area of ​​the read cache table. The method further includes: updating the first-level mapping table and the second-level mapping table to the read cache table. Therefore, the electronic device can subsequently obtain the correspondence between the logical address and the physical address of the first data from the resident area of ​​the read cache table, and then read the corresponding data from the second memory based on the determined physical address, thereby improving data reading efficiency.

[0014] In one possible implementation of the first aspect, the read cache table includes a compressed cache table and an uncompressed cache table. The compressed cache table includes a first resident area, and the uncompressed cache table includes a second resident area. Updating the three-level mapping table to the resident area of ​​the read cache table includes: identifying whether the logical address of the data for the first attribute is a contiguous logical address with the logical address of the data already stored in the first resident area. If yes, the three-level mapping table corresponding to the data for the first attribute is synchronized to the first resident area; otherwise, the three-level mapping table corresponding to the data for the first attribute is synchronized to the second resident area.

[0015] In one possible implementation of the first aspect, the logical address of the data of the first attribute can also be compared with the logical address of the data already stored in the second resident area. If the logical address of data 1 is continuous with the logical address of data 2 already stored in the second resident area, then the three-level mapping tables corresponding to data 1 and data 2 are jointly stored in the first resident area, and the entry corresponding to data 2 in the second resident area is deleted. Specifically, storing the three-level mapping tables corresponding to data 1 and data 2 jointly in the first resident area involves: determining the start logical address 1 and the end logical address 1 from the logical addresses of data 1 and data 2; storing the start logical address 1 and its corresponding physical address, the end logical address 1 and its corresponding physical address, and the total number of logical addresses of data 1 and data 2 in the first resident area. In other words, for the first data, it is compared with the logical addresses of the data in both the first and second resident areas. Only when the logical address of the first data is not continuous with the logical addresses of the stored data is the first data considered random data, and the three-level mapping table of this first data is stored in the second resident area.

[0016] In one possible implementation of the first aspect, synchronizing the three-level mapping table corresponding to the data of the first attribute to the first resident area includes: identifying the logical address of the data of the first attribute based on the three-level mapping table; determining the starting logical address and the ending logical address from the logical address of the data of the first attribute and the logical address of the stored data; and storing in the first resident area the starting logical address and the physical address corresponding to the starting logical address, the ending logical address and the physical address corresponding to the ending logical address, and the total number (length) of the logical addresses of the data of the first attribute and the logical addresses of the stored data.

[0017] In one possible implementation of the first aspect, the method further includes: an electronic device receiving a read instruction; wherein the read instruction is used to read first data, and the read instruction includes tag information of the first data and a logical address of the first data; the tag information of the first data is used to indicate the attributes of the first data. The electronic device finds the table entry information of the first data based on the tag information of the first data, then finds the physical address of the first data from the table entry information based on the logical address of the first data, and finally reads the first data from the second memory based on the physical address of the first data. Thus, the electronic device can directly find the table entry information of the data from the resident area of ​​the first memory, determine the physical address corresponding to the data based on the table entry information, and then read the data from the second memory, improving data reading efficiency.

[0018] In one possible implementation of the first aspect, retrieving the table entry information of the first data based on the tag information of the first data includes: in response to the attribute of the first data being a first attribute, searching for the table entry information of the first data in the write cache table of the first memory. When data of the first attribute is written to memory, the table entry information is first stored in the write cache table and then synchronized to the read cache table. Therefore, the electronic device can first query the table entry information of the data in the write cache table, and if it is not found, then query the read cache table.

[0019] In one possible implementation of the first aspect, if the entry information for the first data is not found in the write cache table of the first memory, the method further includes: based on the logical address of the first data, searching for the corresponding target second-level mapping table in the first memory's read cache; searching for the corresponding target third-level mapping table in the found target second-level mapping table; and determining the physical address of the first data from the found target third-level mapping table. In the three-level mapping relationship, only the logical address of the data needs to be obtained. By calculating and offsetting this logical address, the corresponding entry in each level of the mapping table can be obtained, and finally, the physical address of the data can be found.

[0020] In one possible implementation of the first aspect, retrieving the table entry information of the first data based on the tag information of the first data includes: the electronic device, in response to the attribute of the first data being a second attribute, searches for the table entry information of the first data in the write cache table of the first memory; if the table entry information of the first data is not found in the write cache table of the first memory, it retrieves the table entry information of the first data from the second memory. Since the data of the second attribute refers to low-frequency, unimportant data, even if table entry information needs to be retrieved from the second memory, the probability of reading this data is relatively low, so it will not have a significant impact on the performance of the electronic device. Furthermore, storing the table entry information in the second memory can also save storage space in the first memory, allowing the first memory to store more table entry information for the first attribute data.

[0021] In one possible implementation of the first aspect, after obtaining the table entry information of the first data from the second memory, the method further includes: synchronizing the table entry information of the first data to a non-resident area of ​​the read cache table of the first memory. For example, the compressed cache table in the read cache table includes a first resident area, and the uncompressed cache table includes a second resident area. The table entry information of the first data is synchronized to the first non-resident area and / or the second non-resident area of ​​the read cache table of the first memory. Specifically, if the first data is continuous data, the table entry information of the first data is stored in the first non-resident area; if the first data is random data, i.e., data with non-contiguous storage addresses (or physical addresses), the table entry information of the first data is stored in the second non-resident area. Therefore, when subsequently reading data of the second attribute, the table entry information of the second attribute data can be searched first from the first non-resident area and / or the second non-resident area, improving data reading efficiency.

[0022] Specifically, it is determined whether the logical address of the first data is contiguous with the logical address of the data already stored in the first non-resident area of ​​the read cache table. If so, the third-level mapping table corresponding to the first data is synchronized to the first non-resident area; otherwise, the third-level mapping table corresponding to the first data is synchronized to the second non-resident area. Furthermore, before synchronizing the third-level mapping table corresponding to the first data to the second non-resident area, it is determined whether the logical address of the first data is contiguous with the logical address of the data already stored in the second non-resident area of ​​the read cache table. If so, the third-level mapping table of the first data and the entries in the second non-resident area that are contiguous with the logical address of the first data are stored together in the first non-resident area; otherwise, the third-level mapping table corresponding to the first data is synchronized to the second non-resident area.

[0023] Specifically, the above-mentioned storage of the three-level mapping table of the first data and the entries of the data (data 3) in the second non-resident area that are logically consecutive with the first data in the first non-resident area is as follows: From the logical addresses of the first data and data 3, the starting logical address 2 and the ending logical address 2 are determined. The mapping relationship of the starting logical address 2, the mapping relationship of the ending logical address 2, and the total number of logical addresses of the first data and data 3 are stored in the first non-resident area. Furthermore, the electronic device deletes the entry corresponding to data 3 in the second non-resident area. In other words, for the first data, both the logical addresses in the first and second non-resident areas are compared. Only when the logical address of the first data is not consecutive with the logical addresses of the already stored data is the data of the second attribute considered random data, and the three-level mapping table of the first data is stored in the second non-resident area.

[0024] In one possible implementation of the first aspect, the first memory is SRAM; the second memory is NADA flash memory.

[0025] In a second aspect, this application provides an electronic device comprising: a first memory, a second memory, and one or more processors; the first memory and the second memory being coupled to the processors; wherein the first memory and / or the second memory store computer program code, the computer program code including computer instructions, which, when executed by the processor, cause the electronic device to perform the method described in any one of the first aspects.

[0026] It should be understood that the computer program code in this application is not limited to being stored in the first memory and / or the second memory, and the electronic device may also include a third memory for storing the computer program code.

[0027] Thirdly, this application provides a computer-readable storage medium storing instructions that, when executed on a computer, enable the computer to perform the method described in any one of the first aspects above.

[0028] Fourthly, this application provides a computer program product containing instructions that, when run on a computer, enable the computer to perform the method described in any one of the first aspects above.

[0029] It is understood that the electronic device described in the second aspect, the computer-readable storage medium described in the third aspect, and the computer program product described in the fourth aspect are all used to perform the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here. Attached Figure Description

[0030] Figure 1 A system call structure diagram of NAND flash memory provided in this application embodiment;

[0031] Figure 2 This application provides a structural diagram of host call data.

[0032] Figure 3 A schematic diagram of a three-level mapping in a UFS device provided in an embodiment of this application;

[0033] Figure 4 A time-based schematic diagram illustrating the timing of hitting an entry in SRAM and loading an entry in NAND, provided for embodiments of this application;

[0034] Figure 5 This is a schematic diagram illustrating the specific workflow of a data writing method provided in an embodiment of this application.

[0035] Figure 6 This application provides a schematic diagram of the structure of a read cache table according to an embodiment of the present application.

[0036] Figure 7 This application provides a schematic diagram illustrating the flushing of table entries in a write cache table, as shown in an embodiment of the present application.

[0037] Figure 8 A flowchart for reading data is provided as an embodiment of this application;

[0038] Figure 9 A schematic diagram of a reserved field in a read instruction provided for an embodiment of this application;

[0039] Figure 10 A software architecture diagram of an electronic device provided for embodiments of this application;

[0040] Figure 11 A hardware structure diagram of an electronic device provided in an embodiment of this application;

[0041] Figure 12 This is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0043] It should be noted that the terms "first," "second," etc., used below are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0044] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0045] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0046] To better illustrate the technical solution of this application, the terminology involved in this application is briefly summarized below.

[0047] (1) Universal Flash Storage (UFS) Devices: The industry typically refers to mobile storage devices based on the UFS protocol as UFS devices. The UFS protocol is a communication interface protocol developed for mobile storage devices. UFS devices are widely used in smartphones, tablets, virtual reality (VR) devices, augmented reality (AR) devices, and other fields. A UFS device consists of a controller and NAND flash memory.

[0048] (2) NAND flash memory (or NAND): It is a non-volatile memory used to store data. NAND flash memory uses a logic "switching" method to determine the presence of data based on the flow of current.

[0049] The controller is responsible for the management of NAND flash memory and data flow control.

[0050] (3) LBA: LBA is a general mechanism for describing the block of data on a computer storage device, typically used in auxiliary memory devices such as hard drives. LBA can refer to the address of a data block or the data block pointed to by an address, providing a unified addressing method for storage devices. This allows the operating system to more easily manage and access data on storage devices, such as read / write operations and partition management. File systems can also utilize LBA to organize and manage data on storage devices, improving the efficiency and reliability of data access.

[0051] (4) PBA: This is the physical address (or physical block address) used inside the storage device to locate data blocks, ensuring that the storage device can accurately read and write data blocks. It is the basic addressing method at the hardware level of the storage device. Under normal circumstances, the operating system and applications cannot directly access the PBA.

[0052] When accessing a storage device, the address translation module within the hard disk controller translates the logical address (LBA) into the actual physical address (PBA). This allows the operating system and applications to access the storage device using a unified LBA, without needing to know the physical structure of the storage device.

[0053] Because NAND flash memory has a limited write / erase cycle life and is prone to bad blocks during manufacturing and use, UFS devices do not directly expose the PBA (Physical Block Architecture) of the NAND flash memory to the host in order to improve the reliability and performance of the storage medium. Instead, they provide an abstraction layer by maintaining a mapping table between LBA and PBA internally. This mapping table can be simply referred to as the L2P (Logical to Physical) mapping table. Therefore, the host does not need to understand the specific implementation details of the underlying NAND flash memory; it only needs to process the LBA.

[0054] When a host initiates a read / write request for specific LBA data, the UFS device can first find the PBA corresponding to the LBA in the L2P table, and then read / write the data from the NAND flash memory based on the PBA. The speed at which the PBA is looked up in the L2P table (i.e., the lookup rate) significantly impacts the performance of the UFS device.

[0055] To minimize power consumption and cost considerations, embedded UFS storage devices lack internal Dynamic Random-Access Memory (DRAM) for caching L2P table entries. Instead, they cache entries in Static Random-Access Memory (SRAM). However, SRAM has limited space for storing entries, only a few tens of kilobytes (KB), allowing only a small portion of entries to be cached. This leaves the majority of entries stored in NAND flash memory. Therefore, if the UFS device cannot find the PBA corresponding to the LBA in SRAM (i.e., a table miss), it must download the entry from NAND flash memory and then search for the corresponding PBA in the downloaded L2P table. This reduces the lookup rate and significantly slows down the UFS device's performance.

[0056] Please see Figure 1 , Figure 1 This is a system call structure diagram of a NAND flash memory provided in an embodiment of this application. For example... Figure 1 As shown, the operating system (OS) includes the file system and underlying drivers, while the solid-state drive (SSD) includes the SSD interface, flash translation layer (FTL), NAND interface, and multiple NAND flash memory modules. The FTL includes bad block management, address translation, garbage collection, and wear leveling. The SSD interface is the physical and electrical connection specification connecting the SSD to the computer motherboard or other devices, ensuring stable and efficient data transfer and instruction reception between the SSD and the system. The NAND interface refers to the interface used for data communication between the NAND flash memory and external devices (such as processors, controllers, etc.).

[0057] like Figure 1 As shown, the file system in the operating system initiates a call request, which passes through the underlying driver, the SSD interface, FTL, and NAND interface of the SSD, reaching multiple NAND flash memory modules. Upon receiving the call request, the NAND flash memory module, through the NAND interface, FTL, SSD interface, and the underlying driver in the operating system, returns a corresponding call response to the file system. Based on... Figure 1 It is known that if it is necessary to download relevant content from NAND flash memory, such as downloading the L2P table, it is necessary to go through multiple nodes such as the underlying driver, the SSD interface in the SSD, FTL, and NAND interface. The download time is long, which affects the speed of table lookup based on L2P table and greatly slows down the performance of UFS device.

[0058] The relationship between the size of the L2P table and the data size is typically 1 / 1024, meaning that 1TB of data requires 1 gigabyte (GB) of space to store the corresponding table entries. As can be seen, embedded UFS storage devices only have megabytes of SRAM to cache table entries, which is insufficient to cache all entries of the L2P table. Cached only a portion of the L2P table entries in the NAND cache, leading to a decrease in table lookup speed and significantly slowing down UFS device performance. To solve this problem, a three-level mapping method can be used in the UFS device to cache all entries of the L2P table.

[0059] The three-level mapping refers to the use of a first-level mapping table, a second-level mapping table, and a third-level mapping table. The entries in the first-level mapping table include indexes of the second-level mapping table entries, the entries in the second-level mapping table include indexes of the third-level mapping table entries, and the entries in the third-level mapping table indicate the physical address corresponding to the data. The total size of the first-level mapping table is 1KB, and the total size of the second-level mapping table is 1MB. The first-level mapping table can reside permanently in SRAM, while a small portion of the second-level / third-level mapping table is stored in SRAM. However, due to device prediction based on host behavior, the second-level / third-level mapping table in SRAM is frequently updated.

[0060] In this application, "resident" refers to an area that persists throughout the program's execution and is not easily refreshed or overwritten, thus possessing non-volatile characteristics. Conversely, "non-resident" refers to an area that may be refreshed or overwritten during program execution, thus possessing volatile characteristics.

[0061] After adopting a three-level mapping, the specific process of reading data in a UFS device is as follows: Taking a 1 terabyte (TB) UFS device as an example, the size of the first-level mapping table is about 1kb, and the first-level mapping table is stored in SRAM. Then, when reading data, the first-level mapping table is used to look up the corresponding second-level mapping table, the second-level mapping table is used to look up the corresponding third-level mapping table, and the physical address on the NAND flash memory is read from the found third-level mapping table. Finally, the corresponding actual data is read from the NAND flash memory based on the physical address.

[0062] Please see Figure 2 , Figure 2 This is a structure diagram of host call data provided for the implementation of this application. For example... Figure 2As shown, the host's Central Processing Unit (CPU) can interact with the Solid State Drive (SSD). The host's CPU can also interact with DRAM. The SSD includes a PCI-Express (Peripheral Component Interconnect Express, PCI-E) interface or a Serial ATA (SATA, Serial ATA, SATA) interface, a CPU, SRAM, and a flash memory controller. The SRAM can cache a mapping table (L2P table). The SSD can interact with multiple NAND flash memory modules, which also store mapping tables (L2P tables). Therefore, when the host initiates a data read request, it needs to query the L2P table cached in the SRAM and then read the corresponding data from the NAND flash memory.

[0063] like Figure 3 As shown, Figure 3 This is a schematic diagram of a three-level mapping in a UFS device provided in an embodiment of this application. For example... Figure 3 As shown, the SRAM data table block stores a first-level mapping table (L1), a portion of the second-level mapping table (L2), and a portion of the third-level mapping table (L3). The NAND flash memory data table block stores a portion of the second-level mapping table (L2) and a portion of the third-level mapping table (L3). The L1 table contains N entries, each with an entry ID. The entry IDs for the N entries in the L1 table are 0, 1, 2, 3, ..., N-1. The entry information (entry INFO) for each entry in the L1 table includes the physical address of the L2 table (L2_TABLE_FAA) and the table identifier of the L2 table (L2_TABLE_ID). Here, FAA represents the aforementioned PBA.

[0064] The L2 table cache pool in SRAM contains multiple L2 tables, each with its own table identifier. Each L2 table also contains N entries, with corresponding entry identifiers of 0, 1, 2, 3, ..., N-1. The entry information for each L2 table includes the physical address of the L3 table (L3_TABLE_FAA) and the L3 table identifier (L3_TABLE_ID).

[0065] The L3 table cache pool in SRAM contains multiple L3 tables, each with its own table identifier. Each L3 table contains 1024 data entries, and each entry in each L3 table stores the physical address of the data (DATA_FAA).

[0066] The data table blocks of NAND flash memory include an L2 table pool and an L3 table pool. The L2 table pool contains multiple L2 tables, each with a corresponding table identifier, such as L2 table (0), L2 table (1), etc. Each L2 table contains 1024 entries, and the entry information is the physical address of the L3 table. The L3 table pool contains multiple L3 tables, each with a corresponding table identifier, such as L3 table (0), L3 table (1), etc. Each L3 table contains 1024 entries, and the entry information is the physical address of the data.

[0067] like Figure 3 As shown, the process first searches for the address information of the L2 table in the L1 table. The entry identifier of the L2 table in the L1 table can be calculated based on the logical address of the data to be read. If the L2 table is found in the information corresponding to entry identifier M, the corresponding L2 table is then searched in the SRAM based on the L2 table's identifier and physical address. If the corresponding L2 table is found in the SRAM, the search continues in the L3 table. If the corresponding L3 table is found in the SRAM, the physical address of the data is read from the found L3 table, and then the corresponding data is read from the NAND flash memory based on that physical address.

[0068] If the corresponding L2 table is not found in SRAM, the corresponding L2 table is searched in NAND flash memory based on the L2 table identifier and physical address. Then, the corresponding L3 table is searched within the L2 table. After the corresponding L3 table is found, the physical address of the data is read from the found L3 table, and then the corresponding data is read from the NAND flash memory based on the physical address of the data.

[0069] Therefore, although the three-level mapping method can save storage space in SRAM, requiring only a portion of the entries to be stored in SRAM, if the corresponding L2 table is not found in SRAM, it is necessary to first read the second-level mapping table from the NAND flash memory, and then use the second-level mapping table to look up the corresponding third-level mapping table. Figure 1 As shown in the NAND flash memory data reading process, reading data from the NAND chip requires going through multiple nodes, which is a complicated process. Even when reading the corresponding data from the three-level mapping table of the NAND chip, the performance overhead of the read operation is still large, affecting the performance of the UFS device.

[0070] Taking a certain UFS device as an example, the SRAM of this UFS device only allocates about 16 4kb buffers of storage space for the secondary mapping table, which can only cover the entire 64GB of data on the disk. The remaining data entries are stored on the NAND chip. To read data from the remaining secondary mapping tables, the secondary mapping table must first be read from the NAND chip, and then the corresponding tertiary mapping table must be looked up through the secondary mapping table to read the corresponding data from the tertiary mapping table on the NAND chip. Compared to read operations in SRAM, read operations in NAND have a significant performance overhead, which not only affects the performance of the UFS device, but is also unacceptable for some high-performance scenarios such as loading large AI models.

[0071] Please see Figure 4 , Figure 4 This illustrates the timing of hitting an entry in SRAM and loading an entry in NAND. (See diagram.) Figure 4 It is known that by adding trace points to the read / write process of the UFS device's firmware (FW) and analyzing the table lookup time, it can be seen that the time for a table entry to be hit in SRAM is approximately 110–120 µs, while the time to load the table entry from NAND when the table entry is not hit in SRAM is approximately 4–6 ms. Therefore, the performance difference between read operations in SRAM and read operations in NAND is significant, with read operations in NAND incurring substantial performance overhead.

[0072] In summary, this application provides a data storage method and an electronic device. In this method, the electronic device resident the table information (or simply table entry) of data with a first attribute in SRAM. The first attribute can refer to performance-sensitive important data. When a read request for data A with the first attribute is received, all table entries corresponding to data A can be found in the SRAM. Therefore, the electronic device only needs to follow the correspondence between the logical address and physical address indicated by the table entry information for data A to read the data A corresponding to the table entry information from the NAND flash memory. That is, this data read can be performed with only one NAND operation, improving the performance of the UFS device.

[0073] In this approach, electronic devices can allocate a portion of SRAM space as a resident area for important data entries, disallowing the replacement of non-essential entries; that is, this resident area cannot store / cache entries containing non-essential data. Simultaneously, to address the issue of insufficient SRAM space, a compressed read table is proposed, capable of storing large amounts of data that can be read and written sequentially.

[0074] Important data can refer to artificial intelligence (AI) data, frequently used data, etc. Insignificant data can refer to data with low usage frequency, etc. In this embodiment, important data can be designated as the first attribute, and insignificant data as the second attribute. Data that is read and written continuously can refer to data with consecutive logical or physical addresses, while data that is read and written discontinuously can refer to data with non-consecutive logical or physical addresses.

[0075] In this embodiment, the data storage method can be executed by an electronic device, which includes a first memory and a second memory. The access efficiency of the first memory is higher than that of the second memory. The first memory includes a resident area, which is used to store table entry information for data of the first attribute and table entry information that does not support storing data of the second attribute. The electronic device can be a UFS device or a device including a module supporting the UFS protocol. The device including a module supporting the UFS protocol can be called a host (or host machine). The following example uses an electronic device as a UFS device, with the UFS device and host deployed independently. The specific workflow of this method is as follows: Figure 5 As shown, steps S101-S108 are as follows:

[0076] Step S101: Receive the write command and the data to be stored.

[0077] The write instruction may include the tag information of the data to be stored and the logical address of the data to be stored. The tag information of the data to be stored may be used to indicate the attributes of the data to be stored. The attributes of the data to be stored may be a first attribute or a second attribute.

[0078] In this embodiment, the host sends the data to be stored and a write command to the UFS device. The UFS device receives the write command and the data to be stored from the host. The write command can be a Write10 command. The reserved field in this write command contains tag information. Subsequently, the UFS device can identify the attributes of the data to be stored by the host based on the tag. The write command also includes the logical address of the data to be stored.

[0079] Step S102: In response to the write command, identify the tag information of the data in the write command.

[0080] If the identified tag information is tag information 1, it means that the attribute of the data to be stored is the first attribute, and steps S103-S105 are executed. If the identified tag information is tag information 2, it means that the attribute of the data to be stored is the second attribute, and steps S106-S108 are executed.

[0081] In this embodiment, after receiving a write command, the UFS device can identify the tag information contained in the write command.

[0082] The Host Interface Layer (HCI) of the UFS device can identify tag information. If the identified tag information is valid, or tag information 1 is identified, the data is marked as data of the first attribute. Otherwise, the data is marked as data of the second attribute. The tag information can refer to an identifier bit. For example, an identifier bit of 1 indicates that the corresponding tag information is valid, or that the corresponding tag information is tag information 1. An identifier bit of 0, or any number other than 1, indicates that the corresponding tag information is invalid, or that the corresponding tag information is tag information 2.

[0083] Step S103: Store the data of the first attribute in the second memory.

[0084] In this embodiment, volatile memory is designated as the first memory, where volatile memory can refer to SRAM. Non-volatile memory is designated as the second memory, where non-volatile memory can refer to NAND flash memory. The UFS device first writes the data of the first attribute to the NAND flash memory (second memory), and the physical address of the data of the first attribute will exist in the NAND. Subsequently, the data of the first attribute can be read from the NAND flash memory based on the physical address of the data of the first attribute.

[0085] In some embodiments, when a UFS device receives a write instruction, it stores the data to be stored in a second memory. Then, the UFS device identifies the tag information contained in the write instruction and performs subsequent write operations based on the attributes of the data to be stored indicated by the tag information.

[0086] Step S104: Store the table entry information of the first attribute data into the write cache table of the first memory.

[0087] The SRAM (first memory) includes a write cache table (WCT) and a read cache table (RCT). After the data of the first attribute is written to the NAND flash memory, the table entry information of the first attribute data is first stored in the write cache table.

[0088] In this embodiment, the UFS device calculates a three-level mapping relationship in WCT based on the correspondence between the logical address and physical address of the data of the first attribute, namely, a first-level mapping table, a second-level mapping table, and a third-level mapping table. This three-level mapping relationship is then used as the table entry information for the data of the first attribute. The table entry information for the data of the first attribute can be used to indicate the correspondence between the logical address and the physical address of the data of the first attribute.

[0089] Among them, the table entry information of the first attribute data stored in the write cache table also carries the second tag information (which can be called tag information 3). The tag information 3 is used to indicate that the table entry information of the data to be stored is the table entry information of the first attribute data.

[0090] Step S105: Flush the table entry information of the first attribute data into the second memory, and update the read cache table at the same time.

[0091] In this embodiment, the UFS device will flush the table entry information of the first attribute data in the WCT to the NAND flash memory. The table entry information of the first attribute data carries tag information 3 (mark bit) during the flushing process. That is, the table entry information of the first attribute data stored in the NAND flash memory will also contain tag information indicating that the data belongs to the first attribute. Flushing the table entry information of the first attribute data to the second memory includes downloading the table entry information of the first attribute data from the current WCT and storing it in the second memory. Specific implementation details can refer to existing technologies and will not be elaborated further.

[0092] When the table entries for the first attribute data in the WCT are flushed to the NAND flash memory, the table entries for the first attribute data are also synchronously updated in the RCT. The RCT includes resident and non-resident areas. The UFS device synchronously updates the L3 level-three mapping table of the first attribute data in the WCT to the resident area of ​​the RCT, and also synchronously updates the L1 level-one mapping table and L2 level-two mapping table in the WCT to other areas of the RCT. Other areas of the RCT refer to areas other than the resident and non-resident areas.

[0093] The RCT also includes a Compression Read Table (CRT). The CRT and L3 table are at the same level, both used to store the physical addresses of data. The CRT stores entries for consecutive LBA data, while the L3 table stores entries for random LBA data. The CRT includes resident and non-resident areas. The resident area stores entries for consecutive LBA data with a first attribute, and the non-resident area stores entries for consecutive LBA data with a second attribute. Similarly, the RCT's L3 table includes resident and non-resident areas. The resident area stores entries for random LBA data with a first attribute, and the non-resident area stores entries for random LBA data with a second attribute. Consecutive LBA data can refer to data with consecutive logical addresses, while random LBA data can refer to data with non-consecutive logical addresses.

[0094] Subsequently, when the electronic device reads data and queries the secondary mapping table L2, if it determines that a certain entry in the L2 table is the target entry, the entry information of that entry can be the table identifier of the L3 table or the table identifier of the CRT. Then, the electronic device finds the corresponding L3 table or CRT based on the table identifier of the L3 table or the table identifier of the CRT.

[0095] In this embodiment, the UFS device identifies whether the logical address of the data of the first attribute is a consecutive logical address with the logical address of the data already stored in the CRT's resident area. If yes, the L3 table corresponding to the data of the first attribute is synchronized to the CRT's resident area. If not, the L3 table corresponding to the data of the first attribute is synchronized to the resident area of ​​the L3 table.

[0096] Specifically, synchronizing the L3 table corresponding to the data of the first attribute to the CRT's resident area includes: identifying the logical address of the data of the first attribute based on the L3 table; determining the start logical address and the end logical address from the logical address of the data of the first attribute and the logical addresses of the stored data; and then storing in the first resident area of ​​the CRT the start logical address and its corresponding physical address, the end logical address and its corresponding physical address, and the total number of logical addresses of the data of the first attribute and the logical addresses of the stored data.

[0097] In some embodiments, before synchronizing the L3 table corresponding to the data of the first attribute to the resident area of ​​the L3 table, the UFS device identifies whether the logical address of the data of the first attribute and the logical address of the already stored data in the resident area of ​​the L3 table are consecutive logical addresses. If yes, the UFS device synchronizes the L3 table corresponding to the data of the first attribute and the L3 table corresponding to the already stored data in the resident area of ​​the L3 table to the resident area of ​​the CRT, and deletes the entry in the resident area of ​​the L3 table containing the L3 table corresponding to the already stored data. If no, the UFS device synchronizes the L3 table corresponding to the data of the first attribute to the resident area of ​​the L3 table. The specific steps for synchronizing the L3 table corresponding to the data of the first attribute and the L3 table corresponding to the already stored data in the resident area of ​​the L3 table to the resident area of ​​the CRT are described above in the description of synchronizing the L3 table to the resident area of ​​the CRT.

[0098] In some embodiments, the table entry information of the first attribute data is the correspondence between logical addresses and physical addresses. After the UFS device writes this table entry information into the WCT, it then flushes the table entry information to the NAND flash memory and simultaneously synchronizes it to the RCT. The table entry information is directly stored in the resident area of ​​the RCT.

[0099] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating the storage of an RCT as provided in an embodiment of this application. For example... Figure 6 As shown, the RCT can store L1, L2, L3 tables and CRTs. Each CRT contains resident and non-resident areas. Each CRT also has a corresponding table identifier. The entry information for each entry in a CRT can include the starting LBA (also called LAA) / PBA (also called FAA) and the total number, where the total number refers to the length of the compressed data.

[0100] Each 4B entry can record a maximum of 4MB of continuous data. A typical CRT contains 1K entries, allowing for a maximum of 4GB of continuous data, thus meeting the needs of large models and demonstrating the optimization process. Furthermore, after optimization is complete, the status of the UFS device can be retrieved again, providing an optimization score.

[0101] The L3 table contains 1024 entries. The entry identifiers can be 0, 1, ..., 1023, and the entry information is the physical address of the data.

[0102] In this embodiment, the resident area of ​​SRAM is not refreshed in real time. Only when a write instruction for a certain data that has been stored in the L3 table in the resident area is received again, and the data is written according to the write instruction, if the correspondence between the logical address and physical address of the data is updated, the L3 table corresponding to the data in the resident area is updated.

[0103] Among them, the aforementioned resident area can use a data structure management method such as a ring buffer. When the resident area is not full, the entries are stored normally. When the resident area is full, the entries are overwritten in a circular manner, that is, the newly stored entries in the resident area overwrite the oldest stored entries.

[0104] Step S106: Store the data of the second attribute in the second memory.

[0105] In this embodiment, the UFS device writes the data of the second attribute to NAND flash memory (second memory), and the physical address of the data of the second attribute will exist in the NAND. Subsequently, the corresponding data of the second attribute can be read from the NAND flash memory based on the physical address of the data of the second attribute.

[0106] Step S107: Store the table entry information of the second attribute data into the write cache table of the first memory.

[0107] In this embodiment, after the data of the second attribute is written to the NAND flash memory, the corresponding data table entry of the second attribute data is first stored in the write cache table WCT.

[0108] The UFS device calculates a three-level mapping relationship in WCT based on the correspondence between the logical address and physical address of the data in the second attribute. This includes a first-level mapping table, a second-level mapping table, and a third-level mapping table. The calculated three-level mapping relationship is used as the table entry information for the data in the second attribute. This table entry information can be used to indicate the correspondence between the logical address and the physical address of the data in the second attribute.

[0109] Step S108: Flush the table entry information of the second attribute data into the second memory.

[0110] After the table entry information of the second attribute data is calculated in WCT, the table entry information of the second attribute data will be stored in NAND flash memory (second memory).

[0111] Therefore, the electronic device stores the table information of the first attribute data in the RCT. After receiving the read instruction for the first attribute data issued by the host, it can find the mapping table entry of the data in the RCT and read the first attribute data with high performance.

[0112] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating a WCT-based method for flushing table entries, as provided in an embodiment of this application. Figure 7As shown, the host issues a write command, and after writing the data to the NAND flash memory, the WCT stores the table entry information for that data. Then, the WCT flushes the table entry information to the data block table of the NAND flash memory. The data block table of the NAND flash memory stores an L2 table pool and an L3 table pool. The L2 table pool contains multiple L2 tables, each with a corresponding table identifier, such as L2 table (0), L2 table (1), etc. Each L2 table contains 1024 entries, and the entry information is the physical address of the L3 table. The L3 table pool contains multiple L3 tables, each with a corresponding table identifier, such as L3 table (0), L3 table (1), etc. Each L3 table contains 1024 entries, and the entry information is the physical address of the data.

[0113] When WCT flushes table entry information to the NAND flash memory's data block table, if the data is of the first attribute, it will also synchronize the table entry information to RCT. RCT can read information from the L3 table stored in the NAND flash memory and, based on this information, distinguish between continuous and random data. RCT can store L1, L2, L3 tables, and CRT. RCT directly stores the L3 table corresponding to random data and stores the L3 table of continuous data in the CRT. Each entry in the CRT can include the LBA / PBA of the starting position and the length of the data.

[0114] The host can issue a read command to directly read the data of the first attribute from the RCT.

[0115] The following section details the specific process of reading data, such as... Figure 8 As shown, the entity performing the data reading is a UFS device, and the specific process of reading the data may include steps S201-S217:

[0116] Step S201: Receive read command.

[0117] In this embodiment, the host sends a read command to the UFS device, and the UFS device receives the read command from the host.

[0118] The read instruction can refer to the Read 10 command, used to read data. The reserve field in this read instruction contains a tag (which can be called third-party tag information), indicating whether the data's attribute is a first attribute or a second attribute. The read instruction also includes the logical address of the data to be read (or the first data).

[0119] Please see Figure 9 , Figure 9 This shows the location of the reserved field in the read command, such as... Figure 9 The area highlighted by the black box 801 can contain a Tag in the reserve field. In addition, the read instruction also includes the logical address of the data to be read. Besides these, the read instruction includes other fields; the meanings and locations of these other fields are described in existing technology and will not be elaborated upon here.

[0120] Step S202: In response to the read command, identify the tag information of the data to be read in the read command.

[0121] In this embodiment, after receiving a read command, the UFS device can identify the tag information contained in the read command.

[0122] The HCI layer of the UFS device can identify tag information. If the identified tag information is valid, or if the tag information indicates that the data's attribute is a first attribute, then the data is marked as data with the first attribute. If the identified tag information indicates that the data's attribute is a second attribute, then the data is marked as data with the second attribute.

[0123] Further optionally, if the attribute of the data to be read is identified as a first attribute, proceed to steps S203-S206. If the attribute of the data to be read is identified as a second attribute, proceed to steps S207-S217.

[0124] Step S203: In response to the attribute of the data to be read being the first attribute, search for the table entry information of the data to be read in the write buffer of the first memory.

[0125] In this embodiment, after identifying that the attribute of the data to be read is the first attribute, the corresponding table entry information is first searched in the WCT of the first memory.

[0126] It's understandable that when data for each first attribute is written to memory, the table entry information is first stored in the WCT (Write-Ahead Table) and then synchronized to the RCT (Read-Ahead Table). Therefore, if a read command for that data is received before the table entry information in the WCT has been synchronized to the RCT, the table entry information for that data will be found in the WCT. If the table entry information for that data is not found in the WCT, it means that the WCT may have refreshed, overwritten, or deleted the table entry information for that data, and then the table entry information for that data can be retrieved from the RCT.

[0127] Step S204: Read the data to be read from the second memory based on the lookup result of the write buffer.

[0128] Optionally, after finding the corresponding physical address in WCT based on the logical address of the data to be read, the data to be read is read from the NAND flash memory according to the physical address of the data to be read. Furthermore, the read data is returned to the host.

[0129] Step S205: Search for the table entry information of the data to be read from the read cache of the first memory.

[0130] Optionally, if the table entry information for the data to be read is not found in the WCT, the table entry information for the data to be read is searched in the RCT.

[0131] For example, if the WCT has already synchronized the table entry information of the data to be read to the RCT, and then the WCT is refreshed in real time, the WCT no longer stores the table entry information of the data to be read. In this case, the UFS device can retrieve the table entry information of the data to be read from the RCT.

[0132] Specifically, the UFS device first queries the L1 table in the RCT based on the logical address of the data to be read, and then retrieves the address information of the corresponding L2 table from the L1 table. Next, the UFS device queries the L2 table to find the address information of the corresponding L3 table or the address information of the CRT for the data to be read.

[0133] Step S206: Read the data to be read from the second memory according to the lookup result of the read buffer.

[0134] Finally, the corresponding L3 table or CRT is located based on the address information of the L3 table or the CRT, and the data to be read is read from the L3 table or CRT.

[0135] Step S207: In response to the attribute of the data to be read being the second attribute, search for the table entry information of the data to be read in the write buffer of the first memory.

[0136] In this embodiment, after identifying that the attribute of the data to be read is the second attribute, the corresponding table entry information is also first searched in the WCT of the first memory.

[0137] Step S208: Read the data to be read from the second memory based on the lookup result of the write buffer.

[0138] Optionally, after finding the corresponding physical address in WCT based on the logical address of the data to be read, the data to be read is read from the NAND flash memory based on the physical address of the data to be read.

[0139] Step S209: Search for the table entry information of the data to be read from the L1 table in the read cache.

[0140] Optionally, if the table entry information for the data to be read is not found in the WCT, the table entry information for the data to be read is searched in the RCT. Specifically, the UFS device first queries the L2 table corresponding to the data to be read from the L1 table of the RCT.

[0141] Step S210: Locate the table entry information of the data to be read from the L2 table of the second memory.

[0142] Optionally, if the L2 table corresponding to the data to be read is not in the RCT, the table entry information of the data to be read is searched from the L2 table in the NAND flash memory.

[0143] Step S211: Locate the table entry information of the data to be read from the L3 table of the second memory.

[0144] Optionally, after finding the address information of the L3 table from the L2 table in the NAND flash memory, the physical address of the data to be read is then found from the L3 table.

[0145] Step S212: Read the data to be read from the second memory according to the lookup result of the L3 table.

[0146] Optionally, the data to be read is read from the NAND flash memory based on the physical address of the data to be read found in the L3 table. Then, the read data is returned to the host.

[0147] Step S213: Search for the table entry information of the data to be read from the L2 table in the read cache.

[0148] Optionally, after finding the address information of the L2 table from the L1 table in the RCT, the address information of the L3 table corresponding to the data to be read is then found from the L2 table of the RCT.

[0149] Step S214: Locate the table entry information of the data to be read from the L3 table of the second memory.

[0150] Optionally, if the L3 table corresponding to the data to be read is not in the RCT, the table entry information of the data to be read is searched from the L3 table in the NAND flash memory.

[0151] In this embodiment, after obtaining the table entry information of the data to be read from the NAND flash memory, the table entry information of the data is synchronized to the non-resident area of ​​the RCT. Specifically, it is identified whether the data is continuous data. If it is continuous data, the table entry information of the data is synchronized to the non-resident area of ​​the CRT. If it is random data, the table entry information of the data is synchronized to the non-resident area of ​​the L3 table.

[0152] Among them, it can identify whether the data is continuous data, that is, determine whether the logical address of the data is continuous with the logical address of the data already stored in the non-resident area of ​​the RCT. If so, the data is continuous data; otherwise, the data is random data.

[0153] Step S215: Read the data to be read from the second memory according to the lookup result of the L3 table.

[0154] Optionally, the data to be read can be retrieved from the NAND flash memory based on the physical address of the data to be read found in the L3 table. The retrieved data is then returned to the host.

[0155] Step S216: Locate the table entry information of the data to be read from the L3 table or compressed read table in the read buffer.

[0156] Optionally, the address information of the L3 table or CRT can be found in the L2 table of the RCT, and then the physical address of the data to be read can be found in the L3 table or CRT.

[0157] Step S217: Read the data to be read from the second memory according to the lookup result of the L3 table.

[0158] Optionally, the data to be read can be retrieved from the NAND flash memory based on the physical address of the data to be read found in the L3 table or CRT. The retrieved data is then returned to the host.

[0159] In summary, upon receiving a read command, the corresponding table entry information can be retrieved from different regions based on the attributes of the data to be read. If the attribute of the data to be read is the first attribute, it is not necessary to obtain the table entry information from NAND; the corresponding table entry information can be directly obtained from SRAM, and then the data can be read directly from NAND based on the query result, thus improving data reading efficiency. If the data to be read is the second attribute, and the corresponding table entry information is not found in SRAM, the table entry information can be obtained from NAND, and the data can be read from NAND based on the query result. This solution only changes the logic of storing table entry information in SRAM, but all table entry information is still stored in NAND flash memory for subsequent reloading.

[0160] In this embodiment, if the UFS device experiences a normal power outage, the data stored in the RCT is discarded without processing. Since the table entries in the RCT are only backups of the NAND, the UFS device can scan the table entries in the NAND again upon the next power-on and reload the corresponding table entries back into the RCT based on the flag bits carried by the data (such as tag information used to indicate whether the data attribute is a first attribute or a second attribute).

[0161] If the UFS device experiences an abnormal power outage, such as an anomaly during WCT flashing, the WCT flashing anomaly handling procedure will be executed. The WCT flashing anomaly handling procedure can be found in current technology and will not be elaborated upon here.

[0162] For example, if an error occurs while synchronizing table entry information to the RCT, no action needs to be taken. Upon the next power-on, the UFS device can scan the table entry information in the NAND again and reload the corresponding table entry information back to the RCT.

[0163] It should be understood that the normal execution of the above method embodiments requires the support of the specific hardware and software structure of the electronic device. The hardware and software structure of the electronic device are described below. Figure 10 The diagram shows the internal software architecture of an electronic device. A layered architecture divides the software into several layers, each with a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, the internal architecture of an electronic device can be divided into five layers, from top to bottom: the application layer, the application framework layer, the Android runtime (ART) and native C / C++ libraries, the hardware abstraction layer (HAL), and the kernel layer.

[0164] The application layer can include a series of application packages.

[0165] like Figure 10 As shown, the application package may include applications such as gallery, calendar, calling, maps, navigation, WLAN, Bluetooth, music, and SMS.

[0166] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0167] like Figure 10 As shown, the application framework layer may include a window manager, content provider, view system, resource manager, notification manager, activity manager, input manager, etc.

[0168] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display interface including a text notification icon could include views for displaying text and views for displaying images.

[0169] The notification manager allows applications to display notifications in the status bar. These notifications can be used to deliver informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify users of completed downloads or message alerts. The notification manager can also display notifications as icons or scrolling text in the top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights.

[0170] The input manager can provide an input management service (IMS), which can be used to manage system inputs, such as touchscreen input, keypad input, and sensor input. IMS retrieves events from input device nodes and, through interaction with the WMS, distributes these events to the appropriate windows.

[0171] The Android runtime consists of the core libraries and the Android runtime itself. The Android runtime is responsible for converting source code into machine code. The Android runtime primarily employs ahead-of-time (AOT) compilation and just-in-time (JIT) compilation techniques.

[0172] The core library primarily provides basic Java class library functionalities, such as libraries for fundamental data structures, mathematics, I / O, tools, databases, and networking. It also provides APIs for users to develop Android applications.

[0173] Native C / C++ libraries can include multiple functional modules. Examples include: surface manager, media framework, libc, OpenGL ES, SQLite, Webkit, etc.

[0174] The Hardware Abstraction Layer (HAL) runs in user space, encapsulates kernel-level drivers, and provides calling interfaces to higher layers. The HAL includes at least a UFS module, a display module, and a sensor module.

[0175] The kernel layer is the layer between hardware and software. The kernel layer contains at least the UFS driver, display driver, and sensor driver.

[0176] In this embodiment, the UFS driver is responsible for direct interaction with the UFS device's controller, including initialization, configuration, and power management, and handling various operation requests. The UFS driver parses information in the device tree, starts and configures the hardware, bringing it into a working state.

[0177] Figure 11This illustration shows a hardware structure diagram of an electronic device 100. The electronic device 100 may include at least one of the following: mobile phone, foldable electronic device, tablet computer, desktop computer, laptop computer, handheld computer, laptop, ultra-mobile personal computer (UMPC), netbook, cellular phone, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, wearable device, in-vehicle device, smart home device, or smart city device. This application does not impose any special limitations on the specific type of the electronic device 100.

[0178] Electronic device 100 may include processor 110, external memory interface 120, internal memory 121, universal serial bus (USB) connector 130, charging management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, sensor module 180, button 190, camera 191, and display screen 192.

[0179] The sensor module 180 may include pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, position sensors, etc. The touch sensor can also collect user touch data.

[0180] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0181] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0182] The processor can generate operation control signals based on the instruction opcode and timing signals to control the instruction fetching and execution. For example, the processor can execute instructions to implement the data storage method provided in this application.

[0183] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 may be a cache memory. This memory can store instructions or data that the processor 110 has used or that are used frequently. If the processor 110 needs to use the instruction or data, it can directly retrieve it from this memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0184] In some embodiments, the processor 110 may include one or more interfaces. These interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc. The processor 110 can connect to modules such as touch sensors, audio modules, wireless communication modules, displays, and cameras through at least one of these interfaces.

[0185] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0186] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0187] In this embodiment, the internal memory 121 can be divided into a first memory and a second memory. The first memory is SRAM, and the second memory is NAND flash memory. The SRAM is used to store table entry information, and the NAND flash memory is used to store data. Specifically, the first memory may have the storage partitions present in the method embodiments of this application, such as a resident area and a non-resident area.

[0188] It should be understood that Figure 9 The illustration shown is an example, except Figure 9 Besides the aforementioned components, the electronic device may also include other components, without limitation. Figure 9 The specific functions of the components of the electronic device shown, excluding the processor and internal memory, can be found in the existing descriptions and will not be repeated here.

[0189] The methods described in the foregoing embodiments can all be implemented in the electronic device 100 having the aforementioned hardware and software structures.

[0190] This application also provides a chip system, such as... Figure 12 As shown, the chip system 900 includes at least one processor 901 and at least one interface circuit 902. The processor 901 and the interface circuit 902 are interconnected via lines. For example, the interface circuit 902 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 902 can be used to send signals to other devices (e.g., the processor 901). Exemplarily, the interface circuit 902 can read instructions stored in the memory and send those instructions to the processor 901. When the instructions are executed by the processor 901, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete components, and this application embodiment does not specifically limit this.

[0191] This application also provides a computer storage medium that includes computer instructions. When the computer instructions are executed on the electronic device, the electronic device causes the electronic device to perform various functions or steps performed by the mobile phone in the above method embodiment.

[0192] This application also provides a computer program product that, when run on a computer, causes the computer to perform the various functions or steps performed by the mobile phone in the above method embodiments.

[0193] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0194] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0195] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0196] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0197] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0198] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data storage method, characterized in that, The method is applied to an electronic device, which includes a first memory and a second memory. The access efficiency of the first memory is higher than that of the second memory. The first memory includes a resident area for storing table entry information of data with a first attribute and table entry information that does not support storing data with a second attribute. The data with the first attribute is more important than the data with the second attribute. Receive a write instruction and data to be stored; wherein, the write instruction includes first tag information and the logical address of the data to be stored, and the first tag information is used to indicate the attributes of the data to be stored; The data to be stored is stored in the second memory; When the first tag information indicates that the attribute of the data to be stored is the first attribute, the table entry information of the data to be stored is stored in the resident area of ​​the first memory; the table entry information of the data to be stored is used to indicate the correspondence between the logical address and the physical address of the data to be stored.

2. The method according to claim 1, characterized in that, The first memory includes a write cache table; before storing the table entry information of the data to be stored in the resident area of ​​the first memory, the method further includes: In response to the data to be stored being stored being stored in the second memory, table entry information for the data to be stored is generated; Store the table entry information of the data to be stored in the write cache table; The table entry information of the data to be stored in the write cache table is flushed to the second memory.

3. The method according to claim 2, characterized in that, The first memory further includes a read cache table, and the resident area is included in the read cache table; storing the table entry information of the data to be stored into the resident area of ​​the first memory includes: Determine the table entry information of the first attribute in the table entry information of the data to be stored; Update the table entry information of the first attribute data in the read cache table to the resident area of ​​the read cache table.

4. The method according to claim 3, characterized in that, The step of storing the table entry information of the first attribute data into the write cache table includes: In response to the first tag information indicating that the attribute of the data to be stored is the first attribute, the table entry information of the data to be stored and the second tag information are stored in the write cache table accordingly, wherein the second tag information is used to indicate that the table entry information of the data to be stored is the table entry information of the data with the first attribute; The step of determining the table entry information of the first attribute in the table entry information of the data to be stored includes: determining the table entry information of the read cache table that corresponds to the second tag information as the table entry information of the first attribute.

5. The method according to claim 3, characterized in that, The step of updating the table entry information of the first attribute data in the read cache table to the resident area of ​​the read cache table includes: A first-level mapping table, a second-level mapping table, and a third-level mapping table are generated based on the table entry information of the data of the first attribute. The table entry of the first-level mapping table includes the index of the table entry of the second-level mapping table, the table entry of the second-level mapping table includes the index of the table entry of the third-level mapping table, and the table entry of the third-level mapping table is used to indicate the physical address of the data of the first attribute. Update the three-level mapping table to the resident area of ​​the read cache table; The method further includes updating the first-level mapping table and the second-level mapping table to the read cache table.

6. The method according to claim 5, characterized in that, The read cache table includes a compressed cache table and an uncompressed cache table. The compressed cache table includes a first resident area, and the uncompressed cache table includes a second resident area. The step of updating the third-level mapping table to the resident area of ​​the read cache table includes: Identify whether the logical address of the data of the first attribute is a continuous logical address with the logical address of the data already stored in the first resident area; If so, then synchronize the third-level mapping table corresponding to the data of the first attribute to the first resident area; If not, then synchronize the third-level mapping table corresponding to the data of the first attribute to the second permanent area.

7. The method according to claim 6, characterized in that, The step of synchronizing the third-level mapping table corresponding to the data of the first attribute to the first resident area includes: The logical address of the data for the first attribute is identified based on the three-level mapping table; Determine the start logical address and the end logical address from the logical address of the data of the first attribute and the logical address of the stored data; The first resident area stores the starting logical address and the physical address corresponding to the starting logical address, the ending logical address and the physical address corresponding to the ending logical address, and the total number of logical addresses of the data of the first attribute and the logical addresses of the stored data.

8. The method according to any one of claims 1-7, characterized in that, include: Receive a read instruction; wherein the read instruction is used to read first data, the read instruction includes tag information of the first data and logical address of the first data; the tag information of the first data is used to indicate the attributes of the first data; The table entry information of the first data is obtained by searching the tag information of the first data; Based on the logical address of the first data, the physical address of the first data is found from the table entry information of the first data; based on the physical address of the first data, the first data is read from the second memory.

9. The method according to claim 8, characterized in that, The step of finding the table entry information of the first data based on the tag information of the first data includes: In response to the attribute of the first data being the first attribute, the table entry information of the first data is retrieved from the write cache table of the first memory.

10. The method according to claim 9, characterized in that, If the table entry information for the first data is not found in the write cache table of the first memory, the method further includes: Based on the logical address of the first data, the corresponding target second-level mapping table is searched from the first-level mapping table in the read cache of the first memory; Find the corresponding target tertiary mapping table from the found target secondary mapping table; The physical address of the first data is determined from the found target three-level mapping table.

11. The method according to claim 8, characterized in that, The step of finding the table entry information of the first data based on the tag information of the first data includes: In response to the attribute of the first data being the second attribute, the table entry information of the first data is retrieved from the write cache table of the first memory; If the table entry information of the first data is not found in the write cache table of the first memory, then the table entry information of the first data is obtained from the second memory.

12. The method according to claim 11, characterized in that, After retrieving the table entry information of the first data from the second memory, the method further includes: The table entry information of the first data is synchronized to the non-resident area of ​​the read cache table of the first memory.

13. The method according to any one of claims 1-12, characterized in that, The first memory is a static random access memory (SRAM); The second memory is NADA flash memory.

14. An electronic device, characterized in that, The electronic device includes: a first memory, a second memory, and one or more processors; the first memory, the second memory, and the processors are coupled; the first memory and / or the second memory are used to store computer program code, the computer program code including computer instructions, which, when executed by the electronic device, cause the electronic device to perform the method as described in any one of claims 1-13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed in an electronic device, cause the electronic device to perform the method as described in any one of claims 1 to 13.

16. A computer program product, characterized in that, The computer program product includes instructions that, when executed in a terminal device, cause the terminal device to perform the method as described in any one of claims 1 to 13.

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