Method and electronic device for memory management

Abstract

A method and an electronic device for memory management are provided. The processor-implemented method includes determining whether a page usage of a first sub-memory area of a first memory node among a plurality of memory nodes of a memory is greater than or equal to a first threshold value, in response to the page usage of the first sub-memory area being greater than or equal to the first threshold value, determining a second sub-memory area of the first memory node, determining a target page among pages of the determined second sub-memory area, and allocating the target page of the determined second sub-memory area to the first sub-memory area.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0175922, filed on November 29, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to methods and electronic devices for memory management. Background Technology

[0003] In a typical system-on-a-chip (SoC) architecture with multiple cores, the mapping method between physical memory addresses and memory nodes (or address space partitioning) can be programmable; however, the mapping method used is fixed after the SoC is booted. When the typical mapping between physical memory addresses and memory nodes is set at SoC boot time, this mapping cannot be dynamically modified during SoC operation, which can lead to the problem of over-utilizing memory on specific memory nodes. Furthermore, some applications may use memory nodes that do not meet their required characteristics due to the above mapping, which can hinder the achievement of the application's desired performance. Summary of the Invention

[0004] The present invention is provided in a simplified form to introduce the choice of concepts further described in the following detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0005] In one or more general aspects, a processor-implemented method includes: determining whether a page utilization rate of a first sub-memory region of a first memory node among a plurality of memory nodes of memory is greater than or equal to a first threshold; in response to the page utilization rate of the first sub-memory region being greater than or equal to the first threshold, determining a second sub-memory region of the first memory node; determining a target page among the pages of the determined second sub-memory region; and allocating the target page of the determined second sub-memory region to the first sub-memory region.

[0006] In response to a page utilization rate of a first sub-memory region being greater than or equal to a first threshold, the step of determining a second sub-memory region of a first memory node may include: determining the second sub-memory region based on the page utilization rates of multiple sub-memory regions of the first memory node.

[0007] The step of allocating a target page of a second sub-memory region to a first sub-memory region may include associating the target physical address of the target page with a first sub-region identifier corresponding to the first sub-memory region.

[0008] The step of allocating a target page of a second sub-memory region to a first sub-memory region may include: changing the value of a first field in the bit field indicating the target physical address of the target page to a preset value; and changing the value of a second field in the bit field indicating the sub-memory region to be reallocated to the target physical address of the target page to the value of a first sub-region identifier.

[0009] The bit field of the target physical address of the target page can be generated by partitioning the memory and booting the electronic device, or by partitioning the memory and booting the electronic device.

[0010] The bit field may include a first field, a second field, a third field indicating the index of the target page, a fourth field indicating the index of the cached line within the target page, and a fifth field relating to the offset of the bit field.

[0011] The third field may include: a sub-region identifier field, in which the value corresponding to the default sub-memory region allocated to the target page is indicated when the bit field is generated; and a memory node identifier field, used to identify the memory node corresponding to the target page.

[0012] In response to the number of the plurality of memory nodes being 2 n The memory node identifier field can consist of n bits, and n can be a natural number.

[0013] The number of sub-memory regions corresponding to the first memory node is 2. m The subregion identifier field can consist of m bits, and m can be a natural number.

[0014] The method may include: receiving a target physical address from a first application executed by an electronic device; in response to receiving the target physical address, determining whether the value of a first field of the bit fields of the target physical address is a preset value; in response that the value of the first field is a preset value, obtaining the value of a second field; determining a target hash function based on the value of the second field; obtaining a value corresponding to a first memory node by inputting the value of a memory node identifier field into the target hash function; sending the target physical address to the first memory node; receiving target data from the first memory node; and sending the target data to the first application.

[0015] In one or more general aspects, a non-transitory computer-readable storage medium may store code that, when executed by one or more processors, configures the one or more processors to perform any, any combination or all of the operations and / or methods disclosed herein.

[0016] In one or more general aspects, an electronic device includes a memory comprising a plurality of memory nodes; and one or more processors configured to: determine whether a page utilization rate of a first sub-memory region of a first memory node among the plurality of memory nodes is greater than or equal to a first threshold; in response to the page utilization rate of the first sub-memory region being greater than or equal to the first threshold, determine a second sub-memory region of the first memory node; determine a target page among the pages of the second sub-memory region; and allocate the target page of the second sub-memory region to the first sub-memory region.

[0017] The one or more processors may include: a first core associated with a first memory node, and the first core may be configured to perform the step of determining whether the page utilization rate of a first sub-memory region is greater than or equal to a first threshold; and perform the step of determining a second sub-memory region of the first memory node in response to the page utilization rate of the first sub-memory region being greater than or equal to the first threshold.

[0018] In order to allocate a target page, the one or more processors may be configured to associate the target physical address of the target page with a first sub-region identifier corresponding to the first sub-memory region.

[0019] In order to allocate a target page, the one or more processors may be configured to: change the value of a first field in the bit field indicating the target physical address of the target page, indicating that the sub-memory region allocated to the target page has been changed, to a preset value; and change the value of a second field in the bit field indicating the sub-memory region to be reallocated, indicating the target physical address of the target page, to the value of a first sub-region identifier.

[0020] The bit field of the target physical address of the target page can be generated by partitioning the memory and booting the electronic device, or by one or both.

[0021] The bit field may include a first field, a second field, a third field indicating the index of the target page, a fourth field indicating the index of the cached line within the target page, and a fifth field relating to the offset of the bit field.

[0022] The third field may include: a sub-region identifier field, in which the value corresponding to the default sub-memory region allocated to the target page is indicated when the bit field is generated; and a memory node identifier field, used to identify the memory node corresponding to the target page.

[0023] In response to the number of the plurality of memory nodes being 2 n The memory node identifier field can consist of n bits, and n can be a natural number.

[0024] The number of sub-memory regions corresponding to the first memory node is 2. mThe subregion identifier field can consist of m bits, and m can be a natural number.

[0025] Other features and aspects will become clear from the following detailed description, drawings and claims. Attached Figure Description

[0026] Figure 1 An example of the configuration of an electronic device is shown.

[0027] Figure 2 An example of the configuration of an electronic device is shown.

[0028] Figure 3 An example of virtual memory is shown.

[0029] Figure 4A An example of a method for dividing a dynamic hash region is shown.

[0030] Figure 4B An example is shown of multiple partitioned sub-memory regions existing within a first memory node in a dynamic hash region.

[0031] Figure 4C An example of the first sub-memory region that exists within a partitioned dynamic hash region is shown.

[0032] Figure 4D An example of a partitioned second sub-memory region existing within a dynamic hash region is shown.

[0033] Figure 4E An example of a partitioned third sub-memory region existing within a dynamic hash region is shown.

[0034] Figure 4F An example of a fourth sub-memory region that exists within a dynamically hashed region is shown.

[0035] Figure 5 An example of a data transmission method is shown.

[0036] Figure 6 An example of a memory management method is shown.

[0037] Figure 7 An example of a method for allocating a target page of a second sub-memory region to a first sub-memory region is shown.

[0038] Figure 8 This illustrates an example of a method for sending data allocated to a target page of a first sub-memory region to a first application.

[0039] Throughout the accompanying drawings and detailed description, unless otherwise described or provided, the same reference numerals will be construed as indicating the same elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Implementation

[0040] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding the disclosure of this application. For example, the order of operations described herein is merely illustrative, except for operations that must occur in a specific order, and is not limited to the order of operations set forth herein, but may be changed as will become apparent upon understanding the disclosure of this application. Furthermore, for clarity and brevity, descriptions of features known upon understanding the disclosure of this application may be omitted.

[0041] The terminology used herein is for the purpose of describing various examples only and is not intended to limit disclosure. Articles are intended to include plural forms as well, unless the context clearly indicates otherwise. As non-limiting examples, the terms “comprising,” “including,” and “having” specify the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof, or alternatives to the stated features, quantities, operations, components, elements, and / or combinations thereof. Furthermore, while one embodiment may use such terms “comprising,” “including,” and “having” to specify the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, other embodiments may have one or more of the stated features, quantities, operations, components, elements, and / or combinations thereof absent.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and based on the understanding of the disclosure of this application. It will also be understood that, unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and in the disclosure of this application, and shall not be interpreted in an idealized or overly formal sense. The use of the term “may” herein with respect to examples or embodiments (e.g., regarding what an example or embodiment may include or implement) indicates the existence of at least one example or embodiment that includes or implements such a feature, but not all examples are limited thereto. The use of the terms “example” or “embodiment” herein has the same meaning (e.g., the phrase “in one example” has the same meaning as “in one embodiment,” and “one or more examples” has the same meaning as “in one or more embodiments”).

[0043] When describing the examples with reference to the accompanying drawings, the same reference numerals denote the same components, and repeated descriptions related to them will be omitted. In the description of the examples, descriptions of well-known related structures or functions will be omitted where such detailed descriptions would lead to an obscure interpretation of this disclosure.

[0044] Although terms such as “first,” “second,” and “third,” or A, B, (a), (b), etc., may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Each of these terms is not used to define, for example, the nature, order, or sequence of the corresponding component, assembly, region, layer, or part, but only to distinguish the corresponding component, assembly, region, layer, or part from other components, assemblies, regions, layers, or parts. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part mentioned in the examples may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0045] Throughout the specification, when a component or element is described as being "on" another component, element, or layer, "connected" to another component, element, or layer, "bonded" to another component, element, or layer, or "attached" to another component, element, or layer, it may be directly (e.g., in contact with another component, element, or layer) "on" another component, element, or layer, "connected" to another component, element, or layer, "bonded" to another component, element, or layer, or "attached" to another component, element, or layer, or one or more other components, elements, or layers may reasonably be present therein. When a component or element is described as being "directly on" another component, element, or layer, "directly connected" to another component, element, or layer, "directly bonded" to another component, element, or layer, or "directly attached" to another component, element, or layer, no other components, elements, or layers may be present therein. Similarly, expressions such as “between” and “immediately between”, as well as “adjacent to” and “closely adjacent to”, can also be interpreted as described above.

[0046] As used herein, the term “and / or” includes any one of the associated listed items and any combination of any two or more. Unless the corresponding description and embodiments require that items be interpreted as having a combined meaning (e.g., “at least one of A, B, and C”), the phrases “at least one of A, B, and C”, “at least one of A, B, or C”, etc., are intended to have a separate meaning, and these phrases “at least one of A, B, and C”, “at least one of A, B, or C”, etc., also include examples of one or more of each of A, B, and / or C (e.g., any combination of one or more of each of A, B, and C).

[0047] The same names can be used to describe the components included in the examples described above and components that share a common function. Unless otherwise mentioned, the descriptions of the examples are applicable to the examples below, and therefore, for the sake of brevity, repeated descriptions will be omitted.

[0048] Figure 1 An example of the configuration of an electronic device is shown.

[0049] Electronic device 100 may include communicator 110, processor 120 (e.g., one or more processors) and memory 130 (e.g., one or more memories).

[0050] The communicator 110 may be connected to the processor 120 and the memory 130, and transmits data to and receives data from the processor 120 and the memory 130. The communicator 110 may also be connected to additional external devices, and transmits data to and receives data from those external devices. The expression "transmit and / or receive A" as used herein may be interpreted as transmitting and / or receiving information or data indicating A.

[0051] The communicator 110 may be implemented as a circuit in the electronic device 100. For example, the communicator 110 may include an internal bus and an external bus. In another example, the communicator 110 may be an element that connects the electronic device 100 to an external device. The communicator 110 may be an interface. The communicator 110 may receive data from an external device and send data to the processor 120 and the memory 130.

[0052] Processor 120 can process data received via communicator 110 and data stored in memory 130. The "processor" can be a hardware-implemented data processing device having physically structured circuitry to perform desired operations. Desired operations may include, for example, code or instructions included in a program. Hardware-implemented data processing devices may include, for example, microprocessors, central processing units (CPUs), processor cores, multi-core processors, multiprocessors, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0053] Processor 120 can execute computer-readable code (e.g., software) stored in memory (e.g., memory 130) and instructions triggered by processor 120. For example, memory 130 may be or include a non-transitory computer-readable storage medium that stores code that, when executed by processor 120, configures processor 120 to execute (see reference herein). Figures 1 to 8 Any, any combination or all of the disclosed operations and / or methods.

[0054] Memory 130 may store data received via communicator 110 and data processed by processor 120. For example, memory 130 may store programs (or applications, or software). For example, the programs to be stored may be a set of syntaxes encoded by processor 120 and executable to manage memory.

[0055] The memory 130 may include at least one of, for example, volatile memory, non-volatile memory, random access memory (RAM), flash memory, hard disk drive, and optical disk drive.

[0056] The memory 130 may store a set of instructions (e.g., software) for operating the electronic device 100. The set of instructions for operating the electronic device 100 is executed by the processor 120.

[0057] The following will refer to Figures 2 to 8 Examples of communicator 110, processor 120 and memory 130 are described in detail.

[0058] Figure 2 An example of the configuration of an electronic device is shown.

[0059] According to the example, electronic device 200 (e.g., Figure 1 The electronic device 200 may include multiple memory nodes 210, 220, and 230. For example, when the processor of the electronic device 200 (e.g., Figure 1 When the processor 120 includes multiple cores, the multiple memory nodes 210, 220, and 230 can be non-uniform memory access (NUMA) nodes. For example, the electronic device 200 can be a system-on-a-chip (SoC) including multiple cores. For example, the electronic device 200 can be a server providing cloud services.

[0060] According to the example, a first memory node 210 may include a first memory 212, and a first core 211 (e.g., a first memory controller) may be associated with (e.g., included in) the first memory node 210. For example, the first memory node 210 may include the first core 211 and the first memory 212. A second memory node 220 may include a second memory, and a third memory node 230 may include a third memory. Furthermore, in one example, the second memory node 220 may include a second core, and the third memory node 230 may include a third core. Each of the plurality of memory nodes 210, 220, and 230 may have a memory node identifier (ID). Although Figure 2 Three memory nodes 210, 220 and 230 are shown, but the example is not limited to this, and in other examples, the electronic device 200 may include two or fewer memory nodes, or four or more memory nodes.

[0061] According to the example, each of the plurality of memory nodes 210, 220, and 230 may have a specific range of physical address ranges. The physical address ranges may vary depending on the memory structure, SoC architecture, and / or mapping method. For example, the first memory node 210 may have a physical address range from 0x00000000 to 0x3FFFFFFF, and the second memory node 220 may have a physical address range from 0x40000000 to 0x7FFFFFFF. The physical address ranges set in the plurality of memory nodes 210, 220, and 230 may be determined by partitioning or booting the electronics 200 (or memory).

[0062] The first core 211 can perform overall functions for controlling the first memory node 210. The first core 211 can be implemented as a CPU, graphics processing unit (GPU), application processor (AP), etc., however, the examples are not limited to these. For example, the first core 211 can operate not only using the first memory 212 of the first memory node 210, but can also operate using the memory of another memory node (e.g., a second memory node 220). That is, each of the cores within the electronic device 200 can operate using any or all of the memory within the electronic device 200.

[0063] According to the example, each of the plurality of memory nodes 210, 220, and 230 may correspond to an independent computing device. The plurality of memory nodes 210, 220, and 230 may communicate with each other. For example, electronic device 200 may be a server system using a cluster system, and each of the plurality of memory nodes 210, 220, and 230 may be a server.

[0064] According to the example, the first memory node 210 may also include an accelerator for computation. The accelerator can handle tasks that, due to the characteristics of the task, can be handled more efficiently by a separate dedicated processor (i.e., the accelerator) rather than by a general-purpose first core 211. In this case, one or more processing elements (PEs) included in the accelerator may be used. The accelerator may correspond to, for example, a neural processor (NPU), a tensor processor (TPU), a digital signal processor (DSP), a GPU, and / or a neural engine that performs operations according to a neural network. In one example, the first core 211 may include a processor (e.g., a CPU, GPU, and / or AP) that performs overall functions for controlling the first memory node 210, and the first core 211 may also include an accelerator (e.g., an NPU, TPU, DSP, GPU, and / or neural engine) that performs operations according to a neural network. In another example, the first core 211 may include a processor, and the first memory 212 may include an accelerator.

[0065] According to the example, multiple memory nodes 210, 220, and 230 can share virtual memory. For example, multiple memory nodes 210, 220, and 230 can share virtual memory based on Global Shared Memory (GSM) technology. Multiple memory nodes 210, 220, and 230 can share virtual memory, allowing all cores to use the same address space. The virtual memory can be referred to as GSM. Multiple memory nodes 210, 220, and 230 can read data from and write data to memory nodes sharing the virtual memory. The virtual memory can actually be memory distributed across each memory node, but applications can recognize it as local memory. Therefore, applications can access the virtual memory using typical load and store instructions. For example, each memory node can also access data stored in memory included in other memory nodes based on memory layers.

[0066] The following reference Figure 3 This section will describe an example of virtual memory shared by multiple memory nodes.

[0067] Figure 3 An example of virtual memory is shown.

[0068] According to the example, multiple memory nodes 310, 320 and 330 may share virtual memory 300 (e.g., GSM).

[0069] Virtual memory 300 may represent a virtual memory space shared by multiple memory nodes 310, 320, and 330. Regions of virtual memory 300 may correspond to regions physically distributed among the multiple memory nodes 310, 320, and 330. For example, at least a portion of the physical memory regions of the multiple memory nodes 310, 320, and 330 may be allocated to virtual memory 300.

[0070] For example, when an application running on the first memory node 310 uses virtual memory 300, the application may use memory regions allocated to the virtual memory 300 included in the first memory node 310, memory regions allocated to the virtual memory 300 included in another memory node (e.g., the second memory node 320 or the third memory node 330), and dedicated local memory regions of the first memory node 310. A dedicated local memory region may represent a memory region within the physical memory region of a memory node that is not allocated to virtual memory 300. In one example, the dedicated local memory region may not exist in the memory node.

[0071] Figure 4A An example of a method for dividing a dynamic hash region is shown.

[0072] Based on the example, the Address Space Partitioning (ASP) method can be considered. This method processes access requests for specific physical addresses as requests for access to specific memory nodes by mapping physical addresses of memory to memory node IDs. According to the ASP method, different memory nodes can be mapped for each cache line that forms a page. When an application requests allocation of a memory region, the hypervisor can search for available pages (or frames) and provide the found pages to the application.

[0073] When the first application is to be implemented with low latency, the allocated memory region can be a region of memory physically located near the core on which the first application is executed. For example, when the first application is executed by a core of a first memory node, the memory region allocated to the first application can be a region of the memory of the first memory node (e.g., the first memory). When the first memory is used by other cores (e.g., for high bandwidth), a portion of the entire region of the first memory can be pre-allocated for other purposes. When the region of the first memory available for allocation to the first application becomes insufficient, a method can be performed to reallocate a region of the first memory allocated for another purpose to the first application.

[0074] For the method described above, a memory region shared by multiple cores in the physical address space 400a of the electronic device (or SoC) memory can be defined as a dynamic hash region 410a. For example, according to the example, the dynamic hash region 410a of the physical address space 400a can be related to the above-mentioned... Figure 3 The virtual memory 300 described corresponds to this. After understanding this disclosure, those skilled in the art will understand the conversion between physical memory and virtual memory, and therefore, its description will be omitted below. The electronic device can partition the dynamic hash region 410a using a preset method. Examples of the preset partitioning method will be described in detail below.

[0075] The physical address space 400a may consist of one or more M sub-memory regions of the same size, and each sub-memory region may have a separate strategy for connecting physical addresses and memory node IDs. For example, each of the M sub-memory regions may have a value from 0 to M-1 as a sub-region ID to distinguish the sub-memory regions. Each sub-memory region may include one or more memory node groups. For example, when the sub-region ID used to identify the sub-memory region is 0 (e.g., sub-region 0), each of the memory node groups in the corresponding sub-memory region may include only one memory node. For example, the number of memory nodes associated with each sub-memory region (e.g., corresponding to and / or included in each sub-memory region) may be expressed as a power of 2. The constraints above in one or more embodiments can reduce the complexity of the design and mapping logic. To form memory node groups, the location of the physical memory nodes may be considered. For example, memory node groups may be preferentially formed between physically adjacent memory nodes.

[0076] According to the example, the dynamic hash region 410a can be divided into a first array 411a, such that different sub-memory regions are interleaved in units of pages. Figure 4A In this context, the horizontal length of the dynamic hash region 410a corresponds to the page size, and the page size can correspond to the frame size. The following will refer to... Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F A detailed description of an example of a dynamically hashed region 410a that is divided by interleaving different sub-memory regions.

[0077] Figure 4B An example is shown of multiple partitioned sub-memory regions existing within a first memory node in a dynamic hash region.

[0078] According to the example, when the number of sub-memory regions is 4 and the number of memory nodes is 16, the dynamic hash region 410b of the physical address space 400b can be divided into the first array 411b.

[0079] In the first array 411b, subregion 0_0 has a subregion ID of 0 and represents group 0. For example, a memory node included in group 0 can be memory node 0 (e.g., first memory node 210). A group (e.g., a node group) can include any number of memory nodes that can be expressed as a power of 2.

[0080] In the first array 411b, subregion 1_{0,1} has a subregion ID of 1 and represents group {0,1}. Group {0,1} may represent a group consisting of memory node 0 and memory node 1 (e.g., second memory node 220). For example, memory nodes in group {0,1} may be physically close to or adjacent to each other.

[0081] In the first array 411b, subregion 2_{0,1,2,3} has a subregion ID of 2 and represents the group {0,1,2,3}. The group {0,1,2,3} can represent a group consisting of memory node 0, memory node 1, memory node 2, and memory node 3. For example, the memory nodes in the group {0,1,2,3} can be located in the same physically direction.

[0082] In the first array 411b, sub-region 3_{0, ..., 15} has 3 sub-region IDs and represents the group {0, ..., 15}. The group {0, ..., 15} can represent a group consisting of memory nodes 0 to 15. For example, the memory nodes in the group {0, ..., 15} can be all the memory nodes of an electronic device or a SoC.

[0083] In the first array 411b, sub-region 0_1 has a sub-region ID of 0 and represents group 1. Group 1 may represent memory node 1.

[0084] In the first array 411b, subregion 1_{2,3} has a subregion ID of 1 and represents group {2,3}. Group {2,3} may represent a group consisting of memory node 2 and memory node 3. For example, the memory nodes in group {2,3} may be physically close to or adjacent to each other.

[0085] In the first array 411b, subregion 2_{4,5,6,7} has a subregion ID of 2 and represents the group {4,5,6,7}. The group {4,5,6,7} can represent a group consisting of memory node 4, memory node 5, memory node 6, and memory node 7. For example, the memory nodes in the group {4,5,6,7} can be located in the same physically direction.

[0086] After the pages in subregion 2_{4,5,6,7}, the pages in subregion 3_{0,...,15} may appear again. In the same manner as above, the pages of the first array 411b can be mapped, and the last page of the first array 411b can be a page from subregion 3_{0,...,15}.

[0087] According to the example, bit fields (such as those in Table 1 below) can be used, for example, to generate the first array 411b above.

[0088] Table 1:

[0089] Table 1 shows an example of a 64-bit bit field used as the physical address, from bit 0 to bit 63. The cache line size can be 64 bytes (B), the page size can be 4 kilobytes (KB), the number of memory nodes can be N, and the number of sub-memory regions can be M. The range of bits used for cache lines and pages can have the same structure as the bit field used to represent the physical address.

[0090] The bit fields of Table 1, used to partition the dynamic hash region 410b using sub-memory regions, can define a flag field, a remapped sub-region ID field, and a memory node ID field and a sub-region ID field within the page index field. Bits (m+11) through 12 of the page index field can be used to identify the sub-region ID. m can satisfy log2(M). For example, the sub-region ID can represent the sub-region ID initially mapped to the corresponding physical address (e.g., at startup or partitioning). After identifying the sub-region ID, bits (m+n+11) through (m+12) can be used to identify the memory node ID. n can satisfy log2(N). For example, the memory node ID can represent the ID of the memory node initially mapped to the corresponding physical address (e.g., at startup or partitioning). The flag field, being the higher bit of the bit fields, can be set to 0 in the initial state before the corresponding physical address is used for remapping, and can be set to 1 when the corresponding physical address has been used for remapping. The remapped sub-region ID field can be set to the value of the sub-region ID that has been remapped (or reallocated) to the corresponding physical address.

[0091] The bit fields may include a first field, a second field, a third field, a fourth field, and a fifth field. The first field is a flag field, the second field is a remapped sub-region ID field, the third field is a page index field, the fourth field is a cache line index field, and the fifth field is a byte offset field. The third field may include a sub-region ID field and a memory node ID field. The sub-region ID field indicates the value corresponding to the default sub-memory region allocated to the page when the bit fields are generated, and the memory node ID field is used to identify the memory node corresponding to the page. For example, when the number of multiple memory nodes is 2... n In this case, the memory node ID field can consist of n bits, and n can be a natural number greater than 0. When the number of sub-memory regions of the first memory node is 2... m In this case, the memory node ID field can consist of m bits, and m bits can be natural numbers greater than 0. In one embodiment, the first field can indicate that the sub-memory region allocated to the page has been changed.

[0092] Pages (e.g., cache lines) within the first array 411b can be mapped based on the bit fields in Table 1.

[0093] According to the example, when cache lines for memory node 0 (e.g., cache lines representing a group of nodes including memory node 0) are combined among cache lines within the first array 411b, the second array 420b can be logically generated as a result of the combination. The memory region of memory node 0 can be divided into memory regions for each of the plurality of sub-memory regions.

[0094] In the second array 420b, memory node 0_0 can be a region where subregion ID is 0 and memory node ID is connected to 0. The region of memory node 0_0 can be used independently by an application executing through the core of memory node 0.

[0095] In the second array 420b, memory node 0_1 can be a region where subregion ID is 1 and memory node ID is connected to 0. The region of memory node 0_1 can be used by an application executed through the core of memory node 0 or the core of memory node 1 (that is, the core of group {0,1}).

[0096] In the second array 420b, memory node 0_2 can be a region where subregion ID is 2 and memory node ID is connected to 0. The region of memory node 0_2 can be used by an application executed through the core of memory node 0, the core of memory node 1, the core of memory node 2, or the core of memory node 3 (that is, the core of group {0,1,2,3}).

[0097] In the second array 420b, memory node 0_3 can be a region where subregion ID is 3 and memory node ID is connected to 0. The region of memory node 0_3 can be used by an application executing through one of the cores of memory node 0 to memory node 15 (that is, the cores of group {0,…,15}).

[0098] Figure 4C An example of the first sub-memory region that exists within a partitioned dynamic hash region is shown.

[0099] According to the example, when pages from a first sub-memory region (e.g., a memory region with sub-region ID 0) within pages of the first array 411b are combined, the third array 430 can be logically generated as a result of the combination. The third array 430 can be divided into pages from multiple memory nodes. Pages can consist of cache lines from the same memory node.

[0100] Figure 4D An example of a partitioned second sub-memory region existing within a dynamic hash region is shown.

[0101] According to the example, when pages from a second sub-memory region (e.g., a memory region with sub-region ID 1) within pages of the first array 411b are combined, the fourth array 431 can be logically generated as a result of the combination. Pages in the fourth array 431 can consist of cache lines from a set of memory nodes corresponding to the respective pages. For example, a page in sub-region 1_{0,1} can consist of cache lines from memory node 0 and cache lines from memory node 1. Similarly, a page in sub-region 1_{2,3} can consist of cache lines from memory node 2 and cache lines from memory node 3.

[0102] Figure 4E An example of a partitioned third sub-memory region existing within a dynamic hash region is shown.

[0103] According to the example, when pages from a third sub-memory region (e.g., the memory region with sub-region ID 2) within the pages of the first array 411b are combined, the fifth array 432 can be logically generated as a result of the combination. Pages in the fifth array 432 can consist of cache lines from a set of memory nodes corresponding to the respective pages. For example, pages in sub-region 2_{0,1,2,3} can consist of cache lines from memory node 0, memory node 1, memory node 2, and memory node 3. Similarly, pages in sub-region 2_{4,5,6,7} can consist of cache lines from memory node 4, memory node 5, memory node 6, and memory node 7.

[0104] Figure 4F An example of a fourth sub-memory region that exists within a dynamically hashed region is shown.

[0105] According to the example, when pages from the fourth sub-memory region (e.g., the memory region with sub-region ID 3) within the pages of the first array 411b are combined, the sixth array 433 can be logically generated as a result of the combination. Pages in the sixth array 433 can consist of cache lines from a set of memory nodes corresponding to the respective pages. For example, pages in sub-region 3_{0,…,15} can consist of cache lines from memory node 0 to memory node 15.

[0106] Figure 5 An example of a data transmission method is shown. Figure 5 Operations 510 to 590 may be performed in the order and manner shown. However, without departing from the spirit and scope of the exemplary embodiments described herein, the order of one or more of the operations may be changed, one or more of the operations may be omitted, two or more of the operations may be performed in parallel or simultaneously, and / or additional operations may be performed.

[0107] By applying the above reference Figures 4A to 4F An electronic device describing a method for partitioning (or mapping) a dynamically hashed region of memory (e.g., Figure 1 Electronic device 100 or Figure 2 The data transmission method performed by the electronic device 200 may include operations 510 to 590.

[0108] In operation 510, the electronic device may receive the target physical address of the first application. For example, the first application may be connected to a first memory node (e.g., Figure 2 First memory node 210 or Figure 3 The first memory node (310) is associated with an application executed by the core. The first application can send a target physical address to an electronic device to load (or obtain) data stored at the target physical address.

[0109] In operation 520, the electronic device may, in response to receiving a target physical address, determine whether the value of the first field of the bit field of the target physical address is a preset value. The first field may be a higher bit of a bit field. For example, the first field may be as described above. Figure 4B The description flag field. The first field can be set to 0 in the initial state when the corresponding physical address has not yet been used for remapping, and can be set to 1 when the corresponding physical address has already been used for remapping.

[0110] For example, operation 530 can be executed when the value of the first field is 1 (the default value), and operation 540 can be executed when the value of the first field is not 1 (the default value).

[0111] In operation 530, when the value of the first field is a preset value, the electronic device can obtain the value of the second field. The second field can be, for example, as shown in the reference above. Figure 4B The remapped sub-region ID field is described.

[0112] In operation 540, when the value of the first field is not a preset value, the electronic device can obtain a portion of the value of the third field. For example, the third field could be the value referenced above. Figure 4B The page index field is described, and a portion of the value of the third field can be the value of the sub-region ID field. For example, the value of the sub-region ID field can be the value from the (m+11)th to the twelfth position of the bit field.

[0113] In operation 550, the electronic device can determine the target hash function based on the obtained value. For example, different hash functions can be defined for the value in the sub-region ID field. For instance, a first hash function can be determined when the value of the sub-region ID field is 0, and a second hash function can be determined when the value of the sub-region ID field is 1.

[0114] In operation 560, the electronic device can obtain the value corresponding to the target memory node by inputting the value of the memory node ID field in the third field into the target hash function. For example, the memory node ID field in the third field can be as described above. Figure 4B The described memory node ID field. The value corresponding to the target memory node obtained through the target hash function can be the memory node ID. The target memory node corresponding to the target physical address can be determined by the memory node ID.

[0115] According to the example, the length of the bits obtained from the memory node ID field can vary depending on the value of the sub-region ID field or the target hash function. For example, when the value of the sub-region ID field is 0, bits (m+n+11) to (m+12) of the bit field can be obtained from the memory node ID field. For example, when the value of the sub-region ID field is 1, bits (m+n+10) to (m+12) of the bit field can be obtained from the memory node ID field. For example, when the value of the sub-region ID field is 2, bits (m+n+9) to (m+12) of the bit field can be obtained from the memory node ID field. For example, when the value of the sub-region ID field is 3, bits (m+n+8) to (m+12) of the bit field can be obtained from the memory node ID field.

[0116] As shown in the example, the bits in the fourth field can also be input into the target hash function. For example, the fourth field could be as described above. Figure 4B The cache line index field describes the cache. The bits in the fourth field can be used to identify a memory node within the identified group ID.

[0117] Based on the example, the method for obtaining the value corresponding to the target memory node based on each hash function will be described for the case where the number of multiple memory nodes is 4 (i.e., n=2) and the number of multiple sub-memory regions is 16 (i.e., m=4).

[0118] For subregion 0, bits 17 to 14 of the bit field can be obtained from the memory node ID field as addr[17:14]. When the number of bits obtained is 4, a hash function can be used to identify multiple memory nodes without overlap.

[0119] For subregion 1, bits 16 to 14 of the bit field can be obtained from the memory node ID field as addr[16:14], and bit 6 of the bit field can be obtained from the cache line index field as addr[6]. A group ID including two memory nodes can be identified based on addr[16:14], and a target memory node can be identified within the group ID based on addr[6].

[0120] For subregion 2, bits 15 through 14 of the bit field can be obtained from the memory node ID field as addr[15:14], and bits 7 through 6 of the bit field can be obtained from the cache line index field as addr[7:6]. A group ID comprising four memory nodes can be identified based on addr[15:14], and a target memory node can be identified within the group ID based on addr[7:6].

[0121] For subregion 3, bits 9 through 6 of the bit field can be obtained from the cache line index field as addr[9:6]. Since the number of bits obtained is 4, a hash function can be used to identify multiple memory nodes without overlap.

[0122] In operation 570, the electronic device can send the target physical address to the target memory node.

[0123] In operation 580, the electronic device may receive target data from the target memory node. For example, the target data may be data stored in a memory region corresponding to the target physical address.

[0124] In operation 590, the electronic device can send the target data to the first application.

[0125] Figure 6 An example of a memory management method is shown. Figure 6 Operations 610 to 640 may be performed in the order and manner shown. However, without departing from the spirit and scope of the exemplary embodiments described herein, the order of one or more of the operations may be changed, one or more of the operations may be omitted, two or more of the operations may be performed in parallel or simultaneously, and / or additional operations may be performed.

[0126] When all available pages of the first sub-memory region are used by a first application that exclusively uses the first sub-memory region of the first memory node, the first application may no longer use pages of the first memory node and may have to use pages of the second memory node (e.g., pages of the second sub-memory region of the second memory node). When the first application is executed through the first core of the first memory node, the first application using pages of the second memory node can cause latency in data processing. Therefore, a method of reallocating memory regions of other sub-memory regions allocated to the first memory node to the first sub-memory region can be considered.

[0127] By applying the above reference Figures 4A to 4F An electronic device describing a method for partitioning (or mapping) a dynamically hashed region of memory (e.g., Figure 1 Electronic device 100 or Figure 2 The memory management method executed by the electronic device 200 may include operations 610 to 640.

[0128] In operation 610, the electronic device may determine that the page utilization rate of a first sub-memory region (e.g., a memory region where the sub-region ID is 0) of a first memory node among a plurality of memory nodes is greater than or equal to a first threshold (e.g., 90%). When the page utilization rate of the first sub-memory region is greater than or equal to the first threshold, operation 620 may be performed.

[0129] According to the example, each of the multiple memory nodes may include a memory controller that monitors the page utilization of the sub-memory regions of the corresponding memory node (e.g., Figure 2 The first core (211). The memory controller can be implemented as hardware including processing circuitry. The memory controller can determine whether the page utilization rate of the first sub-memory region of the first memory node is greater than or equal to a first threshold. When the page utilization rate of the first sub-memory region of the first memory node is greater than or equal to the first threshold, the memory controller generates an interrupt for the address remapping module, which will be described below. The memory controller receives an acknowledgment (ACK) for the interrupt from the address remapping module.

[0130] In operation 620, the electronic device may determine a second sub-memory region of the first memory node (e.g., a memory region where sub-region ID is 1). The electronic device may determine the second sub-memory region based on the page utilization rates of multiple sub-memory regions of the first memory node. For example, the sub-memory region with the lowest page utilization rate may be determined as the second sub-memory region. The memory controller may determine the second sub-memory region of the first memory node.

[0131] According to the example, the electronic device can determine the amount of pages that will be reallocated from the second sub-memory region to the first memory region.

[0132] The memory controller sends information about the first sub-memory region of the received page, the second sub-memory region of the transferred page, and the number of pages to be transferred to the address remapping module.

[0133] In operation 630, the electronic device may determine a target page within the pages of the second sub-memory region. The electronic device may allocate one or more pages from the second sub-memory region to the first sub-memory region according to page transfer rules between the first and second sub-memory regions. For example, the electronic device may associate the target physical address of the target page with a first sub-region ID corresponding to the first sub-memory region.

[0134] To easily describe the page transfer rules, assume that the number of memory nodes belonging to sub-region ID is 2. ID Furthermore, the number of groups included in each sub-region ID is SR_ID. At this point, the pattern generated by representing the sub-region ID and group ID as tuples for each sub-memory region can be as follows.

[0135] - Subregion 0 has (0,0), (0,1), ..., (0,SR_0), and until the same result tuple is a step size of 4KB×M region×SR_0 group KB.

[0136] - Subregion 1 has (1,0), (1,1), ..., (1,SR_1), and until the same result tuple is a step size of 4Kb×M region×SR_1 group KB.

[0137] - Subregion 2 has (2,0), (2,1), ..., (2,SR_2), and until the same result tuple is a step size of 4Kb×M region×SR_2 group KB.

[0138] -……

[0139] - Subregion M has (M,0), (M,1), ..., (M,SR_M), and until the same tuple result is a step size of 4KB × M region × SR_M group KB.

[0140] Considering the pattern above, the rules for reallocating pages from one sub-memory region to another can be as follows. Here, the memory node ID included in the corresponding group is used instead of (SR_ID, SR group ID). For example, when the SR group ID 0 of sub-region 1 (SR 1) includes memory nodes 0 and 1, it is represented as (SR1, {0, 1}).

[0141] a) For SR0.

[0142] i) SR0<->SR1:{(0,{a}),(0,{b})}<->2 (1,{a,b}).

[0143] ii) SR0<->SR2:{(0,{a}),(0,{b}),(0,{c}),(0,{d})}<->4 (2,{a,b,c,d}).

[0144] iii) ...

[0145] b) For SR1.

[0146] i) SR1<->SR2:{(1,{a,b}),(1,{c,d})<->2 (2,{a,b,c,d}).

[0147] ii)……

[0148] c) For SR2.

[0149] SR2<->SR3:{(2,{a,b,c,d}),(2,{d,e,f,g}),(2,{h,i,j,k}),(2,{l,m,o,p})}<->4 (3,{a,b,...,p}).

[0150] Based on the above pattern, even when the number of sub-memory regions increases to m, page transfers between sub-memory regions are feasible through inductive reasoning.

[0151] The electronic device can identify unused pages in the pages of a second sub-memory region as target pages based on the available range and remapping strategy of each sub-memory region set for dynamic remapping.

[0152] As an example, an electronic device may use an address remapping module to determine one or more pages in a second sub-memory region that will be allocated to the first sub-memory region. The address remapping module may be implemented as software or hardware including processing circuitry.

[0153] In operation 640, the electronic device may allocate a target page from the second sub-memory region to the first sub-memory region. For example, the address remapping module may allocate one or more target pages from the second sub-memory region to the first sub-memory region. References will follow below. Figure 7 A detailed example of a method for allocating a target page of a second sub-memory region to a first sub-memory region.

[0154] The electronic device can send information about the target page to the memory controller of the first memory node and receive an ACK from the memory controller. The memory controller of the first memory node can update the size of the sub-memory region and the page utilization.

[0155] The following will refer to Figure 8 This section provides an example of a method for handling access requests when an application receives an access request for the physical address of a target page that has been reassigned to the first sub-memory region.

[0156] Figure 7 An example of a method for allocating a target page of a second sub-memory region to a first sub-memory region is shown. Figure 7 Operations 710 to 720 may be performed in the order and manner shown. However, without departing from the spirit and scope of the exemplary embodiments described herein, the order of one or more of the operations may be changed, one or more of the operations may be omitted, two or more of the operations may be performed in parallel or simultaneously, and / or additional operations may be performed.

[0157] Based on the example, refer to the above. Figure 6 The described operation 640 may include Figure 7 Operations 710 and 720.

[0158] In operation 710, electronic devices (e.g., Figure 1 Electronic device 100 or Figure 2 The electronic device 200 can change the value of the first field in the bit field of the target physical address of the target page to a preset value. For example, the first field can be the value mentioned above. Figure 4B The description flag field. For example, the default value can be 1. The bit field representing the target physical address of the target page, which can be generated by partitioning memory or by booting an electronic device. The value of the first field of the initial bit field can be 0.

[0159] In operation 720, the electronic device may change the value of the second field within the bit field of the target physical address of the target page to the value of the first sub-region ID (e.g., a "0" indicating sub-region 0). The second field may be, for example, as described above. Figure 4B The remapped sub-region ID field describes the region. The value of the second field of the initial bit field may not be specified.

[0160] Figure 8 This illustrates an example of a method for sending data allocated to a target page of a first sub-memory region to a first application. Figure 8Operations 810 to 880 may be performed in the order and manner shown. However, without departing from the spirit and scope of the exemplary embodiments described herein, the order of one or more of the operations may be changed, one or more of the operations may be omitted, two or more of the operations may be performed in parallel or simultaneously, and / or additional operations may be performed.

[0161] Based on the example, you can refer to the above when executing. Figure 6 The described operation 640 will be executed later. Figure 8 Operations 810 to 880.

[0162] In operation 810, electronic devices (e.g., Figure 1 Electronic device 100 or Figure 2 The electronic device 200 can receive the target physical address from the first application. For example, the first application may be connected to a first memory node (e.g., Figure 2 First memory node 210 or Figure 3 The first memory node (310) is associated with an application executed by the core. The first application can send a target physical address to an electronic device to load (or obtain) data stored at the target physical address.

[0163] In operation 820, the electronic device may, in response to receiving a target physical address, determine whether the value of the first field of the bit field of the target physical address is a preset value. For example, the first field may be as described above. Figure 4B The description of the flag field. Since the value of the first field of the target physical address's bit field is referenced above... Figure 7 The described operation 710 is changed to "1", so it can be determined that the value of the first field is the default value.

[0164] In operation 830, the electronic device can obtain the value of the second field of the bit field. The second field can be, for example, as shown in the reference above. Figure 4B The description refers to the remapped sub-region ID field. The value of the second field of the bit field used for the target physical address is referenced above. Figure 7 The described operation 720 is changed to the value of the first sub-region ID (e.g., "0" indicating sub-region 0), so the value of the obtained second field can be the value of the first sub-region ID.

[0165] In operation 840, the electronic device may determine the target hash function based on the value of the second field. For example, the first hash function corresponding to the value of the first sub-region ID (e.g., "0") may be determined as the target hash function.

[0166] In operation 850, the electronic device can obtain the value corresponding to the first memory node by inputting the value of the memory node ID field in the third field into the target hash function.

[0167] In operation 860, the electronic device can send the target physical address to the first memory node.

[0168] In operation 870, the electronic device may receive target data from the first memory node. For example, the target data may be data stored in a memory region corresponding to a target physical address.

[0169] In operation 880, the electronic device can send the target data to the first application.

[0170] The electronic devices, communicators, processors, memory, memory nodes, first cores, first memory, electronic device 100, communicator 110, processor 120, memory 130, electronic device 200, memory nodes 210, 220 and 230, first core 211, first memory 212, and memory nodes 310, 320 and 330 (including those related to...) described herein include... Figures 1 to 8The description of the hardware components (as described above) is implemented or represents a hardware component. Examples of hardware components that can be used to perform the operations described in this application, as described above or in addition to those described above, include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components performing the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field-programmable gate arrays, programmable logic arrays, microprocessors, or any other means or combination of means configured to respond to and execute instructions in a defined manner to achieve a desired result). In one example, the processor or computer includes or is connected to one or more memories storing instructions or software executed by the processor or computer. Hardware components implemented by a processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in this application. Hardware components can also access, manipulate, process, create, and store data in response to the execution of instructions or software. For simplicity, the singular terms "processor" or "computer" may be used in the description of the examples described in this application; however, in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements or multiple types of processing elements or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor or two or more processors or a processor and a controller. One or more hardware components may be implemented by one or more processors or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors or an additional processor and an additional controller. One or more processors or a processor and a controller may implement a single hardware component or two or more hardware components. As described above, or in addition to the above description, the example hardware components may have any one or more different processing configurations, examples of which include a single processor, a standalone processor, a parallel processor, a single instruction single data (SISD) multiprocessor, a single instruction multiple data (SIMD) multiprocessor, a multiple instruction single data (MISD) multiprocessor, and a multiple instruction multiple data (MIMD) multiprocessor.

[0171] Figures 1 to 8 Shown and about Figures 1 to 8The methods for performing the operations described in this application are executed by computing hardware (e.g., one or more processors or a computer), which, as described above, is implemented as implementing instructions (e.g., computer or processor / processor-readable instructions) or software for performing the operations described in this application by the methods. For example, a single operation or two or more operations may be executed by a single processor or two or more processors or a processor and a controller. One or more operations may be executed by one or more processors or a processor and a controller, and one or more other operations may be executed by one or more other processors or additional processors and additional controllers. One or more processors or a processor and a controller may execute a single operation or two or more operations.

[0172] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above can be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as machines or special-purpose computers to perform operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executable by one or more processors or computers. In another example, the instructions or software include higher-level code that is executed by one or more processors or computers using an interpreter. Instructions or software can be written using any programming language based on the block diagrams and flowcharts shown in the accompanying drawings and the corresponding description herein, which disclose algorithms for performing operations performed by the hardware components and methods described above.

[0173] Instructions or software used to control computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, along with any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media, and therefore, they are not signals in themselves. Examples of non-transitory computer-readable storage media, as described above, or in addition to those described above, include read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDDs), solid-state drives (SSDs), card-type storage devices (such as multimedia cards or microcards (e.g., Secure Digital (SD) or Extreme Digital (XD)), magnetic tape, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state drives), and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and to provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers, such that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system, such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed by one or more processors or computers in a distributed manner.

[0174] While this disclosure includes specific examples, it will be clear upon understanding this disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered only in a descriptive sense and not for limiting purposes. The description of features or aspects in each example will be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents.

[0175] Therefore, in addition to the above and all the accompanying drawings, the scope of the disclosure also includes the claims and their equivalents, that is, all variations within the scope of the claims and their equivalents shall be interpreted as included in the disclosure.

Claims

1. A processor-implemented method, comprising: Determine whether the page utilization rate of the first sub-memory region of the first memory node among multiple memory nodes of the memory is greater than or equal to a first threshold; In response to the page utilization rate of the first sub-memory region being greater than or equal to a first threshold, a second sub-memory region of the first memory node is determined. Identify the target page within the pages of the identified second sub-memory region; as well as Allocate the target page of the determined second sub-memory region to the first sub-memory region.

2. The method as described in claim 1, wherein, The step of determining a second sub-memory region of a first memory node in response to a page utilization rate of a first sub-memory region being greater than or equal to a first threshold includes: determining the second sub-memory region based on the page utilization rates of multiple sub-memory regions of the first memory node.

3. The method as described in claim 1, wherein, The step of allocating a target page of the second sub-memory region to the first sub-memory region includes associating the target physical address of the target page with a first sub-region identifier corresponding to the first sub-memory region.

4. The method of claim 3, wherein, The steps of allocating a target page from the second sub-memory region to the first sub-memory region include: The value of the first field in the bit field indicating the target physical address of the target page is assigned to a sub-memory region of the target page is changed to a preset value; and Change the value of the second field in the bit field of the target physical address of the target page, which indicates the sub-memory region to be reallocated, to the value of the first sub-region identifier.

5. The method of claim 4, wherein, The bit field of the target physical address of the target page is generated by partitioning one or both of the memory and boot electronics.

6. The method of claim 4, wherein, The bit fields include: a first field, a second field, a third field indicating the index of the target page, a fourth field indicating the index of the cached line within the target page, and a fifth field indicating the offset of the bit fields.

7. The method of claim 6, wherein, The third field includes: The sub-region identifier field, in which the value corresponding to the default sub-memory region allocated to the target page is indicated when the bit field is generated; and The memory node identifier field is used to identify the memory node corresponding to the target page.

8. The method of claim 7, wherein, In response to the number of the plurality of memory nodes being 2 n The memory node identifier field consists of n bits, and n is a natural number greater than 0.

9. The method of claim 7, wherein, The number of sub-memory regions corresponding to the first memory node is 2. m The sub-region identifier field consists of m bits, and m is a natural number greater than 0.

10. The method of claim 7, further comprising: Receive the target physical address from the first application executed by the electronic device; In response to receiving a target physical address, determine whether the value of the first field of the bit field of the target physical address is a preset value; If the value of the first field is a preset value, obtain the value of the second field; The target hash function is determined based on the value of the second field; The value corresponding to the first memory node is obtained by inputting the value of the memory node identifier field into the target hash function; Send the target physical address to the first memory node; Receive target data from the first memory node; as well as Send the target data to the first application.

11. A non-transitory computer-readable storage medium storing code, which, when executed by one or more processors, configures the one or more processors to perform the method as described in any one of claims 1 to 10.

12. An electronic device comprising: Memory, including multiple memory nodes; as well as One or more processors are configured as follows: Determine whether the page utilization rate of the first sub-memory region of the first memory node among the plurality of memory nodes is greater than or equal to a first threshold; In response to the page utilization rate of the first sub-memory region being greater than or equal to a first threshold, a second sub-memory region of the first memory node is determined. Determine the target page within the pages of the second sub-memory region; and Allocate the target page of the second sub-memory region to the first sub-memory region.

13. The electronic device of claim 12, wherein, The one or more processors include: a first core, associated with a first memory node, and The first core is configured as follows: Perform the step of determining whether the page utilization rate of the first sub-memory region is greater than or equal to a first threshold; and Execution: The step of determining the second sub-memory region of the first memory node in response to the page utilization rate of the first sub-memory region being greater than or equal to a first threshold.

14. The electronic device of claim 12, wherein, In order to allocate a target page, the one or more processors are configured to associate the target physical address of the target page with a first sub-region identifier corresponding to the first sub-memory region.

15. The electronic device of claim 14, wherein, In order to allocate the target page, the one or more processors are configured to: The value of the first field in the bit field indicating the target physical address of the target page is assigned to the sub-memory region of the target page is changed to a preset value; and Change the value of the second field in the bit field of the target physical address of the target page, which indicates the sub-memory region to be reallocated, to the value of the first sub-region identifier.

16. The electronic device of claim 15, wherein, The bit field of the target physical address of the target page is generated by partitioning the memory and booting the electronic device, or by one or both.

17. The electronic device of claim 15, wherein, The bit fields include: a first field, a second field, a third field indicating the index of the target page, a fourth field indicating the index of the cached line within the target page, and a fifth field indicating the offset of the bit fields.

18. The electronic device of claim 17, wherein, The third field includes: The sub-region identifier field contains a value that corresponds to the default sub-memory region allocated to the target page, which is indicated when the bit field is generated. The memory node identifier field is used to identify the memory node corresponding to the target page.

19. The electronic device of claim 18, wherein, In response to the number of the plurality of memory nodes being 2 n The memory node identifier field consists of n bits, and n is a natural number greater than 0.

20. The electronic device of claim 18, wherein, The number of sub-memory regions corresponding to the first memory node is 2. m The sub-region identifier field consists of m bits, and m is a natural number greater than 0.

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