Memory control method and storage device

Abstract

The application relates to the technical field of memory control, and discloses a memory control method and a storage device, wherein the method comprises the following steps: judging whether the number of free blocks of a main resource area is greater than the total number of physical blocks of a static reserved area; if yes, setting the state of a memory module to a first stage and setting the garbage collection intensity to a first intensity value; if no, setting the state of the memory module to a second stage and setting the garbage collection intensity to the first intensity value; monitoring the space net growth rate of the main resource area in the second stage; if the space net growth rate is lower than a preset first growth rate threshold for a time length reaching a time length threshold, setting the state of the memory module to a third stage and setting the garbage collection intensity to a second intensity value. The application solves the step-by-step performance jitter caused by sudden space depletion, realizes fine and forward-looking smooth management of garbage collection interference, and guarantees the continuous and stable write-in performance of the storage device.

Description

Technical Field

[0001] This invention relates to the field of memory control technology, and in particular to a memory control method and a storage device. Background Technology

[0002] In NAND flash memory devices, garbage collection is the most critical factor affecting long-term write performance stability. Traditional garbage collection performance management schemes suffer from sudden and abrupt disruptions to storage device performance caused by garbage collection operations. Typically, garbage collection is activated when the user data area is full and begins to consume a fixed amount of reserved space. As the reserved space decreases, the intensity of garbage collection is often forced to increase sharply to cope with the space crisis, resulting in a precipitous drop or severe fluctuation in host write performance.

[0003] Existing technologies alleviate the problem by optimizing waste collection algorithms or increasing fixed reserve space, but they cannot fundamentally change the deep connection between waste collection pressure and resource consumption. This prevents equipment from performing fine-grained, forward-looking, and smooth management of the impact on waste collection performance based on actual load.

[0004] Therefore, a new architecture and methodology are urgently needed to address the problem of waste recycling pressure. Summary of the Invention

[0005] Therefore, it is necessary to propose a memory control method to address the problems of existing memory control technology.

[0006] In a first aspect, a memory control method is provided, applied to a storage device including a memory controller and a memory module. The memory module is configured with a primary resource area, a spare resource area, and a statically reserved area. The parallel write bandwidth of the primary resource area is a preset maximum bandwidth, and the parallel write bandwidth of the spare resource area is less than the parallel write bandwidth of the primary resource area. The method includes: monitoring the number of free blocks in the primary resource area; determining whether the number of free blocks in the primary resource area is greater than the total number of physical blocks in the statically reserved area; if yes, setting the state of the memory module to a first stage; in the first stage, setting the garbage collection intensity to a first intensity value and directing the write path to the primary resource area; if no, setting the state of the memory module to a first stage. The module's state is set to the second stage; in the second stage, the write path is directed to the main resource area and the static reserve area, and the garbage collection intensity is set to a first intensity value; in the second stage, the net space growth rate of the main resource area is monitored; if the net space growth rate is continuously lower than a preset first growth rate threshold for a duration threshold, the state of the memory module is set to the third stage; in the third stage, the write path is directed to the main resource area, the static reserve area, and the spare resource area, the garbage collection intensity is set to a second intensity value, which is greater than the first intensity value, and the main resource area, the static reserve area, and the spare resource area are written using a balanced strategy.

[0007] Secondly, a storage device is provided, the device comprising: a connection interface for electrically connecting to a host system; a memory module including multiple planes, each plane including multiple blocks, each block including multiple pages; and a memory controller including error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module; wherein the memory module is configured to: monitor the number of free blocks in the main resource area; determine whether the number of free blocks in the main resource area is greater than the total number of physical blocks in the static reserved area; if so, set the state of the memory module to a first stage; in the first stage, the garbage collection intensity is set to a first intensity value, and the write path is directed to the main resource area; if If not, the memory module is set to the second stage; in the second stage, the write path is directed to the main resource area and the static reserve area, and the garbage collection intensity is set to a first intensity value; in the second stage, the net space growth rate of the main resource area is monitored; if the net space growth rate is continuously lower than a preset first growth rate threshold for a duration threshold, the memory module is set to the third stage; in the third stage, the write path is directed to the main resource area, the static reserve area, and the spare resource area, the garbage collection intensity is set to a second intensity value, the second intensity value is greater than the first intensity value, and the main resource area, the static reserve area, and the spare resource area are written using a balanced strategy.

[0008] The beneficial effects of this invention are as follows: The memory module is configured with a primary resource area, a backup resource area, and a static reserved area. The parallel write bandwidth of the primary resource area is a preset maximum bandwidth, while the parallel write bandwidth of the backup resource area is less than that of the primary resource area. The number of free blocks in the primary resource area is continuously monitored and compared with the total number of physical blocks in the static reserved area. When space is sufficient, all data is written only to the primary resource area to maintain optimal performance. When space becomes tight, the memory module is set to a second stage, and writes are diverted to the static reserved area. Finally, if space becomes even tighter, the write path points to the primary resource area, the static reserved area, and the backup resource area, participating in writing before the primary resource area is exhausted. This proactively distributes write pressure, preventing all write requests and subsequent garbage collection pressure from concentrating on a single resource pool. This resolves the step-like performance fluctuations caused by sudden space exhaustion, achieving refined and proactive smooth management of garbage collection interference, and ensuring the continuous and stable write performance of the storage device. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] in: Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application; Figure 4 This is a general flowchart of a memory control method according to an embodiment of this application; Figure 5 This is a general flowchart of a memory control method according to another embodiment of this application; Figure 6 This is a flowchart illustrating the process of setting the garbage collection level of a memory module according to an embodiment of this application. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0012] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system installed in a specific carrier (e.g., vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. Furthermore, the storage device 12 can include solid-state drives (SSDs), universal flash storage (UFS), embedded multi-media cards (eMMC), USB flash drives, memory cards, or other types of non-volatile storage devices. It is particularly suitable for fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability, such as industrial control, edge computing, and automotive electronics.

[0013] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0014] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. Multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules are specially selected and tested to meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention.

[0015] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0016] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0017] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host system interface 21, a memory interface 22, and a memory control circuit 23. The host system interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0018] Memory control circuitry 23 is connected to host system interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host system interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0019] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. In particular, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) characteristics, or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0020] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0021] In one embodiment, the memory controller 123 may also include other types of various circuit modules (e.g., power management circuits, etc.), which are not limited in this application.

[0022] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0023] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(0)-301(B). Each physical unit includes multiple storage cells for non-volatile data storage.

[0024] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, the entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0025] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0026] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0027] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0028] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0029] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0030] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0031] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host system 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0032] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0034] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0036] Figure 4 This is a general flowchart of a memory control method according to an embodiment of the present invention. The method is applied to a storage device 12 including a memory module 122. Each flash memory block in the memory module is divided into a primary resource area, a spare resource area, and a statically reserved area based on the integrity of its physical units. The parallel write bandwidth of the primary resource area is a preset maximum bandwidth, and the parallel write bandwidth of the spare resource area is less than the parallel write bandwidth of the primary resource area. The memory control circuit 23 or the memory controller 123 is configured to execute this method. The method begins at step S601.

[0037] S401: Monitor the number of free blocks in the main resource area.

[0038] Specifically, the number of free flash memory blocks currently available for writing in the main resource area is continuously or periodically read, and this number, or its converted available space value, is written to a maintained variable or register. Specifically, this can be achieved by traversing the free bitmap or free block counter of the main resource area, or by maintaining near real-time synchronization through event-driven mechanisms (such as updating the counter after each erase, allocation, or reclamation), avoiding the overhead of a full scan, ultimately obtaining a quantitative indicator reflecting the real-time capacity pressure of the main resource area. Parallel write bandwidth is the maximum write data rate achieved through multi-channel parallel operation of the particles in the main resource area. The method for dividing the main resource area, spare resource area, and static reserved area is as follows: the integrity of each physical block is checked; intact physical blocks are designated as the main performance pool, and the remaining incomplete physical blocks are designated as the spare resource area. Then, the main performance pool is divided according to a preset ratio (e.g., main resource area: static reserved area = 9:1) to obtain the main resource area and the static reserved area.

[0039] S402: Determine whether the number of free blocks in the main resource area is greater than the total number of physical blocks in the static reserved area.

[0040] Specifically, the total number of physical blocks in the static reserved area is a fixed value set based on the total physical capacity (e.g., 7% of the total physical capacity). If it is greater than the total number of physical blocks in the static reserved area, it is considered that the main resource area has sufficient margin; otherwise, it is considered to be in a state of space shortage. The state set by the state machine is set, that is, the state machine is driven according to the comparison result, and it will be marked as the first stage, the second stage, or the third stage.

[0041] S403: If yes, it will be set to the first stage; in the first stage, the garbage collection intensity will be set to the first intensity value, and the write path will be pointed to the main resource area.

[0042] Specifically, when set to the first stage, when each write request arrives, a free block or page is selected from the main resource area for writing. That is, the write path is only directed to the main resource area. Since the parallel write bandwidth of the main resource area is the preset maximum bandwidth, it avoids diverting some write requests to the backup resource area with lower bandwidth, thus avoiding the overall write speed decrease. In addition, the write logic is simple and does not need to select and schedule among multiple target pools, reducing decision-making overhead and further improving response speed.

[0043] S404: If not, set the state of memory module 122 to the second stage; in the second stage, the write path is directed to the main resource area and the static reserved area, the garbage collection intensity is set to the first intensity value, and the write priority of the main resource area is higher than the write priority of the static reserved area.

[0044] Specifically, when the number of free blocks in the main resource area is less than or equal to the total number of physical blocks in the static reserved area, it is judged as the second stage. At this time, the traffic distribution and load balancing strategy is activated to distribute or redundantly write new write commands between the main resource area and the static reserved area to reduce the instantaneous pressure on the main resource area. Specific strategies may include proportional allocation (e.g., dynamically calculating the distribution ratio based on the idle degree), prioritizing writing to the main resource area with the largest bandwidth, and directing a small number of non-critical writes to the static reserved area.

[0045] Since the flash blocks in the static reserved area are usually homogeneous with the main resource area (or even carved out from it), their reliability, durability, and access speed are far superior to those in the spare resource area, which has a smaller write bandwidth. This allows data to be written to two high-performance, high-reliability areas, avoiding the risks of higher error rates, longer read latency, and earlier damage that may result from writing data to degraded blocks in the spare area.

[0046] S405: Monitor the net spatial growth rate of the main resource zone in the second phase; Specifically, the net growth rate of the main resource area is read continuously or at predetermined intervals (e.g., 100 milliseconds). The net growth rate is the difference between the garbage collection release rate and the write consumption rate of the main resource area. When the net growth rate is positive, it indicates that the space pressure of the main resource area will decrease, and the larger the net growth rate, the faster the space pressure will decrease. When the net growth rate is negative, it indicates that the space pressure of the main resource area will increase, and the smaller the net growth rate (considering the actual value, not the absolute value), the faster the space pressure will increase.

[0047] S406: If the net growth rate of space is continuously lower than the preset first growth rate threshold for a period of time, the state of the memory module 122 is set to the third stage; in the third stage, the write path points to the main resource area, the static retention area and the spare resource area, the garbage collection intensity is set to the second intensity value, the second intensity value is greater than the first intensity value, and the main resource area, the static retention area and the spare resource area are written using a balanced strategy.

[0048] Specifically, if the net growth rate of space is continuously lower than the preset first growth rate threshold (e.g., 80 blocks / second) for a duration threshold (e.g., 1 second), it is judged as the third stage. At this time, the traffic distribution and load balancing strategy is activated to distribute or redundantly write new write commands among the main resource area, static reserve area, and standby resource area to reduce the instantaneous pressure on the main resource area. Specific strategies may include proportional allocation (e.g., dynamically calculating the distribution ratio based on idle time), prioritizing writing to the main resource area with the largest bandwidth and directing non-critical writes to the standby resource area or static reserve area, or using different paths for long and short write requests (small random writes are given priority to enter the standby resource area to reduce the write to the main resource area), and increasing the level of garbage collection intensity.

[0049] When the write pressure increases further, the primary resource area, static reserved area and spare resource area are activated at the same time to provide the storage device 12 with the last layer of available space buffer, which postpones the occurrence of the write-full and unresponsive state. Since the write to the spare resource area will consume space faster, it is necessary to increase the garbage collection intensity and accelerate the space reclamation speed. Furthermore, the balanced write strategy can avoid overload of a single area and optimize the overall performance.

[0050] In one embodiment, after the step of setting the state of the memory module 122 to the third stage if the net space growth rate is continuously lower than the preset first growth rate threshold for a duration threshold, the method further includes: monitoring the utilization rate of the backup resource area and the net space growth rate of the main resource area; when the utilization rate of the backup resource area is greater than the preset utilization rate threshold and the net space growth rate is less than the preset second growth rate threshold, setting the garbage collection intensity to a third intensity value, wherein the third intensity value is greater than the second intensity value and the second growth rate threshold is less than the first growth rate threshold.

[0051] When entering the third stage, if the utilization rate of the spare resource area exceeds a preset utilization threshold (e.g., 50%) and the net space growth rate is less than a preset second growth rate threshold (e.g., 0), a contradiction will arise between insufficient recycling response and slow recovery of main pool space. Therefore, it is necessary to proactively upgrade the garbage collection intensity from the second recycling level to a higher third recycling level to further accelerate the generation of recyclable space and coordinate with the backup resource area's diversion strategy. This will smooth the overall write performance of the storage device and replenish the available space of the main resource area as soon as possible, avoiding a sudden surge in recycling pressure.

[0052] Actively increasing recycling intensity can release continuous available blocks as soon as possible, thereby shortening the risk window of main pool space depletion and avoiding recycling surges caused by passive waiting.

[0053] Reference Figure 5 In one embodiment, the memory control method further includes: in the second or third stage, monitoring the number of free blocks in the main resource area; determining whether the number of free blocks in the main resource area is greater than the sum of the total number of physical blocks in the static reserved area and a preset number; if so, returning the state of the memory module 122 to the first stage.

[0054] Specifically, due to the decrease in the number of write commands, the number of free blocks in the main resource area can support the write rate. In order to maximize the write rate, the process will return to the first stage. Specifically, the return condition can be set to determine whether the number of free blocks in the main resource area is greater than the sum of the total number of physical blocks in the static reserved area and the preset number (e.g., 2).

[0055] The preset number is intended to accumulate more free blocks in the main resource area, avoiding frequent switching between the first and second phases due to minor space fluctuations. Each switch involves reconfiguring the write path and GC strategy, which can lead to performance jitter, increased latency, and severely impact user experience and storage reliability.

[0056] In one embodiment, the above-mentioned balancing strategy includes at least: allocating the write ratio of the main resource area, the static reserved area, and the backup resource area according to the number of free blocks and / or the write amplification factor of the main resource area, the static reserved area, and the backup resource area, so that the difference in the number of free blocks between any two resource areas remains within a preset difference range.

[0057] To ensure balanced write operations across physical blocks in the primary, static reserve, and backup resource areas, preventing rapid wear of the primary resource area due to excessive writing, and allowing the static reserve and backup resource areas to bear appropriate write loads to balance wear levels and extend the overall lifespan of the storage device, a write ratio is allocated based on the number of free blocks and / or write amplification factor in each area. This ensures the difference in the number of free blocks between any two resource areas remains within a preset range, favoring areas with more free blocks to quickly balance the number of free blocks in each area, and favoring areas with lower write amplification factors because a lower write amplification factor means less additional writing and higher efficiency. Specifically, the allocation can be based on the proportion of free blocks, using the reciprocal of the write amplification factor as the weight.

[0058] Balanced writing ensures that the garbage collection pressure in the three regions is relatively balanced, avoiding performance bottlenecks in a single region and maintaining overall performance stability. By controlling the difference in the number of free blocks, it can be ensured that all three regions have a certain amount of available space, avoiding performance fluctuations caused by forced emergency garbage collection due to insufficient space in a certain region.

[0059] In one embodiment, after the step of setting the garbage collection intensity to a third intensity value when the utilization rate of the backup resource area is greater than a preset utilization rate threshold and the net space growth rate is less than a preset second growth rate threshold, the method further includes: monitoring the real-time net space growth rate of the main resource area; determining whether the real-time net space growth rate is greater than a first growth rate threshold (e.g., 80 blocks / second); if it is greater than the first growth rate threshold, monitoring the number of read / write instructions cached in the memory controller; determining whether the number of read / write instructions is less than a preset number of instructions; if it is less than the preset number of instructions, adjusting the current garbage collection intensity level according to a preset correspondence table and based on the real-time net space growth rate, wherein the preset correspondence table stores the correspondence between the net space growth rate and the garbage collection intensity.

[0060] Because setting a third intensity value might cause the write pressure to drop after a brief peak, the third intensity value might continue to run, excessively consuming background resources and leading to unnecessary performance overhead and power consumption. Therefore, the garbage collection intensity level can be adjusted based on the real-time net space growth rate of the main resource area and a preset corresponding table. The adjustment can be done in a step-like manner (directly switching to the target level) or gradually (gradually increasing or decreasing the intensity until the target is reached).

[0061] The mechanism of adjusting the waste recycling level by the real-time net space growth rate can basically match the rate of space consumption with the rate of space recycling.

[0062] In one embodiment, the method for constructing a preset correspondence table is as follows: The real-time write bandwidth is calculated based on the real-time write bandwidth and the garbage collection intensity corresponding to each garbage collection level, so as to calculate the write bandwidth loss at each garbage collection level, in order to set the correspondence between the real-time net space growth rate and the corresponding garbage collection intensity. Specifically, a relationship is established based on the maximum write bandwidth and the garbage collection intensity, i.e.: .

[0063] in: The maximum sequential write bandwidth that the device can achieve without GC (e.g., 6.4 GB / s) can be obtained in advance.

[0064] The normalized value corresponding to the highest GC intensity (e.g., 3) can be obtained in advance.

[0065] The scheduling loss coefficient reflects the degree of resource contention between GC and host I / O, and is calibrated experimentally. For a typical multi-channel controller, α is usually between 0.05 and 0.15. By fitting this coefficient according to the formula, the relationship between real-time write bandwidth and garbage collection level can be obtained, thereby calculating the corresponding bandwidth loss. Then, based on the bandwidth loss, the correspondence between the real-time net space growth rate and the corresponding garbage collection intensity is set, i.e., a preset correspondence table is established.

[0066] In one specific embodiment, the steady-state sequential write bandwidth was measured under conditions of no GC, GC intensities 1, 2, and 3, and the α value was obtained by least-squares fitting. For example, the measured values ​​were: No GC: 6400MB / s; Intensity 1: 6100 MB / s → Loss (6400-6100) / 6400 = 4.69%; Intensity 2: 5800 MB / s → Loss 9.38%; Intensity 3: 5200 MB / s → Loss 18.75%; Substituting into the model, we get α≈0.0625, at which point the error between the model prediction and the actual measurement is less than 5%.

[0067] Reference Figure 6In one embodiment, the step of adjusting the current garbage collection intensity level based on a preset correspondence table and the real-time net space growth rate includes: determining whether the real-time net space growth rate is greater than a second growth rate threshold (e.g., 100 blocks / second), where a first growth rate threshold is less than the second growth rate threshold; if the real-time net space growth rate is less than or equal to the second growth rate threshold, obtaining the current garbage collection intensity level of the memory module and downgrading the collection level; if the real-time net space growth rate is greater than the second growth rate threshold, obtaining the current garbage collection intensity level of the memory module and gradually downgrading the collection level, downgrading by one level at a time, until the real-time net space growth rate does not exceed the second growth rate threshold or reaches the first intensity value.

[0068] When the real-time net space growth rate (i.e., the reclamation release rate minus the write consumption rate) exceeds the second growth rate threshold, it indicates that the current storage device's reclamation capacity has exceeded write consumption, and the available space in the main resource area is rapidly increasing. If the garbage collection intensity is not downgraded in time under this situation, it will continue to be collected at a higher intensity, leading to unnecessary energy consumption and additional erasure and write operations (write amplification), accelerating media wear and wasting computing resources; however, if the reclamation level is blindly or reduced too low at once, it may cause response lag under a short-term surge in write load. Therefore, when the net growth rate of space is detected to exceed the preset second growth rate threshold, the current garbage collection intensity level is first read, and then the level is gradually downgraded according to the safety rules (downgrading means lowering the collection level by one). Specifically, it can be downgraded by one level for a preset time and then downgraded a second time until the garbage collection intensity is the first intensity value. If the real-time net growth rate of space is less than or equal to the second growth rate threshold, but greater than the first growth rate threshold, or if the real-time net growth rate of space does not exceed the second growth rate threshold, the current collection level is downgraded. At this time, it is only downgraded by one level. When the subsequent net growth rate of space exceeds the preset second growth rate threshold, or when the number of free blocks in the main resource area is greater than the total number of physical blocks in the static reserve area, it is downgraded back to the first intensity value.

[0069] The use of step-by-step degradation and security verification avoids insufficient response during subsequent write surges due to one-time skipping or blind degradation, ensuring the robustness of the storage device to fluctuating loads; the observation window and hysteresis control after degradation further suppress frequent oscillations and reduce the overhead of mapping update and reclamation scheduling.

[0070] In one embodiment, the memory control method further includes: monitoring the status of each physical block in the main resource area; when a target physical block in each physical block is in a bad state, selecting a corresponding replacement physical block from the spare resource area to replace the target physical block in performing read / write operations.

[0071] In the main resource area, some flash memory blocks will develop unrecoverable bad blocks (physical damage caused by process defects or erase / write fatigue) over time. If logical data continues to be mapped to these bad blocks without a detection and replacement mechanism or if the mechanism is missing or delayed, it will lead to a surge in read / write errors, data retries, and remapping overhead, resulting in increased front-end write latency, decreased garbage collection efficiency, and a sudden drop in host available capacity. Furthermore, if bad blocks are not removed in time, it will distort the available space statistics (misjudging the main pool as having more available space), thus affecting subsequent allocation and reclamation decisions based on available space, ultimately causing the reclamation strategy to fail or triggering emergency reclamation. A bad block scan is performed on each flash memory block in the main resource area (this can be periodic or event-driven, such as triggered when read / erase error rates are abnormal). When a bad block is found, a block that meets the health and lifespan requirements is immediately selected from the spare resource area as a replacement, completing the physical replacement and updating the mapping table and bad block table.

[0072] Bad blocks are detected and replaced in real time in the main resource area to improve the accuracy of subsequent diversion and reclamation decisions and avoid erroneous triggering or delayed response caused by false available space.

[0073] In one embodiment, the step of selecting a corresponding replacement physical block from the spare resource area to perform read / write operations in place of the target physical block when the target physical block in the main resource area is in a bad state includes: when the target physical block in the main resource area is in a bad state, obtaining the number of erase / write operations of each free block in the spare resource area; selecting the free block with the fewest erase / write operations as the replacement physical block to perform read / write operations in place of the target physical block.

[0074] To ensure the stability of physical blocks in the main resource area, it is preferable to select better physical blocks from the spare resource area for supplementation. The number of erase / write cycles is the most direct physical indicator for measuring the lifespan and reliability of flash memory cells, because the block with the fewest erase / write cycles means that its remaining programming / erase lifespan is the longest, and the probability of errors or becoming bad blocks in the future is the lowest. The number of erase / write cycles is the basic metadata that the controller must maintain for each physical block, which can be directly obtained. The free block with the fewest erase / write cycles is selected as the replacement physical block to perform read and write operations in place of the target physical block.

[0075] This helps maintain a relatively high overall block quality in the main resource area and avoids a decline in the average performance of the main resource area due to the introduction of low-quality blocks caused by frequent replacements.

[0076] In one embodiment, the first intensity value, the second intensity value, and the third intensity value correspond to different sets of garbage collection execution parameters, and the parameters in each set of garbage collection execution parameters include at least: the number of flash channels for concurrent garbage collection, the proportion of garbage collection time slices, and the migration load.

[0077] In this embodiment, GC (garbage collection) intensity is defined as a composite index consisting of the following three quantifiable parameters: GC Concurrent Channels C_gc: The number of flash memory channels that participate in garbage collection operations simultaneously.

[0078] GC time slice percentage T_gc: The proportion of controller time occupied by GC tasks within each scheduling cycle (e.g., 1ms).

[0079] GC migration load L_gc: The amount of effective page data migrated by GC per unit time, in MB / s.

[0080] GC intensity level I_gc: Divided into three levels based on the above parameter combinations, the specific value is related to the device's hardware capabilities. Taking a 16-channel solid-state drive with 400MB / s bandwidth per channel as an example, the settings are as follows: The equivalent backend bandwidth is estimated as C_gc×400×T_gc, which is used to approximate the GC's occupation of the flash memory medium.

[0081] In one embodiment, after the step of setting the memory module to the third stage when the net growth rate of space is lower than the preset first growth rate threshold for a certain period of time, the method further includes: when the number of free blocks in the main resource area is greater than the sum of the total number of physical blocks in the static reserve area and the second preset number (e.g., 1000 blocks), monitoring the utilization rate of the backup resource area; determining whether the utilization rate of the backup resource area exceeds the utilization rate threshold; if the utilization rate of the backup resource area exceeds the utilization rate threshold (the sum of the total number of physical blocks in the static reserve area and the second preset number), setting a dedicated garbage collection operation for the backup resource area to be started during the storage device idle period, wherein the dedicated collection operation includes migrating the data in the backup resource area to the main resource area and recycling the erased space back to the backup resource area for reuse, and the storage device idle period is entered when the host command queue is empty for a predetermined time (e.g., 10ms).

[0082] In the third phase, when the number of free blocks in the primary resource area exceeds the sum of the total number of physical blocks in the static reserved area and the second preset number, it indicates that the primary resource area is relatively abundant and can handle garbage collection in the backup resource area. Write requests will be diverted to the backup resource area. If only passive or background generalized garbage collection strategies are relied upon, the backup resource area may gradually become full under continuous high writes or lag in backhaul. Once the cache pool utilization exceeds the safe limit, there is a risk of cache overflow, write rejection, or forced emergency reclamation, leading to a sharp increase in host write latency or performance fluctuations. When the utilization of the backup resource area is detected to exceed the utilization threshold (e.g., 50%), strong reclamation is not immediately performed under high load. Instead, a dedicated garbage collection operation for the backup resource area is initiated during storage device idle periods. This dedicated reclamation includes migrating appropriate data from the cache pool to the primary resource area, erasing the emptied cache blocks, and reclaiming them back to the backup resource area for reuse.

[0083] Performing recycling during idle periods reduces interference with write operations, thereby freeing up a large amount of cache space without sacrificing the write experience and effectively avoiding cache overflow and emergency recycling.

[0084] In one embodiment, the memory control method further includes: calculating and outputting the operating parameters required to achieve the level of waste recycling intensity based on the level of waste recycling intensity, and executing the calculation.

[0085] Different levels require a specific set of execution parameters (e.g., concurrency, candidate selection threshold, reclamation interval, single erase batch size, moveback priority, etc.). Without a mapping and distribution mechanism from levels to specific parameters, the strategy cannot be accurately executed, leading to a mismatch between the reclamation intensity and actual expectations, potentially causing excessive erasure, foreground I / O interference, or response delays. After the level is determined, a set of specific operational parameters is calculated based on the target level, current storage device parameters (such as R_net, U_cache, F_free, host write rate), device health, and security constraints. These parameters are then subject to security restrictions and boundary checks before execution.

[0086] In one embodiment, the step of monitoring the net spatial growth rate of the main resource area in the second stage includes: detecting a first rate at which the main resource area releases space through garbage collection and a second rate at which space is consumed by writing data; and subtracting the second rate from the first rate to obtain the net spatial growth rate.

[0087] The first rate at which garbage collection frees up space refers to the speed at which the memory controller cleans up invalid data and releases available space from the main resource area through the garbage collection mechanism. It is usually measured in MB / s or GB / s and represents the effective space released per unit of time (i.e., the actual usable space after reclamation). The second rate at which data is written to consume space refers to the speed at which application programs or storage devices consume storage space when writing new data to the main resource area. The net space growth rate is calculated by subtracting the second rate (consumption rate) from the first rate (release rate). A positive value indicates that available space is increasing, while a negative value indicates that available space is decreasing.

[0088] In one embodiment, the write priority of the main resource area is higher than the write priority of the static reserved area. Specifically, when a host write request arrives, the target physical block is selected and allocated in the main resource area first, and it is detected whether the main resource area meets the preset allocation failure condition during the allocation process. If the preset allocation failure condition is met, the target physical block is allocated in the spare resource area.

[0089] Specifically, the priority order is as follows: primary resource area → backup resource area → static reserved area. The workflow is as follows: all host write requests are first directed to the primary resource area. At this point, the physical block status table of the primary resource area is scanned, the wear leveling status of available blocks is evaluated, and the optimal target physical block is selected (considering P / E cycles, bad block rate, etc.). During the allocation process, three indicators are monitored in real time: space availability: the number of remaining allocable blocks in the primary resource area; performance threshold: whether the current write latency exceeds the preset requirement; health indicator: whether the bad block rate exceeds the safety threshold; failover mechanism: when any of the following preset allocation failure conditions are triggered, automatic switch to the backup resource area is established: three consecutive failed allocation attempts, the number of available blocks is less than 5% of the total capacity, the average write latency exceeds 500μs, or the bad block rate exceeds 0.1%.

[0090] By prioritizing storage, resource utilization can be improved while ensuring reliability, so that the use of each resource area can reach a balanced state.

[0091] In one embodiment, the duration threshold and the first growth rate threshold are set based on the total number of physical blocks in the static reservation area.

[0092] Specifically, the first growth rate threshold (ΔS) t ): This is typically set to 0.5%-1% of the total number of blocks in the static reserve per second. For example, if the static reserve has 10,000 physical blocks, then ΔS t =50-100 blocks / s, the duration threshold (T) is positively correlated with the static reserve capacity, and the calculation formula is: ;in This represents the total number of blocks in the static reserved area. The typical waste recycling cycle time is represented by k, which is an adjustment coefficient (usually set between 2 and 3).

[0093] It implements a threshold setting that is related to the physical blocks in the static reserved area, adapting to various storage capacities, avoiding resource waste in small capacity configurations, and ensuring timely intervention capabilities in large capacity scenarios.

[0094] Comparison between the present invention and traditional solutions: 1. During the basic performance maintenance phase, the core performance indicators (GC intensity and write performance) of the traditional solution and the back-zone solution of this invention are completely consistent: the GC intensity is maintained at level 1, and the write performance is maintained at 100%. This indicates that the construction of the tiered resource pool did not affect the initial write performance.

[0095] 2. Pressure Load and Smooth Transition Phase The limitations of traditional no-return-area solutions are becoming apparent: to cope with space pressure, GC intensity is passively increased to level 2. Although write performance is temporarily maintained at 100%, memory thrashing (performance fluctuation risk) occurs as a result. The proposed solution achieves a breakthrough through a buffer mechanism in the B area (backup resource area): the GC intensity is always maintained at level 1, and the write performance is stable at "100%". The optimization effect is reflected in the delayed GC triggering. The B area acts as a temporary buffer layer, so the storage device does not need to immediately upgrade the GC level due to a sudden increase in space pressure, thus allowing the high-performance state to last longer.

[0096] 3. Deep Load and Controllable Degradation Phase Traditional B-area-less solutions are caught in a performance cliff dilemma: GC intensity jumps to level 4 (the highest level), write performance drops precipitously by about 40% (i.e., the "performance cliff phenomenon"), and the storage device's processing capacity is severely degraded; The return zone scheme of this invention achieves a breakthrough in controllability through hierarchical control and smooth degradation mechanism: The first step is to activate the B-area buffer to "bear the write pressure" and delay the sharp increase in GC intensity; The second step is to smoothly adjust the GC intensity from the peak to level 2 or 3, so that the write performance drops linearly from 100% to 50%-70% (rather than a cliff drop).

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory control method, characterized in that, The invention relates to a storage device comprising a memory controller and a memory module, wherein the memory module is provided with a main resource area, a spare resource area and a static reserved area, the parallel write bandwidth of the main resource area is a preset maximum bandwidth, and the parallel write bandwidth of the spare resource area is less than the parallel write bandwidth of the main resource area. The method includes: Determine whether the number of free blocks in the main resource area is greater than the total number of physical blocks in the static reserved area; If so, set the state of the memory module to the first stage; In the first stage, the waste recycling intensity is set to a first intensity value, and the write path is pointed to the main resource area; If not, set the state of the memory module to the second stage; In the second stage, the write path is pointed to the main resource area and the static retention area, and the garbage collection intensity is set to the first intensity value; During the second phase, the net spatial growth rate of the main resource zone is monitored; If the duration of the net spatial growth rate being lower than the preset first growth rate threshold reaches a duration threshold, the state of the memory module is set to the third stage. In the third stage, the write path is directed to the main resource area, the static retention area, and the backup resource area, and the garbage collection intensity is set to a second intensity value, which is greater than the first intensity value.

2. The memory control method according to claim 1, characterized in that, After the step of setting the state of the memory module to the third stage if the net spatial growth rate is lower than a preset first growth rate threshold for a certain duration, the method further includes: Monitor the utilization rate of the backup resource zone and the net spatial growth rate of the main resource zone; When the utilization rate of the backup resource area is greater than a preset utilization rate threshold, and the net growth rate of the space is less than a preset second growth rate threshold, the waste recycling intensity is set to a third intensity value, which is greater than the second intensity value and the second growth rate threshold is less than the first growth rate threshold.

3. The memory control method according to claim 1, characterized in that, The method further includes: In the second or third stage, monitor the number of free blocks in the main resource area; Determine whether the number of free blocks in the main resource area is greater than the sum of the total number of physical blocks in the static reserved area and a preset number; If so, return the state of the memory module to the first stage.

4. The memory control method according to claim 1, characterized in that, The main resource area, the static reserved area, and the spare resource area are written using a balanced writing strategy; The balancing strategy includes at least the following: allocating the write ratio of the main resource area, the static reserved area, and the backup resource area according to the number of free blocks and / or the write amplification factor of the main resource area, the static reserved area, and the backup resource area, so that the difference in the number of free blocks between any two resource areas remains within a preset difference range.

5. The memory control method according to claim 2, characterized in that, After the step of setting the waste recycling intensity to a third intensity value when the utilization rate of the backup resource area is greater than a preset utilization rate threshold and the net space growth rate is less than a preset second growth rate threshold, the method further includes: Monitor the real-time net spatial growth rate of the main resource zone; Determine whether the real-time net spatial growth rate is greater than the first growth rate threshold; If the number of read / write instructions cached in the memory controller is greater than the first growth rate threshold, then monitor the number of read / write instructions cached in the memory controller. Determine whether the number of read / write instructions is lower than the preset number of instructions; If the number is less than the preset number of instructions, the recycling level of the current waste recycling intensity is adjusted according to the preset correspondence table and based on the real-time net space growth rate. The preset correspondence table stores the correspondence between the net space growth rate and the waste recycling intensity.

6. The memory control method according to claim 5, characterized in that, The step of adjusting the recycling level of the current waste recycling intensity based on a preset correspondence table and the real-time net spatial growth rate includes: Determine whether the real-time net spatial growth rate is greater than the second growth rate threshold, wherein the first growth rate threshold is less than the second growth rate threshold; If the real-time net growth rate of space is less than or equal to the second growth rate threshold, then the current garbage collection intensity level of the memory module is obtained, and the collection level is downgraded. If the real-time net space growth rate is greater than the second growth rate threshold, the current garbage collection intensity level of the memory module is obtained, and the collection level is gradually downgraded, downgrading by one level at a time, until the real-time net space growth rate does not exceed the second growth rate threshold or reaches the first intensity value.

7. The memory control method according to claim 1, characterized in that, The method further includes: Monitor the status of each physical block in the main resource area; When a target physical block is found to be bad in any of the physical blocks, a corresponding replacement physical block is selected from the spare resource area to replace the target physical block in performing read / write operations.

8. The memory control method according to claim 7, characterized in that, The step of selecting a corresponding replacement physical block from the spare resource area to perform read / write operations on the target physical block when a target physical block in any of the physical blocks is in a bad state includes: When a target physical block in any physical block is in a bad state, the erase / write count of each free block in the spare resource area is obtained. The free block with the fewest erase / write cycles is selected as the replacement physical block to perform read / write operations in place of the target physical block.

9. The memory control method according to claim 1, characterized in that, The first intensity value, the second intensity value, and the third intensity value correspond to different sets of garbage collection execution parameters, and the parameters in each set of garbage collection execution parameters include at least: the number of flash channels for concurrent garbage collection, the proportion of garbage collection time slices, and the migration load.

10. The memory control method according to claim 1, characterized in that, After the step of setting the state of the memory module to the third stage if the net spatial growth rate is lower than a preset first growth rate threshold for a certain duration, the method further includes: When the number of free blocks in the main resource area is greater than the sum of the total number of physical blocks in the static reserved area and the second preset number, the utilization rate of the backup resource area is monitored; Determine whether the utilization rate of the backup resource area exceeds the utilization rate threshold; If the utilization rate of the backup resource area exceeds the utilization rate threshold, a dedicated garbage collection operation for the backup resource area is initiated during the idle period of the storage device. The dedicated collection operation includes migrating the data in the backup resource area to the main resource area and recycling the erased space back to the backup resource area for reuse.

11. The memory control method according to claim 1, characterized in that, Also includes: Calculate and output the operational parameters required to achieve the required level of waste recycling intensity based on the waste recycling intensity level; The garbage collection operation is performed based on the aforementioned operating parameters.

12. The memory control method according to claim 1, characterized in that, The step of monitoring the net spatial growth rate of the main resource zone in the second stage includes: The first rate at which the garbage collection and release space in the main resource area is detected, and the second rate at which the space is consumed by writing data are detected. Subtracting the second rate from the first rate yields the net spatial growth rate.

13. The memory control method according to claim 1, characterized in that, Also includes: In the second stage, the write priority of the main resource area is higher than the write priority of the static reserved area. When a host write request arrives, the target physical block is selected and allocated in the main resource area first. During the allocation process, it is detected whether the main resource area meets the preset allocation failure condition. If the preset allocation failure condition is met, the target physical block is allocated in the static reserved area.

14. The memory control method according to claim 1, characterized in that, The duration threshold and the first growth rate threshold are set according to the total number of physical blocks in the static reservation area.

15. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 14.

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