Back contact cells, photovoltaic modules and photovoltaic systems

Abstract

The application discloses a back contact cell, a photovoltaic module and a photovoltaic system. The back contact cell comprises a substrate and first regions and second regions arranged on the back of the substrate, the first regions and the second regions are arranged alternately along a first direction; the first regions are provided with a first intrinsic silicon film layer, a quantum dot hole transport layer, a first TCO layer and a P-type electrode which are stacked in sequence. The application can reduce the recombination of the first regions, improve the efficiency of the back contact cell, and improve the absorption and utilization rate of near-infrared light and ultraviolet light of the back contact cell.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more particularly to a back-contact cell, a photovoltaic module, and a photovoltaic system. Background Technology

[0002] Back-contact batteries place both positive and negative electrodes on the back side, reducing shading of the front side of the battery, increasing the short-circuit current, and improving the energy conversion efficiency. Common types of back-contact batteries include TBC batteries and HBC batteries. TBC batteries combine TOPCon and IBC technologies, using tunneling oxide layer passivation contacts, resulting in high passivation quality and good contact characteristics. HBC batteries combine HJT and IBC technologies, forming a heterojunction on the back side of the battery, resulting in high carrier collection efficiency. However, traditional crystalline silicon back-contact batteries have low utilization rates for near-infrared light (>1100nm) and ultraviolet light (300nm~400nm), leading to approximately 50% energy loss in the solar spectrum. In addition, the large interface defects in the P-type doped region of traditional crystalline silicon back-contact batteries result in significant recombination losses on the back side, which is detrimental to improving the efficiency of back-contact batteries. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a back contact battery, a photovoltaic module and a photovoltaic system that reduces recombination in the first region, improves the efficiency of the back contact battery, and improves the absorption and utilization rate of near-infrared and ultraviolet light by the back contact battery.

[0004] To address the aforementioned problems, the present invention discloses a back-contact battery, comprising a substrate and a first region and a second region disposed on the back side of the substrate, wherein the first region and the second region are alternately disposed along a first direction; The first region is provided with a first intrinsic silicon film layer, a quantum dot hole transport layer, a first TCO layer and a P-type electrode stacked in sequence.

[0005] As an improvement to the above technical solution, the quantum dot hole transport layer is formed by depositing a quantum dot compound on the first intrinsic silicon film layer. The crystallinity of the quantum dot compound is 10%~60%, and the size is 1nm~100nm.

[0006] As an improvement to the above technical solution, a quantum dot compound is deposited on the first intrinsic silicon film layer using PVD to form the quantum dot hole transport layer. The conditions for forming the quantum dot hole transport layer include: a vacuum degree of 1×10⁻⁶. -6 Pa ~ 1×10 -5 Pa, argon flow rate 1 cm 3 / min~50cm 3 Sputtering speed: 50W~1000W; sputtering time: 3min~60min.

[0007] As an improvement to the above technical solution, the crystallinity of the first intrinsic silicon film layer is 40%~70%; and / or The refractive index of the first intrinsic silicon film layer is 3.0~4.0.

[0008] As an improvement to the above technical solution, the thickness of the first intrinsic silicon film layer is 1 nm to 50 nm; and / or The thickness of the quantum dot hole transport layer is 50nm~500nm.

[0009] As an improvement to the above technical solution, the hole mobility of the quantum dot hole transport layer is 100 cm⁻¹. 2 / Vs~500cm 2 / Vs, conductivity 10 -4 S / cm ~ 1S / cm.

[0010] As an improvement to the above technical solution, the quantum dot hole transport layer is a PbS layer, a PbSe layer, a PbTe layer, or a PbS layer. 0.8 Se 0.2 Layer, PbS 0.8 Te 0.2 Layer, CdS layer, CdSe layer, CdTe layer, CdS 0.8 Se 0.2 Layer, CdS 0.8 Te 0.2 BiSe layer, BiTe layer, BiS 0.8 Se 0.2 Layer, BiS 0.8 Te 0.2 Layer, Pb 0.9 Bi 0.1 S 0.8 Se 0.2 One or more layers.

[0011] As an improvement to the above technical solution, the second region is provided with a tunneling oxide layer, an N-type doped polysilicon layer, a passivation layer and an N-type electrode stacked sequentially.

[0012] As an improvement to the above technical solution, the first intrinsic silicon film layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer.

[0013] As an improvement to the above technical solution, along the first direction, the width of the first region is 100μm~500μm; and / or The width of the second region is 100μm~500μm.

[0014] As an improvement to the above technical solution, the thickness of the N-type doped polycrystalline silicon layer is 50nm~300nm.

[0015] As an improvement to the above technical solution, the second region is provided with a second intrinsic microcrystalline silicon layer, an N-type doped microcrystalline silicon layer, a second TCO layer and an N-type electrode stacked sequentially.

[0016] As an improvement to the above technical solution, the first intrinsic silicon film layer is a first intrinsic microcrystalline silicon layer.

[0017] As an improvement to the above technical solution, the crystallinity of the first intrinsic microcrystalline silicon layer is greater than that of the second intrinsic microcrystalline silicon layer.

[0018] As an improvement to the above technical solution, the crystallinity of the first intrinsic microcrystalline silicon layer is 50%~70%; and / or The crystallinity of the second intrinsic microcrystalline silicon layer is 40%~60%.

[0019] As an improvement to the above technical solution, the refractive index of the first intrinsic microcrystalline silicon layer is greater than that of the second intrinsic microcrystalline silicon layer.

[0020] As an improvement to the above technical solution, the refractive index of the first intrinsic microcrystalline silicon layer is 3.6~4.0; and / or The refractive index of the second intrinsic microcrystalline silicon layer is 3.2~3.6.

[0021] As an improvement to the above technical solution, along the first direction, the width of the first region is 100μm~500μm; and / or The width of the second region is 100μm~500μm.

[0022] As an improvement to the above technical solution, the thickness of the N-type doped microcrystalline silicon layer is 50nm~300nm.

[0023] As an improvement to the above technical solution, an isolation zone is provided between the adjacent first region and second region.

[0024] Accordingly, the present invention also discloses a photovoltaic module, including the aforementioned back contact battery.

[0025] Accordingly, the present invention also discloses a photovoltaic system, including the photovoltaic module described above.

[0026] Implementing this invention has the following beneficial effects: The first region of this invention comprises a first intrinsic silicon film layer, a quantum dot hole transport layer, a first TCO layer, and a P-type electrode, stacked sequentially. The quantum dot hole transport layer absorbs a wide range of the solar spectrum, enabling it to absorb a broader wavelength of sunlight, generate more photogenerated carriers, and improve the photoelectric conversion efficiency of infrared and ultraviolet light. Furthermore, the stacked structure of the first intrinsic silicon film layer and the quantum dot hole transport layer in the first region can significantly reduce recombination losses in the first region and improve the efficiency of the back-contact battery. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a back contact battery provided in another embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0029] like Figure 1 As shown, the present invention provides a back contact battery, including a substrate 100 and a first region 110 and a second region 120 disposed on the back side of the substrate 100, wherein the second region 120 and the first region 110 are alternately disposed along a first direction; The first region 110 is provided with a first intrinsic silicon film layer 210, a quantum dot hole transport layer 310, a first TCO layer 410 and a P-type electrode 510 stacked sequentially.

[0030] The first region 110 of this invention comprises a first intrinsic silicon film layer 210, a quantum dot hole transport layer 310, a first TCO layer 410, and a P-type electrode 510, which are sequentially stacked. The quantum dot hole transport layer 310 absorbs a wide range of solar spectrum, enabling it to absorb a wider wavelength of sunlight, generate more photogenerated carriers, and improve the photoelectric conversion efficiency of infrared and ultraviolet light. Furthermore, the stacked structure of the first intrinsic silicon film layer 210 and the quantum dot hole transport layer 310 in the first region 110 can significantly reduce recombination losses in the first region 110 and improve the efficiency of the back contact battery.

[0031] Optionally, the substrate 100 can be an N-type silicon substrate or a P-type silicon substrate, and the first direction can be the length direction of the substrate 100.

[0032] In one embodiment, the quantum dot hole transport layer 310 is formed by depositing a quantum dot compound on the first intrinsic silicon film layer 210. The crystallinity of the quantum dot compound is 10% to 60%, exemplarily 15%, 20%, 30%, 40%, or 50%, but not limited thereto. If the crystallinity is too low, holes are easily captured and recombine by defects during transport, resulting in reduced hole mobility. The size of the quantum dot compound is 1 nm to 100 nm, exemplarily 20 nm, 40 nm, 50 nm, 60 nm, or 80 nm, but not limited thereto. If the size is too small, holes are easily blocked inside the quantum dot hole transport layer 310; if the size is too large, hole injection is hindered. In a preferred embodiment, the performance of the quantum dot hole transport layer 310 is optimized by synergistic control of the crystallinity and size of the quantum dot compound, ensuring the growth quality and hole transport uniformity of the quantum dot hole transport layer 310.

[0033] In a preferred embodiment, the quantum dot hole transport layer 310 is formed by depositing a quantum dot compound on the first intrinsic silicon film layer 210 using PVD. The conditions for forming the quantum dot hole transport layer 310 include: a vacuum degree of 1×10⁻⁶. -6 Pa ~ 1×10 -5 Pa, argon flow rate 1 cm 3 / min~50cm 3 The sputtering speed is 50W~1000W, and the sputtering time is 3min~60min. Applying the quantum dot hole transport layer 310 to a traditional crystalline silicon solar cell is difficult to achieve stable bonding through simple spin-coating on the silicon surface; surface passivation of the first intrinsic silicon film layer 210 is required. Furthermore, the quantum dot hole transport layer 310 is made of quantum dot compounds, further increasing the difficulty of bonding with silicon. This invention uses PVD deposition of the quantum dot hole transport layer 310 on the first intrinsic silicon film layer 210, solving the problems of dangling bond passivation on the silicon surface and bonding stability with crystalline silicon.

[0034] The performance of the quantum dot hole transport layer 310 is further improved through the synergistic effect of the first intrinsic silicon film layer 210 and the quantum dot hole transport layer 310, thereby reducing the recombination loss of the first region 110. In one embodiment, the crystallinity of the first intrinsic silicon film layer 210 is 50%~70%, exemplarily 52%, 55%, 60%, 62% or 68%, but not limited thereto. Too little crystallinity will lead to an increase in interface state density and a decrease in hole mobility of the quantum dot hole transport layer 310; too much crystallinity will cause a decrease in the growth quality of the quantum dot hole transport layer 310. The refractive index of the first intrinsic silicon film layer 210 is 3.5~3.9, exemplarily 3.55, 3.6, 3.7, 3.75 or 3.8, but not limited thereto. Matching the refractive index reduces interface reflection loss.

[0035] In one embodiment, the thickness of the first intrinsic silicon film layer 210 is 1nm to 20nm, exemplarily 5nm, 8nm, 10nm, 14nm, or 18nm, but not limited to these. If the thickness is too small, the passivation effect is poor; if the thickness is too large, dangling bond saturation may occur, or even passivation failure due to excessive defects. The thickness of the quantum dot hole transport layer 310 is 50nm to 500nm, exemplarily 80nm, 100nm, 200nm, 300nm, or 400nm, but not limited to these. If the thickness is too small, it cannot cover the first intrinsic layer, causing interface leakage; if the thickness is too large, the film layer is prone to growth defects, and it will also cause interface reflection loss.

[0036] Accordingly, the conductivity of the quantum dot hole transport layer 310 is 0.0001 S / cm to 1 S / cm, and the hole mobility of the quantum dot hole transport layer 310 is 100 cm⁻¹. 2 / Vs~500cm 2 / Vs. By adjusting the crystallinity and size of the quantum dot compound, the properties of the first intrinsic silicon film 210, and the thickness of the first intrinsic silicon film 210 and the quantum dot hole transport layer 310, the conductivity and hole mobility of the quantum dot hole transport layer 310 are synergistically improved.

[0037] In one embodiment, the quantum dot hole transport layer 310 is a PbS layer, a PbSe layer, a PbTe layer, or a PbS layer. 0.8 Se 0.2 Layer, PbS 0.8 Te 0.2 Layer, CdS layer, CdSe layer, CdTe layer, CdS 0.8 Se 0.2 Layer, CdS 0.8 Te 0.2 BiSe layer, BiTe layer, BiS 0.8 Se 0.2 Layer, BiS 0.8 Te 0.2 Layer, Pb 0.9 Bi 0.1 S 0.8 Se 0.2 One or more layers.

[0038] While defining the structure of the first region 110, the structure of the second region 120 can have various options. In one embodiment, the second region 120 is provided with a tunneling oxide layer 220, an N-type doped polycrystalline silicon layer 320, a passivation layer 420, and an N-type electrode 520 stacked sequentially. That is, the second region 120 has a tunneling passivation structure. Correspondingly, the first intrinsic silicon film layer 210 is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer.

[0039] When the second region 120 has a tunneling passivation structure, in one embodiment, the widths of both the first region 110 and the second region 120 are 100μm to 500μm along the first direction. Preferably, the width of the first region 110 is 100μm to 300μm, and the width of the second region 120 is 300μm to 400μm. A larger width of the first region 110 increases the effective length of the hole transport path, ensuring that holes can fully reach the electrode. By stacking the first intrinsic silicon film layer 210 and the quantum dot hole transport layer 310, the present invention can shorten the width of the first region 110. The passivation contact area ratio of the second region 120 is higher than that of traditional crystalline silicon cells, resulting in a higher overall passivation level, lower recombination loss, and further improved conversion efficiency.

[0040] In one embodiment, the thickness of the quantum dot hole transport layer 310 is 50 nm to 500 nm, and the thickness of the N-type doped polysilicon layer 320 is 50 nm to 300 nm. Preferably, the thickness of the quantum dot hole transport layer 310 is 50 nm to 150 nm, and the thickness of the N-type doped polysilicon layer 320 is 150 nm to 300 nm. The thickness of the quantum dot hole transport layer 310 is smaller than the thickness of the N-type doped polysilicon layer 320. Since the conductivity and hole mobility of the quantum dot hole transport layer 310 are both improved, the thickness of the quantum dot hole transport layer 310 can be reduced accordingly. The N-type doped polysilicon layer 320 typically has a lower refractive index and a smaller light absorption coefficient. A larger thickness of the N-type doped polysilicon layer 320 not only does not increase optical loss but also optimizes light reflection.

[0041] In another implementation, such as Figure 2 As shown, the second region 120 is provided with a second intrinsic microcrystalline silicon 230, an N-type doped microcrystalline silicon layer 330, a second TCO layer 430, and an N-type electrode 520 stacked sequentially. That is, the second region 120 has a heterojunction structure. Correspondingly, the first intrinsic silicon film layer 210 is a first intrinsic microcrystalline silicon layer.

[0042] When the second region 120 has a heterojunction structure, the crystallinity of the first intrinsic microcrystalline silicon layer is greater than that of the second intrinsic microcrystalline silicon layer 230. In one embodiment, the crystallinity of the first intrinsic microcrystalline silicon layer is 50%~70%, and the crystallinity of the intrinsic microcrystalline silicon layer is 40%~60%. By adjusting the crystallinity of the first intrinsic microcrystalline silicon layer and the second intrinsic microcrystalline silicon layer 230, band matching and interface barrier control are achieved, which is beneficial for carrier transport.

[0043] The refractive index of the first intrinsic microcrystalline silicon layer is greater than that of the second intrinsic microcrystalline silicon 230 layer. In one embodiment, the refractive index of the first intrinsic microcrystalline silicon layer is 3.6~4.0. The refractive index of the intrinsic microcrystalline silicon layer is 3.2~3.6. By adjusting the refractive indices of the first intrinsic microcrystalline silicon layer and the second intrinsic microcrystalline silicon 230 layer, the refractive indices of the quantum dot hole transport layer 310 and the N-type doped microcrystalline silicon layer 330 are matched, reducing optical loss and improving the efficiency of the back contact cell. It is understood that the thickness of the second intrinsic microcrystalline silicon 230 layer may be the same as or different from the thickness of the first intrinsic microcrystalline silicon layer.

[0044] Furthermore, the first TCO layer 410 and the second TCO layer 430 may be the same or different. The materials of the first TCO layer 410 and the second TCO layer 430 may be ITO, FTO, AZO, IZO, etc., but are not limited to these. The thickness of the first TCO layer 410 may be 20nm~200nm, and the thickness of the second TCO layer 430 may be 20nm~200nm.

[0045] In one embodiment, along the first direction, the widths of both the first region 110 and the second region 120 are 100 μm to 500 μm. Preferably, the width of the first region 110 is 100 μm to 250 μm, and the width of the second region 120 is 250 μm to 500 μm. In one embodiment, the thickness of the quantum dot hole transport layer 310 is 50 nm to 500 nm, and the thickness of the N-type doped microcrystalline silicon layer 330 is 50 nm to 300 nm. Preferably, the thickness of the quantum dot hole transport layer 310 is 50 nm to 150 nm, and the thickness of the N-type doped microcrystalline silicon layer 330 is 150 nm to 300 nm.

[0046] Furthermore, in one embodiment, an isolation zone 130 is provided between adjacent first region 110 and second region 120. The isolation zone 130 can prevent the first region 110 and second region 120 from coming into contact and causing a short circuit.

[0047] Optionally, the front side of the back contact cell can be the same as or different from that of a conventional crystalline silicon cell. In one embodiment, the front side of the substrate 100 has a pyramidal textured structure, and the front side of the back contact cell is also provided with a front passivation layer. The front passivation layer can be one or more of aluminum oxide, silicon nitride, silicon oxide, and silicon oxynitride, but is not limited thereto.

[0048] Accordingly, this invention also provides a photovoltaic module, including the aforementioned back-contact cells. The back-contact cells can form a cell string layer through solder ribbons, insulating layers, and busbars. The photovoltaic module may include the cell string layer, a frame, a cover plate, and an encapsulant film. The encapsulant film can be filled between the cell string layer and the backplate and / or the cover plate. As a filler, the encapsulant film can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulant film can be EVA film or POE film, and the specific choice can be made according to the actual situation, without limitation.

[0049] A cover plate can be placed over the front of the battery string layer. The cover plate can be made of ultra-clear glass, which has high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the back contact batteries while minimizing impact on their efficiency. Simultaneously, an adhesive film bonds the cover plate and the battery string layer together, providing sealing, insulation, and waterproofing / moisture protection for the battery string layer.

[0050] The backplate can be attached to the back of the battery string layer. The backplate can protect and support the battery string layer, and has reliable insulation, water resistance and aging resistance. There are multiple options for the backplate, which can usually be tempered glass, plexiglass, aluminum alloy TPT composite film, etc. The specific choice can be set according to the specific situation, and there are no restrictions here.

[0051] The backsheet, battery string layer, encapsulant film, and cover plate can be installed on the frame. The frame serves as the main external support structure for the entire photovoltaic module and can provide stable support and installation for the photovoltaic module.

[0052] Accordingly, this invention also provides a photovoltaic system, including the aforementioned photovoltaic modules. In this invention, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants, and can also be applied to equipment or devices that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0053] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a back contact battery, including a substrate and a first region and a second region disposed on the back side of the substrate, wherein the first region and the second region are alternately disposed along a first direction.

[0054] The first region comprises a first intrinsic microcrystalline silicon layer, a quantum dot hole transport layer, a first TCO layer, and a P-type electrode, which are stacked sequentially. The first intrinsic microcrystalline silicon layer has a crystallinity of 62%, a refractive index of 3.8, and a thickness of 20 nm. The quantum dot hole transport layer is a PbS layer with a crystallinity of 32% and a size of 25 nm. The thickness of the quantum dot hole transport layer is 300 nm. The thickness of the first TCO layer is 100 nm.

[0055] The second region is provided with a tunneling oxide layer, an N-type doped polysilicon layer, a passivation layer and an N-type electrode stacked in sequence.

[0056] Along the first direction, the width of both the first and second regions is 250 μm, and the thickness of both the quantum dot hole transport layer and the N-type doped polysilicon layer is 200 nm.

[0057] Example 2 This embodiment provides a back contact battery, which differs from Embodiment 1 in that the crystallinity of the first intrinsic microcrystalline silicon layer is 68% and the refractive index is 3.85.

[0058] Everything else is the same as in Example 1.

[0059] Example 3 This embodiment provides a back-contact battery, which differs from Embodiment 1 in that the second region is provided with a second intrinsic microcrystalline silicon layer, an N-type doped microcrystalline silicon layer, a second TCO layer, and an N-type electrode stacked sequentially. The second intrinsic microcrystalline silicon layer has a crystallinity of 61%, a refractive index of 3.76, and a thickness of 20 nm.

[0060] Along the first direction, the width of both the first and second regions is 350 μm, and the thickness of both the quantum dot hole transport layer and the N-type doped polysilicon layer is 205 nm.

[0061] Everything else is the same as in Example 1.

[0062] Example 4 This embodiment provides a back contact battery, which differs from Embodiment 3 in that the crystallinity of the first intrinsic microcrystalline silicon layer is 65% and the refractive index is 3.9.

[0063] Everything else is the same as in Example 3.

[0064] Comparative Example 1 This embodiment provides a back contact battery, which differs from Embodiment 1 in that a tunneling oxide layer, a P-type doped polycrystalline silicon layer, a passivation layer, and a P-type electrode are sequentially stacked on the first region.

[0065] Everything else is the same as in Example 1.

[0066] Comparative Example 2 This embodiment provides a back contact battery, which differs from Embodiment 3 in that the first region is provided with a first intrinsic microcrystalline silicon, a P-type doped microcrystalline silicon layer, a first TCO layer and a P-type electrode stacked sequentially.

[0067] Everything else is the same as in Example 3.

[0068] The back contact batteries provided in Examples 1-4, Comparative Example 1, and Comparative Example 2 were tested, and the specific results are as follows:

[0069] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A back-contact battery, characterized in that, It includes a substrate and a first region and a second region disposed on the back side of the substrate, wherein the first region and the second region are alternately disposed along a first direction; The first region is provided with a first intrinsic silicon film layer, a quantum dot hole transport layer, a first TCO layer and a P-type electrode stacked in sequence.

2. The back contact battery as described in claim 1, characterized in that, The quantum dot hole transport layer is formed by depositing a quantum dot compound on the first intrinsic silicon film layer. The quantum dot compound has a crystallinity of 10% to 60% and a size of 1 nm to 100 nm.

3. The back contact battery as described in claim 2, characterized in that, The quantum dot hole transport layer is formed by depositing a quantum dot compound on the first intrinsic silicon film layer using PVD. The conditions for forming the quantum dot hole transport layer include: a vacuum degree of 1×10⁻⁶. -6 Pa ~ 1×10 -5 Pa, argon flow rate 1 cm 3 / min~50cm 3 Sputtering speed: 50W~1000W; sputtering time: 3min~60min.

4. The back contact battery as described in claim 1, characterized in that, The crystallinity of the first intrinsic silicon film layer is 40%~70%; and / or The refractive index of the first intrinsic silicon film layer is 3.0~4.

0.

5. The back contact battery as described in claim 1, characterized in that, The thickness of the first intrinsic silicon film layer is 1 nm to 50 nm; and / or The thickness of the quantum dot hole transport layer is 50nm~500nm.

6. The back contact battery as described in claim 1, characterized in that, The hole mobility of the quantum dot hole transport layer is 100 cm⁻¹ 2 / Vs~500cm 2 / Vs, conductivity 10 -4 S / cm ~ 1S / cm.

7. The back contact battery as described in claim 1, characterized in that, The quantum dot hole transport layer is a PbS layer, a PbSe layer, a PbTe layer, and a PbS layer. 0.8 Se 0.2 Layer, PbS 0.8 Te 0.2 Layer, CdS layer, CdSe layer, CdTe layer, CdS 0.8 Se 0.2 Layer, CdS 0.8 Te 0.2 BiSe layer, BiTe layer, BiS 0.8 Se 0.2 Layer, BiS 0.8 Te 0.2 Layer, Pb 0.9 Bi 0.1 S 0.8 Se 0.2 One or more layers.

8. The back contact battery as described in any one of claims 1 to 7, characterized in that, The second region is provided with a tunneling oxide layer, an N-type doped polysilicon layer, a passivation layer and an N-type electrode stacked sequentially.

9. The back contact battery as described in claim 8, characterized in that, The first intrinsic silicon film layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer.

10. The back contact battery as described in claim 8, characterized in that, Along the first direction, the width of the first region is 100μm~500μm; and / or The width of the second region is 100μm~500μm.

11. The back contact battery as described in claim 8, characterized in that, The thickness of the N-type doped polycrystalline silicon layer is 50 nm to 300 nm.

12. The back contact battery according to any one of claims 1 to 7, characterized in that, The second region is provided with a second intrinsic microcrystalline silicon layer, an N-type doped microcrystalline silicon layer, a second TCO layer and an N-type electrode stacked sequentially.

13. The back contact battery as described in claim 12, characterized in that, The first intrinsic silicon film layer is a first intrinsic microcrystalline silicon layer.

14. The back contact battery as described in claim 13, characterized in that, The crystallinity of the first intrinsic microcrystalline silicon layer is greater than that of the second intrinsic microcrystalline silicon layer.

15. The back contact battery as described in claim 14, characterized in that, The crystallinity of the first intrinsic microcrystalline silicon layer is 50%~70%; and / or The crystallinity of the second intrinsic microcrystalline silicon layer is 40%~60%.

16. The back contact battery as described in claim 13, characterized in that, The refractive index of the first intrinsic microcrystalline silicon layer is greater than that of the second intrinsic microcrystalline silicon layer.

17. The back contact battery as described in claim 16, characterized in that, The refractive index of the first intrinsic microcrystalline silicon layer is 3.6~4.0; and / or The refractive index of the second intrinsic microcrystalline silicon layer is 3.2~3.

6.

18. The back contact battery as described in claim 17, characterized in that, Along the first direction, the width of the first region is 100μm~500μm; and / or The width of the second region is 100μm~500μm.

19. The back contact battery as described in claim 12, characterized in that, The thickness of the N-type doped microcrystalline silicon layer is 50 nm to 300 nm.

20. The back contact battery as claimed in claim 1, characterized in that, An isolation zone is provided between the adjacent first and second regions.

21. A photovoltaic module, characterized in that, Including the back contact battery as described in any one of claims 1 to 20.

22. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 21.

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