Apparatus and method for manufacturing display panel and electronic device including display panel

Abstract

An apparatus for manufacturing a display panel, a method for manufacturing a display panel, and an electronic device including a display panel are provided. The apparatus for manufacturing a display panel can include a deposition source and a deposition mask including a plurality of openings corresponding to a plurality of emission areas of the display panel, and at least some of the plurality of openings in the deposition mask can have a second shape corresponding to a first shape obtained by overlapping the plurality of emission areas with each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0172771, filed on November 27, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to apparatus and methods for manufacturing a display panel, and electronic devices including the display panel. Background Technology

[0004] A display panel can provide an image through multiple pixels. Pixels may include light-emitting diodes with an emission layer. The pixels of a display panel can be implemented by arranging one or more suitable layers, including the emission layer, on a substrate. These layers (e.g., emission layers) can be formed into a deposition pattern by depositing a deposition material on the substrate. To generate this deposition pattern (for these suitable layers on the substrate, e.g., to achieve the deposition pattern), a deposition mask can be used.

[0005] A deposition mask can be arranged with one surface facing the substrate, and deposition material can be sprayed toward both the deposition mask and the substrate. The deposition material passes through openings provided in the deposition mask and is deposited on the substrate, forming a pattern that matches the shape of the openings in the deposition mask. The pattern of the deposited material (e.g., the deposited material deposited on the substrate and having the shape of the openings in the deposition mask) is called a deposition pattern. Summary of the Invention

[0006] One or more embodiments of this disclosure relate to apparatus for manufacturing a display panel comprising a plurality of emitting regions. For example, regions in which light-emitting diodes of the display panel emit light (e.g., emitting regions) can be provided with one or more suitable shapes. To achieve these emitting regions of one or more suitable shapes, emitting layers of one or more suitable shapes can be disposed on a substrate. To arrange the emitting layers of one or more suitable shapes, it may be desirable or required that the deposition mask have one or more openings of suitable shapes. Achieving openings of different shapes in the deposition mask may reduce the production efficiency of the deposition mask and / or the accuracy of the deposition process.

[0007] For example, aspects of one or more embodiments may focus on an apparatus for manufacturing a display panel having multiple emitting regions. These regions where the light-emitting diodes emit light can have various shapes. To achieve these shapes, the emitting layer is arranged on a substrate using a deposition mask with openings of different shapes. However, having openings of different shapes in the deposition mask may reduce the productivity and accuracy of the deposition process.

[0008] Additional aspects of one or more embodiments of this disclosure will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the embodiments presented in this disclosure.

[0009] According to one or more embodiments, the apparatus includes a deposition source and a deposition mask, the deposition mask including a plurality of openings corresponding to a plurality of emission regions of a display panel, wherein at least some of the plurality of openings in the deposition mask have a second shape corresponding to a first shape obtained by overlapping the plurality of emission regions with each other. This apparatus is for manufacturing a display panel.

[0010] In one or more embodiments, a first shape can be obtained by connecting at least some of the outermost portions of a plurality of overlapping emission regions.

[0011] In one or more embodiments, the shape of at least one of the plurality of emission regions may be different from the shape of another emission region among the plurality of emission regions.

[0012] In one or more embodiments, a first shape can be obtained by aligning the centers of multiple emission regions and overlapping the multiple emission regions.

[0013] In one or more embodiments, the shapes of the multiple openings in the deposition mask may be identical to each other.

[0014] In one or more embodiments, the size of the second shape may be larger than the size of the first shape.

[0015] In one or more embodiments, the first shape and the second shape may be geometrically identical, and the outer dimensions of the second shape may be larger than those of the first shape.

[0016] In one or more embodiments, in a plan view, the edge of each of the plurality of openings in the deposition mask (e.g., the plurality of openings in the deposition mask) may be spaced apart and / or separated (e.g., separated or separated) from the contour of each of the plurality of emission regions.

[0017] In one or more embodiments, the multiple emission regions may have an elliptical shape having a major axis extending in different directions from each other (e.g., the multiple emission regions may have an elliptical shape, each having a major axis extending in different directions from each other).

[0018] According to one or more embodiments, the method includes: arranging a pixel defining layer including a plurality of emission regions on a substrate; arranging a deposition mask including a plurality of openings corresponding to the plurality of emission regions on the pixel defining layer; and spraying a deposition material toward the deposition mask and the pixel defining layer, wherein at least some of the plurality of deposition masks have a second shape corresponding to a first shape obtained by overlapping the plurality of emission regions. This method is for manufacturing a display panel.

[0019] In one or more embodiments, a first shape can be obtained by connecting at least some of the outermost portions of a plurality of overlapping emission regions.

[0020] In one or more embodiments, the shape of at least one of the plurality of emission regions may be different from the shape of another emission region among the plurality of emission regions.

[0021] In one or more embodiments, a first shape can be obtained by aligning the centers of multiple emission regions and overlapping the multiple emission regions.

[0022] In one or more embodiments, the shapes of the multiple openings in the deposition mask may be identical to each other.

[0023] In one or more embodiments, the size of the second shape may be larger than the size of the first shape.

[0024] In one or more embodiments, the first shape and the second shape may be geometrically identical, and the outer dimensions of the second shape may be larger than those of the first shape.

[0025] In one or more embodiments, the pixel defining layer may include a plurality of holes defining a plurality of emission regions, and if viewed in the direction of ejecting deposited material (e.g., when viewed in the direction of ejecting deposited material), the edge of each of the plurality of openings in the deposition mask is spaced apart and / or separated (e.g., separated or separated) from the edge of each of the plurality of holes in the pixel defining layer.

[0026] In one or more embodiments, the multiple emission regions may have an elliptical shape having a major axis extending in different directions from each other (e.g., the multiple emission regions may have an elliptical shape, each having a major axis extending in different directions from each other).

[0027] According to one or more embodiments, a display panel includes: a substrate; a plurality of pixel electrodes disposed on the substrate; a pixel defining layer disposed on the plurality of pixel electrodes and including a plurality of holes defining a plurality of emission regions; an intermediate layer overlapping the plurality of holes, disposed on the pixel defining layer and including a plurality of deposition patterns, each of the plurality of deposition patterns having a portion disposed within a corresponding hole in the plurality of holes; and a counter electrode disposed on the intermediate layer, wherein, in a plan view, at least some of the plurality of deposition patterns have a second shape corresponding to a first shape obtained by overlapping the plurality of holes.

[0028] In one or more embodiments, the shape of at least one of the plurality of holes may be different from the shape of another of the plurality of holes.

[0029] In one or more embodiments, a first shape can be obtained by aligning the centers of multiple holes and overlapping the multiple holes.

[0030] In one or more embodiments, the size of the second shape may be larger than the size of the first shape.

[0031] In one or more embodiments, the first shape and the second shape may be geometrically identical, and the outer dimensions of the second shape may be larger than those of the first shape.

[0032] In one or more embodiments, one of the multiple deposition patterns may have a first portion at a corresponding hole in the pixel-defining layer (e.g., disposed in the corresponding hole) and a second portion on the top surface of the pixel-defining layer (e.g., disposed on the top surface).

[0033] In one or more embodiments, a first portion of a deposition pattern may be connected to a second portion of a deposition pattern.

[0034] According to one or more embodiments, an electronic device (e.g., an apparatus) includes a display panel comprising a plurality of emitting regions, wherein the display panel includes: a substrate; a plurality of pixel electrodes disposed on the substrate; a pixel defining layer disposed on the plurality of pixel electrodes and including a plurality of holes defining the plurality of emitting regions; an intermediate layer overlapping the plurality of holes, disposed on the pixel defining layer and including a plurality of deposition patterns, each of the plurality of deposition patterns having a portion disposed within a corresponding hole in the plurality of holes; and a counter electrode disposed on the intermediate layer, wherein, in a plan view, at least some of the plurality of deposition patterns have a second shape corresponding to a first shape obtained by overlapping the plurality of holes. Attached Figure Description

[0035] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram of an electronic device according to one or more embodiments; Figure 2 , Figure 3 and Figure 4 Each is a schematic diagram illustrating an electronic device according to one or more embodiments; Figure 5 It is a schematic plan view of a display panel according to one or more embodiments; Figure 6A , Figure 6B and Figure 6C Each is an equivalent circuit diagram of the pixels of a display panel according to one or more embodiments; Figure 7 It is a cross-sectional view of a display panel according to one or more embodiments; Figure 8A It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 8B It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 9A It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 9B It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 10A It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 10B It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 11A It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 11B It is a plan view showing a portion of a display panel according to one or more embodiments; Figure 12 This is a cross-sectional view showing a display panel manufacturing apparatus according to one or more embodiments; Figure 13 This is an exploded perspective view showing a deposition mask according to one or more embodiments; Figure 14A , Figure 15A and Figure 16A Each is a schematic diagram of a launch area according to one or more embodiments; Figure 14B , Figure 14C and Figure 14D These are schematic diagrams showing a first shape and a second shape according to one or more embodiments; Figure 15B , Figure 15C and Figure 15D These are schematic diagrams showing a first shape and a second shape according to one or more embodiments; and Figure 16B , Figure 16C and Figure 16D These are schematic diagrams showing a first shape and a second shape according to one or more embodiments. Detailed Implementation

[0036] Reference will now be made in more detail to one or more embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals denote the same elements throughout and their repeated description may not be provided in the specification. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, one or more embodiments are described in more detail only with reference to the accompanying drawings to explain various aspects of this specification.

[0037] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their description will not be repeated. Furthermore, portions unrelated to the description of one or more embodiments may be omitted for clarity.

[0038] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity. Furthermore, crosshairs and / or shading are typically used in the drawings to clarify boundaries between adjacent elements. Therefore, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or attributes of the elements, unless otherwise stated.

[0039] This document describes one or more suitable embodiments with reference to cross-sectional views that serve as schematic diagrams of implementations and / or intermediate structures. Therefore, variations in the shapes shown in the illustrations will be expected due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but rather include deviations in shape due to factors such as manufacturing processes.

[0040] For example, an implantation region shown as rectangular may have a rounded or curved shape and / or a gradient of implantation concentration at its edges, rather than a binary change from an implantation region to a non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the area between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the regions of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in one or more suitable different ways, all without departing from the spirit and scope of this disclosure and its equivalents.

[0041] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of one or more suitable embodiments. However, it will be apparent that one or more suitable embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring one or more suitable embodiments.

[0042] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element and another(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements will be oriented “above” other elements. Thus, the exemplary terms “below” and “below” can encompass both the orientations above and below. The device may have other orientations (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, if a first part is described as being arranged “on” a second part (e.g., when the first part is described as being arranged “on” a second part), this means that the first part is arranged on the upper or lower side of the second part, and not limited to its upper side based on the direction of gravity.

[0043] Furthermore, in this specification, the phrase "in a plane" or "in a plan view" means the target portion viewed from the top, while the phrase "in a cross section" means the cross section formed by vertically cutting the target portion viewed from the side.

[0044] For the purposes of this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” following a list of elements modify the entire list of elements, rather than individual elements within the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as: only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, XZ, and YZ, or any variation thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Furthermore, the expression “at least one of A and B” means A, B, or A and B.

[0045] Furthermore, when describing embodiments of this disclosure, the use of "may" refers to "one or more embodiments of this disclosure".

[0046] The same reference numerals denote the same components. Furthermore, in the drawings, the thickness, proportions, and dimensions of the components are exaggerated for the purpose of effectively describing the technical content. The expression "and / or" includes one or more combinations that the associated components can define.

[0047] One or more suitable modifications may be applied to this embodiment, and specific embodiments will be shown in the accompanying drawings and described in the detailed description section. The effects and features of this disclosure, as well as methods of implementing it, will become clearer with reference to the detailed description and the accompanying drawings. However, this embodiment may be implemented in one or more suitable forms, and is not limited to the one or more embodiments presented.

[0048] In the following description, one or more embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding components are indicated by the same reference numerals, and redundant descriptions thereof are not provided.

[0049] In the following embodiments, it will be understood that if a component such as a layer, film, region, or plate is referred to as "formed" "on" another layer, film, region, or plate (e.g., when a component such as a layer, film, region, or plate is referred to as "formed" "on" another layer, film, region, or plate), then it can be formed directly or indirectly on said other layer, film, region, or plate. For example, intermediate layers, films, regions, or plates may be present. Furthermore, for ease of explanation, the dimensions of the components in the figures may be exaggerated or reduced. For example, because the dimensions and thicknesses of the components in the figures are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto. It will be understood that although the terms "first," "second," etc., may be used herein to describe one or more suitable components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the proper scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Singular expressions include plural expressions unless otherwise clearly indicated in the context.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0051] In the following embodiments, the expression "x-direction" can refer to both the +x and -x directions, i.e., the ±x direction. In the following embodiments, the expression "y-direction" can refer to both the +y and -y directions (e.g., both +y and -y directions simultaneously), i.e., the ±y direction. In the following embodiments, the expression "z-direction" can refer to both the +z and -z directions (e.g., both +z and -z directions simultaneously), i.e., the ±z direction. In the following embodiments, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, the second direction, and / or the third direction.

[0052] In this disclosure, it will be understood that the terms "comprising / including / including," "containing / including / including," or "having / owning / with" specify the presence of the stated feature, integral, quantity, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, quantities, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms "comprising / including / including," "containing / including / including," or "having / owning / with," or similar terms include or support the terms "consisting of" and "substantially consisting of," indicating the presence of the stated feature, integral, step, operation, element, and / or component, without excluding or substantially not excluding the presence or addition of other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0053] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes the value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. When one or more embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of the described sequence.

[0054] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges with the same numerical precision contained within said range. For example, the range “1.0 to 10.0” is intended to include all subranges between (and inclusive of) said minimum value 1.0 and said maximum value 10.0, such as having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0055] Unless otherwise specified, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted as having an overly ideal or formal meaning unless expressly defined herein.

[0056] It will be understood that if a component (e.g., element, region, layer, part, section, area, etc.) is referred to as being "on", "formed" on, "set" on, "connected" to, "connected" to, or "attached" to another component (e.g., when a component (e.g., element, region, layer, part, section, area, etc.) is referred to as being "on", "formed" on, "set" on, "connected" to, "connected" to, or "attached" to, another component), then this means that the component can be directly on, directly formed on, directly set on, directly connected to, directly connected to, or directly attached to the other component, or indirectly on, indirectly formed on, indirectly set on, indirectly connected to, or indirectly attached to the other component, such that one or more intermediary components can exist between them. For example, when an element, layer, component, part, region, or assembly is referred to as "electrically connected" or "electrically coupled" to another element, layer, component, part, region, or assembly, it can be directly electrically connected or directly coupled to said other element, layer, component, part, region, or assembly, or there may be intervening elements, layers, components, parts, regions, or assemblies. However, "direct connection / direct coupling" means that one component is directly connected or directly coupled to another component without any intermediate components. On the other hand, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent to," and "directly adjacent to," can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between those two elements or layers, or there may be one or more intervening elements or layers.

[0057] A display panel / device according to one or more embodiments can be applied to one or more suitable electronic devices / equipment. For example, an electronic device according to one or more embodiments may include a display device, and in addition to the display device, may also include modules or devices, each with additional functions. A display device according to one or more embodiments may include a display panel.

[0058] Figure 1 This is a block diagram of an electronic device according to one or more embodiments. (Reference) Figure 1 The electronic device 10 may include a display panel 11, a processor 12, a memory 13, and a power module 14.

[0059] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In one or more embodiments, processor 12 may be divided and provided as two or more parts from a functional or structural perspective. For example, processor 12 may include a main processor having a first driver chip in the form of a CPU and an auxiliary processor having a second driver chip in the form of a controller that receives image signals from the main processor and processes the image signals to match the interface specifications of display panel 11.

[0060] The memory 13 may include at least one of non-volatile memory and volatile memory. The memory 13 may store data information required for the operation of the processor 12 or the display panel 11. If the processor 12 executes an application stored in the memory 13 (e.g., when the processor 12 executes an application stored in the memory 13), image data signals and / or input control signals may be transmitted to the display panel 11, and the display panel 11 may process the received signals and output image information through the display screen.

[0061] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10. The power conversion performed by the power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and / or DC-AC conversion.

[0062] The electronic device 10 may also include an input module 15, a non-image output module 16, and / or a communication module 17.

[0063] Input module 15 can provide input information to processor 12 and / or display panel 11. Input module 15 may include physical buttons, keyboard, microphone and / or one or more suitable sensor modules. Examples of sensor modules may include touch sensors, pressure sensors, distance sensors, position sensors, digitizers, motion recognition sensors, camera sensors, light receiving sensors, photoelectric conversion sensors, temperature sensors and / or biometric sensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors and / or heart rate sensors.

[0064] The non-image output module 16 can receive information other than the image received from the processor 12 and provide that information to the user. Examples of the non-image output module 16 may include an audio module, a haptic module, and / or a light-emitting module, and may include other functional modules that are unique to the electronic device 10 (e.g., a cooling module for a refrigerator).

[0065] The communication module 17 is responsible for sending and receiving information between the electronic device 10 and external devices, and may include a receiver and a transmitter. The communication module 17 may include one or more suitable wireless communication modules such as a mobile communication module, a Wi-Fi module, and a Bluetooth module, and / or one or more suitable wired communication modules.

[0066] In one or more embodiments, at least one of the components of the electronic device 10 may be included in the display device. Furthermore, some of the individual modules included in a single module may be functionally included in the display device, while other modules (e.g., other individual modules not included in the display device) may be provided separately from the display device. For example, the display device may include a display panel 11, while the processor 12, memory 13, and power module 14 may be provided as components within the electronic device 10 but not within the display device. In some embodiments, the power module 14 may be disposed within the display device and may supply power to the processor 12 and memory 13 disposed within the electronic device 10 but not within the display device, and this disclosure is not limited to these examples.

[0067] Figures 2 to 4 Each of these is a schematic diagram illustrating an electronic device according to one or more embodiments. Figures 2 to 4 Each illustrates an example of one or more suitable electronic devices that apply a display device according to one or more embodiments.

[0068] Figure 2 Examples of electronic devices shown are a smartphone 10_1a, a tablet computer 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0069] In addition to the display panel, the smartphone 10_1a may also include an input module and / or a communication module, such as a touch sensor. The smartphone 10_1a can process information received through the communication module or other input modules and display that information through the display panel of the display device.

[0070] Similar to the smartphone 10_1a, the tablet computer 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e may include a display panel and an input module, and in some cases, may also include a communication module.

[0071] Figure 3 This illustration shows an application of an electronic device, including a display panel, in a wearable electronic device. The wearable electronic device may include smart glasses 10_2a, a head-mounted display 10_2b, and a smartwatch 10_2c.

[0072] The smart glasses 10_2a and the head-mounted display 10_2b may include a display panel for displaying images and a reflector for reflecting the displayed screen and providing it to the user's eyes, thereby providing a virtual reality and / or augmented reality screen to the user.

[0073] The smartwatch 10_2c may include a biometric sensor as an input device and can provide the user with biometric information identified by the biometric sensor through a display panel.

[0074] Figure 4 The illustration shows an application of electronic devices, including a display panel, in a vehicle. For example, electronic device 10_3 can be applied to the vehicle's dashboard or central instrument panel, or it can be applied to a central information display (CID) arranged on the vehicle's dashboard and / or an interior mirror display that replaces the side mirrors.

[0075] In one or more embodiments, the electronic device using the display device can include not only devices focused on a screen display, such as billboards, electronic billboards, and / or gaming devices, but also one or more suitable household appliances that display information via a display panel, such as refrigerators, washing machines, dryers, air conditioners, and / or robotic vacuum cleaners. Furthermore, if the display panel has the function of transmitting light (e.g., when the display panel has the function of transmitting light), the display panel can be applied to electronic devices such as smart windows and / or transparent display devices that display a background and a displayed image together. The type (variety) of electronic devices according to one or more embodiments is not limited to the examples provided above, and other one or more suitable electronic devices not provided as examples can also be applied.

[0076] Figure 5 It is a schematic plan view of a display panel according to one or more embodiments.

[0077] refer to Figure 5 The display panel 11 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the area for displaying images and is an area where multiple pixels can be arranged. The display area DA may have one or more suitable shapes, such as circular, elliptical, polygonal, and / or specific shapes. For example, Figure 5 The display area DA is shown to have a roughly rectangular shape with rounded corners.

[0078] The peripheral region PA can be arranged outside the display region DA. The peripheral region PA may include a first peripheral region PA1 and a second peripheral region PA2, wherein the first peripheral region PA1 is around (e.g., surrounding) at least a portion of the display region DA, and the second peripheral region PA2 is adjacent to one side of the display region DA and extends in the y-direction. The width of the second peripheral region PA2 in the x-direction may be smaller than the width of the display region DA. This structure makes it easier to bend at least a portion of the second peripheral region PA2. In one or more embodiments, the display panel 11 can be bent around (e.g., around) a bending axis that crosses the second peripheral region PA2.

[0079] Figure 5 The shape of the planar surface of the display panel 11 shown may be substantially the same as the shape of the substrate 100 included in the display panel 11. If the display panel 11 includes a display area DA and a peripheral area PA outside the display area DA (e.g., when the display panel 11 includes a display area DA and a peripheral area PA outside the display area DA), then it may substantially mean that the substrate 100 includes the display area DA and the peripheral area PA outside the display area DA, or that the display area DA and the peripheral area PA outside the display area DA are defined on the substrate 100. Hereinafter, for ease of explanation, it is described that the substrate 100 includes the display area DA and the peripheral area PA.

[0080] Substrate 100 may include glass, metal, and / or polymer resin. Substrate 100 may include, for example, polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate. Substrate 100 may have a multilayer structure comprising two layers containing the aforementioned polymer resin and an inorganic layer disposed between the two layers.

[0081] Pixels can be located at the display area DA (e.g., arranged in the display area DA). The display panel 11 can provide an image by light emitted from the pixels (or subpixels).

[0082] In one or more embodiments, each of a pixel may include a plurality of sub-pixels. Sub-pixels may emit different light from each other. In one or more embodiments, a pixel may include a red sub-pixel, a green sub-pixel, and / or a blue sub-pixel. In one or more embodiments, a pixel may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and / or a white sub-pixel. Each of the sub-pixels may include a pixel circuit PC and a light-emitting diode (LED) electrically connected to the pixel circuit PC.

[0083] In one or more embodiments, each of the pixels may include a pixel circuit PC and a light-emitting diode (LED). Multiple pixels emitting different light from each other may be arranged in the display area DA. In one or more embodiments, red pixels, green pixels, and / or blue pixels may be arranged in the display area DA. In one or more embodiments, red pixels, green pixels, blue pixels, and / or white pixels may be arranged in the display area DA.

[0084] In this specification, the term "pixel" may refer to a pixel comprising a plurality of subpixels, each of which includes a light-emitting diode (LED), or may refer to a pixel comprising a single light-emitting diode (LED).

[0085] The pad portion 31, scan driver 32, data driver 33, drive voltage supply wiring 35, common voltage supply wiring 36, and input line 37 may be located at the peripheral area PA (e.g., arranged in the peripheral area PA).

[0086] The scan driver 32 can provide a scan signal to the pixel circuit PC via a scan line SL. The scan line SL can be a gate line connected to the gate of a switching transistor included in the pixel circuit PC. The scan signal can be a gate signal that turns on or off the switching transistor included in the pixel circuit PC. The scan driver 32 can provide an transmit signal to the pixel circuit PC via an transmit line EL. The scan driver 32 can be arranged on both sides (e.g., opposite sides) of the peripheral region PA, with the display region DA between them. Some of the pixel circuit PCs at the display region DA can be electrically connected to the scan driver 32 arranged in the -x direction, and other pixel circuit PCs can be electrically connected to the scan driver 32 in the +x direction. In one or more embodiments, the scan driver 32 can be arranged only on one side of the peripheral region PA.

[0087] The pad portion 31 may be located at the second peripheral region PA2 of the substrate 100 (e.g., disposed within the second peripheral region PA2). The pad portion 31 may be exposed without being covered by an insulating layer and may be electrically connected to the display circuit board 30. The pad portion 34 of the display circuit board 30 may be electrically connected to the pad portion 31 of the display panel 11.

[0088] Display circuit board 30 can transmit control signals to display panel 11. The control signals can be transmitted via display circuit board 30 to scan driver 32 and data driver 33. In one or more embodiments, display circuit board 30 may include a power management integrated circuit (power management IC). The power management IC can provide a first power voltage VDD (see [reference]) to drive voltage supply wiring 35 and common voltage supply wiring 36, respectively. Figure 6A ) and second power voltage VSS (see Figure 6A A first power voltage VDD can be supplied to each of the pixel circuits PC via a drive voltage line PL connected to the drive voltage supply wiring 35, and a second power voltage VSS can be supplied to the opposite electrodes of the light-emitting diodes (LEDs) connected to a common voltage supply wiring 36. The drive voltage supply wiring 35 can extend in the x-direction. The common voltage supply wiring 36 can have a ring shape with one side open and can partially surround the display area DA (e.g., around the display area DA).

[0089] The data signal of the data driver 33 can be transmitted to the pixel circuit PC through the input line 37 and the data line DL electrically connected to the input line 37.

[0090] Figures 6A to 6C Each is an equivalent circuit diagram of the pixels of a display panel according to one or more embodiments.

[0091] refer to Figure 6A A light-emitting diode (LED) corresponding to a pixel can be electrically connected to a pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The pixel circuit PC can be electrically connected to signal lines and voltage lines. The signal lines may include a scan signal line GWL and a data line DL, and the voltage lines may include a first voltage line VDDL.

[0092] The second transistor T2, acting as a data write transistor, can be electrically connected to the scan signal line GWL and the data line DL. The scan signal line GWL can be configured to provide a scan signal GW to the gate electrode of the second transistor T2. The second transistor T2 can be configured to transmit a data signal Dm input from the data line DL to the first transistor T1 based on the scan signal GW input from the scan signal line GWL.

[0093] The storage capacitor Cst can be electrically connected to the second transistor T2 and the first voltage line VDDL, and can store a voltage corresponding to the difference between the voltage received from the second transistor T2 and the first power voltage VDD provided by the first voltage line VDDL.

[0094] A first transistor T1, acting as a driving transistor, can be configured to control the driving current flowing through a light-emitting diode (LED). The first transistor T1 can be connected to a first voltage line VDDL and a storage capacitor Cst. The first transistor T1 can be configured to control the driving current flowing from the first voltage line VDDL to the LED based on the voltage value stored in the storage capacitor Cst. The LED can emit light with a certain brightness depending on the driving current. A first electrode (e.g., a pixel electrode or anode) of the LED can be electrically connected to the first transistor T1, and a second electrode (e.g., a counter electrode or cathode) of the LED can be electrically connected to a second voltage line VSSL that provides a second power voltage VSS.

[0095] Figure 6A The illustration shows a pixel circuit PC including a switching transistor (e.g., a second transistor T2) and a capacitor (e.g., a storage capacitor Cst), but in one or more embodiments, the pixel circuit PC may include two or more switching transistors and / or two or more capacitors.

[0096] refer to Figure 6B The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. The first transistor T1 may be a driving transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may each be a switching transistor.

[0097] The pixel circuit PC can be electrically connected to signal lines and voltage lines. Signal lines may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and emit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a first voltage line VDDL.

[0098] The first voltage line VDDL can be configured to transmit a first power voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to transmit a first initialization voltage Vint to the pixel circuit PC to initialize the first transistor T1. The second initialization voltage line VIL2 can be configured to transmit a second initialization voltage Vaint to the pixel circuit PC to initialize the first electrode (e.g., pixel electrode or anode) of the light-emitting diode LED.

[0099] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting diode LED via the sixth transistor T6. The first transistor T1 can be used as a driving transistor and can be configured to receive the data signal Dm according to the switching operation of the second transistor T2, and to provide driving current to the light-emitting diode LED.

[0100] The second transistor T2, acting as a data write transistor, can be electrically connected to the scan signal line GWL and the data line DL. The second transistor T2 can also be electrically connected to the first voltage line VDDL via the fifth transistor T5. The second transistor T2 can be turned on according to the scan signal GW received through the scan signal line GWL and can be configured to perform a switching operation to transmit the data signal Dm transmitted to the data line DL to the first node N1.

[0101] The third transistor T3 can be electrically connected to the scan signal line GWL, and can be electrically connected to the light-emitting diode (LED) via the sixth transistor T6. The third transistor T3 can be turned on according to the scan signal GW received through the scan signal line GWL, and can be configured as a diode connected to the first transistor T1.

[0102] The fourth transistor T4, serving as the first initialization transistor, can be electrically connected to the initialization control line GIL and the first initialization voltage line VIL1. The fourth transistor T4 can be turned on according to the initialization control signal GI received via the initialization control line GIL, and can be configured to transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate of the first transistor T1, thus initializing the voltage at the gate of the first transistor T1. The initialization control signal GI can correspond to the scan signal of another pixel circuit PC arranged in the row preceding the corresponding pixel circuit PC.

[0103] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emitter control transistor. The fifth transistor T5 and the sixth transistor T6 can be electrically connected to the emitter control line EML, and can be synchronously (e.g., simultaneously) turned on according to the emitter control signal EM received through the emitter control line EML, thereby forming a current path that allows drive current to flow from the first voltage line VDDL to the light-emitting diode LED. The first electrode of the light-emitting diode LED can be electrically connected to the first transistor T1 through the sixth transistor T6, and the second electrode of the light-emitting diode LED can be electrically connected to the second voltage line VSSL that provides the second power voltage VSS.

[0104] The seventh transistor T7, serving as the second initialization transistor, can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on according to the bypass control signal GB received through the bypass control line GBL, and can be configured to transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting diode (LED) and initialize the first electrode of the LED.

[0105] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to the gate of the first transistor T1, and the second capacitor electrode CE2 may be electrically connected to the first voltage line VDDL. The storage capacitor Cst can maintain the voltage applied to the gate of the first transistor T1 by storing and holding a voltage corresponding to the voltage difference between the first voltage line VDDL and the gate of the first transistor T1.

[0106] refer to Figure 6C The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor Cst, and an auxiliary capacitor Ca. The first transistor T1 may be a driving transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may each be a switching transistor.

[0107] The pixel circuit PC can be electrically connected to signal lines and voltage lines. Signal lines may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and emit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, a sustain voltage line VSL, and a first voltage line VDDL.

[0108] The first voltage line VDDL can be configured to transmit a first power voltage VDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to transmit a first initialization voltage Vint to the pixel circuit PC to initialize the first transistor T1. The second initialization voltage line VIL2 can be configured to transmit a second initialization voltage Vaint to the pixel circuit PC to initialize the first electrode of the light-emitting diode LED. The sustaining voltage line VSL can be configured to provide a sustaining voltage VSUS to the second node N2 (e.g., the second capacitor electrode CE2 of the storage capacitor Cst) during the initialization cycle and the data write cycle.

[0109] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8, and can be electrically connected to the light-emitting diode LED via the sixth transistor T6. The first transistor T1 can be used as a driving transistor and can be configured to receive the data signal Dm according to the switching operation of the second transistor T2, and to provide driving current to the light-emitting diode LED.

[0110] The second transistor T2 can be electrically connected to the scan signal line GWL and the data line DL, and can be electrically connected to the first voltage line VDDL via the fifth transistor T5 and the eighth transistor T8. The second transistor T2 can be turned on according to the scan signal GW received through the scan signal line GWL, and can be configured to perform a switching operation to transmit the data signal Dm transmitted to the data line DL to the first node N1.

[0111] The third transistor T3 can be electrically connected to the scan signal line GWL, and can be electrically connected to the light-emitting diode (LED) via the sixth transistor T6. The third transistor T3 can be turned on according to the scan signal GW received through the scan signal line GWL, and can be configured to compensate the threshold voltage of the first transistor T1 by connecting it to the first transistor T1 via a diode.

[0112] The fourth transistor T4 can be electrically connected to the initialization control line GIL and the first initialization voltage line VIL1, and can be turned on according to the initialization control signal GI received through the initialization control line GIL. It can also be configured to transmit the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate of the first transistor T1, and initialize the voltage at the gate of the first transistor T1. The initialization control signal GI can correspond to the scan signal of another pixel circuit PC arranged in the row preceding the corresponding pixel circuit PC.

[0113] The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can be electrically connected to the emitter control line EML and can be synchronously (e.g., simultaneously) turned on according to the emitter control signal EM received through the emitter control line EML, thereby forming a current path that allows drive current to flow from the first voltage line VDDL to the light-emitting diode LED. The first electrode of the light-emitting diode LED can be electrically connected to the first transistor T1 through the sixth transistor T6, and the second electrode of the light-emitting diode LED can be electrically connected to the second voltage line VSSL that provides the second power voltage VSS.

[0114] The seventh transistor T7, serving as the second initialization transistor, can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. The seventh transistor T7 can be turned on according to the bypass control signal GB received through the bypass control line GBL, and can be configured to transmit the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting diode (LED) and initialize the first electrode of the LED.

[0115] The ninth transistor T9 can be electrically connected to the bypass control line GBL, the second capacitor electrode CE2 of the storage capacitor Cst, and the sustaining voltage line VSL. The ninth transistor T9 can be turned on according to the bypass control signal GB received through the bypass control line GBL, and can be configured to deliver the sustaining voltage VSUS to the second node N2 (e.g., the second capacitor electrode CE2 of the storage capacitor Cst) during the initialization cycle and the data write cycle.

[0116] Each of the eighth transistor T8 and the ninth transistor T9 may be electrically connected to the second node N2 (e.g., the second capacitor electrode CE2 of the storage capacitor Cst). In one or more embodiments, the eighth transistor T8 may be turned off and the ninth transistor T9 may be turned on during the initialization cycle and the data write cycle, and the eighth transistor T8 may be turned on and the ninth transistor T9 may be turned off during the transmit cycle.

[0117] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to the gate of the first transistor T1, and the second capacitor electrode CE2 may be electrically connected to the eighth transistor T8 and the ninth transistor T9.

[0118] An auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustaining voltage line VSL, and the first electrode of the light-emitting diode (LED). When the seventh transistor T7 and the ninth transistor T9 are turned on, the auxiliary capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the first electrode of the LED and the sustaining voltage line VSL, thereby preventing or reducing an increase in black brightness if the sixth transistor T6 is in the off state (e.g., when the sixth transistor T6 is in the off state).

[0119] Figure 7 It is a cross-sectional view of a display panel according to one or more embodiments.

[0120] refer to Figure 7Multiple emission regions EA can be defined on the substrate 100. In one or more embodiments, a first emission region EA1, a second emission region EA2, and a third emission region EA3 can be defined on the substrate 100. The first emission region EA1, the second emission region EA2, and the third emission region EA3 can be spaced apart from each other and / or separated (e.g., separated or apart).

[0121] The display panel 11 may include a plurality of light-emitting diodes (LEDs) corresponding to a plurality of emission regions EA. In one or more embodiments, the display panel 11 may include a first light-emitting diode LED1 corresponding to a first emission region EA1, a second light-emitting diode LED2 corresponding to a second emission region EA2, and a third light-emitting diode LED3 corresponding to a third emission region EA3.

[0122] The display panel 11 may include thin-film transistors (TFTs) corresponding to light-emitting diodes (LEDs). Each of the LEDs may be electrically connected to its corresponding TFT. Figure 7 Each of the thin-film transistors (TFTs) shown can schematically represent a reference. Figures 6A to 6C This describes a portion of the pixel circuitry PC. In one or more embodiments, each thin-film transistor (TFT) may correspond to... Figure 6A The first transistor T1, Figure 6B The first transistor T1 or the sixth transistor T6, or Figure 6C The first transistor T1 or the sixth transistor T6.

[0123] Light can be emitted from the emitting region EA by light emitted from a light-emitting diode (LED). In one or more embodiments, the emitting region EA can emit light by light emitted from a light-emitting diode (LED). In one or more embodiments, the area emitting light from a light-emitting diode (LED) can be understood as the emitting region EA. The display panel 11 can display an image by light emitted from the emitting region EA or the light emitted from the light-emitting diode (LED).

[0124] In one or more embodiments, light of different colors can be emitted from the emitting region EA. In one or more embodiments, the first emitting region EA1 and the first light-emitting diode LED1 can emit red light. In one or more embodiments, the second emitting region EA2 and the second light-emitting diode LED2 can emit green light. In one or more embodiments, the third emitting region EA3 and the third light-emitting diode LED3 can emit blue light.

[0125] A first insulating layer 101 may be disposed on a substrate 100. The first insulating layer 101 may completely or substantially cover the substrate 100. The first insulating layer 101 may be planarized (e.g., is flat) and protect the top surface of the substrate 100. The first insulating layer 101 may comprise an inorganic insulating material. In one or more embodiments, the first insulating layer 101 may comprise materials such as silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), etc. x The first insulating layer 101 may be at least one of the inorganic insulating materials selected from silicon oxynitride (e.g., SiON), aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), and zinc oxide (e.g., ZnO2), and may have a single-layer or multi-layer structure comprising the aforementioned materials. In one or more embodiments, the first insulating layer 101 may be a buffer layer.

[0126] Each thin-film transistor (TFT) can be disposed on the first insulating layer 101. Each TFT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. TFTs corresponding to the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3), respectively, can be disposed on the first insulating layer 101. The structures of the TFTs corresponding to the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) can be similar to each other.

[0127] Semiconductor layer 102 may be disposed on first insulating layer 101. Semiconductor layer 102 may include active layer ACT. Active layer ACT may be patterned to correspond to thin film transistors (TFTs). Active layer ACT may include a drain region overlapping with drain electrode DE, a source region overlapping with source electrode SE, and a channel region between drain region and source region. Drain region and source region may be regions doped with impurities (e.g., dopant).

[0128] The second insulating layer 103 may be disposed on the semiconductor layer 102. The second insulating layer 103 may include an inorganic insulating material. In one or more embodiments, the second insulating layer 103 may include materials such as silicon oxide (e.g., SiO2) or silicon nitride (e.g., SiN). x The second insulating layer 103 may be at least one of the inorganic insulating materials selected from silicon oxynitride (e.g., SiON), aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), and zinc oxide (e.g., ZnO2), and may have a single-layer or multi-layer structure comprising the aforementioned materials. In one or more embodiments, the second insulating layer 103 may be the first gate insulating layer. In one or more embodiments, as... Figure 7As shown, the second insulating layer 103 may completely cover the semiconductor layer 102 and the first insulating layer 101. In one or more embodiments, the second insulating layer 103 may be patterned to cover only each of the active layers ACT, without covering the top surface of the first insulating layer 101 between the active layers ACT. In one or more embodiments, the second insulating layer 103 may be patterned to cover only a portion of each of the active layers ACT (e.g., the region overlapping with the gate electrode GE, such as the channel region).

[0129] Storage capacitors Cst can be disposed on the second insulating layer 103. Each of the storage capacitors Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The second capacitor electrode CE2 may be disposed on the first capacitor electrode CE1.

[0130] A first conductive layer 104 may be disposed on a second insulating layer 103. The first conductive layer 104 may include a gate electrode GE and a first capacitor electrode CE1. The gate electrode GE may be patterned to correspond to a thin-film transistor (TFT). The gate electrode GE may overlap with the channel region of the active layer ACT. The first capacitor electrode CE1 may be patterned to correspond to a storage capacitor Cst. In one or more embodiments, as... Figure 7 As shown, the gate electrode GE and the first capacitor electrode CE1 can be integrally formed into a single body. In one or more embodiments, the gate electrode GE and the first capacitor electrode CE1 can be provided separately. In one or more embodiments, the first conductive layer 104 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer structure or a multi-layer structure comprising the above materials.

[0131] The third insulating layer 105 may be disposed on the first conductive layer 104. The third insulating layer 105 may completely cover the first conductive layer 104. The third insulating layer 105 may include an inorganic insulating material. In one or more embodiments, the third insulating layer 105 may include materials such as silicon oxide (e.g., SiO2) or silicon nitride (e.g., SiN). x The third insulating layer 105 may be at least one of the inorganic insulating materials selected from silicon oxynitride (e.g., SiON), aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), and zinc oxide (e.g., ZnO2), and may have a single-layer or multi-layer structure comprising the aforementioned materials. In one or more embodiments, the third insulating layer 105 may be a second gate insulating layer.

[0132] The second conductive layer 106 may be disposed on the third insulating layer 105. The second conductive layer 106 may include a second capacitor electrode CE2 for each storage capacitor Cst. The second capacitor electrode CE2 may be patterned to correspond to the storage capacitor Cst respectively. The second capacitor electrode CE2 may overlap with the first capacitor electrode CE1. In one or more embodiments, the second conductive layer 106 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer structure or a multi-layer structure including the above materials.

[0133] A fourth insulating layer 107 may be disposed on the second conductive layer 106. The fourth insulating layer 107 may completely or substantially cover the second conductive layer 106. The fourth insulating layer 107 may comprise an inorganic insulating material. In one or more embodiments, the fourth insulating layer 107 may comprise materials such as silicon oxide (e.g., SiO2) or silicon nitride (e.g., SiN). x The fourth insulating layer 107 may be at least one of the inorganic insulating materials selected from silicon oxynitride (e.g., SiON), aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), and zinc oxide (e.g., ZnO2), and may have a single-layer or multi-layer structure comprising the aforementioned materials. In one or more embodiments, the fourth insulating layer 107 may be an interlayer insulating layer.

[0134] A third conductive layer 108 may be disposed on a fourth insulating layer 107. The third conductive layer 108 may include a source electrode SE and a drain electrode DE for each thin-film transistor (TFT). The source electrode SE and drain electrode DE may each be patterned to correspond to a respective one of the TFTs. The source electrode SE may overlap with the source region of the active layer ACT. The drain electrode DE may overlap with the drain region of the active layer ACT. The source electrode SE may be connected to the active layer ACT (e.g., the source region of the active layer ACT) through openings defined in the second insulating layer 103, the third insulating layer 105, and the fourth insulating layer 107. The drain electrode DE may be connected to the active layer ACT (e.g., the drain region of the active layer ACT) through openings defined in the second insulating layer 103, the third insulating layer 105, and the fourth insulating layer 107. In one or more embodiments, the third conductive layer 108 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer structure or a multi-layer structure including the above materials.

[0135] A fifth insulating layer 109 may be disposed on the third conductive layer 108. An opening overlapping the drain electrode DE may be defined in the fifth insulating layer 109. The fifth insulating layer 109 may include an organic insulating material. In one or more embodiments, the fifth insulating layer 109 may include an organic insulating material such as a general polymer (such as benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate and / or polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, and / or a vinyl alcohol-based polymer, and may have a single-layer structure or a multilayer structure including the above materials. In one or more embodiments, the fifth insulating layer 109 may be a first via layer.

[0136] A fourth conductive layer 110 may be disposed on a fifth insulating layer 109. The fourth conductive layer 110 may include contact metals CM corresponding to the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3, respectively. Each of the contact metals CM may be patterned to overlap with the corresponding light-emitting diode LED. Each of the contact metals CM may be connected to a corresponding drain electrode DE through an opening defined in the fifth insulating layer 109. In one or more embodiments, the fourth conductive layer 110 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure comprising the aforementioned materials.

[0137] A sixth insulating layer 111 may be disposed on the fourth conductive layer 110. An opening overlapping each contact metal CM of the fourth conductive layer 110 may be defined in the sixth insulating layer 111. The sixth insulating layer 111 may comprise an organic insulating material. In one or more embodiments, the sixth insulating layer 111 may comprise an organic insulating material including, but is not limited to, general-purpose polymers (such as benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate and / or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers and / or vinyl alcohol-based polymers, and may have a single-layer or multi-layer structure comprising the aforementioned materials. In one or more embodiments, the sixth insulating layer 111 may be a second via layer.

[0138] Multiple light-emitting diodes (LEDs) can be arranged on the sixth insulating layer 111. In one or more embodiments, a first LED (LED1), a second LED (LED2), and a third LED (LED3) can be arranged on the sixth insulating layer 111. Each LED may include a corresponding pixel electrode, an intermediate layer, and a counter electrode. In one or more embodiments, the first LED (LED1) may include a first pixel electrode 113a, a first deposition pattern 114a, and a first counter electrode 115a. In one or more embodiments, the second LED (LED2) may include a second pixel electrode 113b, a second deposition pattern 114b, and a second counter electrode 115b. In one or more embodiments, the third LED (LED3) may include a third pixel electrode 113c, a third deposition pattern 114c, and a third counter electrode 115c. Due to the potential difference between the pixel electrode and the counter electrode, the intermediate layer of each LED can emit light through the current flowing through it, and therefore, each LED can emit light.

[0139] A fifth conductive layer 113 may be disposed on a sixth insulating layer 111. The fifth conductive layer 113 may include a first pixel electrode 113a, a second pixel electrode 113b, and a third pixel electrode 113c. The first pixel electrode 113a, the second pixel electrode 113b, and the third pixel electrode 113c may be individually patterned and spaced apart and / or separated from each other (e.g., separated or isolated). Each of the first pixel electrode 113a, the second pixel electrode 113b, and the third pixel electrode 113c may be connected to a corresponding thin-film transistor (TFT) via a corresponding contact metal CM and a drain electrode DE. In one or more embodiments, the fifth conductive layer 113 may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one or more embodiments, the fifth conductive layer 113 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or compounds thereof. The composition and materials of the fifth conductive layer 113 are not limited thereto, and one or more suitable modifications are possible.

[0140] A pixel defining layer 112 may be disposed on a fifth conductive layer 113 and a sixth insulating layer 111. The pixel defining layer 112 may include a plurality of holes overlapping with a plurality of pixel electrodes of the fifth conductive layer 113. For example, the pixel defining layer 112 may cover the edge (or edge region) of each of the pixel electrodes of the fifth conductive layer 113. In one or more embodiments, the pixel defining layer 112 may include a first hole H1 overlapping with a first pixel electrode 113a. For example, the pixel defining layer 112 may cover the edge (or edge region) of the first pixel electrode 113a. In one or more embodiments, the pixel defining layer 112 may include a second hole H2 overlapping with a second pixel electrode 113b. For example, the pixel defining layer 112 may cover the edge (or edge region) of the second pixel electrode 113b. In one or more embodiments, the pixel defining layer 112 may include a third hole H3 overlapping with a third pixel electrode 113c. For example, the pixel defining layer 112 may cover the edge (or edge region) of the third pixel electrode 113c.

[0141] Intermediate layer 114 may be disposed (e.g., deposited) on pixel defining layer 112 and fifth conductive layer 113. Intermediate layer 114 may include a first deposited pattern 114a, a second deposited pattern 114b and a third deposited pattern 114c.

[0142] In one or more embodiments, the intermediate layer 114 may include an emission layer and a functional layer. The emission layer may include a low molecular weight material and / or a polymeric material that emits light if a specific voltage is applied (e.g., when a specific voltage is applied) (or if a specific current flows (e.g., when a specific current flows)). The functional layer may include at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL). Each of the first deposition pattern 114a, the second deposition pattern 114b, and the third deposition pattern 114c may include an emission layer and a functional layer.

[0143] In one or more embodiments, the emitting layers included in the first deposition pattern 114a, the second deposition pattern 114b, and the third deposition pattern 114c may comprise different materials from each other. For example, the emitting layers included in the first deposition pattern 114a, the second deposition pattern 114b, and the third deposition pattern 114c may emit light of different wavelengths (e.g., colors). In one or more embodiments, if current flows (e.g., when current flows), the emitting layer included in the first deposition pattern 114a may emit red light. In one or more embodiments, if current flows (e.g., when current flows), the emitting layer included in the second deposition pattern 114b may emit green light. In one or more embodiments, if current flows (e.g., when current flows), the emitting layer included in the third deposition pattern 114c may emit blue light.

[0144] The first deposited pattern 114a may overlap with the first pixel electrode 113a. A portion (e.g., a first portion) of the first deposited pattern 114a may be disposed in the first aperture H1 in the pixel defining layer 112 and may contact the first pixel electrode 113a. Another portion (e.g., a second portion) of the first deposited pattern 114a may be disposed on the pixel defining layer 112. The first portion and the second portion of the first deposited pattern 114a may be connected to each other. For example, the first portion of the first deposited pattern 114a may be connected to the second portion of the first deposited pattern 114a. That is, the first deposited pattern 114a may cover the edge defining the first aperture H1 of the pixel defining layer 112.

[0145] The second deposited pattern 114b may overlap with the second pixel electrode 113b. A portion (e.g., a first portion) of the second deposited pattern 114b may be disposed in the second aperture H2 in the pixel defining layer 112 and may contact the second pixel electrode 113b. Another portion (e.g., a second portion) of the second deposited pattern 114b may be disposed on the pixel defining layer 112. The first and second portions of the second deposited pattern 114b may be connected to each other. For example, the first portion of the second deposited pattern 114b may be connected to the second portion of the second deposited pattern 114b. That is, the second deposited pattern 114b may cover the edge defining the second aperture H2 of the pixel defining layer 112. For example, a portion of the second deposited pattern 114b is disposed in the second aperture H2 of the pixel defining layer 112 and contacts the second pixel electrode 113b. Another portion of the second deposited pattern 114b is disposed on the pixel defining layer 112. These portions are connected, and the second deposited pattern 114b covers the edge defining the second aperture H2 of the pixel defining layer 112.

[0146] The third deposition pattern 114c may overlap with the third pixel electrode 113c. A portion (e.g., a first portion) of the third deposition pattern 114c may be disposed in the third aperture H3 in the pixel defining layer 112 and may contact the third pixel electrode 113c. Another portion (e.g., a second portion) of the third deposition pattern 114c may be disposed on the pixel defining layer 112. The first and second portions of the third deposition pattern 114c may be connected to each other. For example, the first portion of the third deposition pattern 114c may be connected to the second portion of the third deposition pattern 114c. That is, the third deposition pattern 114c may cover the edge of the defining third aperture H3 of the pixel defining layer 112. For example, a portion of the third deposition pattern 114c is disposed in the third aperture H3 of the pixel defining layer 112 and contacts the third pixel electrode 113c. Another portion of the third deposition pattern 114c is disposed on the pixel defining layer 112. These portions are connected, and the third deposition pattern 114c covers the edge of the defining third aperture H3 of the pixel defining layer 112.

[0147] A counter electrode 115 may be disposed on an intermediate layer 114. The counter electrode 115 may be integrally formed on the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3. The counter electrode 115 may cover the intermediate layer 114. The portion of the counter electrode 115 that overlaps with the first deposition pattern 114a may be considered the first counter electrode 115a. In one or more embodiments, the first counter electrode 115a may cover the first deposition pattern 114a. The portion of the counter electrode 115 that overlaps with the second deposition pattern 114b may be considered the second counter electrode 115b. In one or more embodiments, the second counter electrode 115b may cover the second deposition pattern 114b. The portion of the counter electrode 115 that overlaps with the third deposition pattern 114c may be considered the third counter electrode 115c. In one or more embodiments, the third counter electrode 115c may cover the third deposition pattern 114c.

[0148] The counter electrode 115 may include a conductive material. In one or more embodiments, the counter electrode 115 may include a transparent layer (or a translucent layer) comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or alloys thereof. In one or more embodiments, the counter electrode 115 may also include a layer on top of the transparent layer (or translucent layer) containing the aforementioned materials, comprising materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium oxide (In2O3).

[0149] Due to the potential difference between the fifth conductive layer 113 and the opposing electrode 115, for example, due to the difference between the voltage applied to the fifth conductive layer 113 and the voltage applied to the opposing electrode 115, the intermediate layer 114 can emit light by the current flowing through the intermediate layer 114. In one or more embodiments, due to the difference between the voltage applied to the first pixel electrode 113a and the voltage applied to the first opposing electrode 115a, the first deposited pattern 114a can emit light by the current flowing through the first deposited pattern 114a. In one or more embodiments, due to the difference between the voltage applied to the second pixel electrode 113b and the voltage applied to the second opposing electrode 115b, the second deposited pattern 114b can emit light by the current flowing through the second deposited pattern 114b. In one or more embodiments, due to the difference between the voltage applied to the third pixel electrode 113c and the voltage applied to the third opposing electrode 115c, the third deposited pattern 114c can emit light by the current flowing through the third deposited pattern 114c. In one or more embodiments, since the first relative electrode 115a, the second relative electrode 115b, and the third relative electrode 115c can be integrally formed into a single body, the same voltage can be applied to the first relative electrode 115a, the second relative electrode 115b, and the third relative electrode 115c.

[0150] For the current flowing through the first deposited pattern 114a due to the potential difference between the first pixel electrode 113a and the first opposing electrode 115a, it is desirable or required that the first deposited pattern 114a contact the first pixel electrode 113a and the first opposing electrode 115a. Because the first deposited pattern 114a can fully or substantially contact the first opposing electrode 115a, current can flow through the first deposited pattern 114a in the region contacting the first pixel electrode 113a. The first deposited pattern 114a can emit light in the region contacting the first pixel electrode 113a. Therefore, the region where the first deposited pattern 114a emits light, the region where the first light-emitting diode LED1 emits light, or the first emission region EA1 can be defined by the region where the first deposited pattern 114a and the first pixel electrode 113a are in contact with each other. In one or more embodiments, because the first deposited pattern 114a can contact the first pixel electrode 113a within the first aperture H1 in the pixel defining layer 112, the region where the first deposited pattern 114a and the first pixel electrode 113a are in contact with each other can be defined by the first aperture H1. Therefore, the first emission region EA1 can be defined by the first aperture H1.

[0151] Because a portion of the first deposition pattern 114a can cover the edge defining the first aperture H1 of the pixel defining layer 112 and can be disposed on the top surface of the pixel defining layer 112, the shape or size of the first deposition pattern 114a can differ from the shape or size of the first aperture H1 (or the first emission region EA1). In one or more embodiments, in a planar view (e.g., if viewed in the z-direction, e.g., when viewed in the z-direction)), the shape or size of the first deposition pattern 114a can differ from the shape or size of the first aperture H1 (or the first emission region EA1). The specific relationship between the planar shape of the first deposition pattern 114a and the planar shape of the first aperture H1 (or the first emission region EA1) will be described in more detail.

[0152] Similarly, for the current flowing through the second deposited pattern 114b due to the potential difference between the second pixel electrode 113b and the second opposing electrode 115b, it is desirable or required that the second deposited pattern 114b contact the second pixel electrode 113b and the second opposing electrode 115b. Because the second deposited pattern 114b can fully or substantially contact the second opposing electrode 115b, current can flow through the second deposited pattern 114b in the region contacting the second pixel electrode 113b. The second deposited pattern 114b can emit light in the region contacting the second pixel electrode 113b. Therefore, the region where the second deposited pattern 114b emits light, the region where the second light-emitting diode LED2 emits light, or the second emission region EA2 can be defined by the region where the second deposited pattern 114b and the second pixel electrode 113b are in contact with each other. In one or more embodiments, because the second deposited pattern 114b can contact the second pixel electrode 113b within the second hole H2 in the pixel defining layer 112, the region where the second deposited pattern 114b and the second pixel electrode 113b are in contact with each other can be defined by the second hole H2. Therefore, the second emission region EA2 can be defined by the second aperture H2.

[0153] Because a portion of the second deposition pattern 114b can cover the edge defining the second aperture H2 of the pixel defining layer 112 and can be disposed on the top surface of the pixel defining layer 112, the shape or size of the second deposition pattern 114b can differ from the shape or size of the second aperture H2 (or the second emission region EA2). In one or more embodiments, in a planar view (e.g., if viewed in the z-direction, e.g., when viewed in the z-direction) the shape or size of the second deposition pattern 114b can differ from the shape or size of the second aperture H2 (or the second emission region EA2). The specific relationship between the planar shape of the second deposition pattern 114b and the planar shape of the second aperture H2 (or the second emission region EA2) will be described in more detail.

[0154] Similarly, for the current flowing through the third deposited pattern 114c due to the potential difference between the third pixel electrode 113c and the third opposing electrode 115c, it is desirable or required that the third deposited pattern 114c contact the third pixel electrode 113c and the third opposing electrode 115c. Because the third deposited pattern 114c can fully or substantially contact the third opposing electrode 115c, current can flow through the third deposited pattern 114c in the region contacting the third pixel electrode 113c. The third deposited pattern 114c can emit light in the region contacting the third pixel electrode 113c. Therefore, the region where the third deposited pattern 114c emits light, the region where the third light-emitting diode LED3 emits light, or the third emission region EA3 can be defined by the region where the third deposited pattern 114c and the third pixel electrode 113c are in contact with each other. In one or more embodiments, because the third deposited pattern 114c can contact the third pixel electrode 113c within the third hole H3 in the pixel defining layer 112, the region where the third deposited pattern 114c and the third pixel electrode 113c are in contact with each other can be defined by the third hole H3. Therefore, the third emission region EA3 can be defined by the third aperture H3.

[0155] Because a portion of the third deposition pattern 114c can cover the edge of the defined third aperture H3 of the pixel defining layer 112 and can be disposed on the top surface of the pixel defining layer 112, the shape or size of the third deposition pattern 114c can differ from the shape or size of the third aperture H3 (or the third emission region EA3). In one or more embodiments, in a planar view (e.g., if viewed in the z-direction, e.g., when viewed in the z-direction) the shape or size of the third deposition pattern 114c can differ from the shape or size of the third aperture H3 (or the third emission region EA3). The specific relationship between the planar shape of the third deposition pattern 114c and the planar shape of the third aperture H3 (or the third emission region EA3) will be described in more detail.

[0156] A thin-film encapsulation layer (TFE) can be disposed on the opposing electrode 115. The TFE can cover the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3). In one or more embodiments, the TFE may include at least one inorganic layer and at least one organic layer. For example, such as... Figure 7As shown, the thin-film encapsulation layer TFE may include a first inorganic encapsulation layer 116 disposed on the opposing electrode 115, an organic encapsulation layer 117 disposed on the first inorganic encapsulation layer 116, and a second inorganic encapsulation layer 118 disposed on the organic encapsulation layer 117. The first inorganic encapsulation layer 116 and the second inorganic encapsulation layer 118 may include inorganic insulating materials. In one or more embodiments, the first inorganic encapsulation layer 116 and / or the second inorganic encapsulation layer 118 may include at least one inorganic insulating material, such as silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), etc. x The organic encapsulation layer 117 may include organic insulating materials such as silicon oxynitride (e.g., SiON), aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), and / or zinc oxide (e.g., ZnO2). The organic encapsulation layer 117 may also include organic insulating materials. In one or more embodiments, the organic encapsulation layer 117 may include polymer-based materials. Examples of polymer-based materials may include silicone resins, acrylic resins, epoxy resins, polyimides, and / or polyethylene. In one or more embodiments, the organic encapsulation layer 117 may be provided as a planarization layer having a flat top surface.

[0157] Figure 8A It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 8B It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 8A and Figure 8B It can be the display area DA (see Figure 5 (A floor plan of ). Figure 8A The pixel-defining layer 112 is shown, and Figure 8B The pixel-defining layer 112 and the intermediate layer 114 on the pixel-defining layer 112 are shown.

[0158] refer to Figure 8A and Figure 8B The pixel defining layer 112 may include multiple holes defining multiple emission regions EA.

[0159] In one or more embodiments, a first emission region EA1, a second emission region EA2, and a third emission region EA3 may be defined in the pixel defining layer 112. For example, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be defined by a corresponding hole in the pixel defining layer 112.

[0160] The first emission region EA1 may include a first-1 emission region EA1-1, a first-2 emission region EA1-2, a first-3 emission region EA1-3, and a first-4 emission region EA1-4. The first-1 emission region EA1-1 may be defined by a first-1 aperture H1-1 in the pixel defining layer 112. The first-2 emission region EA1-2 may be defined by a first-2 aperture H1-2 in the pixel defining layer 112. The first-3 emission region EA1-3 may be defined by a first-3 aperture H1-3 in the pixel defining layer 112. The first-4 emission region EA1-4 may be defined by a first-4 aperture H1-4 in the pixel defining layer 112.

[0161] The first emission region EA1 may have one or more suitable shapes. In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 may each have an elliptical shape. In one or more embodiments, the first-1 emission region EA1-1 may have an elliptical shape with its major axis extending in the x-direction. In one or more embodiments, the first-2 emission region EA1-2 may have an elliptical shape with its major axis extending in the first direction DR1. In one or more embodiments, the first-3 emission region EA1-3 may have an elliptical shape with its major axis extending in the y-direction. In one or more embodiments, the first-4 emission region EA1-4 may have an elliptical shape with its major axis extending in the second direction DR2.

[0162] In one or more embodiments, the first direction DR1 may form an angle of approximately 45 degrees with the +y direction and an angle of approximately 135 degrees with the +x direction. In one or more embodiments, the second direction DR2 may form an angle of approximately 45 degrees with the +y direction and an angle of approximately 45 degrees with the +x direction.

[0163] In one or more embodiments, the lengths of the major axes of the elliptical shapes of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 may be the same as each other. In one or more embodiments, the lengths of the minor axes of the elliptical shapes of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 may be the same as each other. For example, the first emission region EA1 or the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 may have a shape obtained by rotating an ellipse of the same size at an angle (e.g., about 45 degrees) based on the aligned center of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4. For example, the major axis lengths of the elliptical shapes of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 can be the same. Similarly, the minor axis lengths of these elliptical shapes can also be the same. For example, the first emission region EA1 or the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 can have a shape obtained by rotating an ellipse of the same size at an angle (e.g., about 45 degrees) based on the center of alignment of these emission regions.

[0164] The second emission region EA2 may include a second-1 emission region EA2-1, a second-2 emission region EA2-2, a second-3 emission region EA2-3, and a second-4 emission region EA2-4. The second-1 emission region EA2-1 may be defined by a second-1 aperture H2-1 in the pixel defining layer 112. The second-2 emission region EA2-2 may be defined by a second-2 aperture H2-2 in the pixel defining layer 112. The second-3 emission region EA2-3 may be defined by a second-3 aperture H2-3 in the pixel defining layer 112. The second-4 emission region EA2-4 may be defined by a second-4 aperture H2-4 in the pixel defining layer 112.

[0165] The second emission region EA2 may have one or more suitable shapes. In one or more embodiments, the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may each have an elliptical shape. In one or more embodiments, the second-1 emission region EA2-1 may have an elliptical shape with its major axis extending in the x-direction. In one or more embodiments, the second-2 emission region EA2-2 may have an elliptical shape with its major axis extending in the first direction DR1. In one or more embodiments, the second-3 emission region EA2-3 may have an elliptical shape with its major axis extending in the y-direction. In one or more embodiments, the second-4 emission region EA2-4 may have an elliptical shape with its major axis extending in the second direction DR2.

[0166] In one or more embodiments, the lengths of the major axes of the elliptical shapes of the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may be the same as each other. In one or more embodiments, the lengths of the minor axes of the elliptical shapes of the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may be the same as each other. For example, the second emission region EA2 or the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may have a shape obtained by rotating ellipses of the same size at an angle (e.g., about 45 degrees).

[0167] The third emission region EA3 may include a third-1 emission region EA3-1, a third-2 emission region EA3-2, a third-3 emission region EA3-3, and a third-4 emission region EA3-4. The third-1 emission region EA3-1 may be defined by a third-1 aperture H3-1 in the pixel limiting layer 112. The third-2 emission region EA3-2 may be defined by a third-2 aperture H3-2 in the pixel limiting layer 112. The third-3 emission region EA3-3 may be defined by a third-3 aperture H3-3 in the pixel limiting layer 112. The third-4 emission region EA3-4 may be defined by a third-4 aperture H3-4 in the pixel limiting layer 112.

[0168] The third emission region EA3 may have one or more suitable shapes. In one or more embodiments, the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4 may each have an elliptical shape. In one or more embodiments, the third-1 emission region EA3-1 may have an elliptical shape with its major axis extending in the x-direction. In one or more embodiments, the third-2 emission region EA3-2 may have an elliptical shape with its major axis extending in the first direction DR1. In one or more embodiments, the third-3 emission region EA3-3 may have an elliptical shape with its major axis extending in the y-direction. In one or more embodiments, the third-4 emission region EA3-4 may have an elliptical shape with its major axis extending in the second direction DR2.

[0169] In one or more embodiments, the lengths of the major axes of the elliptical shapes of the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4 may be the same as each other. In one or more embodiments, the lengths of the minor axes of the elliptical shapes of the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4 may be the same as each other. For example, the third emission region EA3 or the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4 may have a shape obtained by rotating ellipses of the same size at an angle (e.g., about 45 degrees).

[0170] In one or more embodiments, the first emission region EA1 may be a red emission region. For example, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 may be red emission regions. Therefore, light of the same color can be emitted from the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4.

[0171] In one or more embodiments, the second emission region EA2 may be a green emission region. For example, the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may be green emission regions. Therefore, light of the same color can be emitted from the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4. In one or more embodiments, the size of each of the second emission regions EA2 may be larger than the size of each of the first emission regions EA1, for example, the size of each of the second-1 emission regions EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may be larger than, for example, the size of each of the first-1 emission regions EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4.

[0172] In one or more embodiments, the third emission region EA3 may be a blue emission region. For example, the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4 may be blue emission regions. Therefore, light of the same color can be emitted from the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4. In one or more embodiments, the size of each of the third emission regions EA3 may be larger than the size of each of the second emission regions EA2, for example, the size of each of the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4 may be larger than, for example, the size of each of the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4.

[0173] The intermediate layer 114 may be disposed on the pixel defining layer 112 and may include a first deposition pattern 114a, a second deposition pattern 114b and a third deposition pattern 114c.

[0174] The first deposition pattern 114a may include a first-1 deposition pattern 114a1, a first-2 deposition pattern 114a2, a first-3 deposition pattern 114a3, and a first-4 deposition pattern 114a4. The first-1 deposition pattern 114a1 may overlap with the first-1 emission region EA1-1 and may occupy the first-1 aperture H1-1. The first-2 deposition pattern 114a2 may overlap with the first-2 emission region EA1-2 and may occupy the first-2 aperture H1-2. The first-3 deposition pattern 114a3 may overlap with the first-3 emission region EA1-3 and may occupy the first-3 aperture H1-3. The first-4 deposition pattern 114a4 may overlap with the first-4 emission region EA1-4 and may occupy the first-4 aperture H1-4. The regions where the first-1 deposition pattern 114a1, the first-2 deposition pattern 114a2, the first-3 deposition pattern 114a3, and the first-4 deposition pattern 114a4 overlap with the first-1 aperture H1-1, the first-2 aperture H1-2, the first-3 aperture H1-3, and the first-4 aperture H1-4, respectively, can be regions where actual light emission occurs. The size of the first deposition pattern 114a can be larger than the size of the corresponding first emission region EA1. Therefore, a portion of the first deposition pattern 114a (e.g., the portion that does not overlap with the corresponding first emission region EA1) can be disposed on the top surface of the pixel defining layer 112, as referenced above. Figure 7 As described.

[0175] In one or more embodiments, the first deposition pattern 114a (e.g., first-1 deposition pattern 114a1, first-2 deposition pattern 114a2, first-3 deposition pattern 114a3, and first-4 deposition pattern 114a4) may have the same shape and the same size. In one or more embodiments, the first deposition pattern 114a (e.g., first-1 deposition pattern 114a1, first-2 deposition pattern 114a2, first-3 deposition pattern 114a3, and first-4 deposition pattern 114a4) may each have, for example, the first deposition pattern 114a1, first-2 deposition pattern 114a2, first-3 deposition pattern 114a3, and first-4 deposition pattern 114a4) have, respectively, the first deposition pattern 114a1, first-2 deposition pattern 114a2, first-3 deposition pattern 114a3, and first-4 deposition pattern 114a4. Figure 8B The circular shape shown is not necessarily limited to this, and the first deposition pattern 114a may each have another shape, such as an elliptical shape or a polygonal shape.

[0176] The shape of the first deposition pattern 114a can be determined as follows. First, the first shape can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4, or by overlapping the first-1 aperture H1-1, the first-2 aperture H1-2, the first-3 aperture H1-3, and the first-4 aperture H1-4 (by aligning their centers). In one or more embodiments, the first shape can be obtained by drawing the outline (or edge) (or edge region) of the overlapping first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4, or the overlapping first-1 aperture H1-1, the first-2 aperture H1-2, the first-3 aperture H1-3, and the first-4 aperture H1-4. Next, the first deposition patterns 114a can each be arranged to have a second shape corresponding to the first shape. The second shape can be sufficiently or relatively larger than the first shape to ensure process allowance. In one or more embodiments, the second shape may be geometrically identical to the first shape, but with a larger size. In one or more embodiments, the second shape may be any shape that can fully or relatively cover the first shape. For example, the second shape may be a circular or elliptical shape that can fully or substantially cover the first shape. Figure 8B One or more embodiments are shown in which the second shape (e.g., the shape of each of the first deposition patterns 114a) is circular.

[0177] Therefore, the first emission regions EA1 (e.g., first-1 emission region EA1-1, first-2 emission region EA1-2, first-3 emission region EA1-3, and first-4 emission region EA1-4) can have different shapes from each other, while the corresponding first deposition patterns 114a (e.g., first-1 deposition pattern 114a1, first-2 deposition pattern 114a2, first-3 deposition pattern 114a3, and first-4 deposition pattern 114a4) can have the same shape. This simplifies the process of arranging the first deposition patterns 114a as described in more detail.

[0178] For example, if the description refers to the first-1 deposition pattern 114a1 and the first-1 emission region EA1-1 (e.g., when the description refers to the first-1 deposition pattern 114a1 and the first-1 emission region EA1-1), the process allowance may correspond to the size difference between the x-direction edge of the ellipse of the first-1 emission region EA1-1 and the x-direction edge of the first-1 deposition pattern 114a1. In some embodiments, if the description refers to the first-3 deposition pattern 114a3 and the first-3 emission region EA1-3 (e.g., when the description refers to the first-3 deposition pattern 114a3 and the first-3 emission region EA1-3), the process allowance may correspond to the size difference between the y-direction edge of the ellipse of the first-3 emission region EA1-3 and the y-direction edge of the first-3 deposition pattern 114a3.

[0179] In this way, by arranging the first deposition patterns 114a (e.g., first-1 deposition patterns 114a1, first-2 deposition patterns 114a2, first-3 deposition patterns 114a3 and first-4 deposition patterns 114a4) to have a shape (e.g., a first shape) corresponding to the shape obtained by overlapping the first emission regions EA1 (e.g., first shape) with each other, all the first emission regions EA1 can be covered by the first deposition patterns 114a with the same shape, and at the same time, the desired or required process margin of all the first emission regions EA1 can be ensured.

[0180] For example, by arranging the first deposition patterns 114a (e.g., first-1 deposition pattern 114a1, first-2 deposition pattern 114a2, first-3 deposition pattern 114a3, and first-4 deposition pattern 114a4) to have a shape (e.g., a second shape) corresponding to the shape obtained by overlapping the first emission regions EA1 (e.g., a first shape), all the first emission regions EA1 are covered by the first deposition patterns 114a having the same shape. This arrangement ensures that the required process margin for all the first emission regions EA1 is guaranteed.

[0181] The features of the first deposition pattern 114a can be similarly applied to the second deposition pattern 114b and the third deposition pattern 114c.

[0182] The second deposition pattern 114b may include a second-1 deposition pattern 114b1, a second-2 deposition pattern 114b2, a second-3 deposition pattern 114b3, and a second-4 deposition pattern 114b4. The second-1 deposition pattern 114b1 may overlap with the second-1 emission region EA2-1 and may occupy the second-1 aperture H2-1. The second-2 deposition pattern 114b2 may overlap with the second-2 emission region EA2-2 and may occupy the second-2 aperture H2-2. The second-3 deposition pattern 114b3 may overlap with the second-3 emission region EA2-3 and may occupy the second-3 aperture H2-3. The second-4 deposition pattern 114b4 may overlap with the second-4 emission region EA2-4 and may occupy the second-4 aperture H2-4. The regions where the second-1 deposition pattern 114b1, the second-2 deposition pattern 114b2, the second-3 deposition pattern 114b3, and the second-4 deposition pattern 114b4 overlap with the second-1 aperture H2-1, the second-2 aperture H2-2, the second-3 aperture H2-3, and the second-4 aperture H2-4, respectively, can be regions where actual light emission occurs. The size of the second deposition pattern 114b can be larger than the size of the corresponding second emission region EA2. Therefore, a portion of the second deposition pattern 114b (e.g., the portion that does not overlap with the corresponding second emission region EA2) can be disposed on the top surface of the pixel defining layer 112, as referenced above. Figure 7 As described.

[0183] In one or more embodiments, the second deposition pattern 114b (e.g., second-1 deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) may have the same shape and the same size. In one or more embodiments, the second deposition pattern 114b (e.g., second-1 deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) may each have, for example, the second deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) have, for example, the second deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) have, for example, the second deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) each ... Figure 8B The circular shape shown is not necessarily limited to this, and the second deposition pattern 114b may each have another shape, such as an elliptical shape or a polygonal shape.

[0184] The shape of the second deposition pattern 114b can be determined as follows. First, a first shape can be obtained by overlapping the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4, or by overlapping the second-1 aperture H2-1, the second-2 aperture H2-2, the second-3 aperture H2-3, and the second-4 aperture H2-4 (by aligning their centers). In one or more embodiments, the first shape can be obtained by drawing the outlines (or edges) (or edge regions) of the overlapping second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4, or the overlapping second-1 aperture H2-1, the second-2 aperture H2-2, the second-3 aperture H2-3, and the second-4 aperture H2-4. Next, each of the second deposition patterns 114b can be arranged to have a second shape corresponding to the first shape. The second shape can be sufficiently or relatively larger than the first shape to ensure process allowance. In one or more embodiments, the second shape may be geometrically identical to the first shape, but with a larger size. In one or more embodiments, the second shape may be any shape that can fully or substantially cover the first shape. For example, the second shape may be a circular or elliptical shape that can fully or substantially cover the first shape. Figure 8B One or more embodiments are shown in which the second shape (i.e. the shape of each of the second deposition patterns 114b) is circular.

[0185] Therefore, the second emission regions EA2 (e.g., second-1 emission region EA2-1, second-2 emission region EA2-2, second-3 emission region EA2-3, and second-4 emission region EA2-4) can have different shapes from each other, while the corresponding second deposition patterns 114b (e.g., second-1 deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) can have the same shape. This simplifies the process of arranging the second deposition patterns 114b as described in more detail.

[0186] For example, if the description refers to the second-1 deposition pattern 114b1 and the second-1 emission region EA2-1 (e.g., when describing the second-1 deposition pattern 114b1 and the second-1 emission region EA2-1), the process allowance may correspond to the dimensional difference between the x-direction edge of the ellipse of the second-1 emission region EA2-1 and the x-direction edge of the second-1 deposition pattern 114b1. As another example, if the description refers to the second-3 deposition pattern 114b3 and the second-3 emission region EA2-3 (e.g., when describing the second-3 deposition pattern 114b3 and the second-3 emission region EA2-3), the process allowance may correspond to the dimensional difference between the y-direction edge of the ellipse of the second-3 emission region EA2-3 and the y-direction edge of the second-3 deposition pattern 114b3.

[0187] In this way, by arranging the second deposition patterns 114b (e.g., second-1 deposition pattern 114b1, second-2 deposition pattern 114b2, second-3 deposition pattern 114b3, and second-4 deposition pattern 114b4) to have a shape (e.g., a second shape) corresponding to the shape obtained by overlapping the second emission regions EA2 (e.g., second-1 emission region EA2-1, second-2 emission region EA2-2, second-3 emission region EA2-3, and second-4 emission region EA2-4) with each other, all the second emission regions EA2 can be covered using the second deposition patterns 114b with the same shape, and at the same time, the desired or required process margin for all the second emission regions EA2 can be ensured. For example, this arrangement ensures that the required process margin for all the second emission regions EA2 is ensured.

[0188] The third deposition pattern 114c may include a third-1 deposition pattern 114c1, a third-2 deposition pattern 114c2, a third-3 deposition pattern 114c3, and a third-4 deposition pattern 114c4. The third-1 deposition pattern 114c1 may overlap with the third-1 emission region EA3-1 and may occupy the third-1 aperture H3-1. The third-2 deposition pattern 114c2 may overlap with the third-2 emission region EA3-2 and may occupy the third-2 aperture H3-2. The third-3 deposition pattern 114c3 may overlap with the third-3 emission region EA3-3 and may occupy the third-3 aperture H3-3. The third-4 deposition pattern 114c4 may overlap with the third-4 emission region EA3-4 and may occupy the third-4 aperture H3-4. The regions where the third-1 deposition pattern 114c1, the third-2 deposition pattern 114c2, the third-3 deposition pattern 114c3, and the third-4 deposition pattern 114c4 overlap with the third-1 aperture H3-1, the third-2 aperture H3-2, the third-3 aperture H3-3, and the third-4 aperture H3-4, respectively, can be regions where actual light emission occurs. The size of the third deposition pattern 114c can be larger than the size of the third emission region EA3. Therefore, a portion of the third deposition pattern 114c (e.g., the portion that does not overlap with the corresponding third emission region EA3) can be disposed on the top surface of the pixel defining layer 112, as referenced above. Figure 7 As described.

[0189] In one or more embodiments, the third deposition pattern 114c (e.g., third-1 deposition pattern 114c1, third-2 deposition pattern 114c2, third-3 deposition pattern 114c3, and third-4 deposition pattern 114c4) may have the same shape and the same size. In one or more embodiments, the third deposition pattern 114c (e.g., third-1 deposition pattern 114c1, third-2 deposition pattern 114c2, third-3 deposition pattern 114c3, and third-4 deposition pattern 114c4) may each have as follows: Figure 8B The circular shape shown is not necessarily limited to this, and the third deposition pattern 114c may each have another shape, such as an elliptical shape or a polygonal shape.

[0190] The shape of the third deposition pattern 114c can be determined as follows. First, a first shape can be obtained by overlapping the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4, or by overlapping the third-1 aperture H3-1, the third-2 aperture H3-2, the third-3 aperture H3-3, and the third-4 aperture H3-4 (by aligning their centers). In one or more embodiments, the first shape can be obtained by drawing the outline (or edge) (or edge region) of the overlapping third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4, or the overlapping third-1 aperture H3-1, the third-2 aperture H3-2, the third-3 aperture H3-3, and the third-4 aperture H3-4. Next, each of the third deposition patterns 114c can be arranged to have a second shape corresponding to the first shape. The second shape can be sufficiently or relatively larger than the first shape to ensure process allowance. In one or more embodiments, the second shape may be geometrically identical to the first shape, but with a larger size. In one or more embodiments, the second shape may be any shape that can fully or substantially cover the first shape. For example, the second shape may be a circular or elliptical shape that can fully or substantially cover the first shape. Figure 8B One or more embodiments are shown in which the second shape (i.e. the shape of each of the third deposition patterns 114c) is circular.

[0191] Therefore, the third emission regions EA3 (e.g., third-1 emission region EA3-1, third-2 emission region EA3-2, third-3 emission region EA3-3, and third-4 emission region EA3-4) can have different shapes from each other, while the corresponding third deposition patterns 114c (e.g., third-1 deposition pattern 114c1, third-2 deposition pattern 114c2, third-3 deposition pattern 114c3, and third-4 deposition pattern 114c4) can have the same shape. This simplifies the process of arranging the third deposition patterns 114c as described in more detail.

[0192] For example, if a description is given for the third-1 deposition pattern 114c1 and the third-1 emission region EA3-1 (e.g., when a description is given for the third-1 deposition pattern 114c1 and the third-1 emission region EA3-1), the process allowance may correspond to the dimensional difference between the x-direction edge of the ellipse of the third-1 emission region EA3-1 and the x-direction edge of the third-1 deposition pattern 114c1. As another example, if a description is given for the third-3 deposition pattern 114c3 and the third-3 emission region EA3-3 (e.g., when a description is given for the third-3 deposition pattern 114c3 and the third-3 emission region EA3-3), the process allowance may correspond to the dimensional difference between the y-direction edge of the ellipse of the third-3 emission region EA3-3 and the y-direction edge of the third-3 deposition pattern 114c3.

[0193] In this way, by arranging the third deposition patterns 114c (e.g., the third-1 deposition pattern 114c1, the third-2 deposition pattern 114c2, the third-3 deposition pattern 114c3, and the third-4 deposition pattern 114c4) to have a shape (e.g., a first shape) corresponding to the shape obtained by overlapping the third emission regions EA3 (e.g., the third-1 emission region EA3-1, the third-2 emission region EA3-2, the third-3 emission region EA3-3, and the third-4 emission region EA3-4) with each other (e.g., a first shape), all the first emission regions EA1 can be covered by the third deposition patterns 114c with the same shape, and the desired or required process margin of all the third emission regions EA3 can be ensured simultaneously (e.g., at the same time).

[0194] Figure 8B One or more embodiments are shown in which the first deposition pattern 114a, the second deposition pattern 114b, and the third deposition pattern 114c are spaced apart and / or separated from each other (e.g., separated or apart), but this disclosure is not necessarily limited thereto. In one or more embodiments, adjacent portions of the first deposition pattern 114a, the second deposition pattern 114b, and the third deposition pattern 114c may overlap each other.

[0195] The arrangement of each of the emitter regions EA and intermediate layers 114 is described below. Because the deposition pattern DPT of the intermediate layer 114 can overlap with the corresponding emitter region EA, the arrangement of the emitter region EA is mainly described in this specification.

[0196] In one or more embodiments, the second emission region EA2 may be arranged in odd-numbered pixel rows (e.g., first pixel row PXR1, third pixel row PXR3, and fifth pixel row PXR5), and the first emission region EA1 and the third emission region EA3 may be alternately arranged in even-numbered pixel rows (e.g., second pixel row PXR2, fourth pixel row PXR4, and sixth pixel row PXR6). In one or more embodiments, the type (variety) of the second emission region EA2 arranged in odd-numbered pixel rows (e.g., first pixel row PXR1, third pixel row PXR3, and fifth pixel row PXR5) may vary. In one or more embodiments, the type (variety) of the first emission region EA1 and the third emission region EA3 arranged in even-numbered pixel rows (e.g., second pixel row PXR2, fourth pixel row PXR4, and sixth pixel row PXR6) may vary.

[0197] In one or more embodiments, the second-1 emission region EA2-1, the second-2 emission region EA2-2, the second-3 emission region EA2-3, and the second-4 emission region EA2-4 may be arranged in the x-direction within the first pixel row PXR1. In one or more embodiments, the third-1 emission region EA3-1, the first-1 emission region EA1-1, the third-2 emission region EA3-2, and the first-2 emission region EA1-2 may be arranged in the x-direction within the second pixel row PXR2. In one or more embodiments, the second-4 emission region EA2-4, the second-2 emission region EA2-2, the second-4 emission region EA2-4, and the second-4 emission region EA2-4 may be arranged in the x-direction within the third pixel row PXR3. In one or more embodiments, the first-3 emission region EA1-3, the third-3 emission region EA3-3, the first-4 emission region EA1-4, and the third-4 emission region EA3-4 may be arranged in the x-direction within the fourth pixel row PXR4. In one or more embodiments, the second-3 emission region EA2-3, the second-4 emission region EA2-4, the second-1 emission region EA2-1, and the second-2 emission region EA2-2 may be arranged in the x-direction within the fifth pixel row PXR5. In one or more embodiments, the third-1 emission region EA3-1, the first-4 emission region EA1-4, the third-4 emission region EA3-4, and the first-2 emission region EA1-2 may be arranged in the x-direction within the sixth pixel row PXR6.

[0198] In one or more embodiments, if viewed in the y-direction (e.g., when viewed in the y-direction), each of the rows of emission regions EA aligned in the x-direction may not be aligned with each other. For example, if viewed in the y-direction (e.g., when viewed in the y-direction), the centers of emission regions EA arranged in odd-numbered pixel rows (e.g., the first pixel row PXR1, the third pixel row PXR3, and the fifth pixel row PXR5) and the centers of emission regions EA arranged in even-numbered pixel rows (e.g., the second pixel row PXR2, the fourth pixel row PXR4, and the sixth pixel row PXR6) may not overlap. In one or more embodiments, if viewed in the x-direction (e.g., when viewed in the x-direction), each of the columns of emission regions EA aligned in the y-direction may not be aligned with each other. In one or more embodiments, emission regions EA may be aligned in a first direction DR1 and simultaneously (e.g., concurrently) in a second direction DR2.

[0199] Figure 9A It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 9B It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 9A and Figure 9B It can be the display area DA (see Figure 5 (A floor plan of ). Figure 9A The pixel-defining layer 112 is shown, and Figure 9B The pixel-defining layer 112 and the intermediate layer 114 on the pixel-defining layer 112 are shown.

[0200] refer to Figure 9A and Figure 9BThe first launch area EA1 may include the first-1 launch area EA1-1, the first-2 launch area EA1-2, and the first-4 launch area EA1-4. The second launch area EA2 may include the second-1 launch area EA2-1, the second-2 launch area EA2-2, and the second-4 launch area EA2-4. The third launch area EA3 may include the third-2 launch area EA3-2, the third-3 launch area EA3-3, and the third-4 launch area EA3-4. The pixel limiting layer 112 may include a first-1 hole H1-1 corresponding to the first-1 emission region EA1-1, a first-2 hole H1-2 corresponding to the first-2 emission region EA1-2, a first-4 hole H1-4 corresponding to the first-4 emission region EA1-4, a second-1 hole H2-1 corresponding to the second-1 emission region EA2-1, a second-2 hole H2-2 corresponding to the second-2 emission region EA2-2, a second-4 hole H2-4 corresponding to the second-4 emission region EA2-4, a third-2 hole H3-2 corresponding to the third-2 emission region EA3-2, a third-3 hole H3-3 corresponding to the third-3 emission region EA3-3, and a third-4 hole H3-4 corresponding to the third-4 emission region EA3-4.

[0201] The first deposition pattern 114a may include a first-1 deposition pattern 114a1, a first-2 deposition pattern 114a2, and a first-4 deposition pattern 114a4. The second deposition pattern 114b may include a second-1 deposition pattern 114b1, a second-2 deposition pattern 114b2, and a second-4 deposition pattern 114b4. The third deposition pattern 114c may include a third-2 deposition pattern 114c2, a third-3 deposition pattern 114c3, and a third-4 deposition pattern 114c4.

[0202] The relationships between the first emission region EA1 and the first deposition pattern 114a, the second emission region EA2 and the second deposition pattern 114b, and the third emission region EA3 and the third deposition pattern 114c are as described above. Figure 8A and Figure 8B As stated above.

[0203] In one or more embodiments, the first deposition pattern 114a may overlap with the adjacent second deposition pattern 114b. Figure 9B One or more embodiments are shown in which the second deposition pattern 114b is arranged on the first deposition pattern 114a in the region where the first deposition pattern 114a and the second deposition pattern 114b overlap each other, but this disclosure is not necessarily limited thereto, and the vertical arrangement may be reversed.

[0204] In one or more embodiments, the second deposition pattern 114b may overlap with the adjacent third deposition pattern 114c. Figure 9B One or more embodiments are shown in which the third deposition pattern 114c is arranged on the second deposition pattern 114b in the region where the third deposition pattern 114c overlaps with the second deposition pattern 114b, but this disclosure is not necessarily limited thereto, and the vertical arrangement may be reversed.

[0205] One of the first launch areas EA1, one of the second launch areas EA2, and one of the third launch areas EA3 can be combined together.

[0206] In one or more embodiments, the first-1 transmission region EA1-1, the second-1 transmission region EA2-1, and the third-3 transmission region EA3-3 can be combined together. In this group, the first-1 transmission region EA1-1 can be arranged in the y-direction relative to the second-1 transmission region EA2-1, and the third-3 transmission region EA3-3 can be arranged in the x-direction relative to the first-1 transmission region EA1-1 and the second-1 transmission region EA2-1. The group of the first-1 transmission region EA1-1, the second-1 transmission region EA2-1, and the third-3 transmission region EA3-3 can be arranged in the x-direction.

[0207] In one or more embodiments, the first-2 transmission region EA1-2, the second-2 transmission region EA2-2, and the third-4 transmission region EA3-4 can be combined together. In this group, the first-2 transmission region EA1-2 can be arranged in the y-direction relative to the second-2 transmission region EA2-2, and the third-4 transmission region EA3-4 can be arranged in the x-direction relative to the first-2 transmission region EA1-2 and the second-2 transmission region EA2-2. The group of the first-2 transmission region EA1-2, the second-2 transmission region EA2-2, and the third-4 transmission region EA3-4 can be arranged in the x-direction.

[0208] In one or more embodiments, the first-fourth transmission region EA1-4, the second-fourth transmission region EA2-4, and the third-twoth transmission region EA3-2 can be combined together. In this group, the first-fourth transmission region EA1-4 can be arranged in the y-direction relative to the second-fourth transmission region EA2-4, and the third-twoth transmission region EA3-2 can be arranged in the x-direction relative to the first-fourth transmission region EA1-4 and the second-fourth transmission region EA2-4. The group of the first-fourth transmission region EA1-4, the second-fourth transmission region EA2-4, and the third-twoth transmission region EA3-2 can be arranged in the x-direction.

[0209] In one or more embodiments, the first-second transmission region EA1-2, the second-second transmission region EA2-2, and the third-second transmission region EA3-2 can be combined together. In this group, the first-second transmission region EA1-2 can be arranged in the y-direction relative to the second-second transmission region EA2-2, and the third-second transmission region EA3-2 can be arranged in the x-direction relative to the first-second transmission region EA1-2 and the second-second transmission region EA2-2. The group of the first-second transmission region EA1-2, the second-second transmission region EA2-2, and the third-second transmission region EA3-2 can be arranged in the x-direction.

[0210] In one or more embodiments, with Figure 9A and Figure 9B As shown, different groups can be arranged in the x-direction.

[0211] In one or more embodiments, the first transmission region EA1 can be aligned in the x-direction. In one or more embodiments, the second transmission region EA2 can be aligned in the x-direction. In one or more embodiments, the first transmission region EA1 and the second transmission region EA2 can be aligned in the y-direction. In one or more embodiments, the third transmission region EA3 can be aligned in both the x-direction and the y-direction.

[0212] Figure 10A It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 10B It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 10A and Figure 10B It can be the display area DA (see Figure 5 (A floor plan of ). Figure 10A The pixel-defining layer 112 is shown, and Figure 10B The pixel-defining layer 112 and the intermediate layer 114 on the pixel-defining layer 112 are shown.

[0213] refer to Figure 10A and Figure 10BThe first emission region EA1 may include a first-2 emission region EA1-2 and a first-4 emission region EA1-4. The second emission region EA2 may include a second-2 emission region EA2-2 and a second-4 emission region EA2-4. The third emission region EA3 may include a third-2 emission region EA3-2 and a third-4 emission region EA3-4. The pixel defining layer 112 may include a first-2 hole H1-2 corresponding to the first-2 emission region EA1-2, a first-4 hole H1-4 corresponding to the first-4 emission region EA1-4, a second-2 hole H2-2 corresponding to the second-2 emission region EA2-2, a second-4 hole H2-4 corresponding to the second-4 emission region EA2-4, a third-2 hole H3-2 corresponding to the third-2 emission region EA3-2, and a third-4 hole H3-4 corresponding to the third-4 emission region EA3-4.

[0214] The first deposition pattern 114a may include a first-2 deposition pattern 114a2 and a first-4 deposition pattern 114a4. The second deposition pattern 114b may include a second-2 deposition pattern 114b2 and a second-4 deposition pattern 114b4. The third deposition pattern 114c may include a third-2 deposition pattern 114c2 and a third-4 deposition pattern 114c4.

[0215] The relationships between the first emission region EA1 and the first deposition pattern 114a, the second emission region EA2 and the second deposition pattern 114b, and the third emission region EA3 and the third deposition pattern 114c are as described above. Figure 8A and Figure 8B As stated above.

[0216] In one or more embodiments, the first deposition pattern 114a may overlap with the adjacent second deposition pattern 114b. Figure 10B One or more embodiments are shown in which the second deposition pattern 114b is arranged on the first deposition pattern 114a in the region where the first deposition pattern 114a and the second deposition pattern 114b overlap each other, but this disclosure is not necessarily limited thereto, and the vertical arrangement may be reversed.

[0217] In one or more embodiments, the second deposition pattern 114b may overlap with the adjacent third deposition pattern 114c. Figure 10B One or more embodiments are shown in which the third deposition pattern 114c is arranged on the second deposition pattern 114b in the region where the third deposition pattern 114c overlaps with the second deposition pattern 114b, but this disclosure is not necessarily limited thereto, and the vertical arrangement may be reversed.

[0218] In one or more embodiments, the third deposition pattern 114c may overlap with the adjacent first deposition pattern 114a. Figure 10B One or more embodiments are shown in which the third deposition pattern 114c is arranged on the first deposition pattern 114a in the region where the third deposition pattern 114c and the first deposition pattern 114a overlap, but this disclosure is not necessarily limited thereto, and the vertical arrangement may be reversed.

[0219] One of the first launch areas EA1 and one of the second launch areas EA2 can be combined together.

[0220] In one or more embodiments, the first-2 transmission region EA1-2 and the second-2 transmission region EA2-2 can be combined into a first group GR1, and the second-2 transmission region EA2-2 can be arranged relative to the first-2 transmission region EA1-2 in a second direction DR2. In one or more embodiments, the first-4 transmission region EA1-4 and the second-4 transmission region EA2-4 can be combined into a second group GR2, and the first-4 transmission region EA1-4 can be arranged relative to the second-4 transmission region EA2-4 in a first direction DR1.

[0221] In one or more embodiments, the first group GR1 and the second group GR2 may be arranged alternately in the x-direction within the first pixel row PXR1 and the third pixel row PXR3. In one or more embodiments, the third-2 emission region EA3-2 may be arranged in the x-direction within the second pixel row PXR2. In one or more embodiments, the third-4 emission region EA3-4 may be arranged in the x-direction within the fourth pixel row PXR4.

[0222] In one or more embodiments, the first group of GR1 can be arranged and aligned in the y-direction. In one or more embodiments, the second group of GR2 can be arranged and aligned in the y-direction. In one or more embodiments, the third-2 emission region EA3-2 and the third-4 emission region EA3-4 can be arranged alternately in the y-direction and can be aligned with each other.

[0223] In one or more embodiments, the second group GR2, the third-4 launch area EA3-4, the first group GR1, and the third-2 launch area EA3-2 can be arranged on the first direction DR1.

[0224] In one or more embodiments, the second group GR2, the third-4 launch area EA3-4, the first group GR1, and the third-2 launch area EA3-2 can be arranged on the second direction DR2.

[0225] Figure 11A It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 11B It is a plan view showing a portion of a display panel according to one or more embodiments. Figure 11A and Figure 11B It can be the display area DA (see Figure 5 (A floor plan of ). Figure 11A The pixel-defining layer 112 is shown, and Figure 11B The pixel-defining layer 112 and the intermediate layer 114 on the pixel-defining layer 112 are shown.

[0226] refer to Figure 11A and Figure 11B The first launch area EA1 may include the first-1 launch area EA1-1, the first-2 launch area EA1-2, the first-3 launch area EA1-3, and the first-4 launch area EA1-4. The second launch area EA2 may include the second-2 launch area EA2-2 and the second-4 launch area EA2-4. The third launch area EA3 may include the third-2 launch area EA3-2 and the third-4 launch area EA3-4. The pixel limiting layer 112 may include a first-1 hole H1-1 corresponding to the first-1 emission region EA1-1, a first-2 hole H1-2 corresponding to the first-2 emission region EA1-2, a first-3 hole H1-3 corresponding to the first-3 emission region EA1-3, a first-4 hole H1-4 corresponding to the first-4 emission region EA1-4, a second-2 hole H2-2 corresponding to the second-2 emission region EA2-2, a second-4 hole H2-4 corresponding to the second-4 emission region EA2-4, a third-2 hole H3-2 corresponding to the third-2 emission region EA3-2, and a third-4 hole H3-4 corresponding to the third-4 emission region EA3-4.

[0227] The first deposition pattern 114a may include a first-1 deposition pattern 114a1, a first-2 deposition pattern 114a2, a first-3 deposition pattern 114a3, and a first-4 deposition pattern 114a4. The second deposition pattern 114b may include a second-2 deposition pattern 114b2 and a second-4 deposition pattern 114b4. The third deposition pattern 114c may include a third-2 deposition pattern 114c2 and a third-4 deposition pattern 114c4.

[0228] The relationships between the first emission region EA1 and the first deposition pattern 114a, the second emission region EA2 and the second deposition pattern 114b, and the third emission region EA3 and the third deposition pattern 114c are as described above. Figure 8A and Figure 8B As stated above.

[0229] In one or more embodiments, the third deposition pattern 114c may overlap with the adjacent first deposition pattern 114a. Figure 11B One or more embodiments are shown in which the third deposition pattern 114c is arranged on the first deposition pattern 114a in the region where the third deposition pattern 114c and the first deposition pattern 114a overlap, but this disclosure is not necessarily limited thereto, and the vertical arrangement may be reversed.

[0230] Figure 11B The first deposition pattern 114a and the second deposition pattern 114b are shown to be non-overlapping, but this disclosure is not necessarily limited thereto.

[0231] Two of the first launch zones EA1, one of the second launch zones EA2, and one of the third launch zones EA3 can be combined together.

[0232] In one or more embodiments, the first-1 transmission region EA1-1, the first-3 transmission region EA1-3, the second-4 transmission region EA2-4, and the third-2 transmission region EA3-2 can be combined together. In this group, the first-1 transmission region EA1-1 can be arranged in the +x direction relative to the second-4 transmission region EA2-4 and in the +y direction relative to the third-2 transmission region EA3-2. In this group, the second-4 transmission region EA2-4 can be arranged in the -x direction relative to the first-1 transmission region EA1-1 and in the +y direction relative to the first-3 transmission region EA1-3. In this group, the first-3 transmission region EA1-3 can be arranged in the -x direction relative to the third-2 transmission region EA3-2 and in the -y direction relative to the second-4 transmission region EA2-4. In this group, the third-2 transmission region EA3-2 can be arranged in the +x direction relative to the first-3 transmission region EA1-3 and in the -y direction relative to the first-1 transmission region EA1-1. The groups of launch zones EA1-1 (first-1), EA1-3 (first-3), EA2-4 (second-4), and EA3-2 (third-2) can be arranged in the x-direction.

[0233] In one or more embodiments, the first-1 transmission region EA1-1, the first-3 transmission region EA1-3, the second-2 transmission region EA2-2, and the third-4 transmission region EA3-4 can be combined together. In this group, the first-1 transmission region EA1-1 can be arranged in the +x direction relative to the second-2 transmission region EA2-2 and in the +y direction relative to the third-4 transmission region EA3-4. In this group, the second-2 transmission region EA2-2 can be arranged in the -x direction relative to the first-1 transmission region EA1-1 and in the +y direction relative to the first-3 transmission region EA1-3. In this group, the first-3 transmission region EA1-3 can be arranged in the -x direction relative to the third-4 transmission region EA3-4 and in the -y direction relative to the second-2 transmission region EA2-2. In this group, the third-4 transmission region EA3-4 can be arranged in the +x direction relative to the first-3 transmission region EA1-3 and in the -y direction relative to the first-1 transmission region EA1-1. The groups of launch zones EA1-1 (first-1), EA1-3 (first-3), EA2-2 (second-2), and EA3-4 (third-4) can be arranged in the x-direction.

[0234] In one or more embodiments, the first-2 transmission region EA1-2, the first-4 transmission region EA1-4, the second-2 transmission region EA2-2, and the third-4 transmission region EA3-4 can be combined together. In this group, the first-2 transmission region EA1-2 can be arranged in the +x direction relative to the second-2 transmission region EA2-2 and in the +y direction relative to the third-4 transmission region EA3-4. In this group, the second-2 transmission region EA2-2 can be arranged in the -x direction relative to the first-2 transmission region EA1-2 and in the +y direction relative to the first-4 transmission region EA1-4. In this group, the first-4 transmission region EA1-4 can be arranged in the -x direction relative to the third-4 transmission region EA3-4 and in the -y direction relative to the second-2 transmission region EA2-2. In this group, the third-4 transmission region EA3-4 can be arranged in the +x direction relative to the first-4 transmission region EA1-4 and in the -y direction relative to the first-2 transmission region EA1-2. The groups of the first-2 launch area EA1-2, the first-4 launch area EA1-4, the second-2 launch area EA2-2, and the third-4 launch area EA3-4 can be arranged in the x direction.

[0235] In one or more embodiments, with Figure 11A and Figure 11B As shown, different groups can be arranged in the x-direction.

[0236] In one or more embodiments, the first transmission region EA1 and the second transmission region EA2 may be arranged alternately in the x-direction. In one or more embodiments, the first transmission region EA1 and the second transmission region EA2 may be arranged alternately in the y-direction. In one or more embodiments, the first transmission region EA1 and the third transmission region EA3 may be arranged alternately in the x-direction. In one or more embodiments, the first transmission region EA1 and the third transmission region EA3 may be arranged alternately in the y-direction.

[0237] In the foregoing, one or more embodiments in which the shape of the emission region EA of the pixel defining layer 112 is elliptical have been shown and primarily described; however, this disclosure is not necessarily limited to one or more embodiments in which the emission region EA has an elliptical shape. Furthermore, one or more embodiments of the arrangement of the emission region EA and the intermediate layer 114 are merely examples and do not limit this disclosure.

[0238] In the following text, see references Figures 12 to 16D Methods and apparatus are described for forming deposition patterns DPT (e.g., first deposition pattern 114a, second deposition pattern 114b and third deposition pattern 114c) having the above-described features.

[0239] Figure 12 This is a cross-sectional view showing a display panel manufacturing apparatus according to one or more embodiments.

[0240] refer to Figure 12 The display panel manufacturing apparatus 20 may include a chamber 21, a first support 22, a second support 23, a deposition source 24, a deposition mask 25, a magnetic unit 26, a vision unit 27, and a pressure control unit 28.

[0241] The display substrate DS can be an aspect to be processed or applied by the display panel manufacturing apparatus 20. (Return to Reference) Figure 7 and combined Figure 12 In the process of manufacturing the display panel 11, the display substrate DS can be a semi-finished product. In one or more embodiments, the display substrate DS can be a semi-finished product in the state where the pixel defining layer 112 has already been formed in the assembly of the display panel 11. In one or more embodiments, Figure 8A , Figure 9A , Figure 10A and Figure 11A It can be a planar view of the substrate DS. In one or more embodiments, Figure 8B , Figure 9B , Figure 10B and Figure 11BThis may be a plan view of the display substrate DS after the process utilizing the display panel manufacturing apparatus 20 described in more detail. In one or more embodiments, the display panel manufacturing apparatus 20 may be a deposition apparatus (e.g., disposing an intermediate layer 114 on the display substrate DS). In one or more embodiments, the display panel manufacturing method may include a deposition process (e.g., disposing an intermediate layer 114 on the display substrate DS). This disclosure is not limited to the deposition of the intermediate layer 114 only, and the display panel manufacturing apparatus 20 and the manufacturing method may be used for one or more suitable deposition processes. In one or more embodiments, one display substrate DS does not necessarily correspond to one display panel 11, and multiple display panels 11 may be manufactured using one display substrate DS. In one or more embodiments, multiple display panels 11 may be obtained by dicing one display substrate DS.

[0242] The chamber 21 may have a space formed therein and may have an opening. In this case, a gate valve 21-1 may be installed in the opening of the chamber 21. The opening of the chamber 21 may be opened or closed depending on the operation of the gate valve 21-1.

[0243] The display substrate DS can be placed on and supported by the first support member 22. In one or more embodiments, the first support member 22 can be in the form of a plate fixed within the chamber 21. In one or more embodiments, the first support member 22 can hold the display substrate DS and can be in the form of a shuttle capable of linear movement within the chamber 21. In one or more embodiments, the first support member 22 can include an electrostatic chuck or an adhesive chuck arranged in the chamber 21 for fixing to the chamber 21 or for being able to move up and down within the chamber 21. Hereinafter, for ease of explanation, the case where the first support member 22 is in the form of a plate fixed within the chamber 21 will be described primarily.

[0244] The deposition mask 25 can be placed on the second support 23. In this case, the second support 23 can be arranged within the chamber 21. The second support 23 can precisely adjust the position of the deposition mask 25. In one or more embodiments, the second support 23 may include a separate drive unit or alignment unit to move the deposition mask 25 in different directions. In one or more embodiments, the second support 23 may be in the form of a shuttle. In this case, the second support 23 can place the deposition mask 25 and can transfer the deposition mask 25. For example, the second support 23 can be moved to the outside of the chamber 21 and can enter the chamber 21 from the outside after the deposition mask 25 has been placed on it.

[0245] The first support member 22 and the second support member 23 can be integrally formed into a single body. In this case, the first support member 22 and the second support member 23 can each include a movable shuttle. In this case, the first support member 22 and the second support member 23 can each include a structure that fixes the deposition mask 25 and the display substrate DS while the display substrate DS is placed on the deposition mask 25, and can simultaneously move the display substrate DS and the deposition mask 25 linearly.

[0246] In the following text, for ease of explanation, the first support member 22 and the second support member 23 are mainly described at different positions within the chamber 21.

[0247] The deposition source 24 can be arranged within the chamber 21 facing the deposition mask 25. In this case, the deposition source 24 can contain the deposition material, and the deposition material can evaporate or sublimate by applying heat to it. The deposition source 24 can be fixed within the chamber 21, or it can be arranged within the chamber 21 to allow linear movement in one direction. In the following description, for ease of explanation, the case where the deposition source 24 is fixed within the chamber 21 will be primarily described. Figure 12 The illustration shows a deposition source 24 positioned below the display substrate DS; however, in one or more embodiments, the deposition source 24 may be positioned above the display substrate DS and may spray deposition material downwards. For example, Figure 12 The +z direction is shown as the direction of gravity, but in one or more embodiments, the +z direction may be opposite to the direction of gravity.

[0248] The deposition mask 25 may include a mask frame 251, a first support rod 252 and a second support rod 253, and a tensioning plate 254.

[0249] Magnetic unit 26 can be arranged within chamber 21 facing the display substrate DS. In this case, magnetic unit 26 can apply magnetic force to tension plate 254 and press deposition mask 25 toward display substrate DS. Specifically, magnetic unit 26 can not only prevent or reduce sagging of tension plate 254, but also allow tension plate 254 to be in close contact with display substrate DS. Furthermore, magnetic unit 26 can uniformly (e.g., substantially uniformly) maintain the gap between tension plate 254 and display substrate DS relative to the longitudinal direction of tension plate 254.

[0250] A vision unit 27 can be mounted in chamber 21 and can capture images of the positions of the display substrate DS and the deposition mask 25. In this case, the vision unit 27 may include a camera that captures images of the display substrate DS and the deposition mask 25. The positions of the display substrate DS and the deposition mask 25 can be identified based on the images captured by the vision unit 27, and based on the images, the first support member 22 can precisely adjust the position of the display substrate DS, or the second support member 23 can precisely adjust the position of the deposition mask 25. The following description focuses primarily on the case where the second support member 23 precisely adjusts the position of the deposition mask 25 to align the positions of the display substrate DS and the deposition mask 25.

[0251] The pressure control unit 28 can be connected to the chamber 21 and control the pressure inside the chamber 21. For example, the pressure control unit 28 can control the pressure inside the chamber 21 to be the same as or similar to atmospheric pressure. In addition, the pressure control unit 28 can control the pressure inside the chamber 21 to be the same as or similar to a vacuum state.

[0252] The pressure control unit 28 may include a connecting pipe 281 connected to the chamber 21 and a pump 282 mounted on the connecting pipe 281. Depending on the operation of the pump 282, external air may be introduced through the connecting pipe 281, or gas in the chamber 21 may be guided to the outside through the connecting pipe 281.

[0253] The following describes one or more embodiments of the operation of the display panel manufacturing apparatus 20.

[0254] First, if the pressure control unit 28 causes the interior of chamber 21 to have a pressure that is the same as or similar to atmospheric pressure (for example, when the pressure control unit 28 causes the interior of chamber 21 to have a pressure that is the same as or similar to atmospheric pressure), then the gate valve 21-1 can be operated to open the opening portion of chamber 21.

[0255] In the following description, the display substrate DS can be loaded into the cavity 21 from the outside of the cavity 21. The display substrate DS can be loaded into the cavity 21 in one or more suitable ways. In one or more embodiments, the display substrate DS can be loaded into the cavity 21 from the outside of the cavity 21 by a robotic arm arranged outside the cavity 21. In one or more embodiments, if the first support member 22 is formed in a shuttle shape (e.g., when the first support member 22 is formed in a shuttle shape), the first support member 22 can be carried from the inside of the cavity 21 to the outside of the cavity 21, and then the display substrate DS can be placed on the first support member 22 by a separate robotic arm arranged outside the cavity 21, and the first support member 22 can be loaded into the cavity 21 from the outside of the cavity 21. In the following description, for ease of explanation, the case where the display substrate DS is loaded into the cavity 21 from the outside of the cavity 21 by a robotic arm arranged outside the cavity 21 is mainly described.

[0256] The deposition mask 25 may be disposed within the chamber 21. In one or more embodiments, the deposition mask 25 may be loaded into the chamber 21 from the outside in a manner substantially the same as or similar to that of the display substrate DS. Hereinafter, for ease of explanation, the case in which only the display substrate DS is loaded into the chamber 21 from the outside while the deposition mask 25 is disposed within the chamber 21 will be described.

[0257] In one or more embodiments, it is also possible that the first support 22 and the second support 23 are each in the form of a shuttle, and are each loaded into the cavity 21 from outside the cavity 21 after the display substrate DS and the deposition mask 25 are fixed.

[0258] If the display substrate DS is loaded into the chamber 21 (e.g., when the display substrate DS is loaded into the chamber 21), the display substrate DS can be placed on the first support 22. The vision unit 27 can capture images of the positions of the display substrate DS and the deposition mask 25. For example, the vision unit 27 can capture images of a first alignment mark on the display substrate DS and a second alignment mark on the deposition mask 25.

[0259] The positions of the display substrate DS and the deposition mask 25 can be identified based on the captured first alignment mark and second alignment mark. In this case, the display panel manufacturing apparatus 20 includes a separate control unit to identify the positions of the display substrate DS and the deposition mask 25.

[0260] If the positions of the display substrate DS and the deposition mask 25 are identified (e.g., when the positions of the display substrate DS and the deposition mask 25 are identified), the second support 23 can precisely adjust the position of the deposition mask 25 to align with the display substrate DS and the deposition mask 25.

[0261] Subsequently, the deposition source 24 can be operated to spray deposition material toward the deposition mask 25 (e.g., in the -z direction), and the deposition material that has passed through the openings in the deposition mask 25 (e.g., multiple openings in the tension sheet 254) can be arranged (e.g., deposited) on the display substrate DS.

[0262] In one or more embodiments, pump 282 draws gas from chamber 21 and discharges the gas to the outside, thereby allowing the pressure inside chamber 21 to be maintained at the same or similar level as a vacuum.

[0263] The operation described above can be repeated on multiple display substrates DS. In one or more embodiments, if the number of deposits on multiple display substrates DS reaches a preset number (e.g., when the number of deposits on multiple display substrates DS reaches a preset number), the operation of the display panel manufacturing apparatus 20 can be stopped, and the deposition mask 25 can be removed to the outside of the chamber 21.

[0264] Figure 13 This is an exploded perspective view showing a deposition mask according to one or more embodiments.

[0265] refer to Figure 13 The deposition mask 25 may include a mask frame 251, a first support rod 252 and a second support rod 253, and a tensioning plate 254.

[0266] The mask frame 251 may have multiple frames connected to each other to form a space therein. In one or more embodiments, the mask frame 251 may be in the form of a picture frame with an opening 251-1 formed at its center. In one or more embodiments, the mask frame 251 may be in the form of a grid, such as a window frame including the opening 251-1. Hereinafter, for ease of explanation, the case where the mask frame 251 includes an opening 251-1 at its center will be described primarily. The length of one side (or long side) of the mask frame 251 may be greater than the length of its other side (or short side). In one or more embodiments, the side of the mask frame 251 extending in the x-direction may be defined as the long side of the mask frame 251, and the side of the mask frame 251 extending in the y-direction may be defined as the short side of the mask frame 251. The length of the long side of the mask frame 251 may be greater than the length of the short side of the mask frame 251. This disclosure is not limited thereto, and in one or more embodiments, the long side of the mask frame 251 may extend in the y direction, and the short side of the mask frame 251 may extend in the x direction.

[0267] The mask frame 251 may include a first groove 251-2 and a second groove 251-3 formed in a surface (e.g., in the -z direction). The first groove 251-2 and the second groove 251-3 may not pass through the mask frame 251 in the z direction and may be arranged at intervals. For example, multiple first grooves 251-2 may be provided, and these multiple first grooves 251-2 may be spatially connected to openings 251-1 in the mask frame 251 and may be arranged in the y direction. Similarly, multiple second grooves 251-3 may be provided, and these multiple second grooves 251-3 may be spatially connected to openings 251-1 in the mask frame 251 and may be arranged in the x direction. The first groove 251-2 and the second groove 251-3 may respectively provide space for inserting two (e.g., opposite) ends of a first support rod 252 and a second support rod 253, thereby allowing the first support rod 252 and the second support rod 253 to be secured to the mask frame 251. The first groove 251-2 may pass through the mask frame 251 in the x direction. The second groove 251-3 can pass through the mask frame 251 in the y direction.

[0268] First support rods 252 and second support rods 253 can be arranged on the mask frame 251. In this case, multiple first support rods 252 and multiple second support rods 253 can be provided, and the multiple first support rods 252 and multiple second support rods 253 can be spaced apart and / or separated from each other (e.g., separated or apart). For example, the multiple first support rods 252 and multiple second support rods 253 can be arranged parallel to one side and spaced apart and / or separated from each other (e.g., separated or apart). In one or more embodiments, the first support rod 252 can extend in the x-direction and can be arranged in the y-direction. The first support rod 252 can be parallel to the long side of the mask frame 251. The second support rod 253 can extend in the y-direction and can be arranged in the x-direction. The second support rod 253 can be parallel to the short side of the mask frame 251. In one or more embodiments, the first support rod 252 may not be provided, and only the second support rod 253 may be arranged on the mask frame 251. In one or more embodiments, the second support rod 253 may be omitted, and only the first support rod 252 may be arranged on the mask frame 251.

[0269] In one or more embodiments, the first support rod 252 may have two (e.g., opposite) ends that insert into the first recesses 251-2 and thus be fixed to the mask frame 251, and the second support rod 253 may have two (e.g., opposite) ends that insert into the second recesses 251-3 and thus be fixed to the mask frame 251. In this case, the two (e.g., opposite) side surfaces of the first support rod 252 may be coplanar with the two (e.g., opposite) side surfaces of the mask frame 251. For example, the x-direction-opposite (e.g., facing) side surface of the first support rod 252 may be coplanar with the x-direction-opposite (e.g., facing) side surface of the mask frame 251. Similarly, the two (e.g., opposite) side surfaces of the second support rod 253 may be coplanar with the two (e.g., opposite) side surfaces of the mask frame 251. For example, the side surface of the second support rod 253 opposite to the y-direction (e.g., facing) may be coplanar with the side surface of the mask frame 251 opposite to the y-direction (e.g., facing). In one or more embodiments, the first groove 251-2 and the second groove 251-3 may not be provided, and the first support rod 252 and / or the second support rod 253 may be directly arranged (e.g., welded) to the top surface of the mask frame 251 opposite to the -z-direction (e.g., facing). Figure 13 Four first support rods 252 and seven second support rods 253 are shown, but this disclosure is not necessarily limited to the specific number of first support rods 252 and second support rods 253.

[0270] Tensioner 254 can be configured as at least one. If tensioner 254 is configured as at least two (e.g., when tensioner 254 is configured as at least two), then each of the at least two tensioner 254 can have a shape extending in one direction (e.g., the y-direction) and can be arranged in another direction (e.g., the x-direction). In this case, the side of each of the at least two tensioner 254 extending in the y-direction can be understood as the long side of the tensioner 254, and the side of each of the at least two tensioner 254 extending in the x-direction can be understood as the short side of the tensioner 254. In one or more embodiments, a first support rod 252 extending in the x-direction can intersect with a plurality of tensioner 254, and a second support rod 253 extending in the y-direction can simultaneously overlap with two adjacent tensioner 254.

[0271] The tensioner 254 may include at least one opening 254OP. For example, the tensioner 254 may have a plurality of openings 254OP formed therein. In one or more embodiments, the plurality of openings 254OP in the tensioner 254 may have the same shape. For example, the plurality of openings 254OP in the tensioner 254 may have the same geometry and the same size. The plurality of openings 254OP may be spaced apart and / or separated from each other in one direction (e.g., x-direction or y-direction) at a certain interval and may pass through the tensioner 254. In one or more embodiments, some of the openings 254OP in the tensioner 254 may overlap with the first support rod 252. In one or more embodiments, the openings 254OP in the tensioner 254 may be arranged not to overlap with the first support rod 252. For example, the openings 254OP may not be arranged in the portion of the tensioner 254 that overlaps with the first support rod 252.

[0272] Tensioner tabs 254 can be attached to mask frame 251. For example, tensioner tabs 254 can be welded to the top surface (or the surface opposite to the -z direction, e.g., facing) of mask frame 251. Tensioner tabs 254 can be in contact with each other, or can be spaced apart and / or separated from each other (e.g., spaced apart or separated). If tensioner tabs 254 are spaced apart and / or separated from each other (e.g., spaced apart or separated) (e.g., when tensioner tabs 254 are spaced apart and / or separated from each other (e.g., spaced apart or separated)), a portion of the second support rod 253 can be exposed in the gap between the tensioner tabs 254.

[0273] Alignment rods 255 may be arranged on one side of the outermost tensioning plate 254. In one or more embodiments, alignment rods 255 extending in the y-direction may be arranged on the +x side of the outermost tensioning plate 254 arranged in the +x direction among a plurality of tensioning plates 254. Furthermore, alignment rods 255 extending in the y-direction may also be arranged on the -x side of the outermost tensioning plate 254 arranged in the -x direction among a plurality of tensioning plates 254. Alignment rods 255 may contact, space from, and / or separate from tensioning plates 254 (e.g., spaced apart or separated). Alignment rods 255 may serve as second alignment marks for the deposition mask 25, as referenced. Figure 12 As stated above.

[0274] Return to reference Figure 12 and combined Figure 13By passing through openings 251-1 in the mask frame 251 and multiple openings 254OP in the tension plate 254, deposition material sprayed from the deposition source 24 toward the deposition mask 25 and the display substrate DS can be arranged (e.g., deposited) on the display substrate DS. The deposition material arranged (e.g., deposited) on the display substrate DS by passing through the multiple openings 254OP in the tension plate 254 can correspond to the above reference. Figures 8A to 11B The deposition pattern DPT of the intermediate layer 114 is described.

[0275] In this case, the shape of the deposited pattern DPT can be determined by the opening 254OP in the tension sheet 254. For example, the deposited pattern DPT can have the same shape as the opening 254OP in the tension sheet 254. For example, it can be disposed on the display substrate DS (e.g., disposed on the pixel defining layer 112 (see...)). Figure 7 The shape of the deposition pattern DPT on the tension sheet 254 can be controlled or selected by the design of the shape of the opening 254OP in the tension sheet 254.

[0276] Return to reference Figure 8A and Figure 8B and combined Figure 13 Because the deposition mask 25 can be used to arrange the deposition pattern DPT of the intermediate layer 114 on multiple emitter regions EA, the positions of the multiple openings 254OP in the tensioner 254 of the deposition mask 25 can be aligned with the positions of the multiple emitter regions EA (or the positions of the multiple holes in the pixel defining layer 112). Therefore, one or more suitable tensioners 254 can be provided and utilized, which have the same characteristics as the reference... Figures 8A to 11B The arrangement of one or more suitable arrangements of the launch area EA corresponding to the arrangement of the opening 254OP.

[0277] In one or more embodiments, a first deposition pattern 114a corresponding to a first emission region EA1 can be implemented using a deposition mask 25 (e.g., a first mask), a second deposition pattern 114b corresponding to a second emission region EA2 can be implemented using another deposition mask 25 (e.g., a second mask), and a third deposition pattern 114c corresponding to a third emission region EA3 can be implemented using another deposition mask 25 (e.g., a third mask). The shape of the first deposition pattern 114a can correspond to the shape of the opening 254OP in the tensioner 254 of the first mask. The shape of the second deposition pattern 114b can correspond to the shape of the opening 254OP in the tensioner 254 of the second mask. The shape of the third deposition pattern 114c can correspond to the shape of the opening 254OP in the tensioner 254 of the third mask. In one or more embodiments, the openings 254OP in the tensioning tab 254 of the first mask, the second mask, and the third mask may have the same geometry (e.g., circular) and different dimensions (e.g., diameter). In one or more embodiments, the openings 254OP in the tensioning tab 254 of the first mask, the second mask, and the third mask may have different geometries and different dimensions.

[0278] In the following text, see references Figures 14A to 16D The shape of the opening 254OP in the tensioning plate 254 and the method of designing the opening 254OP are described, the shape of which can simultaneously correspond to the shape of one or more suitable emission regions EA. In the following description, although the first emission region EA1 is used as an example, the following description of the embodiments can be similarly (e.g., substantially equivalently) applied to the second emission region EA2 and / or the third emission region EA3.

[0279] The tensioning sheet 254 of the deposition mask 25 can have a second shape SH2 (see Figure 14B The opening 254OP of the deposition mask 25 can be provided in the tension sheet 254 of the deposition mask 25, for example, the opening 254OP in the tension sheet 254 of the deposition mask 25 can be designed to have the second shape SH2.

[0280] Figure 14A This is a schematic diagram of a launch area according to one or more embodiments. Figures 14B to 14D It is a schematic diagram of a first shape and a second shape according to one or more embodiments.

[0281] refer to Figure 14AThe first launch area EA1 may include the first-1 launch area EA1-1, the first-2 launch area EA1-2, the first-3 launch area EA1-3, and the first-4 launch area EA1-4. Figure 14A Individual first-1 transmission area EA1-1, first-2 transmission area EA1-2, first-3 transmission area EA1-3 and first-4 transmission area EA1-4 are shown, and overlapping first-1 transmission area EA1-1, first-2 transmission area EA1-2, first-3 transmission area EA1-3 and first-4 transmission area EA1-4 are also shown.

[0282] In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 can overlap each other by aligning (e.g., matching) their respective central CTs. In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 can overlap each other by spacing their respective central CTs apart. In this specification, the central CT of the first emission region EA1 may refer to the centroid of the first emission region EA1.

[0283] In one or more embodiments, the first-1 emission region EA1-1 may have a major axis extending in the x-direction and a minor axis extending in the y-direction, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-1 emission region EA1-1 may have a shape obtained by rotating the first-4 emission region EA1-4 clockwise by approximately 45 degrees.

[0284] In one or more embodiments, the first-2 emission region EA1-2 may have a major axis extending in a first direction DR1 and a minor axis extending in a second direction DR2, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-2 emission region EA1-2 may have a shape obtained by rotating the first-1 emission region EA1-1 clockwise by approximately 45 degrees.

[0285] In one or more embodiments, the first-3 emission region EA1-3 may have a major axis extending in the y-direction and a minor axis extending in the x-direction, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-3 emission region EA1-3 may have a shape obtained by rotating the first-2 emission region EA1-2 clockwise by approximately 45 degrees.

[0286] In one or more embodiments, the first-4 emission region EA1-4 may have a major axis extending in the second direction DR2 and a minor axis extending in the first direction DR1, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-4 emission region EA1-4 may have a shape obtained by rotating the first-3 emission region EA1-3 clockwise by approximately 45 degrees.

[0287] In the following text, see references Figures 14A to 14D The first shape SH1 and the second shape SH2 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4. In one or more embodiments, the first shape SH1 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4.

[0288] In one or more embodiments, such as Figure 14B As shown, the first shape SH1 can be obtained by drawing the outermost line of a shape (e.g., an atomic model shape) obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 with each other. In one or more embodiments, the first shape SH1 can be obtained by connecting portions of the respective contours of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 with each other.

[0289] In one or more embodiments, such as Figure 14C and Figure 14D As shown, the first shape SH1 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 with each other, and then arranging tangents between each of the adjacent first emission regions EA1 and drawing the outermost line. Therefore, Figure 14C and Figure 14D The first shape SH1 in the model can be an octagon with approximately rounded corners.

[0290] The size of the second shape SH2, corresponding to the first shape SH1, can be larger than the size of the first shape SH1.

[0291] In one or more embodiments, such as Figure 14B and Figure 14CAs shown, the second shape SH2 can be geometrically identical to the first shape SH1, and can have larger dimensions than the first shape SH1. For example, the second shape SH2 can be geometrically identical to the first shape SH1, but can extend the process allowance MG in all directions.

[0292] In one or more embodiments, such as Figure 14D As shown, the second shape SH2 may be geometrically different from the first shape SH1 and may have a larger dimension than the first shape SH1. For example, the second shape SH2 may be circular or elliptical, each extending a process allowance MG from the outermost edge of the first shape SH1. In this respect, the outermost edge of the first shape SH1 may refer to, for example, the rounded corner of the first shape SH1.

[0293] Figure 15A This is a schematic diagram of a launch area according to one or more embodiments. Figures 15B to 15D It is a schematic diagram of a first shape and a second shape according to one or more embodiments.

[0294] refer to Figure 15A The first launch area EA1 may include the first-1 launch area EA1-1, the first-2 launch area EA1-2, the first-3 launch area EA1-3, the first-4 launch area EA1-4, the first-5 launch area EA1-5, and the first-6 launch area EA1-6. Figure 15A Individual first-1 transmission area EA1-1, first-2 transmission area EA1-2, first-3 transmission area EA1-3, first-4 transmission area EA1-4, first-5 transmission area EA1-5, and first-6 transmission area EA1-6 are shown, as well as overlapping first-1 transmission area EA1-1, first-2 transmission area EA1-2, first-3 transmission area EA1-3, first-4 transmission area EA1-4, first-5 transmission area EA1-5, and first-6 transmission area EA1-6 are also shown.

[0295] In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6 can overlap each other by aligning (e.g., matching) their respective central CTs. In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6 can overlap each other by spacing their respective central CTs apart.

[0296] In one or more embodiments, the third direction DR3 may form an angle of approximately 60 degrees with the +y direction and an angle of approximately 150 degrees with the +x direction. In one or more embodiments, the fourth direction DR4 may form an angle of approximately 30 degrees with the +y direction and an angle of approximately 120 degrees with the +x direction. In one or more embodiments, the fifth direction DR5 may form an angle of approximately 30 degrees with the +y direction and an angle of approximately 60 degrees with the +x direction. In one or more embodiments, the sixth direction DR6 may form an angle of approximately 60 degrees with the +y direction and an angle of approximately 30 degrees with the +x direction. In one or more embodiments, the third direction DR3 and the fifth direction DR5 may be orthogonal to each other (e.g., perpendicular). In one or more embodiments, the fourth direction DR4 and the sixth direction DR6 may be orthogonal to each other (e.g., perpendicular).

[0297] In one or more embodiments, the first-1 emission region EA1-1 may have a major axis extending in the x-direction and a minor axis extending in the y-direction, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-1 emission region EA1-1 may have a shape obtained by rotating the first-6 emission region EA1-6 clockwise by approximately 30 degrees.

[0298] In one or more embodiments, the first-2 emission region EA1-2 may have a major axis extending in the third direction DR3 and a minor axis extending in the fifth direction DR5, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-2 emission region EA1-2 may have a shape obtained by rotating the first-1 emission region EA1-1 clockwise by approximately 30 degrees.

[0299] In one or more embodiments, the first-3 emission region EA1-3 may have a major axis extending in the fourth direction DR4 and a minor axis extending in the sixth direction DR6, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-3 emission region EA1-3 may have a shape obtained by rotating the first-2 emission region EA1-2 clockwise by approximately 30 degrees.

[0300] In one or more embodiments, the first-4 emission region EA1-4 may have a major axis extending in the y-direction and a minor axis extending in the x-direction, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-4 emission region EA1-4 may have a shape obtained by rotating the first-3 emission region EA1-3 clockwise by approximately 30 degrees.

[0301] In one or more embodiments, the first-5 emission region EA1-5 may have a major axis extending in the fifth direction DR5 and a minor axis extending in the third direction DR3, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-5 emission region EA1-5 may have a shape obtained by rotating the first-4 emission region EA1-4 clockwise by approximately 30 degrees.

[0302] In one or more embodiments, the first-6 emission region EA1-6 may have a major axis extending in the sixth direction DR6 and a minor axis extending in the fourth direction DR4, and may be symmetrical about the major and minor axes. In one or more embodiments, the first-6 emission region EA1-6 may have a shape obtained by rotating the first-5 emission region EA1-5 clockwise by approximately 30 degrees.

[0303] In the following text, see references Figures 15A to 15D The first shape SH1 and the second shape SH2 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6. In one or more embodiments, the first shape SH1 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6.

[0304] In one or more embodiments, such as Figure 15B As shown, the first shape SH1 can be obtained by drawing the outermost line of a shape (e.g., an atomic model shape) obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6 with each other. In one or more embodiments, the first shape SH1 can be obtained by connecting portions of the respective contours of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6 with each other.

[0305] In one or more embodiments, such as Figure 15C and Figure 15DAs shown, the first shape SH1 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, and the first-6 emission region EA1-6 with each other, and then arranging tangents between each of the adjacent first emission regions EA1 and drawing the outermost line. Therefore, Figure 15C and Figure 15D The first shape SH1 in the equation can be a dodecagon with approximately rounded corners.

[0306] The size of the second shape SH2, corresponding to the first shape SH1, can be larger than the size of the first shape SH1.

[0307] In one or more embodiments, such as Figure 15B and Figure 15C As shown, the second shape SH2 can be geometrically identical to the first shape SH1, and can have larger dimensions than the first shape SH1. For example, the second shape SH2 can be geometrically identical to the first shape SH1, but can extend the process allowance MG in all directions.

[0308] In one or more embodiments, such as Figure 15D As shown, the second shape SH2 may be geometrically different from the first shape SH1 and may have a larger dimension than the first shape SH1. For example, the second shape SH2 may be circular or elliptical, each extending a process allowance MG from the outermost edge of the first shape SH1. In this respect, the outermost edge of the first shape SH1 may refer to, for example, the rounded corner of the first shape SH1.

[0309] Figure 16A This is a schematic diagram of a launch area according to one or more embodiments. Figures 16B to 16D It is a schematic diagram of a first shape and a second shape according to one or more embodiments.

[0310] refer to Figure 16A The first transmission area EA1 may include the first-1 transmission area EA1-1, the first-2 transmission area EA1-2, the first-3 transmission area EA1-3, the first-4 transmission area EA1-4, the first-5 transmission area EA1-5, the first-6 transmission area EA1-6, the first-7 transmission area EA1-7, the first-8 transmission area EA1-8, the first-9 transmission area EA1-9, the first-10 transmission area EA1-10, the first-11 transmission area EA1-11, and the first-12 transmission area EA1-12. Figure 16AThe following are shown as separate launch zones: EA1-1 (first-1), EA1-2 (first-2), EA1-3 (first-3), EA1-4 (first-4), EA1-5 (first-5), EA1-6 (first-6), EA1-7 (first-7), EA1-8 (first-8), EA1-9 (first-9), EA1-10 (first-10), EA1-11 (first-11), and EA1-12 (first-12). The first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12, which overlap with each other, are also shown.

[0311] In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12 can overlap each other by aligning (e.g., matching) their respective central CTs. In one or more embodiments, the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12 can overlap each other by spacing their respective central CTs apart. As mentioned above, the central CT can refer to the centroid.

[0312] In one or more embodiments, the first-1 emission region EA1-1 may have a major axis extending in the x-direction and a minor axis extending in the y-direction, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-1 emission region EA1-1 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the -x direction is greater than its length in the +x direction. In one or more embodiments, the first-1 emission region EA1-1 may have a shape obtained by rotating the first-12 emission region EA1-12 clockwise by approximately 30 degrees.

[0313] In one or more embodiments, the first-2 emission region EA1-2 may have a major axis extending in the third direction DR3 and a minor axis extending in the fifth direction DR5, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-2 emission region EA1-2 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the third direction DR3 is greater than its length in the direction opposite to the third direction DR3. In one or more embodiments, the first-2 emission region EA1-2 may have a shape obtained by rotating the first-1 emission region EA1-1 clockwise by approximately 30 degrees.

[0314] In one or more embodiments, the first-3 emission region EA1-3 may have a major axis extending in the fourth direction DR4 and a minor axis extending in the sixth direction DR6, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-3 emission region EA1-3 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the fourth direction DR4 is greater than its length in the direction opposite to the fourth direction DR4. In one or more embodiments, the first-3 emission region EA1-3 may have a shape obtained by rotating the first-2 emission region EA1-2 clockwise by approximately 30 degrees.

[0315] In one or more embodiments, the first-4 emission region EA1-4 may have a major axis extending in the y-direction and a minor axis extending in the x-direction, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-4 emission region EA1-4 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the +y direction is greater than its length in the -y direction. In one or more embodiments, the first-4 emission region EA1-4 may have a shape obtained by rotating the first-3 emission region EA1-3 clockwise by approximately 30 degrees.

[0316] In one or more embodiments, the first-5 emission region EA1-5 may have a major axis extending in the fifth direction DR5 and a minor axis extending in the third direction DR3, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-5 emission region EA1-5 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the fifth direction DR5 is greater than its length in the direction opposite to the fifth direction DR5. In one or more embodiments, the first-5 emission region EA1-5 may have a shape obtained by rotating the first-4 emission region EA1-4 clockwise by approximately 30 degrees.

[0317] In one or more embodiments, the first-6 emission region EA1-6 may have a major axis extending in the sixth direction DR6 and a minor axis extending in the fourth direction DR4, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-6 emission region EA1-6 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the sixth direction DR6 is greater than its length in the direction opposite to the sixth direction DR6. In one or more embodiments, the first-6 emission region EA1-6 may have a shape obtained by rotating the first-5 emission region EA1-5 clockwise by approximately 30 degrees.

[0318] In one or more embodiments, the first-7 emission region EA1-7 may have a major axis extending in the x-direction and a minor axis extending in the y-direction, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-7 emission region EA1-7 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the -x direction is less than its length in the +x direction. In one or more embodiments, the first-7 emission region EA1-7 may have a shape obtained by rotating the first-6 emission region EA1-6 clockwise by approximately 30 degrees. In one or more embodiments, the first-7 emission region EA1-7 may be a mirror image of the first-1 emission region EA1-1 with respect to the y-direction.

[0319] In one or more embodiments, the first-8 emission region EA1-8 may have a major axis extending in the third direction DR3 and a minor axis extending in the fifth direction DR5, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-8 emission region EA1-8 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the third direction DR3 is less than its length in the direction opposite to the third direction DR3. In one or more embodiments, the first-8 emission region EA1-8 may have a shape obtained by rotating the first-7 emission region EA1-7 clockwise by approximately 30 degrees. In one or more embodiments, the first-8 emission region EA1-8 may be a mirror image of the first-2 emission region EA1-2 relative to the fifth direction DR5.

[0320] In one or more embodiments, the first-9 emission region EA1-9 may have a major axis extending in the fourth direction DR4 and a minor axis extending in the sixth direction DR6, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-9 emission region EA1-9 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the fourth direction DR4 is less than its length in the direction opposite to the fourth direction DR4. In one or more embodiments, the first-9 emission region EA1-9 may have a shape obtained by rotating the first-8 emission region EA1-8 clockwise by approximately 30 degrees. In one or more embodiments, the first-9 emission region EA1-9 may be a mirror image of the first-3 emission region EA1-3 relative to the sixth direction DR6.

[0321] In one or more embodiments, the first-10 emission region EA1-10 may have a major axis extending in the y-direction and a minor axis extending in the x-direction, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-10 emission region EA1-10 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the +y direction is less than its length in the -y direction. In one or more embodiments, the first-10 emission region EA1-10 may have a shape obtained by rotating the first-9 emission region EA1-9 clockwise by approximately 30 degrees. In one or more embodiments, the first-10 emission region EA1-10 may be a mirror image of the first-4 emission region EA1-4 with respect to the x-direction.

[0322] In one or more embodiments, the first-11 emission region EA1-11 may have a major axis extending in the fifth direction DR5 and a minor axis extending in the third direction DR3, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-11 emission region EA1-11 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the fifth direction DR5 is less than its length in the direction opposite to the fifth direction DR5. In one or more embodiments, the first-11 emission region EA1-11 may have a shape obtained by rotating the first-10 emission region EA1-10 clockwise by approximately 30 degrees. In one or more embodiments, the first-11 emission region EA1-11 may be a mirror image of the first-5 emission region EA1-5 relative to the third direction DR3.

[0323] In one or more embodiments, the first-12 emission region EA1-12 may have a major axis extending in the sixth direction DR6 and a minor axis extending in the fourth direction DR4, and may be symmetrical about the major axis and asymmetrical about the minor axis. In one or more embodiments, the first-12 emission region EA1-12 may have an asymmetrical elliptical shape relative to the minor axis, the length of which in the sixth direction DR6 is less than its length in the direction opposite to the sixth direction DR6. In one or more embodiments, the first-12 emission region EA1-12 may have a shape obtained by rotating the first-11 emission region EA1-11 clockwise by approximately 30 degrees. In one or more embodiments, the first-12 emission region EA1-12 may be a mirror image of the first-6 emission region EA1-6 relative to the fourth direction DR4.

[0324] In the following text, see references Figures 16A to 16DThe first shape SH1 and the second shape SH2 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12. In one or more embodiments, the first shape SH1 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12 with each other.

[0325] In one or more embodiments, such as Figure 16B As shown, the first shape SH1 can be obtained by drawing the outermost line of a shape (e.g., an atomic model shape) obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12 with each other. In one or more embodiments, the first shape SH1 can be obtained by connecting portions of the respective contours of the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12 to each other.

[0326] In one or more embodiments, such as Figure 16C and Figure 16DAs shown, the first shape SH1 can be obtained by overlapping the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, the first-4 emission region EA1-4, the first-5 emission region EA1-5, the first-6 emission region EA1-6, the first-7 emission region EA1-7, the first-8 emission region EA1-8, the first-9 emission region EA1-9, the first-10 emission region EA1-10, the first-11 emission region EA1-11, and the first-12 emission region EA1-12 with each other, and then tangents are arranged between each of the adjacent first emission regions EA1 and the outermost line is drawn. Therefore, Figure 16C and Figure 16D The first shape SH1 in the equation can be a dodecagon with approximately rounded corners.

[0327] The size of the second shape SH2, corresponding to the first shape SH1, can be larger than the size of the first shape SH1.

[0328] In one or more embodiments, such as Figure 16B and Figure 16C As shown, the second shape SH2 can be geometrically identical to the first shape SH1, and can have larger dimensions than the first shape SH1. For example, the second shape SH2 can be geometrically identical to the first shape SH1, but can extend the process allowance MG in all directions.

[0329] In one or more embodiments, such as Figure 16D As shown, the second shape SH2 may be geometrically different from the first shape SH1 and may have a larger dimension than the first shape SH1. For example, the second shape SH2 may be circular or elliptical, each extending a process allowance MG from the outermost edge of the first shape SH1. In this respect, the outermost edge of the first shape SH1 may refer to, for example, the rounded corner of the first shape SH1.

[0330] In one or more embodiments, if a sufficient number of first emission regions EA1 are provided (e.g., when a sufficient number of first emission regions EA1 are provided), the first shape SH1 can be a shape close to a curved body (e.g., circular or elliptical) with substantially no recessed portions. For example, if the number of first emission regions EA1 has reached or exceeded a threshold (e.g., when the number of first emission regions EA1 has reached or exceeded a threshold), such a number of first emission regions EA1 can make the first shape SH1 close to a circular or elliptical shape because the angle formed by the major axes of any two adjacent first emission regions (e.g., first-1 emission region EA1-1 and first-2 emission region EA1-2) is small enough to form nearly (e.g., almost) curved edges at the two (e.g., opposite) ends on the major / longitudinal axes of the two adjacent first emission regions. Even in this case, the second shape SH2 can be geometrically identical to the first shape SH1 or can be geometrically different from the first shape SH1. In either case, the second shape SH2 can ensure a process allowance MG relative to the first shape SH1.

[0331] In one or more embodiments, combined Figures 16A to 16D refer to Figure 12 and Figure 13 If a deposition process is performed on a display substrate DS using a deposition mask 25 including a tension sheet 254 having an opening 254OP having a second shape SH2 (e.g., when a deposition process is performed on a display substrate DS using a deposition mask 25 including a tension sheet 254OP having an opening 254OP having a second shape SH2), then if viewed in the deposition direction (e.g., the z-direction), the edge of the opening 254OP in the tension sheet 254 may be spaced apart and / or separated from the edge (or profile) of the corresponding emission region EA (e.g., separated or separated).

[0332] By implementing the opening 254OP with the second shape SH2 as described above, a process margin MG can be ensured for the deposition error of the deposited material that has passed through the tension sheet 254 of the deposition mask 25 for all emission regions EA. For example, combined with Figures 16A to 16D refer to Figure 8B and Figure 14DBy utilizing an opening 254OP that is larger than the process allowance MG in the x-direction edge of the outermost edge of the first-1 emission region EA1-1, it can be ensured that the first-1 deposition pattern 114a1 completely covers the first-1 emission region EA1-1. This coverage can be similarly ensured for the first-2 emission region EA1-2 and the first-2 deposition pattern 114a2, the first-3 emission region EA1-3 and the first-3 deposition pattern 114a3, and the first-4 emission region EA1-4 and the first-4 deposition pattern 114a4. Meanwhile, instead of providing openings 254OP in the tensioning sheet 254 that have different shapes, such as those corresponding to the first-1 emission region EA1-1, the first-2 emission region EA1-2, the first-3 emission region EA1-3, and the first-4 emission region EA1-4 respectively, an opening 254OP with a single shape (e.g., a second shape SH2) can be provided in the tensioning sheet 254. This facilitates the design and manufacture of the tensioning sheet 254 and the deposition mask 25, and further reduces errors that may occur in the deposition process.

[0333] For example, when a sufficient number of first emission regions EA1 are provided, the first shape SH1 can resemble a curved body, such as a circle or ellipse, without recessed portions. This shape is achieved by overlapping the emission regions EA to form nearly curved edges. The second shape SH2 used in the deposition mask 25 may be geometrically similar to or different from the first shape SH1, but ensures the following: a process allowance MG is guaranteed. During the deposition process, when viewed in the deposition direction, the openings 254OP with the second shape SH2 in the tensioner 254 are spaced apart from the edges of the emission regions EA. This design ensures a process allowance MG for deposition errors and ensures complete coverage of the emission regions EA by the deposition pattern. Using a single-shape opening 254OP in the tensioner 254 facilitates design and manufacturing, thereby reducing errors in the deposition process.

[0334] The foregoing has described a method for designing a second shape SH2 and a tensioning sheet 254 including an opening 254OP having a single shape (e.g., the second shape SH2) capable of covering one or more suitable emission regions EA. This disclosure is not necessarily limited to the references. Figures 8A to 11B The arrangement of the launch area EA is described. Furthermore, this disclosure is not necessarily limited to reference. Figures 14A to 16D The shape of the emission region EA (e.g., elliptical shape).

[0335] In one or more embodiments, a display panel manufacturing apparatus including a deposition mask, a method for manufacturing a display panel by performing a deposition process using a deposition mask, a display panel manufactured using such a manufacturing apparatus and / or manufacturing method, and an electronic device including such a display panel can be provided.

[0336] The display panel may include emission regions having one or more suitable shapes. The deposition mask does not have openings of shapes that correspond to one or more suitable shapes of the emission regions of the display panel, but may instead have a single opening of a shape that can cover all one or more suitable shapes of the emission regions.

[0337] Because the openings formed in the deposition mask can have a single shape rather than separate shapes corresponding to the emission regions, the production time and cost of the deposition mask can be reduced. Furthermore, because the deposition mask includes openings of one or more suitable shapes that can cover all of the emission regions, process margins can be ensured during the deposition process, and misalignment of the deposited material can be reduced.

[0338] In the context of this disclosure, and unless otherwise specified, the terms “use / utilization”, “currently used / utilized” and “used / utilized” may be considered synonymous with the terms “utilization”, “currently utilized” and “utilized”, respectively.

[0339] In light of the entire contents of this disclosure, those skilled in the art will understand that each suitable feature of one or more suitable embodiments of this disclosure may be combined in part or in whole, or combined with one another (or each other), and may be technically interlocked and operated in one or more suitable ways, and each embodiment may be implemented independently of one another (or each other) or in combination with one another (or each other) in any suitable way, unless otherwise stated or implied.

[0340] The display device / apparatus, electronic device / apparatus, manufacturing apparatus, or any other related device / apparatus or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. Alternatively, various components of the device can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard storage devices such as, for example, random access memory (RAM). The computer program instructions can also be stored on other non-transitory computer-readable media, such as, for example, CD-ROMs, flash drives, etc. Furthermore, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of the embodiments of this disclosure.

[0341] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to one or more embodiments of this application without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments of this disclosure are used in a general and descriptive sense only and not for limiting purposes.

[0342] It should be understood that the embodiments described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in one or more embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that one or more suitable changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents. Furthermore, it should be understood that one or more embodiments of this disclosure are not intended to limit this disclosure, and every technical idea within the appended claims and their equivalents is to be included within the scope of this disclosure and its equivalents.

Claims

1. An apparatus for manufacturing a display panel including multiple emission areas, comprising: Sediment source; as well as The deposition mask includes a plurality of openings corresponding to the plurality of emission regions of the display panel. Wherein, at least some of the plurality of openings in the deposition mask have a second shape corresponding to a first shape obtained by overlapping the plurality of emission regions with each other.

2. The apparatus according to claim 1, wherein, The first shape is obtained by connecting at least some of the outermost portions of the plurality of overlapping emission regions.

3. The apparatus according to claim 1, wherein, The shape of at least one of the plurality of launch regions is different from the shape of another launch region selected from the plurality of launch regions.

4. The apparatus according to claim 1, wherein, The first shape is obtained by aligning the centers of the plurality of emission regions and overlapping the plurality of emission regions.

5. The apparatus according to claim 1, wherein, The plurality of openings in the deposition mask have the same shape as each other.

6. The apparatus according to claim 1, wherein, The size of the second shape is larger than the size of the first shape.

7. The apparatus according to claim 6, wherein, The first shape and the second shape are geometrically identical, and the outer dimensions of the second shape are larger than those of the first shape.

8. The apparatus according to claim 1, wherein, In the plan view, the edge of each of the plurality of openings in the deposition mask is spaced apart from or separated from the contour of each of the plurality of emission regions.

9. The apparatus according to claim 1, wherein, The plurality of emission regions have an elliptical shape, the elliptical shape having a major axis extending in different directions from each other.

10. A method for manufacturing a display panel, comprising: A pixel-defining layer comprising multiple emission regions is arranged on a substrate; A deposition mask is disposed on the pixel-defining layer, the deposition mask including a plurality of openings corresponding to the plurality of emission regions; as well as Spraying deposited material toward the deposition mask and the pixel defining layer, Wherein, at least some of the plurality of openings in the deposition mask have a second shape corresponding to a first shape obtained by overlapping the plurality of emission regions.

11. The method according to claim 10, wherein, The first shape is obtained by connecting at least some of the outermost portions of the plurality of overlapping emission regions.

12. The method according to claim 10, wherein, The shape of at least one of the plurality of launch regions is different from the shape of another launch region selected from the plurality of launch regions.

13. The method according to claim 10, wherein, The first shape is obtained by aligning the centers of the plurality of emission regions and overlapping the plurality of emission regions.

14. The method of claim 10, wherein, The plurality of openings in the deposition mask have the same shape as each other.

15. The method according to claim 10, wherein, The size of the second shape is larger than the size of the first shape.

16. The method according to claim 15, wherein, The first shape and the second shape are geometrically identical, and the outer dimensions of the second shape are larger than those of the first shape.

17. The method according to claim 10, wherein, The pixel defining layer includes a plurality of holes defining the plurality of emission regions, and The edge of each of the plurality of openings in the deposition mask is spaced apart from the edge of each of the plurality of holes in the pixel defining layer in the direction of the deposition material ejection.

18. The method according to claim 10, wherein, The plurality of emission regions have an elliptical shape, the elliptical shape having a major axis extending in different directions from each other.

19. An electronic device including a display panel, the display panel including a plurality of emitting areas, wherein, The display panel includes: Substrate; Multiple pixel electrodes are disposed on the substrate; A pixel defining layer is provided on the plurality of pixel electrodes and includes a plurality of holes defining the plurality of emission regions; An intermediate layer, overlapping the plurality of holes on the pixel-defining layer, and comprising a plurality of deposition patterns, each of the plurality of deposition patterns having a portion disposed within a corresponding hole in the plurality of holes; and The opposite electrode is located on the intermediate layer. In the plan view, at least some of the plurality of deposition patterns have a second shape corresponding to a first shape obtained by overlapping the plurality of holes.

20. The electronic device according to claim 19, wherein, One of the plurality of deposition patterns has a first portion at the corresponding hole in the pixel defining layer and a second portion on the top surface of the pixel defining layer, and The first portion of the deposition pattern is connected to the second portion of the deposition pattern.

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