General multi-bank memory model system and memory verification method
By designing a general multi-bank memory model system, the problems of low efficiency, high cost, and insufficient flexibility in existing memory verification methods are solved. It realizes flexible configuration and efficient multi-bank memory architecture support, thereby improving the efficiency and accuracy of chip verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHONGHAO XINYING (HANGZHOU) TECH CO LTD
- Filing Date
- 2026-04-30
- Publication Date
- 2026-06-02
AI Technical Summary
Existing memory verification methods are inefficient, costly, and lack flexibility, and are difficult to effectively support multi-bank memory architectures, resulting in low chip verification efficiency and increased complexity.
A general-purpose multi-bank memory model system is designed, including a UVM verification environment layer, a parameter configuration layer, a multi-bank controller layer, a basic storage unit array layer, a shadow storage array layer, and a hardware backdoor interface layer. Through intelligent address mapping and automatic ECC generation, it supports parallel processing and rapid debugging of multi-bank architecture.
It enables flexible memory model configuration, improves verification efficiency, reduces redundant development costs, supports parallel processing and rapid initialization of multi-bank architecture, and ensures verification accuracy and debugging capabilities.
Smart Images
Figure CN122132222A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip verification technology, and in particular relates to a general multi-bank memory model system and memory verification method. Background Technology
[0002] In the field of modern chip verification, memory models, as a core component of the verification environment, directly impact verification efficiency and quality through their design and implementation. Current chip designs are becoming increasingly complex, requiring verification testing of memory modules with different specifications for each project. However, traditional memory verification methods suffer from numerous technical bottlenecks and practical application problems.
[0003] First, there is a serious problem of redundant development. In the traditional verification process, each chip project requires rewriting dedicated memory model code. This not only wastes a lot of human resources, but also prolongs the verification environment setup cycle, resulting in low development efficiency.
[0004] Secondly, commercial tools are expensive and lack flexibility. While third-party memory verification tools on the market are relatively complete in function, they are expensive, have a complex integration process, and often cannot fully meet the customized needs of specific projects.
[0005] Then there's the problem of low debugging efficiency. Traditional memory verification methods have significant shortcomings in data loading and debugging, especially when dealing with large amounts of memory. Data initialization is slow, and the debugging process is cumbersome, seriously affecting simulation efficiency and debugging cycle.
[0006] Finally, there is the issue of insufficient support for multi-bank (multiple independent, parallel-accessible sub-memory units divided into rows / columns) architectures. With the development of modern high-performance chip design, multi-bank memory architectures have become mainstream, but existing verification schemes struggle to effectively support complex multi-bank memory architectures and cannot meet the verification requirements of complex memory systems in modern high-performance chips. Summary of the Invention
[0007] In view of this, embodiments of the present invention provide a general multi-bank memory model system and memory verification method to solve the problems of low efficiency, high cost, insufficient flexibility and difficulty in effectively supporting multi-bank memory architectures in existing memory verification methods.
[0008] In a first aspect, embodiments of the present invention provide a general multi-bank memory model system, comprising: The UVM verification environment layer provides a standardized UVM interface to enable interaction with upper-layer UVM verification components. The parameter configuration layer is used to configure the key parameters of the Bank model. The multi-Bank controller layer is used to achieve unified management of the multi-Bank architecture, including receiving access incentives from the UVM verification environment layer, resolving the system's total address into Bank number and Bank address through intelligent address mapping, and scheduling the corresponding Bank model to complete read and write operations. The basic storage unit array layer consists of multiple independent Bank models. Each Bank model generates storage units of corresponding specifications based on the key parameters of the parameter configuration layer. The shadow storage array layer is used to maintain a state mirror of the actual hardware memory, recording the original data and ECC checksum for each storage address; The hardware backdoor interface layer is used for backdoors to access actual hardware memory.
[0009] In one possible implementation, the key parameters of the Bank model include: address bit width, data bit width, storage depth, number of Banks, and ECC bit width.
[0010] In one possible implementation, the parameter configuration layer is further used to configure the system's initialization mode; the initialization mode includes at least one of the following: unknown state mode, all 0 mode, all 1 mode, address self-filling mode, and random filling mode.
[0011] In one possible implementation, the shadow storage array layer is used to: automatically call the ECC checksum generation function when the ECC bit width is greater than 0, calculate the ECC checksum for each storage address, and store it in association with the original data.
[0012] In one possible implementation, the hardware backdoor interface layer supports batch backdoor access to actual hardware memory.
[0013] In one possible implementation, the general multi-bank memory model system further includes: a data consistency check module; the data consistency check module is used to: traverse all addresses of the shadow storage array layer, obtain the expected value of each address, read the actual value of the actual hardware memory layer through the hardware backdoor interface layer, compare the expected value with the actual value, and record the inconsistency information.
[0014] In one possible implementation, the general multi-bank memory model system further includes a file operation module; the file operation module is used to enable bidirectional interaction between memory data and external files.
[0015] Secondly, embodiments of the present invention provide a memory verification method, which is applied to a general multi-bank memory model system in the first aspect or any implementation of the first aspect; The method includes: Configure the key parameters and initialization mode of the Bank model; According to the initialization mode, perform memory initialization operation. If ECC function is enabled, automatically calculate the ECC checksum of the data and store it in the shadow storage array. The UVM verification environment sends memory access stimuli. After receiving the stimuli, the multi-Bank controller resolves the system's total address into Bank number and Bank address through intelligent address mapping, and schedules the corresponding Bank model to complete the read and write operations. The read and write results are returned to the UVM verification environment.
[0016] In one possible implementation, the method further includes: Once verification is complete, a data consistency check is triggered. All memory addresses are traversed, and the data and ECC checksum of the shadow storage array are compared with those of the actual hardware memory. Inconsistency information is recorded.
[0017] In one possible implementation, the method further includes: The system checks the coverage rate. If the coverage rate meets the standard and there are no data inconsistency errors, the memory verification is considered successful; otherwise, the error is located and the verification process is re-executed.
[0018] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: This invention proposes a general multi-bank memory model system. The system's basic storage unit array layer consists of multiple independent bank models. Each bank model generates storage units of corresponding specifications based on key parameters from the parameter configuration layer. The parameter configuration layer allows for customization of various characteristics of the storage units, achieving highly flexible configuration capabilities. With the help of a multi-bank controller layer, the system can automatically schedule multiple storage units to work collaboratively, possessing true parallel processing capabilities. Its intelligent address mapping function automatically routes user-input addresses to the correct bank and storage location, eliminating the need for users to concern themselves with complex address mapping details. The shadow storage array layer supports the system in simultaneously maintaining the state of the software model (shadow storage array) and the hardware memory, ensuring verification accuracy and providing the system with powerful debugging capabilities. The hardware backdoor interface layer provides the system with rapid debugging and initialization capabilities through a backdoor access mechanism. This system can quickly generate memory models of corresponding specifications according to different verification requirements. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of the structure of the general multi-bank memory model system provided in the embodiments of the present invention; Figure 2 This is a schematic diagram illustrating the implementation process of the memory verification method provided in this embodiment of the invention. Detailed Implementation
[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.
[0022] To illustrate the technical solution described in this invention, specific embodiments are described below.
[0023] This invention primarily addresses several key application areas in modern chip verification. For example, in SoC chip verification projects, comprehensive verification of various memory components of the on-chip system is required, including processor cache, on-chip SRAM, and various dedicated storage units. In the field of memory verification, functional verification and performance testing of various storage capacities and storage unit partitions are covered. In high-performance computing chip verification, verification of large-capacity, high-bandwidth memory subsystems is required to ensure their stability and performance under high load conditions. In AI chip storage subsystem verification, special application scenarios such as neural network weight storage and activation data caching need to be addressed. Furthermore, in multi-core processor cache system verification, verification of complex cache coherency protocols and multi-level cache architectures is necessary.
[0024] Traditional memory models suffer from severe inflexibility in parameter configuration, mostly employing fixed parameter designs that struggle to adapt to the diverse needs of different verification scenarios. Each time a new memory specification is encountered, redesign and reimplementation are often required. Regarding multi-bank architecture support, existing solutions lack effective mechanisms, particularly in intelligent address mapping and inter-bank coordination, failing to fully leverage the performance advantages of multi-bank architectures. In terms of UVM integration, existing memory models have limited integration with UVM verification methodologies, lacking standardized interfaces and usage methods, resulting in high integration complexity and learning costs. Regarding front-door and back-door access mechanisms, traditional solutions are inadequate in front-door and back-door access and model synchronization, particularly in the rapid initialization and real-time debugging of large-capacity memory. Finally, in terms of ECC (Error Checking and Correction) support, existing solutions lack automated error detection and correction code generation mechanisms, requiring manual calculation and management of ECC checksums, increasing verification complexity and error probability.
[0025] The core innovation of this invention lies in the design of a highly parameterized and modular memory verification solution, capable of rapidly generating memory models of corresponding specifications according to different verification requirements. By flexibly combining different parameters and modules, the system can construct memory models adaptable to various application scenarios. The system has the following core features: First, parameterized configuration capability, allowing users to flexibly combine different configuration parameters like building blocks, enabling a single codebase to adapt to multiple application scenarios; second, a dual storage mechanism, where the system simultaneously maintains the state of the software model (shadow storage array) and hardware memory, ensuring verification accuracy while providing powerful debugging capabilities; third, multi-bank architecture support, enabling the system to automatically manage the collaborative work of multiple storage units, achieving true parallel processing capabilities; fourth, intelligent address mapping function, automatically routing user-provided addresses to the correct bank and storage location, eliminating the need for users to concern themselves with complex address mapping details; and fifth, automatic ECC generation capability, intelligently generating and managing error detection and correction codes, simplifying ECC-related verification work.
[0026] Figure 1 This is a schematic diagram of the structure of a general multi-bank memory model system provided in an embodiment of the present invention. See also... Figure 1 As shown, this system includes: UVM verification environment layer 11 is used to provide a standardized UVM interface to enable interaction with the upper-layer UVM verification components.
[0027] Parameter configuration layer 12 is used to configure key parameters of the Bank model. This layer is responsible for setting and managing various configuration parameters, including key parameters such as address width, data width, storage depth, number of Banks, and ECC width.
[0028] The multi-bank controller layer 13 is used to realize unified management of the multi-bank architecture, including receiving access incentives from the UVM verification environment layer, resolving the system's total address into bank number and internal bank address through intelligent address mapping, and scheduling the corresponding bank model to complete read and write operations.
[0029] The basic storage unit array layer 14 consists of multiple independent Bank models. Each Bank model generates storage units of corresponding specifications based on key parameters of the parameter configuration layer. The Bank model defines the basic characteristics of memory through four key parameters: address width, which determines the number of addressable storage locations; data width, which determines the amount of data that can be stored at one time; storage depth, which determines the total capacity of memory; and ECC width, which determines the error detection and correction capabilities.
[0030] Shadow storage array layer 15 maintains a state mirror of the actual hardware memory, recording the raw data and ECC checksum for each storage address. Shadow storage array layer 15 maintains a complete memory state mirror in software, recording what data should be stored at each storage location, including the raw data and ECC checksum. Through this shadow storage array, the system can quickly perform data queries, state checks, and consistency verifications without accessing the actual hardware memory each time.
[0031] Hardware backdoor interface layer 16 is used for backdoor access to actual hardware memory. The backdoor access mechanism provides the ability to directly access hardware memory, bypassing normal clock cycles and protocol processes. The backdoor write function accepts address and data as parameters to construct the corresponding backdoor path, directly reading and writing to specified locations in hardware memory. The main advantages of the backdoor access mechanism are threefold: First, zero simulation time—backdoor access does not consume simulation clock cycles, enabling instant data transmission, suitable for initializing large-capacity memory; second, rapid initialization capability—backdoor access can instantly load large amounts of test data, significantly shortening simulation preparation time; and finally, debugging convenience—during simulation, the data status at any location can be viewed at any time through backdoor access, providing strong support for debugging.
[0032] Based on the above, this invention proposes a general multi-bank memory model system. The system's basic storage unit array layer consists of multiple independent bank models. Each bank model generates storage units of corresponding specifications based on key parameters from the parameter configuration layer. The parameter configuration layer allows for customization of various characteristics of the storage units, achieving highly flexible configuration capabilities. With the help of a multi-bank controller layer, the system can automatically schedule multiple storage units to work collaboratively, possessing true parallel processing capabilities. Its intelligent address mapping function can automatically route user-input addresses to the correct bank and storage location, eliminating the need for users to concern themselves with complex address mapping details. The shadow storage array layer supports the system in simultaneously maintaining the state of the software model (shadow storage array) and hardware memory, ensuring verification accuracy and providing the system with powerful debugging capabilities. The hardware backdoor interface layer provides the system with rapid debugging and initialization capabilities through a backdoor access mechanism. This system can quickly generate memory models of corresponding specifications according to different verification requirements.
[0033] In one possible implementation, the parameter configuration layer is also used to configure the system's initialization mode; the initialization mode includes at least one of the following: unknown state mode, all 0 mode, all 1 mode, address self-filling mode, and random filling mode.
[0034] This embodiment provides five different memory initialization methods to adapt to different verification requirements: The unknown state mode sets all locations to an unknown state, simulating uninitialized memory; The all-zero mode fills all positions with 0, which is suitable for scenarios that require clearing. The all-1 mode fills all positions with 1s and is used to test the all-1 data pattern; The address autofill mode allows each location to store its own address value, which facilitates address-related testing. Random fill mode randomly fills in data, used for general functional testing.
[0035] This multi-mode initialization mechanism provides flexible options, allowing users to choose the most suitable initialization method based on specific verification requirements without modifying the code or recompiling.
[0036] In one possible implementation, the shadow storage array layer is used to: automatically call the ECC checksum generation function when the ECC bit width is greater than 0, calculate the ECC checksum for each storage address, and store it in association with the original data.
[0037] The automatic ECC generation mechanism automatically generates a corresponding ECC checksum for each data entry after data initialization. This mechanism is implemented by calling a third-party ECC generation function; when the ECC bit width is greater than 0, the system automatically initiates the ECC generation process. For each entry in the shadow storage array, the system calls a function to calculate the corresponding ECC checksum. This function accepts the data bit width, ECC bit width, and the original data as input and returns the calculated checksum. The system then stores these checksums in the ECC bit field of each entry, forming a complete data plus ECC storage format. The advantage of the automatic ECC generation mechanism is that it completely transparently handles the ECC processing. Users do not need to worry about the details of ECC calculation; the system automatically handles all related tasks, simplifying the user's workflow and avoiding errors that may occur from manual ECC calculation, thus improving the accuracy and reliability of verification.
[0038] In one possible implementation, the hardware backdoor interface layer supports batch backdoor access to actual hardware memory.
[0039] Batch backdoor access is a significant extension to the basic backdoor access mechanism, supporting the simultaneous transfer of data between multiple contiguous addresses. This mechanism is particularly suitable for initializing large amounts of memory and processing large volumes of data. Batch backdoor access accepts a starting address, data length, and data array as parameters. It reads and writes all addresses and data within a specified range in batches. The innovation of batch operations lies in their substantial improvement in the efficiency of large-capacity memory operations. Compared to address-by-address operations, batch operations significantly reduce function call overhead and path resolution time, especially when processing contiguous address spaces, where the performance improvement is particularly noticeable. This optimization is of great significance for the validation of modern large-capacity memory.
[0040] In one possible implementation, the general multi-bank memory model system also includes: a data consistency check module; the data consistency check module is used to: traverse all addresses of the shadow storage array layer, obtain the expected value of each address, read the actual value of the actual hardware memory layer through the hardware backdoor interface layer, compare the expected value with the actual value, and record the inconsistency information.
[0041] The data consistency check module is a cross-layer functional module, mounted on top of the core layer architecture. It calls upon the core capabilities of each layer to implement its own functions, while providing standardized interfaces to the upper-layer UVM verification environment. The data consistency check mechanism ensures state synchronization between the software model (shadow storage array) and hardware memory. Consistency checks compare the expected value with the actual value in hardware memory by traversing each entry in the shadow storage array. For each address location, the expected value is first obtained from the shadow array, then the actual value in hardware memory is read through a backdoor, and finally, the two are compared for consistency. If an inconsistency is found, an error message is recorded, and the check continues at other locations until all locations have been checked or the error count limit is reached. The consistency check mechanism can promptly detect data corruption or synchronization problems. In complex verification environments, data may change for various reasons. Regular consistency checks can quickly pinpoint the location and time of problems, providing crucial clues for debugging.
[0042] In one possible implementation, the general multi-bank memory model system also includes a file operation module; the file operation module is used to enable bidirectional interaction between memory data and external files.
[0043] The file operation module is a cross-layer functional module, mounted on top of the core layer architecture. It calls upon the core capabilities of each layer to implement its own functions, while providing standardized interfaces to the upper-layer UVM verification environment. File operation support is a practical feature of the system, allowing users to easily import and export data in memory. This functionality is particularly suitable for loading test vectors, saving debug data, and transferring data between different verification stages.
[0044] The system provides the following file operations: first, loading complete memory data from a file; second, exporting complete memory data to a file. For large memory volumes, the system also supports partial data operations, allowing users to load only a portion of the memory data by specifying start and end addresses to limit the loading range. Similarly, it allows users to export only a portion of the memory data. Furthermore, it supports flexible file naming strategies. Users can specify a parent directory name, and the system will automatically generate a complete filename containing the memory model name, avoiding filename conflicts and facilitating the management of data files for multiple memory models.
[0045] This invention provides a memory verification method, which is applied to the aforementioned general multi-bank memory model system; the method includes: S1, configure the key parameters and initialization mode of the Bank model; S2, depending on the initialization mode, performs memory initialization operations. If ECC function is enabled, it automatically calculates the ECC checksum of the data and stores it in the shadow storage array. S3, the UVM verification environment sends memory access stimuli. After receiving the stimuli, the multi-Bank controller resolves the system's total address into Bank number and Bank address through intelligent address mapping, and schedules the corresponding Bank model to complete the read and write operations. S4 returns the read / write results to the UVM verification environment.
[0046] In one possible implementation, the method further includes: Once verification is complete, a data consistency check is triggered. All memory addresses are traversed, and the data and ECC checksum of the shadow storage array are compared with those of the actual hardware memory. Inconsistency information is recorded.
[0047] In one possible implementation, the method further includes: The system checks the coverage rate. If the coverage rate meets the standard and there are no data inconsistency errors, the memory verification is considered successful; otherwise, the error is located and the verification process is re-executed.
[0048] Figure 2 This embodiment provides an address mapping and data flow diagram, including: I. Input Layer: Unified Reception of Requests and Configurations As the interface between the model and the upper-layer UVM verification environment, it centrally receives all verification requests, operation instructions, and configuration parameters, providing a complete basis for subsequent processing. The core inputs received include address input (system total address), data input (specific to write operations), operation type (read / write instruction), basic configuration parameters (number of banks / data bit width / storage depth), ECC configuration (ECC bit width), and initialization mode (0-4 corresponding to 5 intelligent initialization methods). The input information is split into main data stream (data input) and control signal stream (address / operation type / all configuration parameters) according to type, and synchronously passed down to the address mapping layer to start subsequent processing.
[0049] II. Address Mapping Layer: The Core Component of Address Resolution and Data Preprocessing As the core processing layer of the entire model, it intelligently parses, de-paths, and preprocesses the data and control flows transmitted from the input layer, completing address routing and ECC checksum generation under the multi-bank architecture. All complex logic is encapsulated in this layer and is transparent to the upper layers. The address resolver performs basic resolution on the system's total address, extracting valid address bits to prepare for subsequent Bank selection and Bank address calculation; The Bank selector extracts the Bank number from the parsed address based on the configured number of Banks to determine the target Bank for the data to access. The address calculator calculates the address within a bank based on the bank number parsing results, thus determining the specific storage location of the data in the target bank. The ECC processor performs preprocessing based on the ECC configuration parameters: if the ECC bit width is greater than 0, it automatically calculates the ECC checksum for the input raw data and generates complete data consisting of the raw data and the ECC checksum; if ECC is not enabled, the raw data is directly passed through; after processing, the control signal stream and the main data stream are synchronously transmitted to the corresponding modules in the storage layer according to the branch flow direction.
[0050] III. Storage Layer: Actual Data Storage / Retrieval and Hardware / Software Synchronization As the core storage carrier of the model, it receives instructions and data from the address mapping layer, completes actual read and write operations, multi-bank parallel processing, and hardware and software data synchronization. It also supports independent and rapid backdoor access, making it a key link in data storage. Multi-Bank Storage Unit: Based on the Bank number and internal address in the control signal stream, the corresponding target Bank is scheduled to perform read and write operations. Write operations write complete data, while read operations retrieve stored data plus an ECC checksum (if ECC is enabled). Multi-Bank parallel operation is supported, allowing access requests from different Banks to be executed simultaneously, leveraging the performance advantages of the multi-Bank architecture. Shadow storage array (software model): As a software mirror of the hardware multi-bank storage unit, it synchronously updates / reads its own data while the hardware performs read and write operations, ensuring that the data state of the software and hardware is completely consistent, and providing a benchmark of expected value for subsequent data consistency checks; Backdoor access interface: Provides a fast operation channel independent of the regular process, which can bypass the address mapping layer and read and write to specified locations of hardware memory.
[0051] IV. Output Layer: Full Feedback of Processing Results As the output of the model to the upper-layer UVM verification environment, it summarizes the operation results, verification information and debugging logs of the storage layer, outputs all information in a standardized format, completes the closed-loop processing of an access request, and the output content of read / write operations adapts to the operation type.
[0052] The memory verification method of this invention can cover all types of memory verification with a single code, reducing the amount of code in the verification environment; multi-bank support can be directly applied to the verification of high-bandwidth storage scenarios such as high-performance computing and AI chips; programs or data can be directly loaded into memory through backdoor access without the need for time-consuming writing via the bus, greatly shortening the simulation initialization time; and a real-time inspection method can be provided to compare the hardware and software status at any time during the simulation to quickly locate the moment when data corruption occurs.
[0053] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0054] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A general multi-bank memory model system, characterized in that, include: The UVM verification environment layer provides a standardized UVM interface to enable interaction with upper-layer UVM verification components. The parameter configuration layer is used to configure the key parameters of the Bank model. The multi-Bank controller layer is used to achieve unified management of the multi-Bank architecture, including receiving access incentives from the UVM verification environment layer, resolving the system's total address into Bank number and Bank address through intelligent address mapping, and scheduling the corresponding Bank model to complete read and write operations. The basic storage unit array layer consists of multiple independent Bank models. Each Bank model generates storage units of corresponding specifications based on the key parameters of the parameter configuration layer. The shadow storage array layer is used to maintain a state mirror of the actual hardware memory, recording the original data and ECC checksum for each storage address; The hardware backdoor interface layer is used for backdoors to access actual hardware memory.
2. The general multi-bank memory model system as described in claim 1, characterized in that, The key parameters of the Bank model include: address bit width, data bit width, storage depth, number of Banks, and ECC bit width.
3. The general multi-bank memory model system as described in claim 1, characterized in that, The parameter configuration layer is also used to configure the system's initialization mode; The initialization mode includes at least one of the following: unknown state mode, all 0 mode, all 1 mode, address self-filling mode, and random filling mode.
4. The general multi-bank memory model system as described in claim 1, characterized in that, The shadow storage array layer is used to: automatically call the ECC checksum generation function when the ECC bit width is greater than 0, calculate the ECC checksum for each storage address, and store it in association with the original data.
5. The general multi-bank memory model system as described in claim 1, characterized in that, The hardware backdoor interface layer supports batch backdoor access to actual hardware memory.
6. The general multi-bank memory model system as described in claim 1, characterized in that, Also includes: Data consistency check module; The data consistency check module is used to: traverse all addresses of the shadow storage array layer, obtain the expected value of each address, read the actual value of the actual hardware memory layer through the hardware backdoor interface layer, compare the expected value with the actual value, and record the inconsistency information.
7. The general multi-bank memory model system according to claim 1, characterized in that, Also includes: File operation module; The file operation module is used to enable bidirectional interaction between in-memory data and external files.
8. A memory verification method, characterized in that, Applied to the general multi-bank memory model system as described in any one of claims 1-7; The method includes: Configure the key parameters and initialization mode of the Bank model; According to the initialization mode, perform memory initialization operation. If ECC function is enabled, automatically calculate the ECC checksum of the data and store it in the shadow storage array. The UVM verification environment sends memory access stimuli. After receiving the stimuli, the multi-Bank controller resolves the system's total address into Bank number and Bank address through intelligent address mapping, and schedules the corresponding Bank model to complete the read and write operations. The read and write results are returned to the UVM verification environment.
9. The memory verification method according to claim 8, characterized in that, The method further includes: Once verification is complete, a data consistency check is triggered. All memory addresses are traversed, and the data and ECC checksum of the shadow storage array are compared with those of the actual hardware memory. Inconsistency information is recorded.
10. The memory verification method according to claim 9, characterized in that, The method further includes: The system checks the coverage rate. If the coverage rate meets the standard and there are no data inconsistency errors, the memory verification is considered successful; otherwise, the error is located and the verification process is re-executed.