Methods, apparatus, caches and computer systems for handling memory access requests

Abstract

This application discloses a memory access request processing method, apparatus, cache, and computer system. It uses a temporary buffer with the same depth as the missing state holding register to cache the memory access responses corresponding to each data memory access request. It searches and pops target request entries from the missing state holding register whose readiness state is "data ready" and whose corresponding cache group is unlocked. Based on the cache index in the target request entry, it reads the memory access response corresponding to the cache index from the temporary buffer and stores the read memory access response into the cache line corresponding to the data memory access request. This method ensures that while allocating cache lines for data memory access requests, the total number of memory access responses is at most equal to the depth of the missing state holding register, making the temporary buffer depth controllable. It solves the cache group locking problem in a delayed allocation architecture for set-associative caches and avoids backpressure.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to a memory access request processing method, apparatus, cache, and computer system. Background Technology

[0002] A set-associative cache is a cache that uses a set-associative mapping method. The cache in a set-associative cache is divided into several cache sets, each containing multiple cache lines. Memory blocks can be mapped to any cache line within a specified set. When using late allocation for cache allocation in a set-associative cache, for requests that miss the cache, the physical allocation decision for the data block is delayed until it is actually needed (such as when the data is actually accessed or the system state is clearer). This avoids premature allocation or replacement (such as cache thrashing) caused by short-term, frequent data access patterns, reduces invalid operations, improves resource utilization, and lowers power consumption and overhead.

[0003] When multiple miss requests fall into a single set, and all cachelines in that set have been allocated, the set's resources are exhausted, triggering a set lock on the cache group. This lock prevents multiple requests from simultaneously modifying the same set, which could lead to consistency errors or conflicts. However, the set lock also blocks all new miss requests mapped to the locked cache group, creating backpressure. Therefore, it is crucial to address the cache group locking issue in set-associative caches under a delayed allocation architecture to avoid backpressure. Summary of the Invention

[0004] In view of this, the present invention aims to provide a memory access request processing method, apparatus, cache, and computer system to solve the cache group locking problem of group-associative caches under a delayed allocation architecture and avoid backpressure.

[0005] In a first aspect, embodiments of the present invention aim to provide a memory access request processing method, the method comprising: Search the missing status holding register to determine the target request entry to be popped. The target request entry is the request entry whose preparation status is that the data is ready and the corresponding cache group is not locked. The target request entry is popped up, and the memory access response corresponding to the cache index is read from the temporary buffer according to the cache index in the target request entry. The temporary buffer is used to cache the memory access response corresponding to each data memory access request, and the depth of the temporary buffer is the same as the depth of the missing state holding register. The read memory access response is stored in the target cache line in the cache, and the target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

[0006] Furthermore, the method also includes: Get the cache hit status of data access requests; In response to a cache miss of the data access request, the data access request is stored in the missing status holding register; In response to receiving the memory access response corresponding to the data memory access request, the memory access response is stored in a temporary buffer; Update the request entry corresponding to the data memory access request in the missing state holding register. The request entry includes a cache index and a readiness status. The cache index is used to characterize the storage address of the memory access response in the temporary buffer, and the readiness status is used to characterize whether the data of the request entry is ready.

[0007] Furthermore, the search missing state holding register includes: Missing state-holding registers can be searched using either a polling scheduling method or a leader-one detection method.

[0008] Furthermore, storing the memory access response in a temporary buffer includes: The memory access response is stored in the empty entry of the temporary buffer by searching for an empty entry using a leading zero detection method.

[0009] Furthermore, the data access request includes a memory address, and obtaining the cache hit status of the data access request includes: The cache group corresponding to the data access request is determined based on the preset bit in the memory access address; Match the memory access address with the valid cache lines in the cache group; In response to the absence of a valid cache line matching the memory access address in the cache group, the cache hit status of the data memory access request is determined to be a cache miss.

[0010] Secondly, embodiments of the present invention aim to provide a memory access request processing apparatus, the apparatus comprising: The pop unit is used to search for missing status holding registers, determine the target request entry to be popped, the target request entry is a request entry whose preparation status is data ready and the corresponding cache group is not locked; pop the target request entry; The data reading unit is used to read the memory access response corresponding to the cache index from the temporary buffer according to the cache index in the target request entry. The temporary buffer is used to cache the memory access response corresponding to each data memory access request. The depth of the temporary buffer is the same as the depth of the missing state holding register. A data caching unit is used to store the read memory access response into a target cache line in the cache, wherein the target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

[0011] Thirdly, embodiments of the present invention aim to provide a cache, the cache comprising: The controller is configured to perform the method described in any of the preceding statements; The missing status hold register is configured to store memory access requests for data that have not been cached. A temporary buffer is configured to store the memory access response corresponding to the data memory access request; The data cache area includes multiple cache groups, each cache group comprising multiple cache lines, and each cache line is configured to store data.

[0012] Fourthly, embodiments of the present invention aim to provide a computer system, the computer system comprising: The cache as described above; A computer engine is used to generate data access requests and send the data access requests to the cache.

[0013] Fifthly, embodiments of the present invention aim to provide a computer program product, the computer program product including a computer program / instruction, which, when executed by a processor, implements the method described in any of the preceding claims.

[0014] Sixthly, embodiments of the present invention aim to provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in any of the preceding claims.

[0015] The technical solution of this invention uses a temporary buffer with the same depth as the missing state holding register to cache the memory access responses corresponding to each data memory access request; it searches and pops target request entries in the missing state holding register whose readiness state is data ready and whose corresponding cache group is not locked; it reads the memory access response corresponding to the cache index from the temporary buffer according to the cache index in the target request entry, and stores the read memory access response into the cache line corresponding to the data memory access request in the cache; it can ensure that the total number of memory access responses is at most equal to the depth of the missing state holding register while allocating cache lines for data memory access requests, making the depth of the temporary buffer controllable, solving the cache group locking problem under the set-associative cache delayed allocation architecture, and avoiding backpressure. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a flowchart of a memory access request processing method according to an embodiment of the present invention; Figure 2 This is a flowchart of a method for obtaining the cache hit status of a data access request according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the process of determining the cache hit status of a data access request according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the anti-backpressure process according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a memory access request processing device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a cache according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a computer system according to an embodiment of the present invention. Detailed Implementation

[0017] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0018] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0019] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0020] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0021] In response, it is used to indicate the conditions or states on which the operation performed depends. When the conditions or states on which it depends are met, one or more operations performed can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0022] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0024] Before providing a further detailed description of the embodiments of this application, the terms and attributes involved in the embodiments of this application will be explained, and the terms and attributes involved in the embodiments of this application are subject to the following interpretations.

[0025] Cache: A high-speed cache used to temporarily store frequently accessed data and instructions by the processor, reducing the number of accesses to slower main memory and thus improving overall performance. When the processor needs to retrieve data, it first checks the cache; if the data exists, it is called a cache hit; if the data does not exist, a cache miss occurs.

[0026] Cache line: A data transmission area consisting of several consecutive bytes. It is the smallest unit for data storage and transmission in the cache and for data exchange between main memory and cache. According to the mapping method, it can be divided into three types: direct mapping, set-associative and fully associative.

[0027] Set-associative cache: A cache that uses a set-associative mapping method. In a set-associative cache, the cache is divided into multiple sets, and each set contains several cache lines (also known as the way or associativity). A memory address is mapped to any line within a specific set. This design balances the simplicity of direct-mapped caches with the flexibility of fully associative caches.

[0028] Late Allocation is a strategy used in system resource management. Its core idea is to postpone the actual allocation of resources as much as possible until the resource is actually needed. Before that, only logical / virtual mappings or reserved information are retained. If the resource is not ultimately used, there is no need to actually allocate it, thus saving resources.

[0029] Set lock (cache set lock): is a mechanism that temporarily locks a cache set during cache miss processing to prevent multiple requests from modifying the same set simultaneously, which could lead to consistency errors or conflicts.

[0030] Response backpressure refers to the situation where a downstream module (such as an L3 cache or memory controller) cannot process the response sent from the upstream in a timely manner, and sends a "pause" signal to the upstream (such as an L2 cache) to prevent it from sending new responses, in order to avoid buffer overflow or deadlock.

[0031] MSHR (Missing Status Holding Register): A hardware structure for recording and managing cache miss request sideinfo, supporting concurrent miss handling and data backfill coordination in non-blocking caches.

[0032] MSHR entry: A specific entry or table item in MSHR. Each entry stores detailed information about a missed request, such as memory address and cache line status.

[0033] Side information refers to additional information used to assist in encoding or predicting main information during information processing. Examples include the cache line address associated with the request, hit test results, and request type.

[0034] MSHR Depth: The number of MSHR entries available in MSHR, i.e., the maximum number of independent cache miss requests that can be handled simultaneously.

[0035] Depth of temporary buffer: The maximum number of entries that can be held in a temporary buffer at the same time.

[0036] Based on the above explanation of the nouns and terms involved in the embodiments of this application, the memory access request processing method provided in the embodiments of this application, as well as the cache, computer system, etc. that apply it, are described below.

[0037] To address the set-lock problem in set-associative caches under a late-allocation architecture, this invention provides a memory access request processing method, apparatus, cache, and computer system to solve the set-lock problem in set-associative caches under a late-allocation architecture and avoid backpressure.

[0038] Figure 1 This is a flowchart of a memory access request processing method according to an embodiment of the present invention. The memory access request processing method of this embodiment is applied to a cache (hereinafter referred to as a cache), such as... Figure 1 As shown, the memory access request processing method in this embodiment includes the following steps: In step S110, the missing status holding register is searched to determine the target request entry to be popped. The target request entry is a request entry whose preparation status is "data ready" and whose corresponding cache group is not locked.

[0039] In step S120, the target request entry is popped, and the memory access response corresponding to the cache index is read from the temporary buffer according to the cache index in the target request entry. The temporary buffer is used to cache the memory access responses corresponding to each data memory access request, and the depth of the temporary buffer is the same as the depth of the missing status holding register.

[0040] In step S130, the read memory access response is stored in the target cache line in the cache. The target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

[0041] In this embodiment, after receiving a data access request, a cache hit determination is performed based on the access address in the data access request.

[0042] Figure 2 This is a flowchart of a method for obtaining the cache hit status of a data memory access request according to an embodiment of the present invention. The data memory access request includes a memory address. For a single data memory access request, this embodiment uses, as shown in the flowchart... Figure 2 The following steps are shown to obtain the cache hit status of a data access request; simultaneously, a schematic diagram of the process for determining the cache hit status of a data access request is shown below. Figure 3 As shown.

[0043] In step S210, the cache group corresponding to the data access request is determined according to the preset bit in the memory access address of the data access request.

[0044] In this embodiment, the memory access address of the data access request includes a tag and an index. The index is used to locate whether there is a cache set in the cache that matches the index address.

[0045] In step S220, the memory access address is matched with a valid cache line in the cache group.

[0046] In this embodiment, after determining the cache group corresponding to the data access request, the flag bit in the access address is matched with the flag bit of all valid cache lines in the cache group (i.e., cache lines with valid bit valid=1) to determine whether there is a valid cache line in the cache group that matches the flag bit of the access address.

[0047] In step S230, it is determined whether there is a valid cache line in the cache group that matches the memory access address.

[0048] In this embodiment, if there is a valid cache line in the cache group that matches the memory access address, that is, if there is a valid cache line in the cache group that matches the memory access address flag, then step S240 is executed; and if there is no valid cache line in the cache group that matches the memory access address, then step S250 is executed.

[0049] In step S240, in response to the existence of a valid cache line in the cache group that matches the memory access address, the hit status of the data memory access request is determined to be a cache hit.

[0050] In this embodiment, when a valid cache line matching the memory access address exists in the cache group, it indicates that the cache already stores the data related to the corresponding memory access request. At this time, the hit status of the memory access request is determined as a cache hit, and the operation corresponding to the memory access request is executed by directly using the data stored in the cache, thereby improving data processing efficiency. When the memory access request is a load instruction, it is used to read relevant data from the cache; when the memory access request is a store instruction, it is used to write relevant data into the cache.

[0051] In step S250, in response to the absence of a valid cache line in the cache group that matches the memory access address, the hit status of the data memory access request is determined to be a cache miss.

[0052] In this embodiment, when no valid cache line matches the memory access address in the cache group, it indicates that the cache does not store the data related to the corresponding memory access request. At this time, the hit status of the memory access request is determined to be a cache miss, and a cache line needs to be allocated in the cache to store the data related to the memory access request. When the memory access request is a load instruction, the data related to the memory access request is the data that the memory access request wants to read. When the memory access request is a store instruction, the data related to the memory access request is the data that the memory access request wants to write.

[0053] Furthermore, when a data access request results in a cache miss, this embodiment stores the sideinfo of the cache miss data access request into the request entry (MSHRentry) in the Missing Status Register (MSHR), and updates the status bits in the MSHR. Then, the data access request is sent downstream so that cache line allocation can be performed after the downstream returns the corresponding access response, thus achieving delayed allocation.

[0054] Specifically, upon receiving a memory access response corresponding to a data memory access request, this embodiment searches for empty entries (i.e., unoccupied cache entries) in the temporary buffer to store the memory access response in the temporary buffer. The cache index (entry_index) of the memory access response in the temporary buffer is recorded. This cache index represents the storage address of the memory access response in the temporary buffer, enabling timely processing of the memory access response and avoiding backpressure. Furthermore, since the depth of the temporary buffer and the missing state holding register are consistent, this embodiment ensures that the number of memory access responses returned to the temporary buffer is at most equal to the depth of the missing state holding register. This makes the depth of the temporary buffer controllable, thereby completely eliminating cache group locking and the backpressure caused by cache group locking, avoiding impact on subsequent request hit rates and request processing latency.

[0055] Furthermore, this embodiment also activates and updates the request entries corresponding to data memory access requests in the missing status holding register. Each request entry includes a cache index and a readiness status. The cache index represents the storage address of the memory access response in the temporary buffer; the readiness status represents whether the data for the request entry is ready. Upon receiving the memory access response corresponding to the data memory access request, the readiness status of the request entry is automatically updated to "data ready." Therefore, this embodiment can synchronously store and manage information related to the memory access request and its response for the same data memory access request, reducing request latency and improving the hit rate of subsequent requests.

[0056] Optionally, when storing the memory access response into the temporary buffer, this embodiment can use a leading zero detection method to search for empty entries in the temporary buffer to determine the empty cache entry into which the memory access response should be stored and then store the memory access response into that cache entry. Leading zero detection is a hardware algorithm used to quickly calculate the number of consecutive zeros starting from the most significant bit of a binary number, often implemented using a priority encoder or tree circuit. Searching for empty entries in the temporary buffer using the leading zero detection method can find the first free entry (such as the lowest-numbered empty entry) in parallel within a single cycle, achieving low-latency, high-throughput resource allocation, avoiding blocking the cache pipeline in the temporary buffer, improving memory parallelism and system stability, and enhancing the efficiency of entry management in the temporary buffer as well as the access efficiency of the data stored in the entries.

[0057] Optionally, after determining the cache index of the memory access response in the temporary buffer, this embodiment can perform the operations of storing the memory access response into the temporary buffer and storing the cache index corresponding to the memory access response into the corresponding request entry in a parallel or serial manner. Further, this embodiment uses a parallel processing method, activating the request entry corresponding to the memory access response and storing the cache index corresponding to the memory access response into the corresponding request entry while storing the memory access response into the temporary buffer, thereby further improving the processing efficiency of memory access requests.

[0058] Additionally, after cache-missed data access requests have been stored in the missing state holding register, this embodiment optionally searches the missing state holding register using either a round-robin scheduling method or a leading one method to determine the request entries to be popped from the missing state holding register and their corresponding data access requests. The request entries to be popped are those whose data status is "data ready" and whose corresponding cache set is not locked. Round-robin scheduling is a method that selects resources in a fixed order, avoiding starvation, ensuring all pending requests have a fair chance of being popped, and is simple to implement. Leading one is a method that quickly finds the first valid item (such as the least significant bit "1") in a bit vector, achieving a deterministic selection based on the lowest index. Through oldest-first or low-index priority strategies, it reduces average latency and improves predictability.

[0059] It should be noted that the methods for searching and determining empty entries in the temporary buffer and searching the missing status holding register to determine the request entries to be popped given in this embodiment are merely examples. Other methods that can achieve the same function are also available, and the specific method can be selected according to the actual application scenario. It should also be understood that when multiple data access requests exist in the missing status holding register, each data access request in the missing status holding register is popped sequentially according to the order in which they are searched. For a particular data access request, after being stored in the missing status holding register, it may not be popped immediately after being stored.

[0060] Furthermore, after determining the target request entry (MSHR entry) to be popped from the missing state holding register, this embodiment pops the corresponding request entry according to the pop index (pop_index) of the target request entry to be popped. The pop index can be represented by the MSHR entry identifier. Simultaneously, this embodiment reads the memory access response corresponding to the cache index recorded in the popped request entry from the temporary buffer. Based on the cache set index (set_index) and cache line index (cacheline_index or way_index) corresponding to the data memory access request, the cache line (cacheline) corresponding to the data memory access request in the data cache area is determined, i.e., the target cache line. The data to be read or written by the data memory access request is stored in the target cache line so that the data corresponding to the request can be obtained directly by accessing the cache later, improving the data processing efficiency of the operation corresponding to the request. Here, the data cache area is the region in the cache used to store data or instructions.

[0061] The technical solution of this embodiment stores cache-missed data access requests in a missing state holding register, and uses a temporary buffer with the same depth as the missing state holding register to cache the access responses corresponding to each data access request. It searches and pops target request entries in the missing state holding register that are in a ready state (data ready) and whose corresponding cache group is unlocked. Based on the cache index in the target request entry, it reads the access response corresponding to the cache index from the temporary buffer and stores the read access response into the cache line corresponding to the data access request in the cache. This allows for the allocation of cache lines for data access requests while ensuring that the total number of access responses is at most equal to the depth of the missing state holding register, making the temporary buffer depth controllable, solving the set-lock problem of set-associative caches in the Late Allocation architecture, and avoiding backpressure.

[0062] The following section uses Load requests as an example to further explain the method for handling set lock memory access requests under the Late Allocation architecture and group-associative mapping in this embodiment.

[0063] Figure 4 This is a schematic diagram of the anti-backpressure process according to an embodiment of the present invention. Figure 4 As shown, in this embodiment, the data access request is processed through the following process to solve the set lock problem of the group-associative cache under the Late Allocation architecture and avoid backpressure.

[0064] Specifically, upon receiving a data access request, the cache group corresponding to the access address in the data access request is determined in the cache. Then, a cache hit judgment is performed with all valid cache lines in the cache group to determine the cache hit status of the data access request.

[0065] After determining that the cache hit status of the data memory access request is a cache miss (i.e., the data memory access request is a miss request), the edge information of the data memory access request is stored in the Missing Status Register (MSHR) as a request entry, and the status bits in the MSHR are updated. Then, the data memory access request is sent downstream.

[0066] Upon receiving a memory access response from the downstream, a leading zero-detection method is used to search for empty entries (i.e., unoccupied cache entries) in the temporary buffer (filling SRAM). The depth of the temporary buffer and the depth of the missing status register are both K. Then, the memory access response is stored in the empty entry in the temporary buffer, and the corresponding cache index (entry_index) is recorded. The target request entry in the MSHR corresponding to the memory access response is activated; that is, the request entry in the MSHR containing the data memory access request corresponding to the memory access response. The cache index of the selected temporary buffer (i.e., the identifier of the cache entry occupied by the memory access response in the temporary buffer) is stored in this request entry.

[0067] Optionally, after determining the cache index of the memory access response in the temporary buffer, this embodiment can perform the operations of storing the memory access response into the temporary buffer and storing the cache index corresponding to the memory access response into the corresponding request entry in a parallel or serial manner. Further, this embodiment uses a parallel processing method, activating the request entry corresponding to the memory access response and storing the cache index corresponding to the memory access response into the corresponding request entry while storing the memory access response into the temporary buffer, thereby further improving the processing efficiency of memory access requests.

[0068] For example, after receiving the memory access response 1 corresponding to the data memory access request 1, this embodiment will first determine the cache index entry_index1 for storing response 1 in the temporary buffer. Then, the cache entry corresponding to the cache index entry_index1 of response 1 in the temporary buffer will be stored; at the same time, the request entry MSHR entry1 containing request 1 in MSHR will be activated and entry_index1 will be stored in MSHR entry1.

[0069] It should be noted that in this embodiment, only the request entry corresponding to the memory access response is responsible for triggering the memory access response from the temporary buffer to the data SRAM; other hit-on-miss requests (i.e., requests that are cache misses but whose accessed data is already being loaded (e.g., stored in filling SRAM, written to data SRAM), that is, requests that are hit on the previous miss request) can directly read the relevant data from the data SRAM without having to first obtain the data from the temporary buffer and then store the data in the data SRAM.

[0070] For example, suppose there is a cache miss in request0 before request1, and request0 requests the memory access data that includes the memory access data requested by request1. Then request1 is a hit-on-miss request. When request1 misses the cache, and the memory access response corresponding to request0 has already been stored in the temporary buffer, the memory access data corresponding to request1 can be retrieved from the temporary buffer without waiting for the memory access data to be stored in the data buffer. This saves data retrieval time and improves the overall request processing efficiency.

[0071] When there are cached data requests in MSHR that have not been cached, the MSHR is searched using a round-robin scheduling method or a leading detection method to determine the pop index of the target request entry in MSHR whose data status is ready and whose corresponding cache group is not locked.

[0072] Next, while reading the target request entry to be popped, the corresponding cache entry in the temporary buffer is read according to the cache index recorded in the target request entry. The memory access response read from the cache entry is then stored in the target cache line corresponding to the data memory access request of the memory access response. The target cache line is determined based on the cache set index (set_index) and cache line index (cacheline_index) of the data memory access request corresponding to the read memory access response. After the data in the target cache line is stored, the cache line allocation of the set-associative cache under the Late Allocation architecture is realized, so that subsequent access to the same data can be directly obtained from the cache, improving data processing efficiency.

[0073] Therefore, by processing data memory access requests through the above process in this embodiment, it can be ensured that the total number of returned memory access responses is at most equal to the depth of the MSHR, making the depth of the temporary buffer controllable, completely eliminating backpressure caused by cache group locking, and without affecting cache hit rate and latency, while also keeping the hardware footprint controllable. Furthermore, for the MMU system, excluding the forced miss phase, the cache hit rate of the temporary buffer is much higher than that of the cache. In addition, since a single memory access response involves multiple page tables, the MSHR depth does not need to cover the latency of the entire link, which is beneficial for further reducing the depth of the temporary buffer.

[0074] Figure 5 This is a schematic diagram of a memory access request processing device according to an embodiment of the present invention. Figure 5 As shown, the memory access request processing device in this embodiment includes a pop-up unit 51, a data reading unit 52, and a data cache unit 53.

[0075] Pop-up unit 51 is used to search the missing status holding register, determine the target request entry to be popped, and pop the target request entry. The target request entry is a request entry whose preparation state is "data ready" and whose corresponding cache group is not locked. Data reading unit 52 is used to read the memory access response corresponding to the cache index in the target request entry from a temporary buffer. The temporary buffer is used to cache the memory access responses corresponding to each data memory access request, and its depth is the same as the depth of the missing status holding register. Data caching unit 53 is used to store the read memory access response into the target cache line, and the target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

[0076] Figure 6 This is a schematic diagram of a cache according to an embodiment of the present invention. Figure 6 As shown, the cache in this embodiment includes a missing state holding register 61, a temporary buffer 62, a data buffer 63, and a controller 64.

[0077] Missing status holding register 61 is configured to store data access requests that have missed in the cache. Temporary buffer 62 is configured to store the memory access response corresponding to the data access request. Data cache 63 includes multiple cache groups, each containing multiple cache lines, and each cache line is configured to store data.

[0078] The controller 64 is configured to search the missing state holding register, determine the target request entry to be popped, pop the target request entry, read the memory access response corresponding to the cache index from the temporary buffer according to the cache index in the target request entry, and store the read memory access response into the target cache line in the cache. The target request entry is a request entry whose preparation state is "data is ready" and whose corresponding cache group is not locked; the temporary buffer is used to cache the memory access responses corresponding to each data memory access request, and the depth of the temporary buffer is the same as the depth of the missing state holding register; the target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

[0079] Another embodiment of this example relates to a computer system, such as Figure 7 As shown, the computer system includes a cache 71 and a computer engine 72, wherein the computer engine generates data access requests and sends the data access requests to the cache. The cache, using the aforementioned cache, performs cache management operations based on any of the above implementation methods.

[0080] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0081] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0082] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for handling memory access requests, characterized in that, The method includes: Search the missing status holding register to determine the target request entry to be popped. The target request entry is the request entry whose preparation status is that the data is ready and the corresponding cache group is not locked. The target request entry is popped up, and the memory access response corresponding to the cache index is read from the temporary buffer according to the cache index in the target request entry. The temporary buffer is used to cache the memory access response corresponding to each data memory access request, and the depth of the temporary buffer is the same as the depth of the missing state holding register. The read memory access response is stored in the target cache line in the cache, and the target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

2. The method according to claim 1, characterized in that, The method further includes: Get the cache hit status of data access requests; In response to a cache miss of the data access request, the data access request is stored in the missing status holding register; In response to receiving the memory access response corresponding to the data memory access request, the memory access response is stored in a temporary buffer; Update the request entry corresponding to the data memory access request in the missing state holding register. The request entry includes a cache index and a readiness status. The cache index is used to characterize the storage address of the memory access response in the temporary buffer, and the readiness status is used to characterize whether the data of the request entry is ready.

3. The method according to claim 1, characterized in that, The search missing state holding register includes: Missing state-holding registers can be searched using either a polling scheduling method or a leader-one detection method.

4. The method according to claim 2, characterized in that, The step of storing the memory access response into a temporary buffer includes: The memory access response is stored in the empty entry of the temporary buffer by searching for an empty entry using a leading zero detection method.

5. The method according to claim 2, characterized in that, The data memory access request includes the memory access address, and obtaining the cache hit status of the data memory access request includes: The cache group corresponding to the data access request is determined based on the preset bit in the memory access address; Match the memory access address with the valid cache lines in the cache group; In response to the absence of a valid cache line matching the memory access address in the cache group, the cache hit status of the data memory access request is determined to be a cache miss.

6. A memory access request processing apparatus, characterized in that, The device includes: The pop unit is used to search for missing status holding registers, determine the target request entry to be popped, the target request entry is a request entry whose preparation status is data ready and the corresponding cache group is not locked; pop the target request entry; The data reading unit is used to read the memory access response corresponding to the cache index from the temporary buffer according to the cache index in the target request entry. The temporary buffer is used to cache the memory access response corresponding to each data memory access request. The depth of the temporary buffer is the same as the depth of the missing state holding register. A data caching unit is used to store the read memory access response into a target cache line in the cache, wherein the target cache line is the cache line corresponding to the data memory access request corresponding to the memory access response.

7. A cache, characterized in that, The cache includes: The missing status hold register is configured to store memory access requests for data that have not been cached. A temporary buffer is configured to store the memory access response corresponding to the data memory access request; A data cache area includes multiple cache groups, each cache group including multiple cache lines, each cache line being configured to store data. The controller is configured to perform the method of any one of claims 1-5.

8. A computer system, characterized in that, The computer system includes: The cache as described in claim 7; A computer engine is used to generate data access requests and send the data access requests to the cache.

9. A computer program product, characterized in that, The computer program product includes a computer program / instruction that, when executed by a processor, implements the method of any one of claims 1-5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1-5.

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