Overcurrent protection event processing method and electronic device

Abstract

This application discloses an overcurrent protection event handling method and an electronic device, belonging to the field of electronic device technology. The method includes: acquiring a target OCP event reported by the PMIC; in response to the target OCP event being a non-false alarm event, determining the failure type that triggered the target OCP event, the failure type including hard failure or soft failure; in response to the failure type triggering the target OCP event being a hard failure, controlling the electronic device to output a target prompt; in response to the failure type triggering the target OCP event being a soft failure, adjusting the target parameter that triggered the soft failure.

Description

Technical Field

[0001] This application belongs to the field of electronic equipment technology, specifically relating to an overcurrent protection event handling method and an electronic device. Background Technology

[0002] As electronic devices such as mobile phones integrate more and more functional modules and their hardware performance becomes increasingly advanced, the modules connected to the power supply of these devices and the power consumption of the loads also increase. During the operation of electronic devices, in order to prevent damage to the connected modules due to excessive current in each power supply, over-current protection (OCP) is usually added to each power supply. An OCP event will occur when the current in the power supply exceeds the limit.

[0003] However, when an OCP event is received due to power failure, the relevant technologies usually directly restart the device to deal with the OCP event. However, restarting the device may not be effective in dealing with the OCP event, resulting in low efficiency in handling OCP events. Summary of the Invention

[0004] This application provides an overcurrent protection event handling method and electronic device, which can solve the problem of low efficiency in handling OCP events in related technologies.

[0005] In a first aspect, embodiments of this application provide an overcurrent protection event handling method, applied to an electronic device, the electronic device including: a power management integrated circuit (PMIC); the method includes: Obtain the target OCP event reported by the PMIC; In response to the target OCP event being a non-false alarm event, determine the failure type that triggered the target OCP event, which may be a hard failure or a soft failure. In response to failure types that trigger a target OCP event, including hard failures, the control electronic device outputs a target prompt; in response to failure types that trigger a target OCP event, including soft failures, the target parameters that trigger soft failures are adjusted.

[0006] Secondly, an electronic device provided in this application includes a processor and a memory, wherein the memory stores a program or instructions, and the program or instructions, when executed by the processor, implement the method as described in the first aspect.

[0007] In this embodiment, a target OCP event reported by the PMIC is acquired; in response to the target OCP event being a non-false alarm event, the failure type that triggered the target OCP event is determined, including either a hard failure or a soft failure; in response to the failure type that triggered the target OCP event being a hard failure, the electronic device is controlled to output a target prompt; in response to the failure type that triggered the target OCP event being a soft failure, the target parameters that triggered the soft failure are adjusted. Thus, when acquiring a target OCP event reported by the PMIC, the failure type that triggered the target OCP event can be further determined, and the target OCP event can be handled specifically according to the failure type. Compared to related technologies that directly restart the device without analyzing the failure type that triggered the OCP event, this embodiment can adopt different methods to deal with the target OCP event for different failure types, thereby effectively dealing with OCP events, improving the efficiency of OCP event processing, and solving the problem of low efficiency in OCP event processing in related technologies. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an OCP function provided in an embodiment of this application; Figure 2 This is an example schematic diagram of an electronic device provided in an embodiment of this application; Figure 3 This is a flowchart of an OCP event handling method provided in an embodiment of this application; Figure 4 This is a flowchart of another OCP event handling method provided in the embodiments of this application; Figure 5 This is a flowchart of another OCP event handling method provided in the embodiments of this application; Figure 6 This is a flowchart of another OCP event handling method provided in the embodiments of this application; Figure 7 This is an example flowchart of determining the failure type that triggers a target OCP event, provided in an embodiment of this application. Figure 8 This is a schematic diagram of another electronic device provided in an embodiment of this application; Figure 9 This is a flowchart of another OCP event handling method provided in the embodiments of this application; Figure 10 This is a flowchart of another OCP event handling method provided in the embodiments of this application; Figure 11 This is a schematic diagram illustrating the principle of a downstream power module voltage drop causing the upstream power module to trigger an OCP event, as provided in an embodiment of this application. Figure 12This is a flowchart illustrating a method for responding to an OCP event, as provided in an embodiment of this application. Figure 13 This is a flowchart illustrating a specific OCP event handling method provided in an embodiment of this application; Figure 14 This is a structural block diagram of an OCP event processing device provided in an embodiment of this application; Figure 15 This is a structural block diagram of an electronic device provided in an embodiment of this application; Figure 16 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0010] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0011] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0012] The following is a brief introduction to the OCP involved in the embodiments of this application. Taking a mobile phone as an example, when a user uses the mobile phone heavily (such as playing games or watching videos), the operating load of the CPU, GPU, and peripherals will increase accordingly. In the event that the total power consumption of the power supply exceeds a preset value, in order to avoid damage to the power supply or the modules connected to the power supply due to excessive current, an OCP function will be added to each power supply of the mobile phone.

[0013] For any power supply of an electronic device, a voltage threshold value can be preset for that power supply. This threshold value can be the voltage drain-drain (VDD) overcurrent pressure (OCP) threshold. When the power supply experiences a large current load exceeding its maximum load capacity, the output voltage will be pulled down, resulting in a transient drop. If the voltage drops below the threshold value due to OCP, the OCP event will not be triggered immediately. The PMIC sets a debounce time for this power supply. Only when the duration of the voltage drop below the threshold value is greater than or equal to the debounce time will the PMIC broadcast the OCP event to the CPU. The debounce time refers to the delay time during which the signal stabilizes.

[0014] For reference Figure 1 , Figure 1 This is a schematic diagram of an OCP function provided in an embodiment of this application. Figure 1 As shown, an OCP event will not be triggered if the lower limit of the voltage transient drop caused by OCP is not lower than the voltage threshold. Similarly, an OCP event will not be triggered if the voltage transient drop caused by OCP falls below the voltage threshold, but the duration below the voltage threshold is less than the debouncing wait time. An OCP event will only be triggered if the voltage transient drop caused by OCP falls below the voltage threshold, and the duration below the voltage threshold is greater than or equal to the debouncing wait time.

[0015] The OCP event handling method provided in this application is applied to OCP event handling technology. By analyzing the triggering cause of the OCP event, corresponding countermeasures can be implemented in a targeted manner to prevent the electronic device from experiencing OCP events again, thereby effectively dealing with OCP events and improving the processing efficiency of OCP events.

[0016] The OCP event handling method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0017] The OCP event handling method provided in this application embodiment can be applied to electronic devices, that is, the OCP event handling method can be executed by electronic devices, including power management integrated circuits (PMICs). See also... Figure 2 , Figure 2 This is an example schematic diagram of an electronic device provided in an embodiment of this application. Figure 2As shown, the electronic device includes, for example, five modules: a PMIC, a CPU, a charging management integrated circuit, a flash driver module, and a peripheral module. The charging management integrated circuit may include a pulse width modulation (PWM) module and a battery field-effect transistor (Qbat). The Qbat switch controls the output voltage (VBAT) of the battery (e.g., a lithium-ion battery) to the input voltage terminals of the PMIC and the flash driver module. Figure 2 (IN terminal in the circuit). The PWM module can output a PWM signal to control the flash (e.g., the IN terminal). Figure 2 The flashlight indicator light in the circuit flashes to indicate this. Furthermore, the charging management integrated circuit can transmit data and control commands to the CPU and PMIC via the System Power Management Interface (SPMI) bus.

[0018] The CPU is primarily responsible for controlling the flash driver module. Simultaneously, the CPU can receive the trigger time of OCP events broadcast by the PMIC via the SPMI bus. The SPMI bus includes two signal lines: SPMI CLK and SPMI DATA. The SPMI CLK signal line is the serial clock signal line, providing communication synchronization timing. The SPMI DATA signal line is the serial data line, which can be used for bidirectional transmission of commands, addresses, and register data. The CPU can perform a reset action on the PMIC via the RESET signal. The CPU includes an internal power supply module (…). Figure 2 The Vcpu in the PMIC has an internal power module LDO2 that can output voltage to the CPU's power supply module.

[0019] The PMIC can transmit data and control commands to the CPU via the SPMI bus and can receive the RESET signal (reset signal) transmitted by the CPU. The PMIC may include a first analog-to-digital converter (ADC). Figure 2 Tadc in the first resistor ( Figure 2 (as shown in the NTC), control module ( Figure 2 (Ctrl) and the power module, the power module including, for example, Ctrl) Figure 2The PMIC includes a DC-DC converter (DCDC), a low-dropout regulator (LDO) 1, and an LDO 2. The first resistor can be a thermistor. The Tadc module manages the temperature sensing signal of the first resistor (NTC) within the PMIC. The NTC detects the junction temperature data of various modules within the PMIC and uploads it to the Tadc module. The junction temperature refers to the actual temperature of the PN junction inside the semiconductor device during operation. The DCDC and LDO are integrated power supply modules within the IC, receiving the system voltage (e.g., from the charging management integrated circuit) from the charging management integrated circuit. Figure 2 The power supply (shown as Vsys in the diagram) outputs to various modules such as system hardware (minimum system module) and external devices (peripheral loads). All power supplies within the PMIC can be managed by the Ctrl module within the PMIC.

[0020] The flash driver module's power input comes from the Vsys power supply of the charging management integrated circuit. The flash driver module's signal output is sent to the flash unit. The flash unit can reuse the device's camera flash, flashlight indicator, or power status indicator, etc. In other words, the control of the flash unit in this embodiment does not affect its original function as a camera flash, flashlight indicator, or power status indicator. The CPU can control the switching and timing of the flash unit's output LEDs via the Inter-Integrated Circuit (I2C) bus. The I2C bus can consist of two signal lines: a serial clock line (SCL) and a serial data line (SDL). Peripheral modules include, for example, a liquid crystal module (LCM), a camera, and sensors. The LDO1 inside the PMIC can output voltage to the peripheral modules to power them. It should be noted that... Figure 2 The electronic device described is merely one example, and the embodiments of this application are not limited to applications... Figure 2 The electronic device shown, Figure 2 The components and their connections are not essential; for example, the flash driver module can also be integrated into the charging management integrated circuit.

[0021] Please refer to Figure 3 , Figure 3 This is a flowchart of an OCP event handling method provided in an embodiment of this application. Figure 3 As shown, the method includes the following steps: Step 310: Obtain the target OCP event reported by the PMIC.

[0022] In this embodiment, an OCP event refers to an event triggered by a current protection mechanism when the output current in a circuit or power supply system exceeds a preset safety threshold. When a power supply in the PMIC triggers the current protection mechanism, the PMIC can report the OCP event to the CPU. The OCP event processing method provided in this embodiment is executed, for example, by the CPU of an electronic device. The target OCP event can be either a false alarm event or a non-false alarm event. A false alarm event is an event caused by a logical misjudgment. In the case of a false alarm event, although the target OCP event is triggered, the overcurrent protection mechanism may not be triggered. A non-false alarm event indicates that the overcurrent protection mechanism has actually been triggered; that is, the target OCP event is an OCP event reported by the PMIC due to the triggering of the overcurrent protection mechanism.

[0023] Step 320: In response to the target OCP event being a non-false alarm event, determine the failure type that triggered the target OCP event. The failure type may be a hard failure or a soft failure.

[0024] In this application embodiment, a soft failure refers to a temporary functional abnormality in a device or system, also known as a software failure or soft damage. Generally, soft failures can recover on their own after a power outage and restart or reset. Soft failures are temporary, recoverable, and do not damage the hardware. A hard failure refers to permanent physical damage to components in a device or system, also known as a hardware failure or hard damage. Hard failures are permanent, unrecoverable, and involve hardware damage. If the target OCP event is determined to be a non-false alarm event, the triggering cause of the target OCP event can be further determined, i.e., the failure type that caused the target OCP event.

[0025] In one example, since soft failures can recover automatically after a power-off restart or reset, the electronic device can be restarted, and the failure type of the target OCP event can be determined by whether the OCP event still occurs after the restart operation. In another example, since the output current of the PMIC changes significantly when an OCP event is triggered, the failure type of the target OCP event can be determined by detecting the output current of the power supply component (battery) of the electronic device.

[0026] Furthermore, after receiving the target OCP event reported by the PMIC, if it is determined to be a false alarm—meaning the target OCP event was not triggered by the overcurrent protection mechanism but rather by a software malfunction and does not affect the user's normal use of the electronic device—then the target OCP event can be ignored, and no other operations should be performed in response to it.

[0027] Step 330: In response to a failure type that triggers the target OCP event, including a hard failure, control the electronic device to output a target prompt; in response to a failure type that triggers the target OCP event, including a soft failure, adjust the target parameters that trigger the soft failure.

[0028] In this embodiment, the failure type that triggers the target OCP event is the triggering cause of the target OCP event. If the target OCP event is not a false alarm, it can be further determined whether the failure type is a soft failure or a hard failure, and the corresponding operation can be executed. The operation for a soft failure may differ from the operation for a hard failure. For example, if the failure type is a soft failure, the target parameters that triggered the soft failure can be adjusted to address the target OCP event. If the failure type is a hard failure, the electronic device can be controlled to output a target prompt to remind the user to send the electronic device for repair as soon as possible. In this way, for a soft failure, the device will typically stop reporting the target OCP event after adjusting the target parameters. For a hard failure, the target prompt can prevent the user from continuing to use the electronic device, thus avoiding further hardware damage.

[0029] In this embodiment, a target OCP event reported by the PMIC is acquired; in response to the target OCP event being a non-false alarm event, the failure type that triggered the target OCP event is determined, including either a hard failure or a soft failure; in response to the failure type that triggered the target OCP event being a hard failure, the electronic device is controlled to output a target prompt; in response to the failure type that triggered the target OCP event being a soft failure, the target parameters that triggered the soft failure are adjusted. Thus, when acquiring a target OCP event reported by the PMIC, the failure type that triggered the target OCP event can be further determined, and the target OCP event can be handled specifically according to the failure type. Compared to related technologies that directly restart the device without analyzing the failure type that triggered the OCP event, this embodiment can adopt different methods to deal with the target OCP event for different failure types, thereby effectively dealing with OCP events, improving the efficiency of OCP event processing, and solving the problem of low efficiency in OCP event processing in related technologies.

[0030] In one embodiment of this application, the target parameters include the performance parameters of the electronic device; the target OCP event is reported when the electronic device executes the first thread. Adjusting the target parameters that trigger a soft failure in step 330 includes: reducing the performance parameters of the electronic device in response to the electronic device executing the second thread. The similarity between the load characteristics of the electronic device executing the second thread and the load characteristics of executing the first thread is greater than a preset threshold.

[0031] In this embodiment, performance parameters include, for example, the CPU's operating frequency, the GPU's operating frequency, or the number of CPU cores. The load characteristics of the electronic device executing the first thread describe the degree of processor resource consumption and behavioral patterns during the execution of the first thread. Similarly, the load characteristics of the electronic device executing the second thread describe the degree of processor resource consumption and behavioral patterns during the execution of the second thread. For example, load characteristics may include indicators such as CPU utilization or CPU saturation. If the similarity between the load characteristics of the electronic device executing the second thread and the load characteristics of executing the first thread is greater than a preset threshold, it can be understood that the electronic device is executing a second thread similar to the first thread.

[0032] Specifically, when the CPU receives a target OCP event reported by the PMIC, it can simultaneously record and store the thread data invoked at the time of the load anomaly (e.g., the first thread, CPU operating frequency, GPU operating frequency, etc.). If the failure type triggered by the target OCP event is subsequently determined to be a soft failure, it can be assumed that under similar thread and CPU scheduling conditions, there is a certain probability that the power module's OCP threshold will be reached. In this case, the thread and scheduling can be treated as a combined event. If a thread similar to the first thread runs again subsequently, the device's performance parameters can be reduced to below the performance parameters at the time the target OCP event was triggered. For example, the CPU or GPU's maximum clock speed can be lowered by one level until it falls below the previously reported anomaly frequency, ensuring that similar events are not triggered again.

[0033] It should be noted that the above method is only one example. This application also supports adjusting the anti-jitter wait time of the power module to address target OCP events. For details, please refer to the following section on... Figure 10 The explanation will not be elaborated here.

[0034] For reference Figure 4 , Figure 4 This is a flowchart of another OCP event handling method provided in an embodiment of this application. For example... Figure 4 As shown, the method includes the following steps: Step 410: Obtain the target OCP event reported by the PMIC.

[0035] Step 420: Obtain the output voltage of the first power module.

[0036] In this embodiment of the application, the PMIC may include a first power module, which is, for example, one of a DC-DC converter and an LDO converter. Figure 2The PMIC uses a DC-DC converter, LDO1, or LDO2. The target OCP event, for example, indicates that an OCP event has occurred in the first power module, and the output voltage is, for example, the output voltage of the first power module. The PMIC can report the target OCP event occurring in the first power module to the CPU, and can also report the trigger time of the target OCP event. In response to receiving the target OCP event, the CPU can send a check signal to the PMIC. In response to receiving the check signal, the PMIC acquires the output voltage of the first power module. The PMIC can determine whether the target OCP event is a false alarm based on the output voltage, facilitating subsequent corresponding measures.

[0037] Step 430: Obtain the first indication information of the first power module; the first indication information is used to indicate whether the first power module has an OCP event at a first time point, and the first time point is the triggering time point of the target OCP event.

[0038] In this embodiment, the PMIC may contain an OCP register. The OCP register is used to configure information related to the OCP function, such as whether an OCP event has occurred in each power supply of the PMIC. The OCP register may store first indication information, as well as second and third indication information mentioned later. That is, the PMIC may include an OCP register, and the first indication information of the first power module can be obtained through the OCP register.

[0039] Taking the first power module as an example, the first indication information can be the register (REG) value of the first power module at the first time point stored in the OCP register. For any power supply in the PMIC, the REG value of the OCP register is usually the first value under normal conditions, and it will be set to the second value after an OCP event occurs in that power supply. That is, if the REG value corresponding to the first power module is set to the first value, it can be determined that the first power module has experienced an OCP event at the first time point; if the REG value corresponding to the first power module is set to the second value, it can be determined that the first power module has not experienced an OCP event at the first time point. Here, the first value is, for example, 0, and the second value is, for example, 1.

[0040] Step 440: When the output voltage is lower than or equal to the preset voltage value, and the first indication information indicates that the first power module has an OCP event at the first time point, determine that the target OCP event is a non-false alarm event.

[0041] In the embodiments of this application, reference can be made to Figure 1When an OCP event occurs in the power module, the output voltage of the first power module will be pulled down. Therefore, taking the first power module as an example, it can be determined whether an OCP event has actually occurred by checking whether the current output voltage of the first power module is less than a preset voltage value. The preset voltage value is, for example, the voltage threshold value (VDD OCP threshold value) mentioned earlier. If the output voltage of the first power module is less than or equal to the preset voltage value, and the REG function of the first power module is set to 1, it indicates that both the voltage feedback and debounce detection circuits inside the PMIC indicate that an OCP event has occurred in the first power module. This confirms that the target OCP event is not a false alarm, meaning that the target OCP event has genuinely triggered the overcurrent protection mechanism. Simultaneously, it can be determined that both the voltage feedback and debounce detection circuits inside the PMIC are in normal working order.

[0042] Step 450: In response to the target OCP event being a non-false alarm event, determine the failure type that triggered the target OCP event, which may be a hard failure or a soft failure.

[0043] Step 460: In response to a failure type that triggers the target OCP event, including a hard failure, control the electronic device to output a target prompt; in response to a failure type that triggers the target OCP event, including a soft failure, adjust the target parameters that trigger the soft failure.

[0044] In this embodiment, the output voltage of the first power module and the first indication information of the PMIC are used to determine whether the target OCP event is a false alarm event. This method considers more comprehensive factors and can more accurately determine whether the target OCP event is a false alarm event.

[0045] In one embodiment of this application, after obtaining the output voltage of the first power module in step 420, the OCP event handling method, in addition to steps 410-460, further includes: determining that the target OCP event is a false alarm event if the output voltage is higher than a preset voltage value. See also... Figure 1 Taking the first power module as an example, when an OCP event occurs in the first power module, the output voltage of the first power module will be pulled down to below a preset voltage value. Therefore, if the output voltage of the first power module is higher than the preset voltage value, it can be determined that the first power module has not actually triggered the overcurrent protection mechanism, that is, the target OCP event is a false alarm.

[0046] Furthermore, embodiments of this application also support determining whether the PMIC is abnormal while determining whether the target OCP event is a false alarm. For example, if the output voltage is higher than a preset voltage value and the first indication information indicates that the first power module has experienced an OCP event, the target OCP event is determined to be a false alarm, and the PMIC hard fails. If the output voltage is higher than the preset voltage value and the first indication information indicates that the first power module has not experienced an OCP event, the target OCP event is determined to be a false alarm.

[0047] Specifically, if the REG value of the first power module stored in the OCP register becomes 1, and the output voltage of the first power module is higher than the preset voltage value, it can be determined that there is a contradiction between the voltage feedback and the detection results of the debounce detection circuit inside the PMIC. Therefore, the target OCP event can be considered to be caused by a power feedback logic error, i.e., the PMIC is malfunctioning. In this case, to prevent further damage and deterioration of the PMIC from continued use, a timely pop-up window on the device's User Interface (UI) can remind the user to send the device for after-sales service for repair.

[0048] If the output voltage of the first power module is greater than the preset voltage value, and the REG value of the first power module is 0, it indicates that both the voltage feedback and debounce detection circuits inside the PMIC indicate that the first power module has not experienced an OCP event. Therefore, the target OCP event can be determined to be a false alarm, possibly caused by a software misreport. Simultaneously, it can be confirmed that the voltage feedback and debounce detection circuits inside the PMIC are functioning normally. OCP events caused by such software misreports do not affect normal user operation of the device and can be left unattended.

[0049] For reference Figure 5 , Figure 5 This is a flowchart of another OCP event handling method provided in an embodiment of this application. For example... Figure 5 As shown, the method includes the following steps: Step 510: Obtain the target OCP event reported by the PMIC.

[0050] Step 520: In response to the target OCP event being a non-false alarm event, determine the target power module that triggered the target OCP event, and restart the PMIC or the target power module.

[0051] In this embodiment, after the PMIC determines whether the target OCP event is a false alarm, it can send the determination result to the CPU via the SPMI bus. The CPU then determines the failure type that triggered the target OCP event. If the target OCP event is a false alarm, it is not processed. If the target OCP event is not a false alarm, the target power module that triggered the target OCP event can be further identified, and the PMIC or the target power module can be restarted. The PMIC may include a first power module, and the target OCP event may indicate that the first power module has experienced an OCP event. However, the first power module and the target power module are different concepts. It should be emphasized that the target power module may or may not be the first power module. That is, it is possible that the first power module experiences the target OCP event, but the target OCP event is not triggered by the first power module itself. For example, the target power module may be either a DC-DC converter or an LDO.

[0052] It is understandable that the occurrence of an OCP event by the first power module does not necessarily mean that the OCP event was triggered by the first power module. Figure 8 As shown, a PMIC includes multiple power modules, such as DC-DC converters and LDO modules. In some cases, a failure of the DC-DC converter will trigger an OCP event; however, in other cases, a failure of the LDO module, due to the cascading relationship between the LDO and DC-DC converters, will also cause an OCP event in the preceding DC-DC converter. This is why an OCP event occurring in the first power module does not necessarily mean that the OCP event was triggered by the first power module; further confirmation is required.

[0053] Step 530: In response to the target power module triggering an OCP event again, determine the failure type that caused the target OCP event, including hard failure.

[0054] In this embodiment, if the failure type triggering the target OCP event is a soft failure, the target power module typically will not report the target OCP event again after the device restarts the PMIC or target power module. If the failure type triggering the target OCP event is a hard failure, the target power module will continue to report the target OCP event after the device restarts the PMIC or target power module. Therefore, whether the failure type triggering the target OCP event is a soft failure or a hard failure can be determined by whether the device still receives the target OCP event after restarting the PMIC or target power module. However, it should be noted that the method of determining the failure type triggering the target OCP event through a restart operation is only one example and is not limited to this method. For example, the triggering failure type of the target OCP event can also be determined by the battery's output current.

[0055] Step 540: In response to the target power module no longer experiencing OCP events, determine the failure type that triggered the target OCP event, including soft failures.

[0056] Step 550: In response to a failure type that triggers the target OCP event, including a hard failure, control the electronic device to output a target prompt; in response to a failure type that triggers the target OCP event, including a soft failure, adjust the target parameters that trigger the soft failure.

[0057] In this application embodiment, a method is provided to determine the failure type that triggers the target OCP event by restarting the PMIC or the target power module. This method is simple in logic and easy to implement.

[0058] In one embodiment of this application, a target power module is used to supply power to a target load. The target load includes at least one of a minimum system module and a peripheral load. Restarting the PMIC or the target power module includes: restarting the PMIC if the target load includes a minimum system module; and restarting the target power module if the target load is a peripheral load.

[0059] In this application embodiment, independent processing is supported for two scenarios: the target load includes a minimum system module, and the target load only includes peripheral loads. The minimum system module is the set of the fewest hardware components necessary for an electronic device to run its most basic program or reach its most basic startup state. That is, it is the most basic hardware system within the electronic device used to maintain device power-on and startup, such as a system-on-chip (SoC), clock integrated circuit, and memory. Peripheral loads are components within the electronic device connected to the core system and responsible for input / output or extended functions, such as displays, cameras, and sensor modules.

[0060] In this embodiment, the internal software of the electronic device can pre-record the power tree data of the circuit and store it in the system as a database. Specifically, for any power supply module inside the PMIC, if the load supplied by the power supply module includes the minimum system module, the flag bit of the power supply module is set to 1 (FLAG=1); if the load supplied by the power supply module only includes peripheral loads, the flag bit of the power supply module is set to 0 (FLAG=0). In this way, by reading the flag bit of the target power module, it can be determined whether the target load supplied by the target power module is only a peripheral load or includes system hardware.

[0061] In this application embodiment, independent processing is supported for two scenarios: the target load includes a minimum system module and the target load only includes peripheral load. The minimum system module can also be referred to as system hardware. The explanation of the minimum system module and peripheral load can be found above, and will not be repeated here.

[0062] The following examples illustrate these two scenarios. The internal software of electronic devices can pre-record the power tree data of the circuit and store it in the system as a database. Specifically, for any power supply module within the PMIC, if the load supplied by that power supply module includes the minimum system module, then the flag bit of that power supply module is set to 1 (FLAG=1); if the load supplied by that power supply module only includes peripheral loads, then the flag bit of that power supply module is set to 0 (FLAG=0). In this way, by reading the flag bit of the target power supply module, it can be determined whether the target load supplied by the target power supply module is only a peripheral load or includes the minimum system module.

[0063] In the scenario where the target load includes a minimum system module (the target power module supplies power only to the minimum system module or simultaneously to both the minimum system module and peripheral loads), after receiving the target OCP event reported by the PMIC, the CPU first reads the FLAG=1 corresponding to this power supply to determine that the target power module includes system power. Simultaneously, it records and stores the thread data invoked by the load at the abnormal time point (the first thread and CPU or GPU operating frequency, etc.). The CPU can also reset the PMIC via the RESET signal, causing the system to restart. If, after the system restarts, the PMIC no longer reports the target power module's OCP event, it can be determined that the previously received target OCP event was caused by a transient high-power load pulling down the voltage, and the minimum system module was undamaged. If, after the device powers on and restarts (e.g., including all processes after a mobile phone is powered on again), the CPU continues to receive the target OCP event reported by the target power module, it is determined that the target OCP event was caused by a hard circuit failure.

[0064] When an OCP event occurs, the junction temperature (operating temperature) of the PMIC can be detected first through the thermistor (NTC) inside the PMIC and the first ADC (Tadc module). Before the mobile phone triggers a restart, the junction temperature data of the PMIC is stored, and the maximum value of the junction temperature is recorded. At the same time, a safety threshold (denoted as Tjs) can be set. When it is determined that the target OCP event is caused by a hard failure of the circuit, the current junction temperature of the PMIC is compared with the safety threshold. If it is detected that the current junction temperature Tj0 < Tjs and it is confirmed by looking up the table that the junction temperature of the PMIC has been less than the safety threshold for a certain period of time before, it is judged that the target OCP event is caused by the abnormality of the minimum system module (small system load module) itself, that is, the trigger reason of the target OCP event is the hardware failure of the minimum system module. If it is detected that the current junction temperature Tj0 > Tjs, it is judged that the target OCP event is an abnormality caused by internal leakage of the PMIC itself.

[0065] It should be noted that whether it is an abnormality of the small system load or an abnormality of a specific DCDC or LDO power supply inside the PMIC that supplies power to the small system, it will cause the small system to be unable to maintain normal operation. Taking the mobile phone as an example, the mobile phone will show system stability problems such as crashing at this time.

[0066] For the situation where the target load is only the peripheral load (that is, the target power module only supplies power to the peripheral load, and the following peripheral load can be simply referred to as the peripheral), after the CPU receives the target OCP event reported by the PMIC, if it reads that the FLAG corresponding to the target power module is 0, it is judged that the target power module does not include system power supply and only supplies power to the peripheral. Then, the CPU sends an instruction to the PMIC through the SPMI bus to control the shutdown of the target power module. At the same time, the background exits all peripheral modules (modules other than the small system, such as the display screen, audio, etc.) loaded by the target power module. After waiting for 10S, the CPU powers on and initializes the peripheral modules powered by the target power module again. If the CPU no longer receives the target OCP event reported by the target power module after the re-power-on initialization is completed, it is judged as a transient soft failure, and the normal operation of the peripheral can be maintained. At the same time, if the target OCP event is an OCP event that occurs in the DCDC power module, and it is further determined that the root cause of the trigger of the target OCP event lies in the LDO, but the previous-stage DCDC triggers first. Then, the anti-shake waiting time (debounce time) of the previous-stage DCDC can be modified through the software background after restarting, and the anti-shake waiting time of the first power module can be extended, for example, from the original 20ms to 60ms, but ensure that the anti-shake waiting time of the input DCDC is less than the anti-shake waiting time of the output LDO.

[0067] If, after power-on initialization, the CPU receives the target OCP event reported by the target power module again, it is determined that a hard damage (hard failure) has occurred. At this time, it is necessary to further determine whether it is the PMIC itself that is abnormal or the peripheral load that is abnormal, as follows. When an OCP event occurs, the junction temperature (operating temperature) of the PMIC can be detected first through the thermistor (NTC) inside the PMIC and the first ADC (Tadc module). Before the mobile phone triggers a restart, the junction temperature data of the PMIC is stored, and the maximum value of the junction temperature is recorded. At the same time, a safety threshold (denoted as Tjs) can be set. When it is detected that the current junction temperature Tj0 < Tjs and it is confirmed by looking up the table that the junction temperature of the PMIC has been less than the safety threshold for a certain period of time before, it is determined that the target OCP event is an abnormality of the peripheral load itself, and the power supply of the target power module is permanently turned off to maintain the normal operation of the system hardware (minimum system module) and other peripheral loads, and a system pop-up window appears: A hard failure has occurred in a certain peripheral module itself, and the relevant circuit has stopped being used, which does not affect the operation of the system and other modules. Please ask the consumer to send it for repair in a timely manner.

[0068] When it is detected through the NTC that the current junction temperature Tj0 > Tjs, it is determined that the target OCP event is an abnormality caused by internal leakage of the PMIC itself, and the abnormal target power module is permanently turned off (other normal power supplies maintain the current state) to maintain the normal operation of the system hardware (minimum system module) and other peripheral loads, and a system pop-up window appears: A hard failure has occurred in the current power module itself, and the relevant circuit has stopped being used. Continuing to use it has a safety risk of aggravating the damage. Please ask the consumer to stop using it as soon as possible and send it for repair.

[0069] Exemplarily, in an embodiment of the present application, the PMIC includes a first power module and a second power module. The output voltage terminal of the first power module is connected to the input voltage terminal of the second power module, and the anti-shake waiting time of the first power module is shorter than the anti-shake waiting time of the second power module. The target OCP event indicates that an OCP event occurs in the first power module; the target parameter includes the anti-shake waiting time of the first power module. Adjusting the target parameter that causes the soft failure in step 550 includes: in response to the target power module being the second power module, extending the anti-shake waiting time of the first power module.

[0070] In this embodiment, if the second power module pulls down its voltage, causing the first power module to pull down its voltage, the voltage drop time of the first power module may reach its anti-jitter wait time before the voltage drop time of the second power module is reached, resulting in the first power module triggering the target OCP event. In this case, the target power module causing the target OCP event is not the first power module, but rather the downstream power module (the second power module). Since this situation is caused by the excessively short anti-jitter wait time of the first power module, it can be addressed by extending the anti-jitter wait time of the first power module, thus avoiding misjudging the target power module triggering the target OCP event as the first power module. This situation can be further addressed in the following section. Figure 10 and Figure 11 The description is omitted here.

[0071] For reference Figure 6 , Figure 6 This is a flowchart of another OCP event handling method provided in an embodiment of this application. For example... Figure 6 As shown, the method includes the following steps: Step 610: Obtain the target OCP event reported by the PMIC.

[0072] Step 620: Obtain the first output current of the power supply component in the first time period; the first time period includes the trigger time of the target OCP event.

[0073] Step 630: Obtain the second output current of the power supply component in the second time period; the second time period is before the first time period.

[0074] Step 640: If the difference between the first output current and the second output current is greater than the preset current value, determine that the target OCP event is a non-false alarm event.

[0075] In this embodiment, the power supply component can be a battery, and the following description uses a battery as an example. For any power supply, when an OCP event actually occurs on that power supply, the output current of that power supply will increase significantly, and the battery's output current will also increase significantly. Therefore, the change in the battery's output current can be used to determine whether the target OCP event is a real event. Specifically, the first output current of the battery during a first time period when the target OCP event occurs, and the second output current of the battery during a second time period before the target OCP event occurs, can be obtained. By comparing the first current and the second output current, it can be determined whether the target OCP event is a real event. Here, the first output current is the average output current of the battery during the first time period, and the second output current can be the average output current of the battery during the second time period.

[0076] For example, the PMIC includes a first power module, and the target OCP event is, for example, an OCP event occurring in the first power module. The duration of the first time period is, for example, the debounce waiting time of the first power module, and the duration of the second time period is, for example, 100 milliseconds (ms). Specifically, when the CPU receives a target OCP event reported by a power supply from the PMIC via the SPMI bus, the battery output current is read backwards for a period of time (i.e., the first time period, T = debounce time) from the first time point that triggers the target OCP event, and the average value is calculated to obtain the first output current, which is denoted as Ibat1. The battery output current is then read backwards for another period of time (i.e., the second time period, T = debounce time + 100ms) from the first time point that triggers the target OCP event, and the average value is calculated to obtain the second output current, which is denoted as Ibat2.

[0077] If Ibat1 ≈ Ibat2 (fluctuation within 10%), then it is determined that no OCP event occurred within the first time period. This means no actual OCP event occurred during the power supply's debounce time, indicating a false alarm; the target OCP event is a spurious event. If Ibat1 > Ibat2 + Ivdd max / (Vbat * 85%), then it is determined that an OCP event is indeed occurring within the first time period. The preset current value is, for example, Ivdd max / (Vbat * 85%), where Ivdd max represents the chip's maximum rated current, Vbat represents the battery voltage, and 85% represents the conversion efficiency. The OCP current threshold of a typical power supply is approximately twice the maximum rated current. By dividing the maximum rated current by Vbat and the conversion efficiency, it can be converted into the equivalent load current of the preceding stage Ibat. The conversion efficiency of a typical power supply is approximately 85%.

[0078] Step 650: In response to the target OCP event being a non-false alarm event, determine the failure type that triggered the target OCP event, which may be a hard failure or a soft failure.

[0079] Step 660: In response to a failure type that triggers the target OCP event, including a hard failure, control the electronic device to output a target prompt; in response to a failure type that triggers the target OCP event, including a soft failure, adjust the target parameters that trigger the soft failure.

[0080] Furthermore, embodiments of this application can also determine whether a target OCP event is a soft failure or a hard failure based on the output current of the power supply component. For example, in one embodiment of this application, determining the failure type that triggers the target OCP event includes: acquiring a third output current of the power supply component during a third time period; the third time period is after the first time period, and the length of the third time period can be the same as the length of the second time period; if the difference between the third output current and the second output current is less than a first preset value, determining that the failure type triggering the target OCP event is a soft failure; if the difference between the third output current and the first output current is less than a second preset value, determining that the failure type triggering the target OCP event is a hard failure.

[0081] The third output current is, for example, the average output current of the power supply component during the third time period. Starting from the first time point that triggers the target OCP event, continue waiting for a period of time (i.e., the third time period, e.g., 100ms), calculate the average current during this period to obtain the third output current, and denote the third output current as Ibat3. The first preset value is, for example, the product of the second output current and the first ratio, and the second preset value is, for example, the product of the first output current and the second ratio. The first and second ratios can be set according to actual conditions; for example, both the first and second ratios can be 10%.

[0082] In other words, if Ibat3 ≈ Ibat2 (fluctuation difference within 10%), then it is determined that the power supply that reported the target OCP event has returned to normal after the event was reported, confirming that the target OCP event was caused by a transient current soft failure, i.e., the triggering failure type of the target OCP event is a soft failure. If Ibat3 ≈ Ibat1 (fluctuation difference within 10%), then it is determined that the power supply that reported the target OCP event remained in a high-current abnormal state after the event was reported, confirming that the triggering failure type of the target OCP event is a hard failure. For the hard failure scenario, the target component that failed can be determined by the operating temperature of the PMIC, which will not be elaborated here.

[0083] For reference Figure 7 , Figure 7 This is an example flowchart illustrating how to determine the failure type that triggers a target OCP event, as provided in an embodiment of this application. Figure 7As shown, the battery output current (Ibat) can be read every 10 milliseconds (ms), and the current data for 1 second (s) before and after the current sampling time is saved. After the CPU receives the target OCP event reported by the PMIC (e.g., an OCP event reported by the DC-DC power supply), it retrieves the first output current (Ibat1) for the first time period and the second output current (Ibat2) for the second time period based on the timestamp. After waiting for 100 milliseconds (ms), the third output current (Ibat3) for the third time period is read. Ibat1 and Ibat2 are compared. If Ibat1 ≈ Ibat2, it is determined that no real OCP event has occurred, which is a logical false alarm; if Ibat1 > Ibat2 + Ivdd max / (Vbat * 85%), it is determined that an OCP event is currently occurring. Then, Ibat3 is compared with Ibat1 and Ibat2 respectively. If Ibat3≈Ibat1, it can be determined that the power supply is continuously in the OCP state, which is judged as a hard failure, and hard failure handling is performed; if Ibat3≈Ibat2, it can be determined that the OCP event has self-recovered, which is judged as a transient soft failure, and soft failure handling is performed.

[0084] In one embodiment of this application, the electronic device further includes a current detection module, one end of which is coupled to a power supply component, and the other end of which is coupled to a CPU. The current detection module is used to detect the output current of the power supply component, which includes a first output current, a second output current, and a third output current. For example, the current detection module is a current sensor.

[0085] For example, a resistor can be connected in series with the power supply component, thereby indirectly detecting the output current of the power supply component by detecting the current in the resistor. See also... Figure 8 , Figure 8 This is a schematic diagram of another electronic device provided in an embodiment of this application. For example... Figure 8 As shown, the electronic device includes a current detection module, which includes a second resistor and a second ADC. One end of the second ADC is connected to one end of the second resistor, and the other end of the second ADC is connected to the other end of the second resistor. Figure 8 For other components, please refer to the previous text. Figure 2 The details of that will not be repeated here.

[0086] The second resistor is, for example, a high-precision resistor with a known resistance value. The second ADC is used to detect the voltage across the second resistor, and thus calculates the current through the resistor using the voltage across the second resistor and the resistance value of the second resistor, thereby obtaining the battery's output current. Figure 8 For example, a 2 milliohm (Ω) is connected in series on the battery VBAT output path. The optimal high-precision sensing resistor (Rsense) is connected to the second ADC (Iadc module) inside the charging management integrated circuit via differential signal lines (Isnsp and Isnsn). The second ADC is responsible for detecting the battery output current. When the system is running normally, the Iadc module in the charging management integrated circuit detects the transient current of the battery output every 10ms through the second resistor connected in series with the battery output, and continuously overwrites and saves the current data for 1 second before and after the current sampling time.

[0087] For reference Figure 9 , Figure 9 This is a flowchart of another OCP event handling method provided in an embodiment of this application. For example... Figure 9 As shown, the method includes the following steps: Step 910: Obtain the target OCP event reported by the PMIC. The PMIC includes the target power module. The target OCP event is triggered by the target power module, which is used to supply power to the target load.

[0088] Step 920: In response to the target OCP event being a non-false alarm event, determine the failure type that triggered the target OCP event.

[0089] Step 930: In response to a failure type that triggers a target OCP event, including a hard failure, identify the target component that failed, including at least one of a PMIC and a target load.

[0090] The target load may include at least one of the minimum system modules and peripheral loads. The minimum system module is the set of the fewest hardware components necessary for an electronic device to run its most basic program or reach its most basic startup state; that is, the most basic hardware system inside the electronic device used to maintain its power-on and startup, such as a SoC chip, clock integrated circuit, and memory. Peripheral loads are components inside the electronic device connected to the core system and responsible for input / output or extended functions, such as displays, cameras, and sensor modules.

[0091] Step 940: Control the electronic device to output a target prompt, which is a prompt indicating that the target component has failed.

[0092] Step 950: In response to the failure type that triggers the target OCP event, including soft failure, adjust the target parameters that trigger soft failure.

[0093] In this application embodiment, when the failure type that triggered the target OCP event is determined to include a hard failure, the target component that failed can be further identified. For example, in one embodiment of this application, identifying the target component that failed includes: obtaining the operating temperature of the PMIC. If the operating temperature is lower than a preset temperature, the target load is identified as the target component that failed. If the operating temperature is higher than or equal to the preset temperature, the PMIC is identified as the target component that failed.

[0094] In this embodiment, the operating temperature may include multiple temperature values ​​of the PMIC within a target time period, with the end of the target time period being the trigger time of the target OCP event. That is, it can be determined whether the temperature of the PMIC is consistently higher than a preset temperature for a period prior to the triggering of the target OCP event, avoiding misjudgments due to instantaneous temperature anomalies. If multiple temperature values ​​are higher than the preset temperature, it can be determined that the target OCP event is caused by internal leakage in the PMIC itself, i.e., a PMIC hard failure. Conversely, it can be determined that the PMIC's operating temperature is normal, and the target OCP event is caused by an abnormality in the target load itself, i.e., a target load hard failure. In this way, the specific hardware triggering the target OCP event can be further located using the PMIC's operating temperature, facilitating subsequent equipment maintenance.

[0095] Exemplarily, embodiments of this application can achieve temperature detection of the PMIC through a first ADC and a first resistor inside the PMIC. Specifically, the PMIC includes a temperature detection module, which is coupled to the CPU. During the process of acquiring the PMIC's operating temperature, the CPU uses the temperature detection module to obtain the PMIC's operating temperature. The temperature detection module includes a first ADC and a first resistor. One end of the first ADC is coupled to the CPU, and the other end of the first ADC is grounded through the first resistor. However, it should be noted that embodiments of this application are not limited to detecting the PMIC's operating temperature using only a first ADC and a first resistor; for example, it can also be achieved by designing a temperature sensor inside the PMIC.

[0096] The first resistor is, for example, a thermistor, a type of temperature-sensitive semiconductor resistor whose resistance changes significantly with temperature. The first ADC can be used to detect the voltage across the first resistor, thereby determining the temperature change of the first resistor by observing the change in voltage across it, thus enabling the detection of the PMIC's operating temperature.

[0097] In one embodiment of this application, the target component includes a target load, which includes at least one of a minimum system module and a peripheral load. When the target load includes a minimum system module, the target prompt is a flashing light prompt. When the target load is a peripheral load, the target prompt is a prompt displayed by the electronic device when the minimum system module is operating normally. For example, the target prompt includes at least one of the following: a vibration prompt, a pop-up prompt, and an audio prompt.

[0098] In this embodiment, a flashing light is used to indicate a hard failure of the minimum system module, reminding the user to send the device for repair in a timely manner. Specifically, as shown... Figure 2 As shown, the electronic device may also include a charging management integrated circuit, a field-effect transistor (FET), and a flash. The CPU is coupled to the charging management integrated circuit, which is coupled to the flash via the FET. The CPU is used to: control the charging management integrated circuit to output a control signal to the FET; the control signal is used to control the flash to blink; the flash indicates that the minimum system module of the electronic device has failed. It should be noted that this is not limited to the form of the target notification when the target load is a peripheral load; for example, it could be a pop-up notification, vibration notification, or sound notification.

[0099] In the embodiments of this application, the field-effect transistor is, for example, a metal-oxide-semiconductor field-effect transistor (MOS), such as... Figure 2 Q1 in the diagram. The charging management integrated circuit is connected to the gate of the MOSFET. The first stage of the MOSFET is connected to the charging management integrated circuit, and the second stage of the MOSFET is connected to the flash lamp. The first stage is one of the source and drain terminals of the MOSFET, and the second stage is the other of the source and drain terminals of the MOSFET.

[0100] For example, see Figure 2 During the device's restart and power-on process, the CPU outputs a signal via the I2C bus to control the flash drive to a high-impedance state. Simultaneously, the charging management IC sends a signal to the MOSFET (i.e.,...) via the PWM module. Figure 2 The Q1 output control signal (PWM signal) controls the MOSFET to switch on and off in a pulse manner, causing the flash to blink. The flash stops after 5 seconds. In this embodiment, this mechanism can be specifically used for the case of a hard failure of the minimum system module. A corresponding explanation can be added to the user manual: a 5-second flash during power-on indicates that the minimum system module (the most basic hardware system that maintains the power-on and startup of the small system, such as the CPU, clock integrated circuit, and memory) has suffered hard damage and needs to be sent for repair immediately.

[0101] For reference Figure 10 , Figure 10 This is a flowchart of another OCP event handling method provided in an embodiment of this application. For example... Figure 10 As shown, the method includes the following steps: Step 1010: Obtain the target OCP event reported by the PMIC, which includes the first power module and the second power module.

[0102] In this configuration, the output voltage terminal of the first power module is connected to the input voltage terminal of the second power module. The anti-jitter wait time of the first power module is shorter than that of the second power module. The anti-jitter wait time can be the delay time for the signal to stabilize. Specifically, the anti-jitter wait time refers to the delay time set to wait for the signal to stabilize before making a judgment, in order to eliminate multiple unstable fluctuations caused by signal switching. The first power module is, for example, a DC-DC power module, and the second power module is, for example, an LDO power module. The output voltage terminal of the first power module is, for example,... Figure 2 In the OUT section, the input voltage terminal of the second power supply module is, for example, OUT. Figure 2 IN1 in the middle.

[0103] Currently, to improve energy efficiency, the input power of the LDO power module is often converted from the DC-DC power module. Typically, the anti-jitter wait time for the LDO power module to trigger OCP detection is longer than that of the preceding DC-DC power module. This is because of brief current spikes (non-continuous faults). If the anti-jitter wait time of the LDO power module is set to be equal to or less than that of the preceding DC-DC power module, the current spike may be misjudged as a continuous overcurrent, thus triggering protection shutdown. By setting the anti-jitter wait time of the LDO power module to be longer, this current spike will not cause any protection action, making the system power supply operate more stably.

[0104] In this scenario, a voltage drop in the downstream LDO power module might indirectly affect the upstream DC-DC power module, triggering an OCP event. (See reference...) Figure 11 , Figure 11 This is a schematic diagram illustrating the principle of how a low voltage from a downstream power module triggers an OCP event in a upstream power module, as provided in an embodiment of this application. Figure 11As shown, the input voltage of the LDO power module is the output voltage of the preceding DC-DC power module. The LDO power module's debouncing wait time is set to 128ms, and the preceding DC-DC power module's debouncing wait time is set to 20ms. If the LDO power module experiences a short circuit and its voltage is continuously pulled low, before the LDO power module's debouncing wait time is reached (i.e., before broadcasting an OCP event), the preceding DC-DC power module's voltage is simultaneously pulled low, and the preceding DC-DC power module's voltage pull-down time reaches its debouncing wait time first. In this case, the preceding DC-DC power module will broadcast an OCP event. Since the preceding DC-DC power supply often powers more than one peripheral device, it typically powers multiple loads simultaneously, including system hardware. Therefore, the preceding DC-DC power module reporting an OCP event will cause a system restart, and conventional solutions cannot mitigate the restart impact caused by the preceding power supply.

[0105] Step 1020: In response to the target OCP event being a non-false alarm event and the target OCP event indicating that the first power module has generated an OCP event, obtain the second indication information of the first power module and the third indication information of the second power module.

[0106] In this embodiment, the second indication information is used to indicate whether an OCP event occurs in the first power module at a second time point, and the third indication information is used to indicate whether an OCP event occurs in the second power module at the second time point. The second time point is after the first time point, where the first time point is the triggering time of the target OCP event, and the time interval between the second time point and the first time point is greater than the anti-jitter waiting time of the second power supply. When the second indication information indicates that the first power module has experienced an OCP event at the second time point, and the third indication information also indicates that the second power module has experienced an OCP event at the second time point, it is determined that the target OCP event is triggered by the second power module. The explanation of the second and third indication information is the same as that given above regarding the first indication information, and will not be repeated here.

[0107] In this embodiment, the PMIC may include an OCP register, through which second and third indication information can be obtained. The target OCP event being triggered by the second power module means that the voltage of the second power module drops, causing the voltage of the first power module to drop, resulting in the first power module reaching the OCP threshold first, i.e., the first power module reporting the OCP event first, and the root cause of this OCP event is the second power module. The above determination process is not limited to execution after determining that the target OCP event is a soft failure. In fact, it can also be executed after determining that the target OCP event is a real event, but before performing a restart operation on the target load; this is not limited here. Furthermore, the above process is only executed when the output voltage terminal of the first power module is connected to the input voltage terminal of the second power module, and the anti-jitter waiting time of the first power module is shorter than that of the second power module. In this case, the first power module may report the target OCP event, but the root cause of the target OCP event is the second power module. Taking a DC-DC power module as an example and an LDO power module as an example, the above process can be executed when the target OCP event is an OCP event reported by the DC-DC power module.

[0108] For example, if the target OCP event is confirmed to have actually occurred, and if it is detected that the target OCP event was reported by the DC-DC power supply, it is necessary to further determine whether the root cause of the target OCP event is triggered by the DC-DC itself, or whether it is caused by the downstream LDO power supply using this DC-DC as input pulling down the upstream input DC-DC while simultaneously short-circuiting it. Specifically, when the CPU receives the target OCP event reported by the DC-DC power supply module, it first maintains the current voltage supply state and waits for a period of time (the duration is greater than or equal to the LDO's debouncing wait time). Then, it checks the REG values ​​of the input DC-DC and the output LDO through the OCP register.

[0109] Step 1030: If the second indication information indicates that the first power module has an OCP event at the second time point, and the third indication information indicates that the second power module has an OCP event at the second time point, then the second power module is identified as the target power module.

[0110] Furthermore, if the second indication information indicates that the first power module experienced an OCP event at the second time point, and the third indication information indicates that the second power module did not experience an OCP event at the second time point, the first power module is identified as the target power module. Taking a DC-DC converter as the first power module and an LDO as the second power module as an example, the second indication information might be the REG value of the DC-DC converter, and the third indication information might be the REG value of the LDO. If the REG value of the DC-DC converter is rewritten to 1, while the REG value of the LDO remains 0, then the target OCP event is determined to be caused by a large current entering the DC-DC converter itself, and the subsequent LDO is normal. If both the REG values ​​of the DC-DC converter and the LDO are rewritten to 1, then the root cause of the target OCP event is determined to be the LDO, and the preceding DC-DC converter reported the OCP event first because its debouncing wait time is shorter. The OCP register can store the REG value of each power supply in the PMIC. Each LDO or DC-DC converter has a different REG address, and the specific power supply experiencing the anomaly can be identified by traversing the OCP register.

[0111] In one embodiment, the OCP event handling method provided in this application, in addition to steps 1010-1080, further includes: in response to a target OCP event indicating that a second power module has generated an OCP event, identifying the second power module as the target power module. For example, if the target OCP event is a non-false alarm event and is an OCP event generated by an LDO, then the target power module that triggers the target OCP event is typically the LDO itself.

[0112] Step 1040: Reboot the PMIC or target power module.

[0113] Step 1050: In response to the target power module triggering an OCP event again, determine the failure type that caused the target OCP event, including hard failure.

[0114] Step 1060: In response to the target power module no longer experiencing OCP events, determine the failure type that triggered the target OCP event, including soft failures.

[0115] Step 1070: In response to the failure type that triggers the target OCP event, including a hard failure, control the electronic device to output a target prompt.

[0116] Step 1080: In response to the failure type that triggers the target OCP event, including soft failure, adjust the target parameter that triggers the soft failure.

[0117] In this embodiment, the target parameter is, for example, the dejitter wait time of the first power module. That is, if it is determined that the target OCP event occurring in the first power module is triggered by the second power module, the dejitter wait time of the first power module can be extended, thereby preventing the aforementioned scenario from recurring. For example, if the root cause of the target OCP event reported by the DC-DC power module is the LDO power module, but the preceding DC-DC power module triggers the target OCP event first, the dejitter wait time of the preceding DC-DC power module can be modified in the software background after a restart operation, extending the dejitter wait time of the preceding DC-DC power module, for example, from the original 20ms to 60ms. However, it should be noted that the extended dejitter wait time of the preceding DC-DC power module must still be less than the dejitter wait time of the subsequent LDO power module.

[0118] In the embodiments of this application, it is not limited to simply reducing the performance parameters of the electronic device or simply extending the anti-shake waiting time of the first power module. It is also possible to simultaneously extend the anti-shake waiting time of the first power module and reduce the performance parameters of the electronic device. The two are not contradictory.

[0119] For reference Figure 12 , Figure 12 This is a flowchart illustrating a method for handling OCP events, as provided in an embodiment of this application. Figure 12 As shown, the first power module is, for example, Figure 2 The CPU receives an OCP (Over-Proof) event from the PMIC (Power Microcontroller Interface) regarding the DC-DC power supply. It then checks if the DC-DC power supply's output voltage Vdd is less than or equal to a preset voltage value (Vdd OCP). If Vdd > Vdd OCP, it further checks if the DC-DC power supply's REG (Reference Value) is 1. If REG = 1, the OCP event is determined to be caused by a PMIC feedback logic anomaly, indicating a hardware failure in the PMIC, and a prompt for repair is sent via the UI. If REG ≠ 1, the OCP event is considered a software false alarm and is not processed.

[0120] When Vdd ≤ Vdd OCP and REG = 1, it is determined that an OCP event has actually occurred in the DC-DC power supply. Then, the voltage state is maintained, and after a period of time (longer than the LDO's debouncing wait time), the REG values ​​of the input DC-DC and output LDO are read. If DC-DC REG = 1 and LDO REG = 0, it is determined that the root cause of the OCP event is triggered by the input DC-DC itself, and the output LDOs are all normal. If DC-DC REG = 1 and LDO REG = 1, it is determined that the root cause of the OCP event is triggered by the output LDO.

[0121] For situations where the root cause of the OCP event is triggered by the input DC-DC converter itself, and all output LDOs are functioning normally, the CPU and GPU scheduling policies (including threads and frequencies) of the system at the time of the anomaly are recorded. The CPU restarts the PMIC by sending a reset signal, and the system restarts accordingly. It is determined whether the DC-DC power supply continues to experience OCP events after the restart. If the DC-DC power supply no longer experiences OCP events after the restart, the OCP event can be considered a recoverable soft failure event. If similar thread scheduling scenarios occur subsequently, the CPU and GPU frequencies are reduced by default, one level lower than during the OCP event. If the DC-DC power supply still experiences OCP events after the restart, the OCP event can be considered an unrecoverable hard failure event. After another restart, the CPU controls the flash driver to output a high-impedance state via the I2C bus, and the charging management IC controls Q1 to turn on the flash LED (Light Emitting Diode) and make it flash via a PWM signal. The flash stops after 5 seconds. The user manual indicates that this indicator status indicates a hard failure and requires immediate repair.

[0122] To address the scenario where the root cause of an OCP event is triggered by an output LDO, further analysis can be performed by reading the power tree flags to determine if the LDO power supply is powered by system hardware. If the LDO power supply is powered by system hardware, the system CPU and GPU scheduling policies (including threads and frequencies) at the time of the anomaly are recorded. The CPU restarts the PMIC by sending a reset signal, and the system subsequently restarts. It is then determined whether the power supply repeatedly reports the OCP event after the restart. If the power supply repeatedly reports the OCP event after the restart, the OCP event is determined to be an unrecoverable hard failure. If the power supply does not repeatedly report the OCP event after the restart, the OCP event is determined to be a recoverable soft failure. Furthermore, the debouncing wait time of the DC-DC converter is extended after the restart, while ensuring that the debouncing wait time of the DC-DC converter is less than that of the LDO.

[0123] If the power supply only powers the peripheral devices, the CPU can send instructions through the SPMI bus to turn off the LDO power supply, exit the application of the peripheral module in the background, wait for 10 seconds, then turn on the LDO power supply, and at the same time power on and initialize the peripheral module again. Determine whether the CPU continues to receive the OCP event reported by the LDO power supply after initialization. If the CPU continues to receive the OCP event reported by the LDO power supply, it is determined that the OCP event is an irrecoverable hard failure. At this time, the LDO power supply state can be maintained, and at the same time, the junction temperature Tj0 of the PMIC is read to determine whether Tj0 is less than the safety threshold. If Tj0 < Tjs, it is determined that the hardware of the peripheral module is damaged, and this power supply is permanently turned off, and a pop-up window is used to prompt the consumer that this module has failed, which does not affect the system hardware and other modules. Please ask the consumer to send it for repair in time. If Tj0 ≥ Tjs, it is determined that the hardware of the PMIC module is damaged, and this power supply is permanently turned off, and a pop-up window is used to prompt the consumer that the system power module has a hard failure and needs to stop using immediately. Continuing to use has a safety risk of household damage and should be sent for repair as soon as possible. If the CPU stops receiving the OCP event reported by this power supply, it is determined that the OCP event is a recoverable soft failure event, and the normal operation of the peripheral device is maintained.

[0124] It can be referred to Figure 13 , Figure 13 is a specific flowchart of an OCP event processing method provided by an embodiment of the present application. As Figure 13 shown, the method includes the following steps: Step 1310: Obtain the target OCP event reported by the PMIC; the PMIC includes a first power module and a second power module, and the target OCP event indicates that an OCP event occurs in the first power module.

[0125] Step 1315: Obtain the output voltage of the first power module.

[0126] Step 1320: Obtain the first indication information of the first power module; the first indication information is used to indicate whether an OCP event occurs in the first power module at the first time point, and the first time point is the trigger time point of the target OCP event.

[0127] Step 1325: Determine that the target OCP event is a non-false alarm event when the output voltage is lower than or equal to the preset voltage value and the first indication information indicates that an OCP event occurs in the first power module at the first time point.

[0128] Step 1330: In response to the target OCP event being a non-false alarm event, determine the target power module that triggers the target OCP event, and restart the PMIC or the target power module.

[0129] The target power module is used to supply power to the target load, which includes at least one of the minimum system module and peripheral loads. The target power module is one of the first power module and the second power module.

[0130] Step 1335: In response to the target power module triggering an OCP event again, determine the failure type that caused the target OCP event, including hard failure.

[0131] Step 1340: In response to the target power module no longer experiencing OCP events, determine the failure type that triggered the target OCP event, including soft failures.

[0132] In the above steps, steps 1315-1325 are used to determine whether the target OCP event is a false alarm, and steps 1330-1340 are used to determine the failure type that triggered the target OCP event. However, it should be noted that... Figure 13 As just one example, the battery's output current can also be used to determine whether a target OCP event is a false alarm, and to determine the type of failure that caused the target OCP event.

[0133] Step 1345: In response to the failure type that triggered the target OCP event, including hard failure, identify the target component that failed; the target component includes at least one of PMIC and target load.

[0134] Step 1350: Control the electronic device to output a target prompt, which is a prompt indicating that the target component has failed.

[0135] Step 1355: In response to the failure type that triggers the target OCP event, including soft failure, adjust the target parameter that triggers the soft failure.

[0136] In the embodiments of this application, the explanations of failure types, target prompts, and target parameters can be found above and will not be repeated here.

[0137] In this embodiment, a target OCP event reported by the PMIC is acquired; in response to the target OCP event being a non-false alarm event, the failure type that triggered the target OCP event is determined, including either a hard failure or a soft failure; in response to the failure type that triggered the target OCP event being a hard failure, the electronic device is controlled to output a target prompt; in response to the failure type that triggered the target OCP event being a soft failure, the target parameters that triggered the soft failure are adjusted. Thus, when acquiring a target OCP event reported by the PMIC, the failure type that triggered the target OCP event can be further determined, and the target OCP event can be handled specifically according to the failure type. Compared to related technologies that directly restart the device without analyzing the failure type that triggered the OCP event, this embodiment can adopt different methods to deal with the target OCP event for different failure types, thereby effectively dealing with OCP events, improving the efficiency of OCP event processing, and solving the problem of low efficiency in OCP event processing in related technologies.

[0138] It is important to understand that, for Figures 3-13 The explanations of the same or corresponding steps can be cross-referenced, for example... Figure 3 The explanation of step 310 is applicable to Figure 4 Step 410 in the process.

[0139] Meanwhile, it should be understood that this application provides an intelligent solution for flexibly identifying the triggering cause of OCP events and responding to power OCP events. Specifically, by distinguishing different loads (including system load or peripheral load only) and different triggering causes (logic false alarms, recoverable soft failures, or hard failure damage), different response strategies can be executed, thereby optimizing the negative user experience caused by power OCP events (such as system crashes and restarts). At the same time, it avoids further hardware deterioration caused by continued use of hardware in the event of a power hard failure, improving the safety and reliability of the mobile phone. Furthermore, this application provides two schemes for determining the triggering cause of OCP events, as detailed below.

[0140] Option 1: First, determine whether the PMIC-triggered OCP event is due to a genuine power supply pull-down or a false alarm caused by the PMIC OCP detection logic by detecting the actual voltage and the REG value read from the OCP register. If the OCP event is confirmed to have occurred, determine whether the root cause of the OCP event is the input DC-DC converter or the output LDO by detecting the REG values ​​of the DC-DC converter and LDO after the debouncing wait time of the OCP event. Then, for systems including power supplies and peripheral power supplies only, perform a system restart and power-on re-energize the power supplies. Finally, determine whether the phenomenon continues to recur after initialization to determine whether it is a persistent hard circuit damage or a recoverable transient power supply pull-down event, and take different measures based on the different determination results.

[0141] Option 2: Determine the triggering cause of the OCP event by detecting the difference in battery output current. Specifically, read the average current for a period of time before the OCP event is reported (i.e., the first output current, denoted as Ibat1), and the average current for a period of time before the OCP event is reported (T = debounce Time + 100ms) (the second output current, denoted as Ibat2). Compare the first and second output currents to determine whether the OCP event is real or a logical false alarm. Then, continue reading the average current for a period of time after the OCP event is reported (the third output current, denoted as Ibat3). By comparing the second and third output currents, and comparing the first and third output currents, determine whether the OCP event is a hard failure or a recoverable soft failure.

[0142] Please see Figure 14 , Figure 14 This is a structural block diagram of an OCP event processing device provided in an embodiment of this application. Figure 14 As shown in the figure, this application provides an OCP event processing device 1400, which includes an acquisition module 1410, a determination module 1420 and a control module 1430.

[0143] Module 1410 is used to acquire the target OCP event reported by the PMIC; The determination module 1420 is used to determine the failure type that caused the target OCP event in response to the target OCP event being a non-false alarm event. The failure type includes hard failure or soft failure. The control module 1430 is used to control the electronic device to output a target prompt in response to a failure type that triggers a target OCP event, including a hard failure; and to adjust the target parameters that trigger a soft failure in response to a failure type that triggers a target OCP event, including a soft failure.

[0144] In this embodiment, a target OCP event reported by the PMIC is acquired; in response to the target OCP event being a non-false alarm event, the failure type that triggered the target OCP event is determined, including either a hard failure or a soft failure; in response to the failure type that triggered the target OCP event being a hard failure, the electronic device is controlled to output a target prompt; in response to the failure type that triggered the target OCP event being a soft failure, the target parameters that triggered the soft failure are adjusted. Thus, when acquiring a target OCP event reported by the PMIC, the failure type that triggered the target OCP event can be further determined, and the target OCP event can be handled specifically according to the failure type. Compared to related technologies that directly restart the device without analyzing the failure type that triggered the OCP event, this embodiment can adopt different methods to deal with the target OCP event for different failure types, thereby effectively dealing with OCP events, improving the efficiency of OCP event processing, and solving the problem of low efficiency in OCP event processing in related technologies.

[0145] The OCP event processing device provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0146] like Figure 15 As shown in the illustration, this application also provides an electronic device 1500. The electronic device 1500 includes a processor 1510 and a memory 1520. The memory 1520 stores programs or instructions, which, when executed by the processor 1510, implement the steps of any of the methods described above. For example, the electronic device is a mobile phone. When the program is executed by the processor 1510, it performs the following process: acquiring a target OCP event reported by the PMIC; in response to the target OCP event being a non-false alarm event, determining the failure type that triggered the target OCP event, where the failure type includes a hard failure or a soft failure; in response to the failure type of the target OCP event being a hard failure, controlling the electronic device to output a target prompt; in response to the failure type of the target OCP event being a soft failure, adjusting the target parameters that triggered the soft failure. Thus, when acquiring the target OCP event reported by the PMIC, the failure type that triggered the target OCP event can be further determined, and the target OCP event can be handled in a targeted manner according to the failure type. Compared with the related technologies that directly restart the device without analyzing the failure type that triggered the OCP event, the embodiments of this application can adopt different methods to deal with the target OCP event for different failure types, thereby effectively dealing with the OCP event, improving the efficiency of handling OCP events, and solving the problem of low efficiency in handling OCP events in related technologies.

[0147] For reference Figure 16 , Figure 16 This is a schematic diagram of the hardware structure of an electronic device that implements various embodiments of the present invention. For example... Figure 16As shown, the electronic device 1600 includes, but is not limited to, components such as: radio frequency unit 1601, network module 1602, audio output unit 1603, input unit 1604, sensor 1605, display unit 1606, user input unit 1607, interface unit 1608, memory 1609, and processor 1610.

[0148] Those skilled in the art will understand that the electronic device 1600 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1610 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 16 The electronic device structures shown are not intended to limit the electronic device. An electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements; these will not be elaborated further here. In embodiments of the present invention, the electronic device includes, but is not limited to, mobile phones, tablet computers, laptops, PDAs, in-vehicle terminals, wearable devices, and pedometers.

[0149] The processor 1610 is used to acquire the target OCP event reported by the PMIC; in response to the target OCP event being a non-false alarm event, it determines the failure type that triggered the target OCP event, including hard failure or soft failure; in response to the failure type that triggered the target OCP event being a hard failure, it controls the electronic device to output a target prompt; in response to the failure type that triggered the target OCP event being a soft failure, it adjusts the target parameters that triggered the soft failure.

[0150] The electronic device provided in this application embodiment acquires a target OCP event reported by the PMIC; in response to the target OCP event being a non-false alarm event, it determines the failure type that triggered the target OCP event, including hard failure or soft failure; in response to the failure type that triggered the target OCP event being a hard failure, it controls the electronic device to output a target prompt; in response to the failure type that triggered the target OCP event being a soft failure, it adjusts the target parameters that triggered the soft failure. Thus, when acquiring a target OCP event reported by the PMIC, the failure type that triggered the target OCP event can be further determined, and the target OCP event can be handled specifically according to the failure type. Compared to related technologies that directly restart the device without analyzing the failure type that triggered the OCP event, this application embodiment can adopt different methods to deal with the target OCP event for different failure types, thereby effectively dealing with OCP events, improving the efficiency of OCP event processing, and solving the problem of low efficiency in OCP event processing in related technologies.

[0151] It should be understood that, in this embodiment of the invention, the radio frequency unit 1601 can be used for receiving and transmitting signals during information transmission or calls. Specifically, it receives downlink data from the base station and processes it with the processor 1610; additionally, it transmits uplink data to the base station. Typically, the radio frequency unit 1601 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, etc. Furthermore, the radio frequency unit 1601 can also communicate with networks and other devices through a wireless communication system.

[0152] Electronic devices provide users with wireless broadband internet access through network module 1602, such as helping users send and receive emails, browse web pages, and access streaming media.

[0153] The audio output unit 1603 can convert audio data received by the radio frequency unit 1601 or the network module 1602 or stored in the memory 1609 into audio signals and output them as sound. Furthermore, the audio output unit 1603 can also provide audio output related to specific functions performed by the electronic device 1600 (e.g., call signal reception sound, message reception sound, etc.). The audio output unit 1603 includes a speaker, a buzzer, and a receiver, etc.

[0154] Input unit 1604 is used to receive audio or video signals. Input unit 1604 may include a graphics processing unit (GPU) 16041 and a microphone 16042. GPU 16041 processes image data of still images or videos acquired by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames can be displayed on display unit 1606. The image frames processed by GPU 16041 can be stored in memory 1609 (or other storage medium) or transmitted via radio frequency unit 1601 or network module 1602. Microphone 16042 can receive sound and process such sound into audio data. The processed audio data can be converted into a format that can be transmitted to a mobile communication base station via radio frequency unit 1601 in telephone call mode.

[0155] The electronic device 1600 also includes at least one sensor 1605, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display panel 16061 according to the ambient light level, and the proximity sensor can turn off the display panel 16061 and / or backlight when the electronic device 1600 is moved to the ear. As a type of motion sensor, an accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity and can be used to identify the posture of the electronic device (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc. The sensor 1605 may also include a fingerprint sensor, pressure sensor, iris sensor, molecular sensor, gyroscope, barometer, hygrometer, thermometer, infrared sensor, etc., which will not be described in detail here.

[0156] The display unit 1606 is used to display information input by the user or information provided to the user. The display unit 1606 may include a display panel 16061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0157] User input unit 1607 can be used to receive input numerical or character information, and generate key signal inputs related to user settings and function control of electronic devices. Specifically, user input unit 1607 includes a touch panel 16071 and other input devices 16072. Touch panel 16071, also known as a touch screen, can collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near touch panel 16071). Touch panel 16071 may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends it to processor 1610, which receives and executes commands from processor 1610. In addition, touch panel 16071 can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 16071, the user input unit 1607 may also include other input devices 16072. Specifically, other input devices 16072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0158] Furthermore, the touch panel 16071 can cover the display panel 16061. When the touch panel 16071 detects a touch operation on or near it, it transmits the information to the processor 1610 to determine the type of touch event. Subsequently, the processor 1610 provides corresponding visual output on the display panel 16061 based on the type of touch event. Although in Figure 16 In this embodiment, the touch panel 16071 and the display panel 16061 are two independent components to realize the input and output functions of the electronic device. However, in some embodiments, the touch panel 16071 and the display panel 16061 can be integrated to realize the input and output functions of the electronic device. The specific implementation is not limited here.

[0159] Interface unit 1608 serves as an interface for connecting external devices to electronic device 1600. For example, external devices may include a wired or wireless headphone port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, and so on. Interface unit 1605 may be used to receive input from external devices (e.g., data, power, etc.) and transmit the received input to one or more components within electronic device 1600, or it may be used to transmit data between electronic device 1600 and external devices.

[0160] The memory 1609 can be used to store software programs and various data. The memory 1609 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area may store data created based on the use of the mobile phone (such as audio data, phonebook, etc.). Furthermore, the memory 1609 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0161] Processor 1610 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs and / or modules stored in memory 1609, and by calling data stored in memory 1609, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Processor 1610 may include one or more processing units; preferably, processor 1610 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 1610.

[0162] In addition, the electronic device 1600 includes some functional modules not shown, which will not be described in detail here.

[0163] This application also provides a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of various embodiments of the OCP event handling method and achieve the same technical effect. To avoid repetition, these steps will not be repeated here.

[0164] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0165] This application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0166] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0167] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0168] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0169] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for handling overcurrent protection events, characterized in that, Applied to electronic devices, the electronic devices including: power management integrated circuits (PMICs); The method includes: Obtain the target overcurrent protection OCP event reported by the PMIC; In response to the target OCP event being a non-false alarm event, the failure type that triggered the target OCP event is determined, and the failure type includes hard failure or soft failure; In response to a failure type that triggers the target OCP event, including a hard failure, the electronic device is controlled to output a target prompt; in response to a failure type that triggers the target OCP event, including a soft failure, the target parameter that triggers the soft failure is adjusted.

2. The method according to claim 1, characterized in that, The PMIC includes a first power module, and the target OCP event indicates that the first power module has an OCP event. Before determining the failure type that triggered the target OCP event, the method further includes: Obtain the output voltage of the first power module; Obtain first indication information of the first power module; the first indication information is used to indicate whether the first power module has an OCP event at a first time point, and the first time point is the triggering time point of the target OCP event; If the output voltage is lower than or equal to a preset voltage value, and the first indication information indicates that the first power module has an OCP event at the first time point, the target OCP event is determined to be a non-false alarm event.

3. The method according to claim 2, characterized in that, After obtaining the output voltage of the first power module, the method further includes: If the output voltage is higher than the preset voltage value, the target OCP event is determined to be a false alarm event.

4. The method according to claim 1, characterized in that, The determination of the failure type that triggered the target OCP event includes: Identify the target power module that triggered the target OCP event; Restart the PMIC or the target power module; In response to the target power module triggering an OCP event again, the failure type that caused the target OCP event is determined to include a hard failure; In response to the target power module no longer experiencing OCP events, the failure type that triggered the target OCP event is determined to include soft failure.

5. The method according to claim 4, characterized in that, The PMIC includes a first power module and a second power module; the output voltage terminal of the first power module is connected to the input voltage terminal of the second power module, and the anti-shake waiting time of the first power module is shorter than that of the second power module. The determination of the target power module that triggers the target OCP event includes: In response to the target OCP event indicating that the first power module has experienced an OCP event, the system acquires second indication information of the first power module and third indication information of the second power module; the second indication information is used to indicate whether the first power module has experienced an OCP event at a second time point, and the third indication information is used to indicate whether the second power module has experienced an OCP event at the second time point. The second time point is after the first time point, the first time point is the trigger time of the target OCP event, and the time interval between the second time point and the first time point is greater than the anti-jitter waiting time of the second power module. If the second indication information indicates that the first power module has an OCP event at the second time point, and the third indication information indicates that the second power module has an OCP event at the second time point, then the second power module is identified as the target power module.

6. The method according to claim 4, characterized in that, The PMIC includes a first power module and a second power module; the output voltage terminal of the first power module is connected to the input voltage terminal of the second power module, and the anti-jitter waiting time of the first power module is shorter than that of the second power module; the target OCP event indicates that an OCP event has occurred in the first power module. The target parameters include the anti-shake waiting time of the first power module; The adjustment of the target parameter that triggers the soft failure includes: In response to the target power module being the second power module, the anti-jitter waiting time of the first power module is extended.

7. The method according to any one of claims 4-6, characterized in that, The target power module is used to supply power to the target load; the target load includes at least one of a minimum system module and a peripheral load. Restarting the PMIC or the target power module includes: If the target load includes the minimum system module, restart the PMIC; If the target load is the peripheral load, restart the target power module.

8. The method according to claim 1, characterized in that, The PMIC includes a target power module, and the target OCP event is triggered by the target power module. The target power module is used to supply power to the target load; Before controlling the electronic device to output the target prompt, the method further includes: Identify the failed target component; The target component includes at least one of the PMIC and the target load, and the target prompt is a prompt indicating that the target component has failed.

9. The method according to claim 8, characterized in that, The identified failed target component includes: Obtain the operating temperature of the PMIC; If the operating temperature is lower than the preset temperature, the target load is identified as the target component that has failed. If the operating temperature is higher than or equal to the preset temperature, the PMIC is identified as a target component that has failed.

10. The method according to claim 8, characterized in that, The target component includes the target load; the target load includes at least one of a minimum system module and a peripheral load. If the target load includes the minimum system module, the target indication is a flashing light indication; When the target load is the peripheral load, the target prompt includes at least one of the following: vibration prompt, pop-up prompt, and sound prompt.

11. The method according to claim 1, characterized in that, The electronic device further includes a power supply component; before determining the failure type that triggered the target OCP event, the method further includes: The first output current of the power supply component is obtained in a first time period; the first time period includes the trigger time of the target OCP event; The second output current of the power supply component is obtained in a second time period; the second time period is before the first time period. If the difference between the first output current and the second output current is greater than a preset current value, the target OCP event is determined to be a non-false alarm event.

12. The method according to claim 11, characterized in that, The determination of the failure type that triggered the target OCP event includes: The third output current of the power supply component in a third time period is obtained; the third time period is after the first time period. If the difference between the third output current and the second output current is less than a first preset value, the failure type that triggers the target OCP event is determined to be a soft failure. If the difference between the third output current and the first output current is less than a second preset value, the failure type that triggers the target OCP event is determined to be a hard failure.

13. The method according to claim 1, characterized in that, The target parameters include the performance parameters of the electronic device; the target OCP event is reported when the electronic device executes the first thread. The adjustment of the target parameter that triggers the soft failure includes: In response to the electronic device executing a second thread, the performance parameters of the electronic device are reduced; The similarity between the load characteristics of the electronic device executing the second thread and the load characteristics of the electronic device executing the first thread is greater than a preset threshold.

14. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 13.

Images