Photovoltaic cell-level independent parallel and pre-storage variable post-digital multiplexing electric energy collection architecture and system

Abstract

A photovoltaic cell-level independent parallel connection and pre-storage and post-transformation digital multiplexing power collection architecture and system are presented. Each cell integrates a micro solid-state energy storage device, a bidirectional converter, a GaN switch, and a control chip on its back, forming an intelligent power generation unit. This achieves local power smoothing and constant power output before and after storage. All unit outputs are directly connected in parallel to a 48V common bus via high-speed switches, completely eliminating the bottleneck effect and hot spot risk caused by series connection. Multiple cells share a high-frequency isolated LLC converter core through time-division multiplexing technology, reducing costs. The central controller is based on an FPGA plus ARM architecture, dynamically scheduling the access time slots of each cell with a period of 10μs. The underlying chip performs microsecond-level fast protection, achieving a system efficiency of over 98%. This architecture realizes full-link decoupling and intelligent collaboration from cells to the grid, significantly improving power generation, reliability, and lifespan.

Description

Technical Field

[0001] This invention belongs to the interdisciplinary innovation field of photovoltaic power generation and power electronics, specifically involving a novel power collection architecture based on independent parallel connection and digital multiplexing at the cell level. The core technology areas encompass photovoltaic power generation technology, focusing on the physical characteristics of cells and intelligent reconfiguration at the module level; power electronics technology focuses on the design and control of high-frequency isolated DC-DC converters, GaN-based high-speed switching devices, and micro-bidirectional energy storage converters; automatic control and scheduling algorithms involve MPPT, energy storage SOC management, and AI-predictive multi-channel real-time scheduling strategies; energy storage technology covers the integration and collaborative management of micro-thin-film solid-state batteries or supercapacitors; microelectronics and integrated circuit technology includes the back-side integration of application-specific integrated circuits (ASICs), sensor fusion, and local protection logic; and communication and information systems enable data interaction and real-time synchronization between cells and a central controller. This invention deeply integrates materials science, semiconductor processes, and intelligent algorithms, constituting a multidisciplinary, system-level innovation. Background Technology

[0002] Traditional photovoltaic (PV) systems typically employ a series-to-parallel topology, using centralized or string inverters to collect electrical energy. However, this architecture inherently suffers from the "weakest link" effect: the overall output power of a series string is limited by the weakest performing module. When partial shading, cell aging, or parameter inconsistencies occur, significant power mismatch losses result. More seriously, mismatch can cause the shaded cells to be reverse-biased, triggering hot spots, which not only reduces power generation but can also burn out the module and cause fires. To mitigate these problems, the industry often connects bypass diodes in parallel within the module junction box; however, this method only partially eliminates the risk of hot spots and cannot solve the power loss caused by current mismatch.

[0003] In recent years, module-level power electronics technologies, represented by photovoltaic power optimizers and microinverters, have been widely applied, effectively improving power generation under mismatch conditions by implementing maximum power point tracking independently for each module. However, existing solutions still remain at the module-level optimization level, requiring each module to be equipped with a complete DC-DC conversion circuit, resulting in a linear increase in system cost with the number of modules. Furthermore, the series connection structure between cells within the module remains unchanged, and hot spot risks and aging mismatch issues persist at the cell level. Therefore, addressing the mismatch problem at the more fundamental cell level, while simultaneously overcoming the trade-off between cost and performance in module-level power electronics, has become a crucial direction for the development of photovoltaic technology. Summary of the Invention

[0004] The invented photovoltaic cell-level independent parallel connection and pre-storage and post-transformation digital multiplexing power collection architecture and system is composed of three core layers from bottom to top, each containing specific innovative structures and functional entities. The bottom layer is the intelligent photovoltaic cell unit, which is the foundation of the system's power generation and energy storage. This unit uses a standard photovoltaic cell as a carrier, and on its back side, it integrates three core components using thin-film deposition and micro-assembly processes: First, a micro thin-film solid-state energy storage device, using lithium ceramic batteries or supercapacitors, with a capacity designed to be 0.1 to 0.2 Wh, is used to smooth local light fluctuations, enabling the cell to exhibit constant power source characteristics; second, a micro bidirectional DC-DC converter, which realizes bidirectional energy flow control between the cell and the energy storage device, and completes maximum power point tracking and energy storage charge and discharge management; third, a GaN-based high-speed switch and dedicated control chip, which integrates data acquisition, local protection, and communication interface functions, and achieves selective connection with the common bus through a high-speed switch. The core feature of this layer is its pre-storage and post-conversion structure. The energy storage unit is located before the converter; energy flows through the cells, is first stored in the storage system, and then converted for output, completely decoupling the power generation and transmission links. The middle layer is a digital multiplexing and aggregation layer, crucial for hardware sharing and low cost. This layer first constructs a series-free, independent parallel bus topology. The outputs of all intelligent cell units are directly connected in parallel to a common DC bus via their respective high-speed switches. The bus voltage is uniformly set by the system, completely eliminating the bottleneck effect and hot spot risks associated with traditional series structures. Secondly, this layer is equipped with a high-frequency isolated shared converter core, typically using a three-phase LLC resonant converter topology, which efficiently boosts the low-voltage DC from the common bus to the grid-connected voltage level while achieving electrical isolation. The core feature of this layer is digital multiplexing and hardware sharing. Instead of each cell having its own independent high-power converter, all cells share the same high-frequency isolated converter core through time-division multiplexing technology. The central controller polls and schedules the connection of each cell at a megahertz frequency, reducing system costs. The top layer is the central control and communication system, serving as the system's scheduling and decision-making hub. This layer includes a central controller based on FPGA or high-performance DSP, and a high-speed communication network covering the entire area. The central controller interacts bidirectionally with the control chips of each solar cell in real time via a dedicated differential bus or power line carrier communication, collecting voltage, current, temperature, and energy storage state of charge information, and issuing dynamic scheduling commands. The core feature of this layer is its three-layer collaborative control architecture: the bottom-layer dedicated solar cell chips are responsible for microsecond-level local rapid response and protection; the multiplexing layer central controller is responsible for millisecond-level time slot allocation and switch matrix scheduling; and the system layer main control unit is responsible for energy management and external grid coordination at the second level and above. Through an AI-based predictive scheduling algorithm, the system can dynamically optimize the access timing and duration of each solar cell based on irradiance prediction and energy storage status, achieving global energy balance and optimal efficiency.The above three layers, through the close coupling of physics and information, constitute a complete power collection system from solar cells to the power grid, and are ultimately connected to the external power grid through a standard grid-connected inverter.

[0005] Micro-thin-film solid-state energy storage devices are core components for achieving cell-level energy buffering. Their design revolves around four aspects: material selection, multilayer structure construction, key performance indicators, and integration processes. In terms of materials, high-voltage spinel-structured lithium manganese nickel oxide is selected as the positive electrode, leveraging its three-dimensional lithium-ion diffusion channels to support rapid charging and discharging. Lithium titanate is used as the negative electrode, ensuring long lifespan due to its zero-strain characteristics and minimal volume change during cycling. The electrolyte is a lithium lanthanum titanium oxide fast-ion conductor, achieving a room-temperature ionic conductivity on the order of 10⁻⁴ S / cm, while also possessing thermal stability and compatibility with thin-film fabrication. In terms of structural design, a sandwich-style multilayer configuration is adopted. The positive electrode, solid electrolyte, and negative electrode films are sequentially deposited on the back of the photovoltaic cell using radio frequency magnetron sputtering technology. The thickness of each layer is controlled at the micrometer level, with a total thickness not exceeding 50 micrometers, ensuring no significant increase in module weight and volume. In terms of performance, the single-cell energy storage capacity is designed to be 0.1 to 0.2 Wh, sufficient to support the cell to continuously output 50% power for 30 seconds under fluctuating light conditions. Regarding cycle stability, laboratory data shows it can stably charge and discharge more than 500 times with good capacity retention, and this can be further improved to the million-cycle level through interface toughening and strain control strategies. In terms of integration technology, vacuum deposition equipment is used to achieve continuous deposition of multilayer films, avoiding vacuum damage to ensure interface purity. Simultaneously, drawing inspiration from dry processes in semiconductor manufacturing, an ultra-thin solid electrolyte membrane is prepared using binder fibrillation technology, reducing the thickness to 18 micrometers, significantly improving energy density. Through the above design, this micro-energy storage device achieves integrated operation with photovoltaic cells, providing a local energy buffer foundation for subsequent digital multiplexing and scheduling.

[0006] The miniature bidirectional DC-DC converter is the core component for controlling the bidirectional energy flow between solar cells and miniature energy storage devices. Its design revolves around four aspects: topology selection, power device selection, control strategy implementation, and expected performance indicators. Regarding the topology, considering the single-cell power level of only a few watts and the extremely high size constraints, a non-isolated buck-boost integrated topology is chosen as the main circuit architecture. This topology employs a four-switch Buck-Boost structure, using a combination of two high-frequency switching transistors and two synchronous rectifier transistors to achieve flexible switching between boost and buck bidirectional operating modes: when the solar cell needs to charge the energy storage device, the converter operates in Buck mode, reducing the solar cell voltage to the energy storage device's appropriate voltage; when the energy storage device needs to discharge to support the solar cell's output, the converter operates in Boost mode, increasing the energy storage device voltage to the bus voltage level. In terms of power device selection, all devices utilize gallium nitride (GaN) high electron mobility transistors (HMTs), which, with their extremely low on-resistance, ultra-fast switching speed, and zero reverse recovery charge, can achieve high-efficiency energy conversion at megahertz-level switching frequencies. In terms of control strategy, a digital PID algorithm based on a dedicated control chip is adopted. By sampling the output voltage and current of the battery cells and the state of charge of the energy storage device in real time, the operating mode switching and power flow of the converter are precisely controlled. To achieve shock-free mode switching, an incremental PID control algorithm is introduced to eliminate power surges caused by sudden changes in the setpoint, ensuring a smooth and stable charging and discharging switching process. Simultaneously, soft switching conditions such as zero-voltage turn-on or zero-current turn-off are achieved by optimizing the switching timing, further reducing switching losses. In terms of performance indicators, the design target is a peak converter efficiency of no less than 98%, a power density in the tens of watts per cubic centimeter range, and a charging and discharging mode switching time controlled in the microsecond range to ensure timing matching with digital multiplexing scheduling. Through the above design, this miniature bidirectional DC-DC converter realizes efficient energy interaction between the battery cells and the miniature energy storage device, providing key support for the battery cells to exhibit constant power source characteristics.

[0007] GaN-based high-speed switches and dedicated control chips are the core components for achieving high-speed switching and intelligent scheduling at the cell level. Together, they form the "execution and decision-making center" of the intelligent photovoltaic cell unit. In terms of high-speed switch design, an enhanced GaN HEMT is selected as the power switching device, whose key advantages lie in its extremely low on-resistance and ultra-fast switching speed. To adapt to the topology requirements of independently parallel cell connections, the switch adopts a bidirectional conduction design, capable of blocking bidirectional voltage and current. Its single-chip integrated structure significantly simplifies the circuit and reduces losses compared to traditional back-to-back connection schemes. Regarding the dedicated control chip design, a dedicated ASIC based on the ARM Cortex-M33 core is used, with a main frequency of up to 216MHz. It integrates a single-precision floating-point unit and a hardware trigonometric function accelerator to support complex real-time control algorithms. This chip integrates a high-precision timer module, capable of outputting PWM pulses with a resolution of up to 145 picoseconds for precise control of the GaN switch's on and off timing. Meanwhile, the chip integrates a multi-channel 12-bit ADC analog-to-digital converter with a sampling rate of 5.3 mega-sampling times per second for real-time acquisition of cell voltage, current, and energy storage state-of-charge data. An on-chip comparator enables rapid hardware response to overcurrent and overvoltage faults, and its output signal can directly block the PWM output, ensuring microsecond-level shutdown in case of a fault. For communication interfaces, the dedicated chip integrates a USART or CAN controller, enabling bidirectional data exchange with the central controller via a high-speed differential bus, uploading status information and receiving scheduling commands. In terms of the collaborative working mechanism, the dedicated control chip generates drive pulses strictly synchronized with the system frame structure using a high-precision timer based on the time slot allocation table issued by the central controller. This precisely controls the GaN switch to conduct within specified microsecond-level time slots, connecting the cells to the common bus. During non-conducting time slots, the switch remains off, and the generated energy from the cells is temporarily stored in a micro-energy storage device. Through the above design, the tight coupling between the GaN high-speed switch and the dedicated control chip enables high-speed on / off control at the megahertz level, switching at the nanosecond level, fault protection at the microsecond level, and precise timing synchronization, providing a hardware foundation for the reliable execution of digital multiplexing scheduling.

[0008] The series-free independent parallel bus topology abandons the core implementation of the traditional photovoltaic module series-then-parallel architecture. Its design revolves around four aspects: establishing the bus voltage system, physical connection structure, power aggregation mechanism, and interface matching with the shared conversion core. Regarding the voltage system, considering both safety and transmission efficiency, the common DC bus voltage is selected as a low-voltage safety level of 48V. This voltage is below the 60V DC safety threshold, eliminating the need for additional electric shock protection design, while supporting power transmission from hundreds of watts to thousands of watts, and also matching well with the input voltage range of the subsequent high-frequency isolation converter. In terms of physical connection structure design, the output terminals of all intelligent photovoltaic cell units are directly connected in parallel to the common bus via their integrated GaN high-speed switches using a star-shaped aggregation method. The bus adopts a low-inductance multilayer PCB board or copper foil stacked structure, with its cross-sectional area determined based on the total system power calculation to ensure a DC voltage drop of less than 0.5%. Each cell's connection point is equipped with a miniature RC absorption circuit to suppress voltage spikes and electromagnetic interference caused by high-frequency switching operations. In terms of power aggregation mechanism, this topology achieves true current superposition: at any given time, the total current on the common bus equals the sum of the output currents of all cells in the conduction slot, and the bus voltage is stabilized at a setpoint of 48V by the shared converter core through closed-loop control. Since there are no series paths between the cells, the current clamping effect caused by series connection in traditional topologies is completely eliminated—when the performance of a cell degrades or is partially blocked, only its own output power decreases, without affecting the normal operation of other parallel cells, thus physically eliminating the bottleneck effect and hot spot risk. Regarding interface matching, the bus output is directly connected to the input port of the high-frequency isolated shared converter core, with only an EMI filter circuit and a pre-charge soft-start circuit between them. The input capacitor of the converter core is connected in parallel with the bus, and its value must meet the requirement of maintaining stable bus voltage within the microsecond intervals of high-speed switching polling. Typically, ceramic or film capacitors with low equivalent series resistance are selected, and the capacitance value is calculated and determined based on the energy of a single input pulse and the allowable voltage fluctuation range. Furthermore, this topology inherently possesses fault redundancy characteristics: when the central controller detects a short-circuit fault in the GaN switch of a solar cell, it can instruct adjacent solar cells to poll and avoid the fault point, and prompt for replacement via a system-level alarm; if a solar cell has an open-circuit fault, it automatically disconnects from the bus, and the system operates at reduced derating without interruption. Through the above design, the series-free independent parallel bus topology constructs a low-impedance, highly reliable, and scalable power pooling platform, providing a physical foundation for efficient operation of digital multiplexing scheduling and shared conversion cores.

[0009] The high-frequency isolated shared converter core is a key component for voltage boosting, electrical isolation, and power aggregation. Its design revolves around four aspects: topology selection, resonant network parameters, soft-switching implementation, and control strategy. In terms of topology, a three-phase LLC resonant converter is selected as the main circuit architecture. This topology, with its inherent suitability for high-frequency operation, ease of soft-switching, and low electromagnetic interference, has become an ideal solution for low-voltage, high-current applications such as 48V residential photovoltaic energy storage systems. The converter uses a three-phase full-bridge structure as the primary inverter stage, with six GaN power switches forming three half-bridges to invert the 48V low-voltage DC from the common DC bus into a high-frequency square wave voltage. The intermediate stage is a high-frequency isolation transformer, employing a high-performance ferrite core and Litz wire windings to achieve electrical isolation and voltage matching. The transformer turns ratio is designed to be 1:8 to 1:10 according to the grid voltage level, boosting the low-voltage side voltage to approximately 400V. The secondary side uses a three-phase full-bridge rectifier circuit to convert high-frequency AC to high-voltage DC output to the subsequent grid-connected inverter. In the resonant network design, each phase is configured with an independent LLC resonant cavity consisting of a resonant inductor, resonant capacitor, and magnetizing inductor. The resonant frequency is designed within the range of 100kHz to 500kHz. The resonant parameters are calculated using the fundamental frequency analysis method to ensure that the converter achieves zero-voltage turn-on of the primary-side switch and zero-current turn-off of the secondary-side rectifier across the entire load range. This soft-switching characteristic significantly reduces switching losses, enabling the converter to achieve a peak efficiency of over 98%. Regarding the collaborative working mechanism with digital multiplexing scheduling, the input ports of the shared conversion core are directly connected in parallel to the common DC bus. The design of its input filter capacitors must meet the requirement of maintaining bus voltage stability within the microsecond-level intervals of high-speed switching polling. Typically, ceramic or film capacitors with low equivalent series resistance are selected, and the capacitance value is calculated and determined based on the energy of a single input pulse and the allowable voltage fluctuation range. In terms of control strategy, the converter core adopts output voltage closed-loop control with the goal of stabilizing the bus voltage: when the total power of the connected solar cells scheduled by the central controller increases, the bus voltage tends to rise. The converter's control loop automatically adjusts the switching frequency or duty cycle to increase the power drawn from the bus, pulling the bus voltage back to the 48V setpoint. This control method achieves automatic power balance under the voltage source bus, and the converter core does not need to sense the connection status of each solar cell, only need to respond to bus voltage fluctuations. To achieve bidirectional power flow capability, the converter adopts a symmetrical LLC resonant cavity design, combined with edge-off variable conduction time modulation, to achieve zero circulating current on the low-voltage side of the transformer and completely symmetrical gain characteristics during bidirectional operation. Through the above design, the high-frequency isolated shared converter core achieves efficient conversion from 48V low-voltage bus to 400V high-voltage DC, providing the system with core functions of electrical isolation, voltage matching, and power aggregation. The central control and communication system serves as the central nervous system for global intelligent scheduling and collaborative operation. Its design revolves around four aspects: the main controller hardware platform, the two-layer communication network architecture, the three-layer collaborative control strategy, and the interface with external systems. In terms of hardware platform design, the central controller employs a heterogeneous computing architecture combining a high-performance FPGA with an ARM core DSP. The FPGA is responsible for the hard logic implementation of microsecond-level real-time scheduling tasks, including timing control of the high-speed switching matrix and parallel acquisition and preprocessing of multi-channel data. The ARM core DSP handles complex algorithm calculations and system management, including AI-based predictive scheduling algorithms, energy storage state-of-charge optimization, and communication with the external power grid. Its main frequency reaches hundreds of megahertz, and it has a built-in floating-point unit to support real-time MPPT calculations. In terms of communication network architecture, the system constructs a two-layer physical channel: the upper layer is a high-speed differential bus between the central controller and the dedicated control chips of each battery cell, which adopts RS-485 physical layer combined with a custom real-time protocol, supports megahertz-level polling frequency and microsecond-level synchronization accuracy, and ensures the real-time uploading of status data of hundreds of battery cells and the reliable issuance of scheduling commands; the lower layer is a backup data channel based on power line carrier communication, which uses a common DC bus as the transmission medium and adopts on / off keying modulation method to support multiple frequency bands from 125kHz to 5MHz, providing redundant communication guarantee when the high-speed bus fails, and is also used for low-speed transmission of non-real-time status data and firmware upgrades. The three-layer collaborative control strategy consists of a bottom layer, the local fast response layer, where dedicated chips for each battery cell perform microsecond-level local protection and power smoothing control; a middle layer, the multiplexing and scheduling layer, where the central controller performs millisecond-level time slot allocation and switch matrix scheduling, calculating the optimal access sequence for each battery cell in real time based on a dynamic priority algorithm, with priority determined by weighted factors such as energy storage state of charge, current power generation, and predicted irradiance changes; and a top layer, the system coordination layer, where the main control unit performs energy management and external grid coordination at the second level or higher, including adjusting system operation strategies based on weather forecasts, coordinating with grid-connected inverters to achieve power factor regulation, and responding to grid dispatch commands to participate in demand response. In terms of external interface design, the central control system is equipped with standard industrial Ethernet and CAN bus interfaces, enabling high-speed data interaction with grid-connected inverters, energy storage systems, and power plant monitoring systems via real-time Ethernet protocols such as EtherCAT, with communication latency controllable to within 1.2 milliseconds; it also supports interface with the upper-level dispatch system via a protocol conversion gateway, compatible with multiple power industry standard protocols such as Modbus RTU and IEC 61850. Furthermore, the system integrates edge computing capabilities, enabling data processing and decision-making locally, reducing reliance on the cloud, minimizing decision latency, and enhancing data privacy and security. Through this design, the central control and communication system achieves end-to-end information connectivity and intelligent collaboration from solar cells to the power grid, providing a decision-making and communication foundation for reliable execution of digital multiplexing scheduling and optimization of overall system efficiency.

[0010] The three-layer collaborative control architecture realizes the core control logic from local rapid response of the solar cell to global energy optimization of the system. Its design revolves around four aspects: time scale decomposition, functional boundary division, information interaction mechanism, and cross-layer collaborative strategy. This architecture divides the control task into a bottom-layer local rapid response layer, a middle-layer reuse scheduling layer, and a top-layer system coordination layer. These three layers are tightly coupled through a clear division of time scales and standardized information interfaces. The bottom-layer local rapid response layer operates on a microsecond-level time scale and is deployed in a dedicated control chip on the back of each solar cell. The main functions of this layer include: real-time acquisition of cell voltage, current, temperature, and energy storage state of charge data, with a sampling rate of several megahertz; execution of rapid overcurrent, overvoltage, and overheat protection based on hardware comparators, with response time controlled at the microsecond level, ensuring that the GaN high-speed switch can be shut down within 1 microsecond in the event of a fault, achieving local isolation; execution of a power smoothing control algorithm, dynamically controlling the operating mode of the micro bidirectional DC-DC converter based on the energy storage state of charge and the real-time output power of the cells, so that the combined cell and energy storage exhibit constant power source characteristics; simultaneously, uploading the acquired state data to the middle layer via a high-speed differential bus, and receiving time slot scheduling commands from the middle layer, generating drive pulses strictly synchronized with the system frame structure through a high-precision timer to precisely control the on and off of the GaN switch. This layer achieves the most direct control of the physical quantities of the cells and is the cornerstone of reliable system operation. The middle layer, multiplexing the scheduling layer, operates on a millisecond timescale and is deployed in the central controller FPGA. The main functions of this layer include: polling all solar cells at megahertz frequencies via a high-speed differential bus to collect real-time data on voltage, current, temperature, and energy storage state of charge (SOC). It runs a dynamic priority scheduling algorithm, calculating the access priority of each solar cell based on multi-dimensional weighting factors, including the deviation of the SOC from the ideal range, the volatility of current power generation, predicted irradiance trends, and fault status. Based on the priority ranking, it dynamically generates the switching timing table for the next frame, using the system-defined multiplexing frame period as the unit, precisely allocating the access time slots and durations for each solar cell. The timing table is broadcast to the dedicated control chips of each solar cell via the high-speed bus, ensuring that the switching actions of hundreds of solar cells are synchronized within microsecond precision. This layer achieves real-time optimized allocation of system resources and is the core of the digital multiplexing scheduling mechanism. The top-level system coordination layer operates on a timescale of seconds or higher and is deployed in the ARM core DSP of the main control unit.The main functions of this layer include: aggregating global state data uploaded from the intermediate layer to establish a system-level energy model; running AI-based predictive scheduling algorithms to predict the power generation trends of each battery cell within the next few minutes to hours using historical irradiance data and weather forecast information, and adjusting the intermediate layer's scheduling strategy in advance, such as adjusting the operating window of each battery cell's energy storage state of charge based on the prediction results to reserve buffer capacity for upcoming irradiance changes; executing energy storage balancing management algorithms to ensure that the state of charge of each battery cell's micro-energy storage is kept within a reasonable range, avoiding long-term overcharging or over-discharging of some energy storage; coordinating with the external grid dispatching system and grid-connected inverters to respond to grid commands and adjust the system's operating strategy, such as participating in primary frequency regulation, reactive power support, or demand response; and also undertaking functions such as system health diagnosis, fault recording and reporting, and firmware upgrade management. This layer realizes intelligent interaction between the system and the external environment and serves as the decision-making center for global energy optimization and grid coordination. The three layers achieve closed-loop collaboration through standardized information interfaces: the bottom layer uploads real-time status data to the middle layer, and the middle layer sends time-slot scheduling instructions to the bottom layer; the middle layer uploads aggregated global status data to the top layer, and the top layer sends optimization targets and scheduling strategy parameters to the middle layer. When a fault is detected, the bottom layer can bypass the middle layer and directly execute fast protection, while simultaneously uploading the fault status. Upon receiving the fault information, the middle layer dynamically adjusts its scheduling strategy, removing the isolated solar cells from the scheduling queue, and the top layer records the fault and triggers an alarm. Through this design, the three-layer collaborative control architecture achieves complete timescale coverage from microsecond-level rapid response to hourly energy planning, ensuring the system's real-time performance, reliability, and global optimality.

[0011] This invention, through a fundamental restructuring of the underlying architecture of photovoltaic systems, brings multi-dimensional advantages unattainable by traditional technologies. Its core value lies in transforming photovoltaic power generation units from passive, mutually coupled energy devices into active, completely decoupled intelligent energy nodes. Firstly, in terms of power generation efficiency, this solution completely eliminates the inherent "weakest link" effect of traditional series structures. Because all cells achieve complete physical and electrical decoupling through independent parallel bus topologies, when the performance of any single cell degrades due to shading, aging, or contamination, the reduction in its output power only affects itself, unlike traditional strings which restrict the current of other normal cells. This significantly increases the actual power generation of the system under complex lighting conditions. More importantly, because each cell is equipped with a micro-energy storage unit for local power smoothing, the subsequent converter always faces a constant power source, allowing it to operate at its optimal efficiency point for extended periods. Combined with the high-frequency isolated shared conversion core's peak efficiency of over 98%, the overall system efficiency is 5 to 7 percentage points higher than traditional solutions. Secondly, in terms of safety and reliability, this solution eradicates the persistent problem of photovoltaic systems—the hot spot effect—from a physical mechanism perspective. In traditional series architectures, shaded solar cells are forced into a reverse bias state, consuming power and generating high temperatures. In this solution, each cell is independently connected in parallel and buffered by local energy storage, making it impossible for it to become a load. Simultaneously, the rapid protection function integrated with the GaN high-speed switch and dedicated control chip can isolate faulty units within microseconds, achieving "self-destructive" isolation of single-point faults and ensuring the safety of the rest of the system. This design gives the system extremely high fault redundancy; damage to any single cell only causes a slight derating of the system, rather than a complete string shutdown, significantly improving power supply reliability and availability. Furthermore, in terms of system economy and scalability, digital multiplexing technology achieves a revolutionary reduction in hardware costs. Traditional component-level power electronics technology requires a complete DC-DC converter for each component, with costs increasing linearly with power. In this invention, hundreds of solar cells share a single high-frequency isolated conversion core through time-division multiplexing, reducing converter costs. Although this increases the cost of micro-energy storage and integrated chips, these costs will rapidly decrease with the maturation of semiconductor processes and thin-film battery technology. More importantly, this architecture inherently supports modular expansion. Whether increasing the number of solar cells or building a larger-scale photovoltaic array, it only requires parallel connection on the existing busbar, without redesigning the topology or replacing core equipment. Finally, in terms of lifespan and intelligence, the introduction of micro-energy storage units not only achieves power smoothing but also acts as an "energy storage coupler." It decouples solar cell power generation from grid-connected output, allowing the system to actively control the charging and discharging behavior of the energy storage units based on grid demand or electricity price signals, achieving true photovoltaic power plant-level energy time-shifting.Meanwhile, the central control system, through a three-layer collaborative architecture, can monitor the health status of each battery in real time and dynamically adjust the scheduling strategy to balance the state of charge and aging of each energy storage unit. This makes the lifespan of the entire system no longer limited by the weakest individual unit, and is expected to extend the effective lifespan of photovoltaic modules from 25 years to more than 30 years, thereby maximizing the reduction of the levelized cost of electricity (LCOE) throughout the entire life cycle. Attached Figure Description

[0012] Appendix Figure 1 This is a diagram showing the overall composition of the photovoltaic cell-level independent parallel connection and the digital multiplexing power collection architecture and system before and after energy storage as described in this invention.

[0013] Appendix Figure 2 This is a schematic diagram of a micro-thin-film solid-state energy storage device based on the photovoltaic cell-level independent parallel connection and the digital multiplexing power collection architecture and system before and after energy storage as described in this invention.

[0014] Appendix Figure 3 This is a schematic diagram of a micro bidirectional DC-DC converter for the photovoltaic cell-level independent parallel connection and pre-storage and post-transformation digital multiplexing power collection architecture and system described in this invention.

[0015] Appendix Figure 4 This is a schematic diagram of the GaN-based high-speed switch and dedicated control chip of the photovoltaic cell-level independent parallel and pre-storage and post-transformation digital multiplexing power collection architecture and system described in this invention.

[0016] Appendix Figure 5 This is a schematic diagram of the independent parallel bus topology of the photovoltaic cell-level independent parallel connection and the digital multiplexing power collection architecture and system before and after energy storage as described in this invention.

[0017] Appendix Figure 6 This is a schematic diagram of the high-frequency isolated shared conversion core of the photovoltaic cell-level independent parallel and pre-storage and post-transformation digital multiplexing power collection architecture and system described in this invention.

[0018] Appendix Figure 7 This is a schematic diagram of the central control and communication system of the photovoltaic cell-level independent parallel and pre-storage and post-transformation digital multiplexing power collection architecture and system described in this invention.

[0019] Appendix Figure 8 This is a schematic diagram of the three-layer collaborative control architecture of the photovoltaic cell-level independent parallel connection and the digital multiplexing power collection architecture and system before and after energy storage as described in this invention.

[0020] Appendix Figure 9 This is a schematic diagram of the software programming of the central controller of the photovoltaic cell-level independent parallel connection and pre-storage and post-transformation digital multiplexing power collection architecture and system described in this invention.

[0021] Appendix Figure 10This is a schematic diagram of the software programming of the local control chip of the photovoltaic cell-level independent parallel connection and pre-storage and post-transformation digital multiplexing power collection architecture and system described in this invention. Detailed Implementation

[0022] The specific implementation of the invented photovoltaic cell-level independent parallel connection and pre-storage and post-transformation digital multiplexing power collection architecture and system is as follows: Standard M6 monocrystalline silicon photovoltaic cells with a peak power of 6.5W are selected. A 0.15Wh thin-film solid-state energy storage device, a 2MHz four-switch Buck-Boost bidirectional converter, a 5mΩ GaN high-speed switch, and a dedicated control chip are integrated on the back of each cell. The output of all cells is directly connected in parallel to a 48V common DC bus via GaN switches. A 10kW three-phase LLC resonant converter with parameters of a switching frequency of 300kHz, a transformation ratio of 1:8, and an efficiency of 98.2% is connected to the bus to boost the voltage to 400V for grid connection. An FPGA plus ARM central controller communicates with each cell via an RS-485 bus, generating multiplexing frames with a 10μs period. Eight time slots are used for cell access, with time slots dynamically allocated based on the energy storage SOC and power generation. For example, under normal lighting conditions, each battery cell is uniformly polled. When a cell is shaded, the local energy storage discharges to maintain a constant power output. Upon detecting a drop in SOC, the controller immediately adds a time slot in the next frame to replenish the energy storage. In case of a fault, the local chip shuts off the switch and reports the fault within 500ns. The controller removes the faulty unit, and the system only experiences a derating of 0.1%. The entire end-to-end control delay is <1.2μs, achieving independent parallel connection of battery cells and digital multiplexing of energy.

[0023] The software and programming implementation is as follows: The central controller is based on the Xilinx Zynq UltraScale+ MPSoC and developed using the Vivado and Vitis toolchains. The FPGA logic is written in Verilog HDL to achieve hard real-time generation of 10μs multiplexed frames, precise timing control of 8 time slots, and the physical layer protocol of the RS-485 bus, ensuring that the delay from bus interrupt to PWM output is less than 200ns. The ARM Cortex-A53 core runs an embedded Linux system. The scheduling algorithm is implemented in C language. The core functions include dynamic priority calculation, with weighting factors of 40% for energy storage SOC deviation, 30% for current power fluctuation, and 30% for historical irradiance trend; faulty cell removal and remapping; and an irradiance prediction module based on a lightweight neural network, deployed using TensorFlow Lite Micro, with a model size of approximately 50KB. The local battery cell control chip is based on the ARM Cortex-M33 and developed in C using the Keil MDK environment. The main program modules include: a 2MHz interrupt service routine for ADC sampling of voltage, current, and temperature, and PID control of the bidirectional converter; a hardware comparator interrupt for fast protection triggering GaN switch turn-off within 500ns; and a communication protocol stack for data interaction with the central controller, employing a custom lightweight protocol including frame headers, IDs, status, and CRC checks. All programs support remote upgrades via Ethernet, and runtime logs are uploaded to the cloud in real time.

Claims

1. A photovoltaic cell-level independent parallel connection and a digital multiplexing power collection architecture and system for energy storage before and after transformation, characterized by: All battery cells By directly connecting to independent parallel buses, complete electrical decoupling between solar cells is achieved. In terms of energy flow, a "storage-before-converter" architecture is created, placing micro-energy storage before the converter, enabling the solar cells to exhibit constant power source characteristics, and ensuring that the downstream converter always operates at its highest efficiency point. In terms of hardware architecture, digital multiplexing technology is adopted, allowing multiple solar cells to share a single high-frequency isolated conversion core through time-division multiplexing, reducing converter costs. In terms of control, the constructed three-layer collaborative control architecture decentralizes control granularity down to each solar cell, achieving full time-scale coverage from microsecond-level local protection to second-level grid coordination. In terms of energy storage integration, micro solid-state energy storage devices are integrated on the back of standard photovoltaic cells, raising the cell-level energy storage power to a practical level. These differentiated features together constitute a fundamental reconstruction of the underlying architecture of photovoltaic systems.

Images