Half-bridgeless pfc circuit, power supply system, computer and method for operating a half-bridgeless pfc circuit

Abstract

This invention relates to the field of circuits, specifically disclosing a semi-bridgeless PFC circuit, a power supply system, a computer, and its operating method. The circuit eliminates the two diodes connected to the reference potential in a traditional rectifier bridge, using a first switching transistor, a second switching transistor, their parallel diodes, and an inductor to form a current loop, reducing conduction and switching losses. The source of the switching transistor shares a common ground with the negative terminal of the DC output, eliminating the need for isolation between drive and voltage sampling, thus simplifying the design. Furthermore, the semi-bridgeless PFC circuit can integrate an intelligent enable control module. This module continuously monitors the power stage status and controls the release of the original drive signal based on safety logic, achieving proactive safety protection. This solution improves efficiency and reliability while using common silicon-based devices, and also reduces the complexity and cost of existing power-saving circuits.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more particularly to semi-bridgeless PFC circuits, power supply systems, computers, and methods for operating semi-bridgeless PFC circuits. Background Technology

[0002] Computers, also known as PCs, have become an indispensable core infrastructure of modern society, evolving from personal computers and workstations to large-scale data center servers, thanks to the rapid development of information technology. In recent years, the explosive growth and widespread application of artificial intelligence technology, especially the massive computing power required for deep learning training and inference, has led to a continuous increase in the power consumption of high-performance computing equipment. The power density of a single AI server rack has increased from several kilowatts to tens of kilowatts. Within a limited space, providing extremely high power while achieving extremely high conversion efficiency, excellent reliability, and superior power quality is essential.

[0003] In order to convert the alternating current (AC) from the power grid into the stable direct current (DC) required by the internal chips of a computer, modern computer power supplies typically employ a two-stage architecture: the front stage performs power factor correction (PFC), and the back stage performs DC-DC conversion.

[0004] Among them, the PFC stage is crucial. It not only improves the power utilization rate on the input side and reduces harmonic pollution to the power grid, but its own conversion efficiency is also the key to determining the overall power supply efficiency.

[0005] Currently, the most widely used PFC solution in computer and server power supplies is the traditional bridged Boost PFC topology based on analog control circuits.

[0006] This scheme uses a rectifier bridge composed of four diodes to perform full-wave rectification of AC power, followed by a boost circuit composed of power switching transistors (usually MOSFETs), inductors, and diodes. The control core is a dedicated analog PFC control chip, which generates pulse width modulation (PWM) signals to drive the switching transistors by sampling the output voltage and inductor current, thereby achieving power factor correction.

[0007] However, this mature and widely used analog circuit solution is gradually becoming outdated in the face of the booming development of artificial intelligence technology. First, the inherent forward voltage drop of the four diodes in the rectifier bridge (approximately 0.7-1V each) generates continuous conduction losses. Simultaneously, during switching, the reverse recovery characteristics of the diodes introduce significant switching losses and electromagnetic interference (EMI). These losses cause the peak efficiency of traditional bridged PFC circuits to typically hover around 96%-97%, becoming a major obstacle to improving overall system efficiency.

[0008] Secondly, in traditional solutions, the switching transistor is directly driven by the control chip. Once the power switching transistor experiences a short circuit due to overvoltage, overcurrent, or its own defects, the drive signal issued by the control chip will be executed without discrimination, which can easily lead to the expansion of the fault and cause consequences such as capacitor explosion and PCB burnout. Existing technologies usually rely on stacking a large number of passive protection components such as fuses and thermal relays for post-event protection.

[0009] To address these issues, the industry has introduced advanced topologies such as totem pole bridgeless PFC. However, these typically require expensive wide-bandgap semiconductor devices such as gallium nitride (GaN) and complex high-speed digital isolation drives and precise timing control, which significantly increases system cost and design complexity, making it difficult to popularize in mainstream, especially cost-sensitive, high-volume computer products. Summary of the Invention

[0010] To address the technical problems of current loss and the excessive cost of totem pole bridgeless PFC, this invention proposes a semi-bridgeless PFC circuit, a power supply system, a computer, and a method for operating the semi-bridgeless PFC circuit.

[0011] A semi-bridgeless PFC circuit, characterized in that the circuit comprises: The first inductor, one end of which is used to connect to the live wire of the AC power supply; The second inductor has one end connected to the neutral terminal of the AC power supply; The first switching unit includes a first switching transistor, the source of which is connected to a reference potential node and the drain of which is connected to the other end of the first inductor. The second switching unit includes a second switching transistor, the source of which is connected to the reference potential node and the drain of which is connected to the other end of the second inductor. The rectifier unit includes a first diode, a second diode, a third diode, and a fourth diode; In this configuration, the anode of the first diode is connected to the drain of the first switching transistor, and the cathode is connected to the positive terminal of the DC output. The anode of the second diode is connected to the drain of the second switching transistor, and the cathode is connected to the positive terminal of the DC output. The cathode of the third diode is connected to the drain of the first switching transistor, and the anode is connected to the reference potential node; The cathode of the fourth diode is connected to the drain of the second switching transistor, and the anode is connected to the reference potential node; An energy storage capacitor is connected between the positive terminal of the DC output and the reference potential node; and PFC control module; The PFC control module is configured to: receive voltage feedback signals and current detection signals, and generate synchronous pulse width modulation control signals based on the signals to drive the first switch and the second switch.

[0012] In some embodiments of the present invention, the circuit further includes an intelligent enable control module, which is electrically connected to the PFC control module and the first switching unit and the second switching unit; the intelligent enable control module is configured to: monitor the status of the first switching unit, the second switching unit, the rectifier unit and the energy storage capacitor, and generate an enable signal based on the monitoring results; The driving terminals of the first and second switching units are configured to turn on only in response to the pulse width modulation control signal generated by the PFC control module when the enable signal is valid.

[0013] In some embodiments of the present invention, the intelligent enable control module includes: A distributed state monitoring network is configured to collect the current and / or voltage status of the switching transistors in the first and second switching units. The logic arbitration and enable generation unit is configured to receive monitoring results from the distributed state monitoring network and generate a valid enable signal when all monitoring results are within a preset safety range. The safety gating drive circuit is configured to perform a logical AND operation on the original drive signal and the enable signal of the PFC control module to generate a valid drive signal applied to the gate of the switching transistor.

[0014] In some embodiments of the present invention, the first switching unit and / or the second switching unit includes a plurality of switching transistors connected in parallel.

[0015] In some embodiments of the present invention, the control algorithm used by the PFC control module includes at least one of average current mode control, critical conduction mode control, and peak current mode control.

[0016] A power supply system, comprising: The filter module is used to connect to the AC power supply to filter out electromagnetic interference; The semi-bridgeless PFC circuit as described in any one of claims 1-5 has its input terminal connected to the output terminal of the filter module; At least one DC-DC converter module, the input of which is connected to the output of the semi-bridgeless PFC circuit; and The system control module is electrically connected to the semi-bridgeless PFC circuit and the DC-DC converter module.

[0017] A computer, comprising: Chassis; The motherboard, processor, memory, and storage devices housed within the chassis; and The power system as described in claim 6 is used to supply power to the motherboard, processor, memory, and storage device.

[0018] A method for operating a semi-bridgeless PFC circuit, the method comprising: Receive voltage feedback signals and current detection signals; Based on the voltage feedback signal and current detection signal, a synchronous PWM drive signal for controlling the first switch and the second switch is generated; The synchronous PWM drive signal is applied to the gates of the first and second switching transistors, so that the first and second switching transistors are controlled to perform synchronous chopping during the positive and negative half-cycles of the AC current, respectively.

[0019] A method for operating a semi-bridgeless PFC circuit, the method comprising: It receives voltage feedback signals and current detection signals, and generates the original drive signals; Monitor the status of the power stage circuit and generate an enable signal based on the monitoring results; Perform a logical AND operation on the original drive signal and the enable signal to generate a valid drive signal; The active drive signal is applied to the gate of the switch only when the enable signal is active.

[0020] A method for implementing power factor correction in a computer, the method comprising: Used for applications such as running a semi-bridgeless PFC circuit to convert AC input to DC. The DC power is converted into the operating voltage required by the computer's internal components via a DC-DC converter module.

[0021] The present invention has the following advantages: This invention eliminates the two diodes connected to the reference potential in traditional bridged PFC circuits through a specific semi-bridgeless topology, thereby eliminating the on-state voltage drop loss and reverse recovery loss of these two diodes, effectively reducing losses in the current path and improving circuit efficiency. Simultaneously, this topology ensures that the sources of all switching transistors share a common ground with the negative terminal of the DC output. This common ground connection eliminates the need for complex isolation devices in the drive circuit and voltage sampling circuit, simplifying the design and reducing costs. By employing multiple transistors in parallel and common silicon-based semiconductor devices, this invention achieves the aforementioned efficiency improvement and structural simplification while avoiding the need for expensive gallium nitride devices and precise isolation drives required in totem-pole PFC solutions, thus achieving an optimized balance between efficiency and cost. Furthermore, to ensure the reliable operation of this simplified and efficient topology, an enable control mechanism based on real-time status monitoring and logic arbitration is introduced. By continuously self-checking and blocking the transmission of drive signals in case of anomalies, the consequences of potential faults are controlled to a safe shutdown state, preventing damage and thus ensuring system safety while improving efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a semi-bridgeless PFC circuit; Figure 2 This is a schematic block diagram of the logic flow of the second embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0024] Example 1: To better understand the inventive points of this invention, a description of the prior art semi-bridgeless PFC circuit is provided before introducing this invention. In this prior art, two controllable switching devices (such as MOSFETs or IGBTs, abbreviated as QA1 and QA2 for ease of understanding) are used to form a bidirectional switching unit, which, together with an inductor, a current transformer, multiple diodes (four diodes are used here for ease of understanding, denoted as D1, D2, D3, and D4) and an energy storage capacitor, achieves the power factor correction function.

[0025] The basic operating logic of the circuit is as follows: When the alternating current is in the positive half-cycle, that is, when the voltage at terminal L is higher than that at terminal N: When the controllable switching devices QA1 and QA2 are turned on, the current flows out from the L terminal, through the first inductor, the controllable switching devices, and the current transformer, and then returns to the N terminal.

[0026] When the controllable switching devices QA1 and QA2 are turned off, the current flows out from the L terminal, through the first inductor, diode D1, energy storage capacitor, and diode D4, and then returns to the N terminal.

[0027] When the alternating current is in the negative half-cycle, that is, when the voltage at the N terminal is higher than that at the L terminal: When the controllable switching devices QA1 and QA2 are turned on, the current flows out from the N terminal, through the current transformer, the controllable switching devices, and the first inductor, and then returns to the L terminal.

[0028] When the controllable switching devices QA1 and QA2 are turned off, the current flows out from the N terminal, through diode D2, energy storage capacitor, diode D3, and the first inductor, and then returns to the L terminal.

[0029] During the above operation, since the drive reference points (source / emitter) of the controllable switching devices QA1 and QA2 are not connected to a fixed reference potential (such as the negative terminal of DC output), complex isolation drive circuits are required.

[0030] Meanwhile, the output voltage cannot be directly fed back for sampling, and isolation sampling is required using methods such as optocouplers, which increases the circuit complexity.

[0031] Furthermore, since the negative terminal of the main capacitor and the switching device are not grounded together, electromagnetic compatibility issues are easily generated. The above circuit structure and its operation are common knowledge in the field of semi-bridgeless PFC technology, and are only introduced here as examples.

[0032] Based on a full understanding of existing technologies, refer to Figure 1 The figure schematically illustrates a semi-bridgeless PFC circuit diagram according to a first embodiment of the present invention.

[0033] like Figure 1 As shown, the semi-bridgeless PFC circuit according to the first embodiment of the present invention is applied between an AC power supply (including the live wire L and the neutral wire N) and a load to achieve power factor correction and output DC voltage.

[0034] The circuit mainly includes: Input filtering module; First inductor L2, second inductor L3; First switching unit, second switching unit; Rectifier unit; Energy storage capacitor C2; Current detection module and PFC control module.

[0035] Specifically, the input filtering module (details not shown in the figure) is connected between the live wire L and the neutral wire N of the AC power supply to filter out high-frequency interference from the power grid side.

[0036] One end of the first inductor L2 is connected to the live wire L. One end of the second inductor L3 is connected to the neutral wire N.

[0037] The first switching unit includes a first switching transistor QA3.

[0038] The source of the first switching transistor QA3 is grounded, and its drain is connected to the other end of the first inductor L2. The second switching unit includes a second switching transistor QA4. The source of the second switching transistor QA4 is grounded, and its drain is connected to the other end of the second inductor L3.

[0039] In this embodiment, the first switch QA3 and the second switch QA4 are preferably N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), whose gates receive drive signals to control the on or off states.

[0040] Understandably, each switching unit may include multiple switching transistors connected in parallel, as shown in the figure, such as QA3 and QB5, QA4 and QB6, in order to reduce the current stress and conduction loss of a single transistor.

[0041] The rectifier unit includes a first diode D5, a second diode D6, a third diode D7, and a fourth diode D8.

[0042] In this configuration, the anode of the first diode D5 is connected to the drain of the first switching transistor QA3, which is the other end of the first inductor L2, and the cathode is connected to the positive terminal Vbus+ of the DC output.

[0043] The anode of the second diode D6 is connected to the drain of the second switching transistor QA4, which is the other end of the second inductor L3, and the cathode is connected to the positive terminal Vbus+ of the DC output.

[0044] The cathode of the third diode D7 is connected to the drain of the first switching transistor QA3, and the anode is connected to the negative DC output terminal Vbus- through the current detection module.

[0045] The cathode of the fourth diode D8 is connected to the drain of the second switching transistor QA4, and the anode is connected to the negative DC output terminal Vbus- through the current detection module.

[0046] In this embodiment, the negative terminal Vbus of the DC output serves as the reference potential node for the circuit.

[0047] The energy storage capacitor C2 is connected between the positive terminal Vbus+ and the negative terminal Vbus- of the DC output, and is used for filtering and energy storage.

[0048] The circuit also includes a voltage feedback network connected between the DC output positive terminal Vbus+ and the reference potential node Vbus-, which is used to sample the output voltage and generate a proportionally reduced voltage feedback signal.

[0049] For example, the voltage feedback network includes a first voltage divider resistor and a second voltage divider resistor connected in series.

[0050] The current detection module includes a current detection resistor RS connected in series in the DC output negative terminal Vbus- path, used to detect the current flowing through this branch and generate a corresponding current detection signal.

[0051] The PFC control module, namely the PFC control IC shown in the figure, is electrically connected to the current sensing resistor RS, the DC output positive terminal Vbus+ connected via the voltage feedback network, the gate of the first switching transistor QA3, and the gate of the second switching transistor QA4.

[0052] The PFC control module is configured to: receive a current detection signal from the current sensing resistor RS and the voltage feedback signal; generate a PWM control signal based on the current detection signal and the voltage feedback signal; and synchronously output the PWM control signal to the gates of the first switch QA3 and the second switch QA4 to control them to be turned on or off synchronously, thereby achieving power factor correction and regulated output.

[0053] The working process of this embodiment is as follows: During the positive half-cycle of the AC power supply, i.e., when the current flows from terminal L to terminal N: When the first switch QA3 is turned on, the current path is: L terminal → first inductor L2 → first switch QA3 (when QA3 is turned on) → current sensing resistor RS → third diode D7 → N terminal.

[0054] When the first switch QA3 is turned off, the current path is: L terminal → first inductor L2 → first diode D5 → energy storage capacitor C2 → current sensing resistor RS → third diode D7 → N terminal.

[0055] During the negative half-cycle of the AC power supply, i.e., when the current flows from the N terminal to the L terminal: When the second switch QA4 is turned on, the current path is: N terminal → second inductor L3 → second switch QA4 (when QA4 is turned on) → current sensing resistor RS → fourth diode D8 → L terminal.

[0056] When the second switch QA4 is turned off, the current path is: N terminal → second inductor L3 → second diode D6 → energy storage capacitor C2 → current sensing resistor RS → fourth diode D8 → L terminal.

[0057] Throughout the entire power frequency cycle, the PFC control module provides the gates of the first switch QA3 and the second switch QA4 with fully synchronized PWM drive signals whose duty cycles vary with the AC phase and load, enabling them to perform high-frequency chopping within the corresponding half-cycle.

[0058] As shown in Table 1, taking 1600W as an example, compared with the traditional full-bridge PFC circuit, in this embodiment, the two diodes in the traditional bridge rectifier circuit are eliminated, namely the two diodes connected to the reference potential in the traditional bridge rectifier. The current loop is directly formed by the first switch QA3, the second switch QA4 and their body diodes or the third and fourth diodes D7 and D8 connected in parallel, and the first inductor L2 and the second inductor L3. This effectively reduces the conduction voltage drop loss and reverse recovery loss of the two diodes, thereby improving the overall efficiency.

[0059] Table 1 Furthermore, it is worth noting that, since this embodiment adopts common ground driving and sampling, the sources of the first switch QA3 and the second switch QA4 are both directly connected to the reference potential node Vbus-, and the negative terminal of the energy storage capacitor C2 is also connected to the same reference potential node.

[0060] The so-called common-ground drive is a specific drive connection architecture used in the semi-bridgeless PFC circuit of this application. It refers to the fact that the sources of the first switch QA3 and the second switch QA4 are both directly connected to the reference potential node Vbus- of the circuit. At the same time, the drive signal output ground terminal of the PFC control module and the reference potential terminal of the gate drive circuit are also connected to the same reference potential node Vbus-.

[0061] Based on the common-ground driven electrical connection, the gate drive signal output from the PFC control module can be applied to the gate of the switching transistor directly or through a non-isolated buffer / amplifier circuit without passing through any electrical isolation components.

[0062] The essence of the common-ground drive architecture is to eliminate potential difference fluctuations in the drive circuit by electrically connecting and equipotentially equipotentially connecting the current return terminal (source) of the power switch to the signal reference terminal (reference potential node) of the entire control system.

[0063] This design eliminates the need for isolation in the drive circuit, allowing it to be directly driven by the PFC control module, thus simplifying the drive circuit design and improving reliability.

[0064] Output voltage feedback sampling does not require isolation and can be directly sampled from the positive and negative terminals of the common ground, simplifying the control loop.

[0065] It also facilitates electromagnetic compatibility (EMC) design, avoiding high-frequency noise interference caused by the floating of the switching transistor.

[0066] It is understood that, through the above optimizations, this embodiment achieves high efficiency between traditional PFC and complex totem pole PFC while using ordinary silicon-based MOSFETs and diodes, providing a cost-effective and low-cost PFC solution.

[0067] Example 2: To achieve better technical results, this embodiment proposes a second embodiment based on the first embodiment.

[0068] like Figure 2 As shown in the figure, this diagram schematically illustrates a semi-bridgeless PFC circuit with intelligent state monitoring and enable control functions according to a second embodiment of the present invention.

[0069] This embodiment is based on the hardware topology of the semi-bridgeless PFC circuit described in the first embodiment. In order to ensure that the architecture can operate safely and reliably under any operating conditions, an intelligent state monitoring and enable control system is introduced, which is built into the drive path, has the ability to prevent and make decisions in advance, and is deeply coupled with the power topology.

[0070] Specifically, the semi-bridgeless PFC circuit of this embodiment includes the input filtering module, the first inductor L2, the second inductor L3, the first switching unit, the second switching unit, the rectifier unit, the energy storage capacitor C2, the current sensing resistor RS, and the PFC control module as in the first embodiment.

[0071] The difference between this embodiment and the first embodiment is that an intelligent enable control module is added between the PFC control module and the driving terminals of the first switch unit and the second switch unit.

[0072] The intelligent enable control module is electrically connected to the PFC control module and the power stage circuit, forming a decoupled, state-self-checking-based permission-driven control architecture.

[0073] The intelligent enabling control module mainly includes: Distributed condition monitoring network: The distributed condition monitoring network is configured to perform real-time health status diagnosis of key semiconductor devices in the power stage.

[0074] Switching transistor health monitoring unit: corresponding to each switching transistor in the first switching unit and the second switching unit, such as QA3, QB5, QA4, and QB6 in the first embodiment.

[0075] Each monitoring unit includes, for example, a small-value sampling resistor connected in series with the source of the switching transistor and a differential amplifier connected across the sampling resistor.

[0076] By monitoring the current flowing through each switch, it is possible to determine if there are potential faults such as overcurrent, short circuit, or open circuit. Alternatively, or additionally, it is possible to determine whether the switch is properly turned on or off by monitoring the voltage Vds between the drain and source of the switch at a specific moment.

[0077] Critical Node Voltage Monitoring Unit: This unit is configured to monitor the DC bus voltage Vbus, the gate drive voltage Vgs of the switching transistor, and the power supply voltage of the PFC control module. These voltage values ​​are compared with internally set safety thresholds, i.e., upper and / or lower limits, to determine whether the power supply environment and drive conditions are normal.

[0078] Logic arbitration and enable generation unit: This unit receives the raw drive signal (PWM_Raw) from the PFC control module and all monitoring results (Status_1…Status_N) from the distributed status monitoring network.

[0079] The original drive signal (PWM_Raw) contains the desired switching timing calculated by the PFC control module based on the voltage loop and current loop.

[0080] The logic arbitration and enable generation unit has a set of preset security logic.

[0081] In this embodiment, for example, the logic is configured such that the unit generates a global enable signal (EN_Global) only when all switch health monitoring units report a normal state and all critical node voltages are within the safe threshold range.

[0082] More specifically, the logic arbitration and enable generation unit may also include a delay module for introducing a brief self-test delay when the system is powered on or recovering from a fault, to ensure that all states are stable before enabling.

[0083] Safety gate drive circuit: This circuit is connected to the gate of each switch in the first switching unit and the second switching unit respectively. The safety gate drive circuit has at least two inputs: one is the original drive signal (PWM_Raw) or its buffered and shaped signal from the PFC control module, and the other is the global enable signal (EN_Global) from the logic arbitration and enable generation unit.

[0084] The safety gate drive circuit is configured to function as an AND gate.

[0085] That is, the final effective drive signal (PWM_Final) applied to the gate of each switch is the result of a logical AND operation between the original drive signal (PWM_Raw) and the global enable signal (EN_Global).

[0086] For example, the safety gating drive circuit can be implemented by an AND gate chip, or it can be composed of discrete logic devices and a drive amplifier.

[0087] The workflow and safety control logic of this embodiment are as follows: During system startup or operation, the PFC control module continuously generates raw drive signals (PWM_Raw) according to its internal algorithm.

[0088] At the same time, the distributed condition monitoring network starts working, continuously collecting real-time condition data of the power stage.

[0089] The logic arbitration and enable generation unit performs parallel analysis and judgment on all monitoring data. If any monitoring result exceeds the safety range, such as abnormal current of a MOSFET, overvoltage of the bus voltage, or insufficient drive voltage, the logic arbitration and enable generation unit will pull the global enable signal (EN_Global) low.

[0090] Once the global enable signal (EN_Global) is low, regardless of the waveform of the original drive signal (PWM_Raw), after the logic AND operation of the safety gate drive circuit, the effective drive signal PWM_Final output to the gate of all switching transistors will always remain at the off level, thereby forcing all switching transistors into the off state and the system stops working.

[0091] Conversely, only when all monitoring points have checked that the global enable signal (EN_Global) is set to a high level can the original drive signal (PWM_Raw) pass through the safety gate drive circuit without obstruction and be converted into a valid drive signal (PWM_Final) to control the switching transistor to perform PFC chopping normally.

[0092] This embodiment, through the above-described technical solution, advances the safety control node from the traditional post-fault shutdown to pre-action authorization. By constructing an enable gating system based on real-time hardware status feedback, the risk of cascading failure or system crash caused by the system still executing drive commands when power devices already have hidden dangers or external conditions are abnormal is reduced. The consequences of the failure are controlled within the scope of safe shutdown, thereby improving the inherent safety of the system.

[0093] Furthermore, the high-efficiency simplified topology disclosed in the first embodiment, due to the elimination of some diodes, places higher demands on the reliability of the switching transistors. The intelligent state monitoring and enable control provided in this embodiment are designed specifically for this circuit, enabling high efficiency and high reliability to be achieved simultaneously in this application.

[0094] By clearly defining the separation of responsibilities between the PFC control module and the intelligent enable control module, the PFC control module can focus on implementing the optimal power conversion algorithm and pursuing maximum efficiency, while the intelligent enable control module is dedicated to managing the hardware safety boundary. This allows the intelligent enable control module to still function independently even if the PFC control logic malfunctions, thus improving the overall fault tolerance.

[0095] Furthermore, the optimal power conversion algorithm of the PFC control module can employ any suitable control algorithm known in the art, such as average current mode control, critical conduction mode control, or peak current mode control, to generate a drive signal based on voltage feedback signal and current detection signal, thereby achieving optimal power conversion efficiency and power factor.

[0096] To better understand this technical solution, this embodiment exemplifies three optimal power conversion algorithms. It should be understood that, as prior art, the exemplified algorithms should not be construed as limiting this application.

[0097] Algorithm 1: Average Current Mode Control Working principle: Control is achieved through two closed loops. The outer loop is a voltage loop, which samples the output voltage and compares it with a reference value. Its output serves as the current command for the current loop. The inner loop samples the inductor current at high frequency, ensuring that its average value tracks the sinusoidal waveform defined by the command in real time. This is currently the most commonly used and most stable Continuous On-Mode (CCM) PFC control method.

[0098] Typical examples of such chips include TI's UC3854 series and Infineon's ICE2PCS01.

[0099] Algorithm 2: Critical On-Mode / Transitional Mode Control Operating principle: The switching frequency is variable. The controller monitors the inductor current and immediately turns on the switching transistor when it drops to zero, causing the inductor current to rise linearly from zero to its peak value. The peak value is determined by the command signal output by the output voltage error amplifier. This mode achieves zero-current turn-on of the switching transistor, eliminating the reverse recovery problem of the diode, but it results in relatively large current ripple.

[0100] Typical chip examples: ON Semiconductor's NCP1605, ST's L6562 series.

[0101] Algorithm 3: Peak Current Mode Control Operating principle: During each switching cycle, when the switching transistor is turned on, the inductor current rises linearly. The controller compares the sampled peak inductor current with a sinusoidal reference signal modulated by the output voltage error signal. Once the current reaches the reference, the switching transistor is turned off.

[0102] Typical chip example: can be used to implement various fixed-frequency current-type controllers.

[0103] Furthermore, more specifically, distributed condition monitoring networks can be designed to distinguish between fault types and locations.

[0104] By identifying which switch's monitoring unit is reporting an error, preliminary fault location can be achieved.

[0105] Example 3: A power supply system including the aforementioned semi-bridgeless PFC circuit; This embodiment provides a power supply system that integrates the semi-bridgeless PFC circuit described in any of the foregoing embodiments to form a complete, efficient and reliable AC-DC power supply solution.

[0106] The power supply system of the third embodiment of the present invention is used to convert AC input electrical energy into one or more stable DC output electrical energy. include: AC input port; Electromagnetic interference (EMI) filtering module; Semi-bridgeless PFC circuit module; At least one DC-DC converter module; System control and monitoring module; And a DC output port.

[0107] The AC input port, exemplarily, includes a live wire (L) terminal, a neutral wire (N) terminal, and a protective earth (PE) terminal for connecting to the mains power grid or an AC generator.

[0108] The EMI filter module is connected after the AC input port to suppress high-frequency interference from the power grid from entering subsequent circuits, while preventing high-frequency switching noise generated inside the power system from being fed into the power grid, ensuring that the system meets relevant electromagnetic compatibility standards.

[0109] The input terminal of the semi-bridgeless PFC circuit module is connected to the output terminal of the EMI filter module.

[0110] The semi-bridgeless PFC circuit module is the semi-bridgeless PFC circuit described in the first or second embodiment of the present invention. As the core power factor correction stage of the power supply system, it is responsible for converting the filtered AC power into high-voltage DC power with a high power factor and outputting it to the intermediate DC bus (Vbus).

[0111] The input of at least one DC-DC converter module is connected to the intermediate DC bus (Vbus) to convert the high-voltage DC output from the PFC stage into one or more isolated or non-isolated stable DC currents of the voltage level required by the load.

[0112] For example, the DC-DC conversion module may include one or more combinations of topologies such as LLC resonant converter, flyback converter, forward converter or buck converter.

[0113] The system control and monitoring module is electrically connected to the semi-bridgeless PFC circuit module and the DC-DC converter module.

[0114] The system control and monitoring module may include a microcontroller unit (MCU) or a digital signal processor (DSP), and is configured to: It receives feedback signals from various parts of the power system, such as PFC stage output bus voltage, DC-DC stage output voltage / current, system temperature, etc. Send control commands or parameter configuration information to the PFC control module and intelligent enable control module (if present) in the semi-bridgeless PFC circuit module; Send a control signal to the DC-DC converter module to adjust its output voltage; Execute system protection logic such as overvoltage, overcurrent, and overtemperature protection, and perform fault diagnosis; Optionally, it can communicate with a host computer or system manager through a communication interface (such as I2C, PMBus, CAN) to report status and receive instructions.

[0115] The DC output port is connected to the output of the DC-DC converter module and is used to provide stable DC power to the external load.

[0116] The beneficial effects of this embodiment are as follows: When the power system is powered on, the AC power is purified by the EMI filter module and then input to the semi-bridgeless PFC circuit module. The semi-bridgeless PFC circuit module performs power factor correction and converts the power to the intermediate DC bus.

[0117] The system control and monitoring module coordinates the operation of the entire system, ensuring that the PFC stage operates stably near its optimal efficiency point, and controls the subsequent DC-DC converter module to generate a stable output voltage.

[0118] Thanks to the inherent high efficiency and high reliability of the semi-bridgeless PFC circuit module, front-end energy loss is reduced. Furthermore, the semi-bridgeless PFC circuit module has a simple topology, a small number of components, and does not require isolation between driving and sampling, thus reducing PCB area and increasing power density.

[0119] In particular, when employing the intelligent safety control of the second embodiment, the co-location design and optional built-in intelligent safety control enhance the robustness of the front-end power stage, thereby improving the mean time between failures (MTBF) of the entire power system.

[0120] Because the semi-bridgeless PFC circuit module has a simple interface with the system main controller (MCU / DSP), it is easy to realize digital precise control and status monitoring, making the power supply system more intelligent and easier to integrate into complex electrical equipment, such as high-end medical devices and personal computer terminals.

[0121] Example 4: A computer incorporating the power supply system.

[0122] This embodiment provides a computer that incorporates the power system described in the third embodiment, thereby achieving a computing device with excellent overall energy efficiency.

[0123] The computer in the fourth embodiment of the present invention may be, but is not limited to, a server, a personal computer, a workstation, or a high-performance computing device.

[0124] Includes: chassis; The motherboard installed inside the chassis; At least one processor; Memory; Storage devices; And the power supply system.

[0125] The motherboard is the core circuit board of the computer, on which necessary circuit traces, chipsets, and expansion interfaces are arranged.

[0126] The at least one processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or an accelerator) is installed on the motherboard as the main computing unit of the computer.

[0127] The memory (e.g., dynamic random access memory DRAM) is installed on the motherboard and electrically connected to the processor for temporary storage of data and instructions.

[0128] The storage device (e.g., solid-state drive SSD, hard disk drive HDD) is connected to the motherboard for long-term data storage.

[0129] The power system is fixedly installed inside the chassis. The AC input terminal is connected to an external AC power source (such as AC mains) via a power cord, and the DC output terminal is electrically connected to the motherboard, processor, memory, and storage devices via cables, providing the necessary stable DC operating voltage for all components of the computer.

[0130] The power supply system is the power supply system according to the third embodiment of the present invention.

[0131] The beneficial effects of this embodiment are as follows: When the computer starts up, external AC power is first input to the built-in power system. The semi-bridgeless PFC circuit module in the power system converts the AC power into high-voltage DC power, and then generates multiple low-voltage DC power (such as +12V, +5V, +3.3V, etc.) required by the motherboard, processor, memory, hard drive, etc. through its DC-DC conversion module, providing power to the entire computer.

[0132] Because the power system uses the semi-bridgeless PFC circuit of the present invention as the front-end core, it reduces the overall loss when the computer draws power from the grid, which not only reduces operating electricity costs and meets the 80 PLUS advanced energy efficiency certification requirements, but also reduces the total cost of ownership and cooling burden in large-scale deployment scenarios such as data centers.

[0133] In particular, the second embodiment can effectively prevent unexpected downtime or hardware damage caused by power supply front-end failure, and is especially suitable for AI servers or workstations that need to run 24 / 7.

[0134] Because the high-efficiency current provided by the semi-bridgeless PFC circuit of this invention means a reduction in the heat generated by the power supply system itself, the overall temperature rise inside the relatively enclosed computer chassis is reduced, thereby simplifying the design of the heat dissipation system, such as eliminating water cooling and using lower-speed fans. This also saves costs and may allow for a more compact chassis design, increasing power density.

[0135] Example 5: A method for operating a semi-bridgeless PFC circuit; This embodiment provides a working method corresponding to the semi-bridgeless PFC circuit described in the first and second embodiments above. The method specifically includes a control flow for implementing basic PFC functions, and a decision flow for optionally integrating intelligent safety control.

[0136] The method for operating a semi-bridgeless PFC circuit includes the following steps: System initialization and power-on procedures; When the power system is powered on, the relevant control circuits begin to work, and the PFC control module and the intelligent enable control module (if present) complete self-testing and initialization.

[0137] Steps for receiving voltage feedback signals and current detection signals; The PFC control module receives a voltage feedback signal (Vfb) from the DC output terminal of the PFC circuit and a current detection signal (Isense) from the current sensing resistor. The voltage feedback signal reflects the actual value of the output voltage, and the current detection signal reflects the total current flowing through the power circuit.

[0138] The steps for executing the PFC control algorithm and generating raw drive instructions are as follows: Based on the error between the voltage feedback signal (Vfb) and the internal reference voltage (Vref), and the current detection signal (Isense), the PFC control module runs a power factor correction control algorithm to calculate the pulse width modulation (PWM) duty cycle for controlling the switching transistor, and generates the original drive instruction (PWM_Raw) accordingly. The original drive instruction (PWM_Raw) contains the timing information of the expected switching transistor operation.

[0139] Optionally, perform power stage status self-test and safety arbitration steps; This step is performed on systems that include a smart enable control module.

[0140] The distributed state monitoring network of the intelligent enable control module collects key states of the power stage in real time, including but not limited to: current or voltage drop of each parallel switch, bus voltage, and drive voltage. The logic arbitration unit analyzes all monitoring data to determine whether they are all within the preset safety threshold range.

[0141] Based on the power stage status self-check and safety arbitration steps, if all monitored states are normal, the logic arbitration unit generates a valid global enable signal (EN_Global = valid) and proceeds to the step of synthesizing the final drive signal and driving the switching transistor.

[0142] Based on the power level status self-test and safety arbitration steps, if any monitored status is abnormal, such as a short circuit, open circuit or voltage exceeding the limit is detected, the logic arbitration unit generates an invalid global enable signal (EN_Global = invalid). At this time, the process will jump to the safety handling and fault response steps, forcing the system to enter the safety shutdown state.

[0143] The step of synthesizing the final drive signal and driving the switching transistor; For the basic implementation (without power stage state self-test and safety arbitration steps): the raw drive instruction (PWM_Raw) generated in the step of executing the PFC control algorithm and generating the raw drive instruction is directly used as the final drive signal (PWM_Final) and sent to the gate drive circuit of the switching transistor.

[0144] For an embodiment that performs power level state self-test and safety arbitration steps: the safety gated drive circuit receives the raw drive command (PWM_Raw) and the global enable signal (EN_Global).

[0145] The PWM_Raw signal can only pass through and be synthesized into the final drive signal (PWM_Final) when the EN_Global signal is valid. If EN_Global is invalid, PWM_Final is forced to remain at the off level.

[0146] The final drive signal (PWM_Final) is applied to the gates of the first switch QA3 and the second switch QA4.

[0147] Steps for implementing PFC function by synchronously chopping the switching transistors; Under the control of the final drive signal (PWM_Final), the first switch QA3 and the second switch QA4 receive fully synchronized PWM drive throughout the entire cycle of the AC power.

[0148] During the positive half-cycle of AC, QA3 is mainly controlled for high-frequency chopping; during the negative half-cycle of AC, QA4 is mainly controlled for high-frequency chopping. Through the energy storage and release of the inductor, the AC input is shaped into a sinusoidal current in phase with the voltage, while the output voltage is regulated.

[0149] Safety procedures and fault response steps; This step is for handling situations triggered by continuous monitoring or detection of abnormal status.

[0150] If a fault is detected during operation through continuous monitoring, the system is immediately shut down, EN_Global is invalidated, thereby blocking the drive in the process of synthesizing the final drive signal and driving the switching transistor, and the system is safely shut down.

[0151] The system can record fault status and report it via indicator lights or communication interface.

[0152] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semi-bridgeless PFC circuit, characterized in that, The circuit includes: The first inductor (L2) has one end connected to the live wire (L) of the AC power supply. The second inductor (L3) has one end connected to the neutral terminal (N) of the AC power supply. The first switching unit includes a first switching transistor (QA3), the source of which is connected to a reference potential node and the drain of which is connected to the other end of the first inductor (L2). The second switching unit includes a second switching transistor (QA4), the source of which is connected to the reference potential node and the drain of which is connected to the other end of the second inductor (L3). The rectifier unit includes a first diode (D5), a second diode (D6), a third diode (D7), and a fourth diode (D8). In this configuration, the anode of the first diode (D5) is connected to the drain of the first switching transistor (QA3), and the cathode is connected to the positive terminal of the DC output. The anode of the second diode (D6) is connected to the drain of the second switching transistor (QA4), and the cathode is connected to the positive terminal of the DC output. The cathode of the third diode (D7) is connected to the drain of the first switching transistor (QA3), and the anode is connected to the reference potential node; The cathode of the fourth diode (D8) is connected to the drain of the second switch (QA4), and the anode is connected to the reference potential node; Energy storage capacitor (C2) is connected between the positive terminal of the DC output and the reference potential node; and PFC control module; The PFC control module is configured to: receive voltage feedback signals and current detection signals, and generate synchronous pulse width modulation control signals based on the signals to drive the first switch (QA3) and the second switch (QA4).

2. The semi-bridgeless PFC circuit according to claim 1, characterized in that, The circuit also includes an intelligent enable control module, which is electrically connected to the PFC control module and the first switching unit and the second switching unit. The intelligent enable control module is configured to monitor the status of the first switching unit, the second switching unit, the rectifier unit and the energy storage capacitor (C2), and generate an enable signal based on the monitoring results. The driving terminals of the first and second switching units are configured to turn on only in response to the pulse width modulation control signal generated by the PFC control module when the enable signal is valid.

3. The semi-bridgeless PFC circuit according to claim 2, characterized in that, The intelligent enabling control module includes: A distributed state monitoring network is configured to collect the current and / or voltage status of the switching transistors in the first and second switching units. The logic arbitration and enable generation unit is configured to receive monitoring results from the distributed state monitoring network and generate a valid enable signal when all monitoring results are within a preset safety range. The safety gating drive circuit is configured to perform a logical AND operation on the original drive signal and the enable signal of the PFC control module to generate a valid drive signal applied to the gate of the switching transistor.

4. The semi-bridgeless PFC circuit according to any one of claims 1-3, characterized in that, The first switching unit and / or the second switching unit includes a plurality of switching transistors connected in parallel.

5. The semi-bridgeless PFC circuit according to any one of claims 1 to 3, characterized in that, The control algorithm used by the PFC control module includes at least one of average current mode control, critical conduction mode control, and peak current mode control.

6. A power supply system, characterized in that, include: The filter module is used to connect to the AC power supply to filter out electromagnetic interference; The semi-bridgeless PFC circuit as described in any one of claims 1-5 has its input terminal connected to the output terminal of the filter module; At least one DC-DC converter module, the input of which is connected to the output of the semi-bridgeless PFC circuit; and The system control module is electrically connected to the semi-bridgeless PFC circuit and the DC-DC converter module.

7. A computer, characterized in that, include: Chassis; The motherboard, processor, memory, and storage devices are housed within the chassis. as well as The power system as described in claim 6 is used to supply power to the motherboard, processor, memory, and storage device.

8. A method for operating a semi-bridgeless PFC circuit as described in claim 1, characterized in that, The method includes: Receive voltage feedback signals and current detection signals; Based on the voltage feedback signal and current detection signal, a synchronous PWM drive signal for controlling the first switch (QA3) and the second switch (QA4) is generated; The synchronous PWM drive signal is applied to the gates of the first switch (QA3) and the second switch (QA4) so ​​that the first switch (QA3) and the second switch (QA4) are controlled to perform synchronous chopping during the positive half-cycle and negative half-cycle of the AC current, respectively.

9. A method for operating a semi-bridgeless PFC circuit as described in claim 2, characterized in that, The method includes: It receives voltage feedback signals and current detection signals, and generates the original drive signals; Monitor the status of the power stage circuit and generate an enable signal based on the monitoring results; Perform a logical AND operation on the original drive signal and the enable signal to generate a valid drive signal; The active drive signal is applied to the gate of the switch only when the enable signal is active.

10. A method for implementing power factor correction in a computer, characterized in that, The method includes: Used to operate a semi-bridgeless PFC circuit as described in claim 9 to convert AC input to DC. The DC power is converted into the operating voltage required by the computer's internal components via a DC-DC converter module.

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