A package circuit board with enhanced structure and a method of manufacturing

By setting a polyimide material with a low coefficient of thermal expansion as an auxiliary structure on the substrate, the warping problem caused by the mismatch of the coefficient of thermal expansion of the Coreless ultrathin substrate is solved, thereby improving the bonding stability and lifespan of the substrate and the chip.

CN122138324AActive Publication Date: 2026-06-02QULIANG ELECTRONICS CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
QULIANG ELECTRONICS CO LTD
Filing Date
2026-04-30
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

In the manufacturing process of Coreless ultrathin substrates, the mismatch of thermal expansion coefficients between materials leads to severe substrate warping. Existing technologies that optimize the thermal expansion coefficients of materials suffer from high R&D investment and long development cycles.

Method used

By setting an auxiliary structure on the substrate, a polyimide material with a low coefficient of thermal expansion is used to replace the edge position of the solder resist layer to form a constraint force and suppress the lateral expansion of the solder resist layer. The auxiliary structure is formed by combining plasma etching and chemical bonding methods.

Benefits of technology

It significantly reduced substrate warpage, improved the bonding stability and overall lifespan of the substrate and chip, and reduced the Moire value from 18.66μm to 12.59μm, thus reducing the risk of cracking.

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Abstract

This invention relates to a reinforced packaged circuit board, comprising a substrate, a first processing area and a second processing area disposed adjacent to each other on a first surface of the substrate, the second processing area being arranged in a ring around the first processing area; a solder resist layer covering the first processing area of ​​the substrate; a chip soldered to the first surface of the solder resist layer; and an auxiliary structure covering the second processing area of ​​the substrate; wherein the coefficient of thermal expansion of the auxiliary structure is lower than that of the solder resist layer. This invention, through the intervention of the auxiliary structure, partially replaces the solder resist layer, forming a constraint on the solder resist layer, thereby releasing substrate stress and suppressing expansion, thus improving warpage.
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