Embedded circuit board and method of manufacturing the same

Abstract

This application proposes an embedded circuit board and its fabrication method. This application connects the embedded components electrically via metal pillars and solder instead of through the circuit board, thus reducing signal loss between circuit board traces, facilitating high-frequency signal transmission, and further improving the integration of the embedded circuit board, aligning with the trend towards thinner and more precise circuit boards.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to an embedded circuit board and its manufacturing method. Background Technology

[0002] Embedded circuit technology refers to the technique of embedding various components and circuits inside a circuit board to improve its performance, density, and reliability. Embedded circuit boards can significantly increase the wiring density of a circuit board without increasing its size, which is crucial for products that pursue miniaturization and lightweight design.

[0003] In conventional embedded circuit boards, different components are usually electrically connected through the circuit board, and signal loss is inevitable when passing through the circuit board. Summary of the Invention

[0004] In view of this, this application provides an embedded circuit board and its manufacturing method to reduce signal loss during transmission.

[0005] This application provides a method for fabricating an embedded circuit board, comprising the following steps: setting a plurality of first metal pillars of different heights on a first component; setting a plurality of second metal pillars of different heights on a second component; setting a plurality of third metal pillars of different heights on a third component; forming a first groove and a second groove spaced apart on a substrate; placing the first component in the first groove and the second component in the second groove; wherein, along the extension direction of the substrate, the plurality of first metal pillars are respectively positioned towards the plurality of second metal pillars; pressing a first insulating layer onto the surface of the substrate, and filling the first groove and the second groove with the first insulating layer, the first insulating layer covering the first component and the second component; removing the structure between the first groove and the second groove, making the first groove and the second groove connected. A cavity is formed, and a portion of the surfaces of the plurality of first metal pillars and the plurality of second metal pillars are exposed from the first insulating layer. Solder is applied to a portion of the third metal pillars, and the third element is placed in the cavity, positioned between the first and second elements. A portion of the third metal pillars with solder is connected to the first metal pillars via the solder, and another portion of the third metal pillars with solder is connected to the second metal pillars via the solder. A second insulating layer is laminated onto the surface of the substrate and fills the cavity. A copper plating layer is applied to the surface of the second insulating layer facing away from the substrate, and the copper plating layer is connected to the third metal pillars without solder. The copper plating layer is fabricated to form a conductive circuit layer, which is connected to the third metal pillars without solder and to the first and second metal pillars.

[0006] One embodiment of this application provides an embedded circuit board, comprising a substrate, a first element, a second element, a third element, an insulating layer, and a conductive circuit layer. The substrate has a cavity extending through it along its thickness direction. The first element is disposed within the cavity and has a plurality of first metal pillars of varying heights. The second element is disposed within the cavity and has a plurality of second metal pillars of varying heights. Along the extension direction of the substrate, the plurality of first metal pillars are respectively disposed facing the plurality of second metal pillars. The third element is disposed within the cavity and located between the first element and the second element, and has a plurality of third metal pillars of varying heights. Solder is disposed on a portion of the third metal pillars, with some of the soldered third metal pillars connected to the first metal pillars via the solder, and other portions of the soldered third metal pillars connected to the second metal pillars via the solder. The insulating layer is located on the surface of the substrate and fills the cavity to enclose the first element, the second element, and the third element. The conductive circuit layer is located on the surface of the insulating layer opposite to the substrate. The conductive circuit layer is connected to a third metal pillar without solder, and is also connected to a first metal pillar and a second metal pillar.

[0007] The embedded circuit board and its manufacturing method disclosed in this application connect the embedded components electrically through metal pillars and solder instead of through the circuit board. This reduces signal loss between circuit board traces, is more conducive to high-frequency signal transmission, and further improves the integration of the embedded circuit board, which is in line with the development trend of circuit boards becoming thinner and more precise. Attached Figure Description

[0008] Figures 1A to 1G A schematic diagram of setting a first metal pillar on a first element.

[0009] Figure 2 A schematic diagram showing the placement of a second metal pillar on a second element.

[0010] Figure 3 A schematic diagram showing the placement of a third metal pillar on a third component.

[0011] Figure 4 This is a cross-sectional view showing the formation of a first groove and a second groove on a substrate.

[0012] Figure 5 To be Figure 1G The first element shown and Figure 2 The second element shown is placed in Figure 4 A schematic diagram of the substrate shown.

[0013] Figure 6 In order to be in Figure 5 A cross-sectional view of the first insulating layer laminated on the substrate of the structure shown.

[0014] Figure 7 In order to be in Figure 6 The diagram shows a cross-sectional view of the cavity formed on the structure.

[0015] Figure 8 In order to be in Figure 7 The cavity of the structure shown is set Figure 3 A schematic diagram of the third element is shown.

[0016] Figure 9 In order to be in Figure 8 The diagram shows a second insulating layer being laminated onto the structure.

[0017] Figure 10 In order to be in Figure 9 A schematic diagram showing a copper-plated layer on the surface of the second insulating layer of the structure shown.

[0018] Figure 11 To be Figure 10 A schematic diagram of an embedded circuit board obtained by forming a conductive circuit layer after the copper plating layer of the structure shown is fabricated in one embodiment.

[0019] Figure 12 In order to be in Figure 11 The diagram shows a further layering process on the surface of the embedded circuit board.

[0020] Explanation of main component symbols

[0021] Embedded circuit board 100

[0022] First Component 10

[0023] First metal pillars 11, 111, 112, 113

[0024] Dry film 12

[0025] Metallic materials 13

[0026] Shielding film 14

[0027] Ontology 101

[0028] Pin 102

[0029] Open window 120

[0030] Second element 20

[0031] Second metal pillars 21, 211, 212, 213

[0032] Third element 30

[0033] Third metal pillars 31, 311, 312, 313, 314

[0034] Substrate 40

[0035] Dielectric layer 41

[0036] Inner circuit layer 42

[0037] First groove 401

[0038] Second groove 402

[0039] Cavity 403

[0040] Adhesive layer 50

[0041] Insulation layer 60

[0042] First insulating layer 61

[0043] Second insulating layer 62

[0044] Solder 70

[0045] 80a copper plating

[0046] Conductive circuit layer 80

[0047] Conductive hole 81

[0048] Add-on circuit layer 90

[0049] The length L of the cavity

[0050] The depth H of the cavity

[0051] The following detailed description, in conjunction with the accompanying drawings, further illustrates the embodiments of this application. Detailed Implementation

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the embodiments of this application. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0053] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0054] It will be understood that when a layer is referred to as "on" another layer, it can be directly on that other layer or there may be an intermediate layer in between. Conversely, when a layer is referred to as "directly on" another layer, there is no intermediate layer. When a component is referred to as "attached to," "mounted to," "set on," or "connected to" another component, it can be directly on that other component or there may be an intervening component. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0055] Embodiments of this application are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate configurations) of this application. Therefore, variations in the shapes illustrated due to manufacturing processes and / or tolerances are foreseeable. Consequently, embodiments of this application should not be construed as limited to the specific shapes of the areas illustrated herein, but should include, for example, deviations in shape due to manufacturing processes. The areas shown in the figures are merely illustrative, and their shapes are not intended to represent the actual shapes of the illustrated devices, nor are they intended to limit the scope of this application.

[0056] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0057] Please see Figures 1A to 12 The first aspect of this application provides a method for fabricating an embedded circuit board 100, which includes steps S1 to S13. It is understood that the step numbers are intended to clearly describe the specific fabrication method and do not imply a limitation on the order of the steps.

[0058] Please see Figures 1A to 1G S1, a plurality of first metal pillars 11 of different heights are provided on the first element 10. The first metal pillars 11 can be formed by the following steps.

[0059] First, such as Figure 1A As shown, a first element 10 is provided, which may be, but is not limited to, a chip. The first element 10 may include a body 101 and pins 102 connected to the body 101, and the number of pins 102 may be multiple. In this embodiment, three pins 102 are shown.

[0060] Then, as Figure 1B As shown, a dry film 12 is laminated onto the surface of the first element 10. The dry film 12 covers the pin 102 and the surface of the body 101 exposed from the pin 102.

[0061] Next, as Figure 1C As shown, the dry film 12 is developed and exposed to form a plurality of windows 120 on the dry film 12. Leads 102 may be exposed from the windows 120. The windows 120 may be, but are not limited to, cylindrical.

[0062] Next, as Figure 1D As shown, electroplating is performed in the window 120 so that each pin 102 is plated with a layer of metal material 13 of a certain height on the surface facing away from the body 101. The metal material 13 can be, but is not limited to, copper. Along the extension direction of the first element 10 (i.e., Figure 1D The horizontal direction (which can be the length direction or the width direction of the first element 10) and the leftmost pin 102 and the metal material 13 on its surface together form the first metal pillar 11. The first metal pillar 11 can be a copper pillar.

[0063] Next, as Figure 1E As shown, a masking film 14 is applied to a portion of the surface of the dry film 12 to cover the leftmost opening 120, and then the metal material 13 is electroplated in the other two openings 120. The leftmost first metal pillar 11 is covered by the masking film 14, so it cannot be electroplated with the metal material 13. The pins 102 in the middle opening 120 and the repeatedly electroplated metal material 13 together form the first metal pillar 11. For clarity, the first metal pillar 11 is divided into a first-gradient first metal pillar 111 and a second-gradient first metal pillar 112 according to its height. The first-gradient first metal pillar 111 is located on the left, and the second-gradient first metal pillar 112 is located in the middle. Along the thickness direction of the first element 10 (i.e. Figure 1E (In the vertical direction), the height of the first metal pillar 112 of the second gradient is greater than the height of the first metal pillar 111 of the first gradient. The material of the masking film 14 may be, but is not limited to, polyimide (PI).

[0064] Next, as Figure 1F As shown, a masking film 14 is applied to a portion of the surface of the dry film 12 to cover the leftmost and middle openings 120, and then metal material 13 is electroplated in the rightmost opening 120. The pins 102 within the rightmost opening 120 and the repeatedly electroplated metal material 13 together form a first metal pillar 11. For clarity, the rightmost first metal pillar 11 is divided into a third-gradient first metal pillar 113. The height of the third-gradient first metal pillar 113 is greater than the height of the second-gradient first metal pillar 112.

[0065] Finally, as Figure 1G As shown, after removing the dry film 12 and the masking film 14, a first element 10 with multiple first metal pillars 11 of different heights is obtained. Along the extending direction of the first element 10, the heights of the first metal pillars 111, 112, and 113 increase sequentially.

[0066] In some embodiments, such as Figure 1GAs shown, the first metal pillars 111, 112, and 113 are all cylindrical, and the diameter of each first metal pillar 11 can be 10μm to 40μm. The spacing between two adjacent first metal pillars 11 (the closest distance between the edges of two adjacent first metal pillars 11) can be 10μm to 50μm to ensure that short circuits or other problems do not occur when connected to the third metal pillar later.

[0067] In some embodiments, the height of the first metal pillar 111 of the first gradient can be 10 μm to 40 μm, the height of the first metal pillar 112 of the second gradient can be 50 μm to 80 μm, and the height of the first metal pillar 113 of the third gradient can be 90 μm to 150 μm.

[0068] In some embodiments, along the extending direction of the first element 10 (i.e. Figure 1G (in the horizontal direction), the length of the first element 10 can be 100μm to 200μm. The sum of the thickness of the first element 10 and the height of the first metal pillar 113 can be 100μm to 150μm.

[0069] Please see Figure 2 S2, Multiple second metal pillars 21 of different heights are disposed on the second element 20. The second element 20 may be, but is not limited to, a chip, and the second metal pillars 21 may be copper pillars. The manufacturing method of the second metal pillars 21 is similar to... Figures 1A to 1G The manufacturing method of the first metal pillar 11 shown is the same, and will not be described again here.

[0070] To clarify the description, the second metal pillar 21 is divided into a first gradient, a second gradient, and a third gradient based on its height. The second metal pillar 21 of the first gradient is represented by 211 in the figure, the second metal pillar 21 of the second gradient is represented by 212, and the second metal pillar 21 of the third gradient is represented by 213. The height of the second metal pillar 212 of the second gradient is greater than the height of the second metal pillar 211 of the first gradient, and the height of the second metal pillar 213 of the third gradient is greater than the height of the second metal pillar 212 of the second gradient. Along the extending direction of the second element 20 (i.e.... Figure 2 (in the horizontal direction), the heights of the second metal pillars 211, 212, and 213 increase sequentially.

[0071] In some embodiments, such as Figure 2 As shown, the second metal pillars 211, 212, and 213 are all cylindrical, and the diameter of each second metal pillar 21 can be 10μm to 40μm. The spacing between two adjacent second metal pillars 21 (the closest distance between the edges of two adjacent second metal pillars 21) can be 10μm to 50μm to ensure that short circuits or other problems do not occur when connected to the third metal pillar later.

[0072] In some embodiments, the height of the second metal pillar 211 of the first gradient can be 10 μm to 40 μm, the height of the second metal pillar 212 of the second gradient can be 50 μm to 80 μm, and the height of the second metal pillar 213 of the third gradient can be 90 μm to 150 μm.

[0073] In some embodiments, along the extending direction of the second element 20 (i.e. Figure 2 (in the horizontal direction), the length of the second element 20 can be 100μm to 200μm. The sum of the thickness of the second element 20 and the height of the second metal pillar 213 can be 100μm to 150μm.

[0074] Please see Figure 3 S3, Multiple third metal pillars 31 of different heights are provided on the third element 30. The third element 30 can be, but is not limited to, a chip, and the third metal pillars 31 can be copper pillars. The fabrication method of the third metal pillars 31 can be referred to Figures 1A to 1G The manufacturing method of the first metal pillar 11 shown will not be described in detail here.

[0075] To clarify the description, the third metal pillar 31 is divided into four gradients based on its height: a first gradient, a second gradient, a third gradient, and a fourth gradient. The third metal pillar 31 of the first gradient is represented by 311 in the figure, the third metal pillar 31 of the second gradient is represented by 312, the third metal pillar 31 of the third gradient is represented by 313, and the third metal pillar 31 of the fourth gradient is represented by 314. The height of the third metal pillar 312 of the second gradient is greater than the height of the third metal pillar 311 of the first gradient, the height of the third metal pillar 313 of the third gradient is greater than the height of the third metal pillar 312 of the second gradient, and the height of the third metal pillar 314 of the fourth gradient is greater than the height of the third metal pillar 313 of the third gradient. That is, the third metal pillar 314 of the fourth gradient is the tallest, and the third metal pillar 311 of the first gradient is the shortest. The tallest third metal pillar 314 is located in the extension direction of the third element 30 (i.e.,...). Figure 3 In the middle area (horizontally), with the highest third metal pillar 314 as the center, the height of the third metal pillars 31 decreases sequentially. That is, the multiple third metal pillars 31 generally exhibit a trend of being high in the middle and low on both sides. The multiple third metal pillars 31 are arranged symmetrically on both sides.

[0076] In some embodiments, such as Figure 3As shown, the number of third metal pillars 314 can be two; in other embodiments, the number of third metal pillars 314 can be one. One of the third metal pillars 314 has a third metal pillar 313 on one side, and the other third metal pillar 314 also has a third metal pillar 313 on one side. Each third metal pillar 313 has a third metal pillar 312 on the side away from the third metal pillar 314, and each third metal pillar 312 has a third metal pillar 311 on the side away from the third metal pillar 313.

[0077] In some embodiments, such as Figure 3 As shown, the third metal pillars 31 are all cylindrical, and the diameter of each third metal pillar 31 can be 10μm to 40μm. The spacing between two adjacent third metal pillars 31 (the closest distance between the edges of two adjacent third metal pillars 31) can be 10μm to 50μm to ensure that short circuits or other problems do not occur when connected to the first metal pillar 11 or the second metal pillar 21.

[0078] In some embodiments, the height of the third metal pillar 311 of the first gradient can be 10 μm to 40 μm, the height of the third metal pillar 312 of the second gradient can be 50 μm to 80 μm, the height of the third metal pillar 313 of the third gradient can be 90 μm to 150 μm, and the height of the third metal pillar 314 of the fourth gradient can be 120 μm to 200 μm.

[0079] In some embodiments, along the extending direction of the third element 30 (i.e. Figure 3 (in the horizontal direction), the length of the third element 30 can be 100μm to 1000μm. The sum of the thickness of the third element 30 and the height of the third metal pillar 314 can be 100μm to 200μm.

[0080] Please see Figure 4 S4, a first groove 401 and a second groove 402 spaced apart can be formed on the substrate 40 by means of, but not limited to, laser etching. The first groove 401 and the second groove 402 can be along the thickness direction of the substrate 40 (i.e., Figure 4 The first groove 401 and the second groove 402 can extend along the extension direction of the substrate 40 (i.e., the vertical direction) through the substrate 40. Figure 4 The horizontal direction of the substrate 40 can be either the length direction or the width direction of the substrate 40.

[0081] In some embodiments, such as Figure 4As shown, the substrate 40 may include a dielectric layer 41 and inner circuit layers 42 located on opposite surfaces of the dielectric layer 41. The dielectric layer 41 may be made of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane (PDMS), liquid crystal polymer (LCP), modified polyimide (MPI), etc. The inner circuit layer 42 may be formed of copper. A first groove 401 and a second groove 402 penetrate the dielectric layer 41 and the inner circuit layer 42.

[0082] Please see Figure 5 S5, place the first element 10 in the first groove 401 and the second element 20 in the second groove 402. Along the extending direction of the substrate 40 (i.e., Figure 5 (in the horizontal direction), the first metal post 11 and the second metal post 21 are each set facing each other. That is, the first metal posts 111, 112, and 113 are set facing the second metal posts 211, 212, and 213, and the second metal posts 211, 212, and 213 are set facing the first metal posts 111, 112, and 113.

[0083] like Figure 5 As shown, an adhesive layer 50 can be adhered to the lower surface of the substrate 40, and the adhesive layer 50 covers at least the bottom of the first groove 401 and the second groove 402. The first element 10 and the second element 20 can be fixed in the first groove 401 and the second groove 402 respectively by the adhesiveness of the adhesive layer 50. The adhesive layer 50 can be, but is not limited to, PI tape.

[0084] like Figure 5 As shown, in some embodiments, the height direction (axial direction of the pillar) of the first metal pillar 11 may be substantially parallel to the extension direction of the substrate 40, and the height direction (axial direction of the pillar) of the second metal pillar 21 may be substantially parallel to the extension direction of the substrate 40. The first metal pillar 111 and the second metal pillar 211 may be located on the same horizontal plane, the first metal pillar 112 and the second metal pillar 212 may be located on the same horizontal plane, and the first metal pillar 113 and the second metal pillar 213 may be located on the same horizontal plane.

[0085] Please see Figure 6S6, a first insulating layer 61 is pressed onto the surface of the substrate 40, and the first insulating layer 61 fills the first groove 401 and the second groove 402. The first insulating layer 61 covers the first element 10 and the second element 20, thereby fixing the first element 10 and the second element 20 in the first groove 401 and the second groove 402 respectively. After the first insulating layer 61 is pressed, the adhesive layer 50 can be removed.

[0086] In some embodiments, the first insulating layer 61 may be, but is not limited to, Ajinomoto Build-up Film (ABF). ABF (trade name) is an insulating resin developed by Ajinomoto, which has advantages such as higher hardness, thinner thickness, and better insulation. In other embodiments, the first insulating layer 61 may be replaced with other materials with insulating properties.

[0087] Please see Figure 7 S7, the structure (including a portion of the substrate 40 and a portion of the first insulating layer 61) between the first groove 401 and the second groove 402 can be removed by means of laser, but not limited to laser, so that the first groove 401 and the second groove 402 are connected to form a cavity 403. In addition, the first insulating layer 61 on the surface of the first metal pillar 11 and the second metal pillar 21 is also partially removed, so that a portion of the surface of each first metal pillar 11 and each second metal pillar 21 is exposed from the first insulating layer 61.

[0088] In some embodiments, such as Figure 7 As shown, the portion of the side surface of the first metal pillar 111 (cylinder) facing away from the first metal pillar 112 and its top surface are exposed. The portion of the side surface of the first metal pillar 112 (cylinder) facing the first metal pillar 111 is exposed, as is its top surface. The portion of the side surface of the first metal pillar 113 (cylinder) facing the first metal pillar 112 is exposed, as is its top surface.

[0089] In some embodiments, such as Figure 7 As shown, the portion of the side surface of the second metal pillar 211 (cylinder) facing away from the second metal pillar 212 and its top surface are exposed. The portion of the side surface of the second metal pillar 212 (cylinder) facing the second metal pillar 211 is exposed, as is its top surface. The portion of the side surface of the second metal pillar 213 (cylinder) facing the second metal pillar 212 is exposed, as is its top surface.

[0090] In some embodiments, such as Figure 7 As shown, along the extension direction of substrate 40 (i.e. Figure 7 The length L of cavity 403 can be 500 μm to 1000 μm (in the horizontal direction of the substrate 40). Along the thickness direction of substrate 40 (i.e., along the horizontal direction of the substrate 40)... Figure 7(Vertical direction in the middle), the depth H of cavity 403 can be 100μm to 150μm. The above dimensions of cavity 403 can be set according to the dimensions of the first element 10, the second element 20, the third element 30 and the metal pillars on them, to ensure that there will be no problems such as poor electrical connection (e.g., open circuit, short circuit, etc.) when connecting the various elements.

[0091] Please see Figure 8 S8, solder 70 is respectively applied to the third metal pillars 31 (311, 312, 313) of the first gradient, second gradient and third gradient, and then the third element 30 is placed in the cavity 403 (wherein, the solder 70 faces downward and the height direction of the third metal pillar 31 is approximately parallel to the thickness direction of the substrate 40), so that the third element 30 is located between the first element 10 and the second element 20, and a portion of the third metal pillars 31 (311, 312, 313) with solder 70 are connected to the first metal pillar 11 through solder 70 (fixed connection and electrical connection), and another portion of the third metal pillars 31 (311, 312, 313) with solder 70 are connected to the second metal pillar 21 through solder 70 (fixed connection and electrical connection).

[0092] In some embodiments, after the third element 30 is placed, the solder 70 can be melted and solidified by a reflow soldering operation, thereby completing the fixed connection and electrical connection between the solder 70 and the first metal pillar 11 or the second metal pillar 21. The solder 70 may be, but is not limited to, tin.

[0093] In some embodiments, such as Figure 8 As shown, the end of the highest third metal pillar 314 facing away from the third element 30 can extend from the cavity 403. Centered on the highest third metal pillar 314, the third metal pillar 311 on its left is connected to the first metal pillar 111 via solder 70, and the third metal pillar 311 is approximately perpendicular to the first metal pillar 111. The third metal pillar 312 on its left is connected to the first metal pillar 112 via solder 70, and the third metal pillar 312 is approximately perpendicular to the first metal pillar 112. The third metal pillar 313 on its left is connected to the first metal pillar 113 via solder 70, and the third metal pillar 313 is approximately perpendicular to the first metal pillar 113.

[0094] In some embodiments, such as Figure 8As shown, with the highest third metal pillar 314 as the center, the third metal pillar 311 on its right is connected to the second metal pillar 211 via solder 70, and the third metal pillar 311 is approximately perpendicular to the second metal pillar 211. The third metal pillar 312 on its right is connected to the second metal pillar 212 via solder 70, and the third metal pillar 312 is approximately perpendicular to the second metal pillar 211. The third metal pillar 313 on its right is connected to the second metal pillar 213 via solder 70, and the third metal pillar 313 is approximately perpendicular to the second metal pillar 211.

[0095] Please see Figure 9 S9, a second insulating layer 62 is laminated onto the surface of the substrate 40, and the second insulating layer 62 is filled into the cavity 403. The second insulating layer 62 and the first insulating layer 61 together enclose the first element 10, the second element 20 and the third element 30, that is, the first element 10, the second element 20 and the third element 30 are embedded in the substrate 40. The second insulating layer 62 may be ABF.

[0096] In some embodiments, such as Figure 9 As shown, a second insulating layer 62 is provided on both the upper and lower surfaces of the substrate 40. One (upper) second insulating layer 62 is located on the surface of the first insulating layer 61 facing away from the substrate 40, while the other (lower) second insulating layer 62 directly covers the surface of the inner circuit layer 42. It is understood that in the actual product, there may not be a clear dividing line between the first insulating layer 61 and the second insulating layer 62, and the two may be fused together to form an insulating layer 60.

[0097] Furthermore, if the second insulating layer 62 is too thick and the third metal pillar 314 cannot be exposed from the second insulating layer 62, a chemical mechanical polishing (CMP) operation can be performed on the second insulating layer 62 so that the surface of the third metal pillar 314 away from the third element 30 is flush with the surface of the second insulating layer 62 away from the inner circuit layer 42.

[0098] Please see Figure 10 S10, a copper plating layer 80a can be formed on the surface of the second insulating layer 62 facing away from the substrate 40 by means of, but not limited to, chemical copper plating. In this embodiment, a copper plating layer 80a is formed on the surface of the upper second insulating layer 62 and the surface of the lower second insulating layer 62, respectively. The lower copper plating layer 80a is connected to the third metal pillar 314, which is not provided with solder 70.

[0099] Please see Figure 11S11, blind vias (not shown) can be formed on the upper copper plating layer 80a and the second insulating layer 62 by means of laser, and also on the lower copper plating layer 80a and the second insulating layer 62 (not shown). Then, copper is electroplated into the blind vias to form conductive vias 81. The number of conductive vias 81 in both the upper and lower layers can be multiple.

[0100] Please continue reading. Figure 11 In step S12, the copper plating layer 80a is fabricated to form a conductive circuit layer 80, resulting in an embedded circuit board 100. The upper conductive circuit layer 80 is electrically connected to the upper inner circuit layer 42 via an upper conductive via 81, and the lower conductive circuit layer 80 is electrically connected to the lower inner circuit layer 42 via a lower conductive via 81. The lower conductive circuit layer 80 also directly contacts the third metal post 314 (where solder 70 is not applied), thus becoming electrically connected to the third metal post 314. The lower conductive circuit layer 80 is also electrically connected to the first metal post 113 and the second metal post 113 via conductive vias 81.

[0101] Please see Figure 12 S13, additional layers can be added to the surface of the conductive line layer 80 to obtain an embedded circuit board 100 with more line layers.

[0102] Specifically, a copper-clad laminate (not shown) can be laminated onto the surface of the conductive circuit layer 80 facing away from the substrate 40. The copper-clad laminate includes a dielectric layer 41 and a copper foil layer (not shown), with the dielectric layer 41 located between the conductive circuit layer 80 and the copper foil layer. Then, the copper foil layer can be fabricated to form an add-on circuit layer 90 using image transfer and etching processes. The above steps can be repeated multiple times to form a multilayer add-on circuit layer 90.

[0103] Please continue reading. Figure 11 and Figure 12 The second aspect of this application provides an embedded circuit board 100, which includes a first element 10, a second element 20, a third element 30, a substrate 40, an insulating layer 60, and a conductive line layer 80.

[0104] The substrate 40 has a cavity 403 extending through the substrate 40 along its thickness direction, and the first element 10, the second element 20 and the third element 30 are all housed in the cavity 403. The substrate 40 may include a dielectric layer 41 and inner circuit layers 42 located on opposite surfaces of the dielectric layer 41.

[0105] The insulating layer 60 may be located on two opposite surfaces of the substrate 40 and fill the cavity 403 to enclose the first element 10, the second element 20, and the third element 30. That is, the first element 10, the second element 20, and the third element 30 are embedded in the substrate 40. The insulating layer 60 may be ABF. The conductive line layer 80 is located on the surface of the insulating layer 60 facing away from the substrate 40.

[0106] The first element 10 is provided with a plurality of first metal pillars 11 of different heights. Specifically, the first metal pillars 11 can be divided into first metal pillars 111 of a first gradient, first metal pillars 112 of a second gradient, and first metal pillars 113 of a third gradient according to their heights, with the heights of the first metal pillars 111, 112, and 113 increasing sequentially.

[0107] The second element 20 is provided with a plurality of second metal pillars 21 of different heights. Specifically, the second metal pillars 21 can be divided into a first-gradient second metal pillar 211, a second-gradient second metal pillar 212, and a third-gradient second metal pillar 213 according to their heights, with the heights of the second metal pillars 211, 212, and 213 increasing sequentially.

[0108] Along the extension direction of substrate 40 (i.e. Figure 11 and Figure 12 (in the horizontal direction), the first metal post 11 and the second metal post 21 are each set facing each other. That is, the first metal posts 111, 112, and 113 are set facing the second metal posts 211, 212, and 213, and the second metal posts 211, 212, and 213 are set facing the first metal posts 111, 112, and 113.

[0109] The third element 30 is located between the first element 10 and the second element 20, and is provided with multiple third metal pillars 31 of different heights. Specifically, the third metal pillars 31 can be divided into a first-gradient third metal pillar 311, a second-gradient third metal pillar 312, a third-gradient third metal pillar 313, and a fourth-gradient third metal pillar 314 according to their height, with the heights of the third metal pillars 311, 312, 313, and 314 increasing sequentially. The multiple third metal pillars 31 generally exhibit a trend of being higher in the middle and lower on both sides, and are arranged symmetrically on both sides. Solder 70 is provided on the third metal pillars 311, 312, and 313 respectively. Some of the third metal pillars 311, 312, and 313 with solder 70 are connected to the first metal pillars 111, 112, and 113 respectively through solder 70, while other third metal pillars 311, 312, and 313 with solder 70 are connected to the second metal pillars 211, 212, and 213 respectively through solder 70. The third metal post 314, which is not equipped with solder 70, is in direct contact with the conductive circuit layer 80 (electrical connection) and is connected to the first metal post 113 and the second metal post 213 through the conductive hole 81.

[0110] In some embodiments, such as Figure 12As shown, the embedded circuit board 100 further includes at least one dielectric layer 41 and at least one add-on circuit layer 90. When there is one dielectric layer 41 and one add-on circuit layer 90, the add-on circuit layer 90 is located between the dielectric layer 41 and the conductive circuit layer 80. When there are multiple dielectric layers 41 and multiple add-on circuit layers 90, one add-on circuit layer 90 is located between the dielectric layer 41 and the conductive circuit layer 80, and a dielectric layer 41 is provided between two adjacent add-on circuit layers 90.

[0111] The embedded circuit board 100 and its manufacturing method in this application embodiment electrically connect the embedded components through metal pillars and solder instead of through the circuit board. Therefore, it can reduce signal loss between circuit board traces, which is more conducive to high-frequency signal transmission. It also further improves the integration of the embedded circuit board 100, which is in line with the development trend of circuit boards becoming thinner and more precise.

[0112] The above description describes some specific embodiments of this application, but in actual applications, the application should not be limited to these embodiments. For those skilled in the art, other modifications and alterations made based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A method for manufacturing an embedded circuit board, characterized in that, Includes the following steps: Multiple first metal pillars of different heights are disposed on the first element; Multiple second metal pillars of different heights are disposed on the second element; Multiple third metal pillars of different heights are set on the third element; A first groove and a second groove are formed at intervals on the substrate; The first element is placed in the first groove, and the second element is placed in the second groove; wherein, along the extension direction of the substrate, the plurality of first metal pillars are respectively disposed toward the plurality of second metal pillars; A first insulating layer is pressed onto the surface of the substrate, and the first insulating layer fills the first groove and the second groove, the first insulating layer covering the first element and the second element; The structure between the first groove and the second groove is removed, so that the first groove and the second groove are connected to form a cavity, and a portion of the surfaces of the plurality of first metal pillars and the plurality of second metal pillars are exposed from the first insulating layer; Solder is applied to a portion of the third metal pillars. The third element is placed in the cavity, with the third element positioned between the first element and the second element. A portion of the third metal pillars with solder is connected to the first metal pillar through the solder, and another portion of the third metal pillars with solder is connected to the second metal pillar through the solder. A second insulating layer is pressed onto the surface of the substrate and the second insulating layer is filled into the cavity. A copper plating layer is provided on the surface of the second insulating layer opposite to the substrate, and the copper plating layer is connected to a third metal pillar without solder. The copper plating layer is used to form a conductive circuit layer, which is connected to a third metal post without solder, and to a first metal post and a second metal post.

2. The preparation method according to claim 1, characterized in that, Along the extension direction of the first element, the plurality of first metal pillars are arranged sequentially in a manner that gradually increases in height. The height of the plurality of first metal pillars is divided into three gradients: the height of the first metal pillar in the first gradient is 10μm to 40μm, the height of the first metal pillar in the second gradient is 50μm to 80μm, and the height of the first metal pillar in the third gradient is 90μm to 150μm. The spacing between two adjacent first metal pillars is 10μm to 50μm, and the diameter of each first metal pillar is 10μm to 40μm.

3. The preparation method according to claim 1, characterized in that, The plurality of second metal pillars are arranged sequentially in a manner that gradually increases in height. The height of the plurality of second metal pillars is divided into three gradients: the height of the second metal pillars in the first gradient is 10μm to 40μm, the height of the second metal pillars in the second gradient is 50μm to 80μm, and the height of the second metal pillars in the third gradient is 90μm to 150μm. The spacing between two adjacent second metal pillars is 10μm to 50μm, and the diameter of each second metal pillar is 10μm to 40μm.

4. The preparation method according to claim 1, characterized in that, Among the plurality of third metal pillars, the tallest third metal pillar is located in the middle region of the extension direction of the third element. With the tallest third metal pillar as the center, the height of the third metal pillars decreases sequentially. The distance between two adjacent third metal pillars is 10μm to 50μm, and the diameter of each third metal pillar is 10μm to 40μm.

5. The preparation method according to claim 4, characterized in that, The height of the highest third metal pillar is 120μm to 200μm. The heights of the remaining third metal pillars are divided into three gradients: the height of the third metal pillars in the first gradient is 10μm to 40μm, the height of the metal pillars in the second gradient is 50μm to 80μm, and the height of the metal pillars in the third gradient is 90μm to 150μm. The third metal pillars in the first gradient are electrically connected to the first metal pillars and the second metal pillars in the first gradient, respectively. The third metal pillars in the second gradient are electrically connected to the first metal pillars and the second metal pillars in the second gradient, respectively. The third metal pillars in the third gradient are electrically connected to the first metal pillars and the second metal pillars in the third gradient, respectively.

6. The preparation method according to claim 1, characterized in that, Along the extension direction of the substrate, the length of the cavity is 500-1000 μm; along the thickness direction of the substrate, the depth of the cavity is 100-150 μm.

7. The preparation method according to claim 1, characterized in that, It also includes the following steps: A copper-clad laminate is laminated on the surface of the conductive circuit layer away from the substrate. The copper-clad laminate includes a dielectric layer and a copper foil layer, with the dielectric layer located between the conductive circuit layer and the copper foil layer. The copper foil layer is used to form an additive circuit layer.

8. An embedded circuit board, characterized in that, include: A substrate having a cavity extending through the substrate along its thickness direction; A first element is disposed within the cavity, and the first element is provided with a plurality of first metal pillars of different heights; A second element is disposed within the cavity, and the second element is provided with a plurality of second metal pillars of different heights; along the extension direction of the substrate, the plurality of first copper pillars are respectively disposed toward the plurality of second metal pillars; A third element is disposed within the cavity and located between the first element and the second element. The third element is provided with a plurality of third metal pillars of different heights. Solder is provided on some of the third metal pillars. Some of the third metal pillars with solder are connected to the first metal pillars through the solder, and other third metal pillars with solder are connected to the second metal pillars through the solder. An insulating layer is located on the surface of the substrate and fills the cavity to enclose the first element, the second element, and the third element. and A conductive circuit layer is located on the surface of the insulating layer opposite to the substrate. The conductive circuit layer is connected to a third metal pillar without solder and to a first metal pillar and a second metal pillar.

9. The embedded circuit board as described in claim 8, characterized in that, The insulating layer comprises Ajinomoto resin.

10. The embedded circuit board as described in claim 8, characterized in that, The embedded circuit board further includes a dielectric layer and an add-on circuit layer, wherein the add-on circuit layer is located between the dielectric layer and the conductive circuit layer.

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