A back contact solar cell structure and method of manufacturing the same

Abstract

This application discloses a back-contact solar cell structure and its manufacturing method, relating to the field of battery technology. In the back-contact solar cell structure of this application, the intrinsic amorphous silicon layer and boron-doped amorphous silicon layer in the positive electrode region are disposed on a plane, compared to the existing back-contact solar cell structures where the intrinsic amorphous silicon layer and boron-doped amorphous silicon layer in the positive electrode region are disposed on a textured pyramid structure. This results in better passivation, while simultaneously reducing the metal ion content in the silicon substrate of the cell, reducing cell recombination, and improving cell efficiency.

Description

Technical Field

[0001] This application relates to the field of battery technology, specifically to a back-contact solar cell structure and its manufacturing method. Background Technology

[0002] Hybrid back contact (HTBC) cells represent the current efficiency ceiling for monocrystalline single-junction silicon cells. Their cell structure and manufacturing process combine the core technologies of TOPCon and HJT cells, and major domestic manufacturers are actively investing in this area, making its R&D a top priority. Currently, TOPCon cell modules have the largest market share. HTBC cells have entered the R&D and pilot production stages, and their manufacturing process is largely finalized, with most manufacturers employing similar process solutions. A cell consists of three distinct regions: the P-region, the N-region, and the PN transition region. The P-region refers to the positive electrode region of the cell, composed of materials such as boron and silicon. The silicon atoms within it lack electrons, hence the term "holes." The N-region refers to the negative electrode region of the cell, composed of phosphorus and silicon. The silicon atoms within it have an abundance of electrons, hence the term "free electrons." Analysis of the cell structure and manufacturing process revealed that the P-region of the cells all exhibits a textured pyramid structure, upon which an IP layer (amorphous silicon layer) is deposited. Compared to depositing an IP layer on a flat, polished silicon wafer, the passivation effect on the textured surface is lower than that on the polished surface, resulting in a relatively lower implied open-circuit voltage (iVoc), which hinders further improvements in cell efficiency. Furthermore, ultra-high-efficiency cells place high demands on silicon wafer quality; metal ions within the silicon wafer itself easily form recombination centers, reducing the minority carrier lifetime and thus impacting the efficiency of HTBC cells. Summary of the Invention

[0003] This application provides a back-contact solar cell structure and its manufacturing method, which can solve the technical problems of poor passivation effect and relatively low implicit open-circuit voltage (iVoc) when depositing amorphous silicon thin film on the textured pyramid structure of the positive electrode region of the cell, and the high requirements for silicon wafer quality of ultra-high efficiency cells, where metal ions contained in the silicon wafer itself are prone to form recombination centers, reducing the minority carrier lifetime of the silicon wafer and affecting the cell efficiency.

[0004] This application provides a back-contact solar cell structure and its manufacturing method, including: N-type crystalline silicon is provided, and a pyramid microstructure is fabricated by texturing and cleaning the front and back sides of the N-type crystalline silicon. A heavily doped phosphosilicate glass layer is fabricated on the front side of the N-type crystalline silicon, and the heavily doped phosphosilicate glass layer located on the back side of the N-type crystalline silicon is etched away. The pyramidal microstructure located on the back side of the N-type crystalline silicon is etched away, so that the back side of the N-type crystalline silicon forms a plane; A tunneling oxide layer and an intrinsic polycrystalline silicon layer are sequentially fabricated on the back side of the N-type crystalline silicon, and the intrinsic polycrystalline silicon layer is subjected to phosphorus diffusion treatment to form an N-type doped layer. The back side of the N-type crystalline silicon is divided into a positive electrode region and a negative electrode region. The tunneling oxide layer and N-type doped layer located in the positive electrode region are removed by laser ablation. Etching removes the phosphorus silica glass layer formed by phosphorus diffusion treatment; An aluminum oxide layer and a silicon nitride layer are sequentially fabricated on the front side of the N-type crystalline silicon. An intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer are sequentially fabricated on the back side of the N-type crystalline silicon. An opening is made in the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer in the negative electrode region, and the opening exposes the N-type doped layer. A transparent conductive film is deposited on the back side of the N-type crystalline silicon, and the transparent conductive film located at the junction of the positive electrode region and the negative electrode region is etched away. A first transparent conductive layer is formed in the negative electrode region, and a second transparent conductive layer is formed in the positive electrode region. Negative electrode fine grid lines and positive electrode fine grid lines are fabricated under the first transparent conductive layer and the second transparent conductive layer, respectively.

[0005] Furthermore, the provision of N-type crystalline silicon, and the texturing and cleaning of the front and back sides of the N-type crystalline silicon to create a pyramidal microstructure, includes: The N-type crystalline silicon is placed in a tank cleaning machine and texturing cleaning is performed using a texturing solution, which includes KOH, H2O and texturing additives. The reaction temperature for texturing cleaning is 80±20℃ and the reaction time is 600±200s, forming a pyramid microstructure on the front and back sides of the N-type crystalline silicon.

[0006] Furthermore, the step of fabricating a heavily doped phosphosilicate glass layer on the front side of the N-type crystalline silicon and etching away the heavily doped phosphosilicate glass layer on the back side of the N-type crystalline silicon includes: The texturized N-type crystalline silicon is placed in a phosphorus diffusion furnace. The back sides of two N-type crystalline silicon wafers are then attached together and inserted into a quartz boat for phosphorus diffusion treatment. The reaction source in the phosphorus diffusion furnace includes POCl3, O2, and N2, with a sheet resistance of 20±2Ω / sq. The thickness of the phosphorus silicon glass layer formed by the phosphorus diffusion treatment is 50±5nm, the reaction temperature is 900±20℃, and the reaction time is 130±5min. A heavily doped phosphorus silicon glass layer is formed on the front side of the N-type crystalline silicon. After diffusion of elemental phosphorus, N-type crystalline silicon is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards. The back side of the N-type crystalline silicon contacts the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the heavily doped phosphorus silicon glass layer located on the back side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 20±5%, the reaction temperature is room temperature, and the speed of the rollers is 4±1 m / min.

[0007] Furthermore, the etching and removal of the pyramidal microstructure located on the back side of the N-type crystalline silicon, thereby forming a plane on the back side of the N-type crystalline silicon, includes: The N-type crystalline silicon is placed in a tank cleaning machine for polishing and cleaning. The polishing solution in the tank cleaning machine includes KOH, H2O and polishing additives. The pyramid microstructure on the back of the N-type crystalline silicon is etched away. The reaction temperature is 70±20℃ and the reaction time is 250±100s, so that the back of the N-type crystalline silicon forms a plane.

[0008] Furthermore, the step of sequentially fabricating a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of the N-type crystalline silicon, and then subjecting the intrinsic polycrystalline silicon layer to phosphorus diffusion treatment to form an N-type doped layer, includes: Two N-type crystalline silicon wafers are attached face-to-face and inserted into a quartz boat. The quartz boat is then placed in a phosphorus diffusion furnace for phosphorus diffusion treatment. The reaction source in the phosphorus diffusion furnace includes POCl3, O2, and N2, with a sheet resistance of 360±80Ω / sq. Due to the phosphorus diffusion treatment, the thickness of the phosphorus-silicon glass layer formed is 35±10nm, the reaction temperature is 870±40℃, and the reaction time is 115±10min, thus forming an N-type doped layer from the intrinsic polycrystalline silicon layer.

[0009] Furthermore, the step of dividing the back surface of the N-type crystalline silicon into a positive electrode region and a negative electrode region, and using laser ablation to remove the tunneling oxide layer and N-type doped layer located in the positive electrode region, includes: An N-type crystalline silicon with the N-type doped layer is placed in a laser, and the phosphorosilicate glass layer in the positive electrode region is removed by laser ablation. After laser ablation treatment, N-type crystalline silicon is placed in a chain hydrofluoric acid cleaning machine with the back side of the N-type crystalline silicon facing upwards. The front side of the N-type crystalline silicon contacts the rollers of the chain hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the phosphosilicate glass layer located on the front side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 30±10%, and the speed of the rollers is 4±1m / min. The N-type crystalline silicon, after being etched with hydrofluoric acid solution, is placed in a tank cleaning machine. It first enters a polishing tank where an alkaline solution is used to etch the N-type doped layer and tunneling oxide layer located on the front side and the positive electrode region of the N-type crystalline silicon. The alkaline solution in the polishing tank includes KOH, H2O and polishing additives. The reaction temperature is 70±10℃ and the reaction time is 300±100s. The alkaline-washed N-type crystalline silicon is then placed in an acid tank to etch the residual phosphosilicate glass layer located on the front and back sides of the N-type crystalline silicon. The acid solution in the acid tank includes HF and H2O. The reaction temperature is room temperature and the reaction time is 220±40s.

[0010] Furthermore, the step of sequentially fabricating an aluminum oxide layer and a silicon nitride layer on the front side of the N-type crystalline silicon includes: The N-type crystalline silicon is placed in an atomic layer deposition apparatus to form an alumina layer on the front and back sides of the N-type crystalline silicon. The reaction gases include TMA, H2O, O3, and N2. The thickness of the alumina layer is 8±2 nm, the reaction temperature is 220±40℃, and the reaction time is 45±4 min. N-type crystalline silicon with the aforementioned alumina layer was placed in a tubular plasma-enhanced chemical vapor deposition furnace. A silicon nitride layer was fabricated on the front side of the N-type crystalline silicon. The furnace was filled with a reactive gas comprising SiH4, NH3, N2O, and N2. The reaction temperature was 500±40℃, and the reaction time was 60±4 min. The thickness of the fabricated silicon nitride layer was 160±20 nm, and the refractive index was 1.8±0.2%. An N-type crystalline silicon with the alumina layer and the silicon nitride layer is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards and the back side of the N-type crystalline silicon in contact with the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the alumina layer and the silicon nitride layer located on the back side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 20±4%, the reaction temperature is room temperature, and the speed of the rollers is 3±0.4 m / min. The N-type crystalline silicon etched with hydrofluoric acid solution is placed in a tank cleaning machine and then sequentially enters tank SC1 and tank SC2 for RCA cleaning to remove residual organic dirt and metal ions. The solution in tank SC1 mainly includes KOH, H2O2, and H2O, while the solution in tank SC2 includes HCl, H2O2, and H2O. The reaction temperature is 55±10℃ and the reaction time is 200±20s.

[0011] Furthermore, the step of creating openings in the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer within the negative electrode region, the openings exposing the N-type doped layer, includes: An opening is created by laser ablation of the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer in the negative electrode region; The N-type crystalline silicon with the opening made is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards and the back side of the N-type crystalline silicon contacting the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the silicon oxide layer formed on the surface of the N-type doped layer due to laser ablation. The concentration of the hydrofluoric acid solution is 5±1%, the reaction temperature is room temperature, and the speed of the rollers is 4.5±1m / min.

[0012] Further, the step of depositing a transparent conductive film on the back side of the N-type crystalline silicon, etching away the transparent conductive film located at the junction of the positive electrode region and the negative electrode region, forming a first transparent conductive layer in the negative electrode region, and forming a second transparent conductive layer in the positive electrode region, includes: The thickness of the transparent conductive film is 100±20nm, the sheet resistance is 50±20Ω / sq, the reaction temperature is 160±20℃, and the reaction time is 300±40s. The transparent conductive film located at the junction of the positive and negative electrode regions is removed by etching with acidic etching paste. A first transparent conductive layer is formed in the negative electrode region, and a second transparent conductive layer is formed in the positive electrode region. The width at the junction of the positive and negative electrode regions is 120±20um. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s. After the N-type crystalline silicon is printed with etching paste, it is placed in a tank cleaning machine and the residual acidic etching paste is cleaned with SC1 solution, which includes KOH, H2O2 and H2O. The reaction temperature is 35±10℃ and the reaction time is 150±20s.

[0013] This application also provides a back-contact solar cell structure, which is manufactured using the manufacturing method for the back-contact solar cell structure described above, and the back-contact solar cell structure includes: N-type crystalline silicon, wherein the front side of the N-type crystalline silicon has a pyramidal microstructure, the back side of the N-type crystalline silicon is a plane, and the back side of the N-type crystalline silicon is divided into a positive electrode region and a negative electrode region; An aluminum oxide layer is disposed on the front side of the N-type crystalline silicon; A silicon nitride layer is disposed on the aluminum oxide layer; A tunneling oxide layer is disposed in the negative electrode region and located below the back surface of the N-type crystalline silicon; An N-type doped layer is disposed in the negative electrode region and located below the tunneling oxide layer; The intrinsic amorphous silicon layer is partially located below the N-type doped layer in the negative electrode region, and partially located below the back surface of the N-type crystalline silicon in the positive electrode region. A boron-doped amorphous silicon layer is disposed below the intrinsic amorphous silicon layer; wherein the boron-doped amorphous silicon layer and the intrinsic amorphous silicon layer located in the negative electrode region are provided with openings; A first transparent conductive layer is disposed below the boron-doped amorphous silicon layer in the negative electrode region and is connected to the N-type doped layer through the opening; A second transparent conductive layer is disposed beneath the boron-doped amorphous silicon layer within the positive electrode region; The negative electrode fine grid line is disposed below the first transparent conductive layer; The positive electrode fine gate line is disposed under the second transparent conductive layer.

[0014] The technical advantages of this application compared to the prior art are as follows: In the back contact solar cell structure of this application, the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer in the positive electrode region are disposed on a plane, while in the existing back contact solar cell structure, the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer in the positive electrode region are disposed on a textured pyramid structure, resulting in better passivation effect, while reducing the metal ion content in the silicon substrate of the cell, reducing cell recombination, and improving cell efficiency. Attached Figure Description

[0015] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of the back-contact solar cell structure provided in the embodiments of this application; Figure 2 A schematic diagram of the back-contact solar cell structure provided in this application; Figure 3 This is a schematic diagram of the metallization scheme for the embodiments and comparative examples.

[0017] The markings in the diagram are as follows: 1. N-type crystalline silicon, 111. Pyramid microstructure, 112. Positive electrode region, 113. Negative electrode region, 2. Tunneling oxide layer, 3. N-type doped layer, 4. Alumina layer, 5. Silicon nitride layer, 6. Intrinsic amorphous silicon layer, 7. Boron-doped amorphous silicon layer, 8. First transparent conductive layer, 9. Second transparent conductive layer, 10. Main gate line, 11. Negative electrode fine gate line, 12. Positive electrode fine gate line. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0021] Please see Figure 1 This application provides a back-contact solar cell structure and its manufacturing method, including: An N-type crystalline silicon 1 is provided, and a pyramidal microstructure 111 is fabricated by texturing and cleaning the front and back sides of the N-type crystalline silicon 1. A heavily doped phosphosilicate glass layer is fabricated on the front side of the N-type crystalline silicon 1, and the heavily doped phosphosilicate glass layer located on the back side of the N-type crystalline silicon is etched away. The pyramidal microstructure 111 located on the back side of the N-type crystalline silicon 1 is etched away, so that the back side of the N-type crystalline silicon 1 is formed into a plane; A tunneling oxide layer 2 (SiO2) and an intrinsic polycrystalline silicon layer (poly) are sequentially fabricated on the back side of the N-type crystalline silicon 1, and the intrinsic polycrystalline silicon layer is subjected to phosphorus diffusion treatment to form an N-type doped layer 3. The back side of the N-type crystalline silicon 1 is divided into a positive electrode region 112 and a negative electrode region 113. The tunneling oxide layer 2 (SiO2) and the N-type doped layer 3 located in the positive electrode region 112 are removed by laser ablation. Etching removes the phosphorosilicate glass (PSG) layer formed by phosphorus diffusion treatment. An aluminum oxide layer 4 and a silicon nitride layer 5 are sequentially formed on the front side of the N-type crystalline silicon 1; An intrinsic amorphous silicon layer 6 (i layer) and a boron-doped amorphous silicon layer 7 (P layer) are sequentially fabricated on the back side of the N-type crystalline silicon 1. An opening is made in the intrinsic amorphous silicon layer 6 and the boron-doped amorphous silicon layer 7 within the negative electrode region 113, and the opening exposes the N-type doped layer 3. A transparent conductive film is deposited on the back side of the N-type crystalline silicon 1, and the transparent conductive film located at the junction of the positive electrode region 112 and the negative electrode region 113 is etched away. A first transparent conductive layer 8 is formed in the negative electrode region 113, and a second transparent conductive layer 9 is formed in the positive electrode region 112. Negative electrode fine grid line 11 and positive electrode fine grid line 12 are respectively fabricated under the first transparent conductive layer 8 and the second transparent conductive layer 9.

[0022] The intrinsic amorphous silicon layer 6 has a thickness of 8±2 nm, the boron-doped amorphous silicon layer 7 has a thickness of 20±4 nm, the reaction temperature is 200±20℃, and the reaction time is 400±40 s.

[0023] The negative electrode fine grid line 11 and the positive electrode fine grid line 12 are obtained by printing metal paste, drying it, and then performing photoinjection. Finally, electrical performance testing (IV testing) and sorting are carried out. The width of the negative electrode fine grid line 11 is 80±40um, the width of the positive electrode fine grid line 12 is 80±40um, the reaction temperature is room temperature, and the reaction time is 0.85±0.1s.

[0024] Furthermore, the provision of N-type crystalline silicon 1, and the texturing and cleaning of the front and back sides of the N-type crystalline silicon 1 to fabricate a pyramidal microstructure 111, includes: The N-type crystalline silicon 1 is placed in a tank cleaning machine and texturing cleaning is performed using a texturing solution, which includes KOH, H2O and texturing additives. The reaction temperature for texturing cleaning is 80±20℃ and the reaction time is 600±200s, forming a pyramidal microstructure 111 on the front and back sides of the N-type crystalline silicon 1.

[0025] Furthermore, the step of fabricating a heavily doped phosphosilicate glass layer on the front side of the N-type crystalline silicon 1 and etching away the heavily doped phosphosilicate glass layer located on the back side of the N-type crystalline silicon includes: The texturized N-type crystalline silicon is placed in a phosphorus diffusion furnace. The back sides of two N-type crystalline silicon wafers are then attached together and inserted into a quartz boat for phosphorus diffusion treatment. The reaction source in the phosphorus diffusion furnace includes POCl3, O2, and N2, with a sheet resistance of 20±2Ω / sq. The thickness of the phosphorus silicon glass layer formed by the phosphorus diffusion treatment is 50±5nm, the reaction temperature is 900±20℃, and the reaction time is 130±5min. A heavily doped phosphorus silicon glass layer is formed on the front side of the N-type crystalline silicon. After diffusion of elemental phosphorus, N-type crystalline silicon is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards. The back side of the N-type crystalline silicon contacts the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the heavily doped phosphorus silicon glass layer located on the back side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 20±5%, the reaction temperature is room temperature, and the speed of the rollers is 4±1 m / min.

[0026] Furthermore, the etching and removal of the pyramidal microstructure 111 located on the back side of the N-type crystalline silicon 1, so that the back side of the N-type crystalline silicon 1 forms a plane, includes: The N-type crystalline silicon 1 is placed in a tank cleaning machine for polishing and cleaning. The polishing solution in the tank cleaning machine includes KOH, H2O and polishing additives. The pyramid microstructure 111 located on the back side of the N-type crystalline silicon 1 is etched away. The reaction temperature is 70±20℃ and the reaction time is 250±100s, so that the back side of the N-type crystalline silicon 1 is formed into a plane.

[0027] Furthermore, the step of sequentially fabricating a tunneling oxide layer 2 and an intrinsic polycrystalline silicon layer on the back side of the N-type crystalline silicon 1, and then subjecting the intrinsic polycrystalline silicon layer to phosphorus diffusion treatment to form an N-type doped layer 3, includes: Two N-type crystalline silicon wafers 1 are attached face-to-face and inserted into a quartz boat. The quartz boat is then placed in a phosphorus diffusion furnace for phosphorus diffusion treatment. The reaction source in the phosphorus diffusion furnace includes POCl3, O2, and N2, with a sheet resistance of 360±80Ω / sq. The thickness of the phosphorus silicon glass layer formed by the phosphorus diffusion treatment is 35±10nm, the reaction temperature is 870±40℃, and the reaction time is 115±10min, thus forming an N-type doped layer 3 from the intrinsic polycrystalline silicon layer.

[0028] Furthermore, the step of dividing the back side of the N-type crystalline silicon 1 into a positive electrode region 112 and a negative electrode region 113, and removing the tunneling oxide layer 2 and the N-type doped layer 3 located in the positive electrode region 112 by laser ablation includes: An N-type crystalline silicon 1 with the N-type doped layer 3 is placed in a laser, and the phosphorosilicon glass layer of the positive electrode region 112 is removed by laser ablation. The N-type crystalline silicon 1 after laser ablation treatment is placed in a chain hydrofluoric acid cleaning machine with the back side of the N-type crystalline silicon 1 facing upwards. The front side of the N-type crystalline silicon 1 contacts the rollers of the chain hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the phosphosilicate glass layer located on the front side and surrounding area of ​​the N-type crystalline silicon 1. The concentration of the hydrofluoric acid solution is 30±10%, and the speed of the rollers is 4±1m / min. The N-type crystalline silicon 1, after being etched with hydrofluoric acid solution, is placed in a tank cleaning machine. It first enters a polishing tank where an alkaline solution is used to etch the N-type doped layer 3 and tunneling oxide layer 2 located on the front side of the N-type crystalline silicon 1 and the positive electrode region 112. The alkaline solution in the polishing tank includes KOH, H2O and polishing additives. The reaction temperature is 70±10℃ and the reaction time is 300±100s. The alkaline-washed N-type crystalline silicon 1 is then placed in an acid tank to etch the residual phosphosilicate glass layer located on the front and back sides of the N-type crystalline silicon 1. The acid solution in the acid tank includes HF and H2O. The reaction temperature is room temperature and the reaction time is 220±40s.

[0029] Furthermore, the step of sequentially fabricating an aluminum oxide layer 4 and a silicon nitride layer 5 on the front side of the N-type crystalline silicon 1 includes: The N-type crystalline silicon 1 is placed in an atomic layer deposition apparatus, and an alumina layer 4 is formed on the front and back sides of the N-type crystalline silicon 1. The reaction special gases include TMA, H2O, O3, and N2. The thickness of the alumina layer 4 is 8±2 nm, the reaction temperature is 220±40℃, and the reaction time is 45±4 min. An N-type crystalline silicon 1 with the alumina layer 4 is placed in a tubular plasma-enhanced chemical vapor deposition furnace. A silicon nitride layer 5 is formed on the front side of the N-type crystalline silicon. A reaction gas, including SiH4, NH3, N2O, and N2, is introduced. The reaction temperature is 500±40℃, and the reaction time is 60±4min. The thickness of the formed silicon nitride layer 5 is 160±20nm, and the refractive index is 1.8±0.2%. An N-type crystalline silicon 1 having the alumina layer 4 and the silicon nitride layer 5 is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon 1 facing upwards and the back side of the N-type crystalline silicon 1 in contact with the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the alumina layer 4 and the silicon nitride layer 5 located on the back side and surrounding area of ​​the N-type crystalline silicon 1. The concentration of the hydrofluoric acid solution is 20±4%, the reaction temperature is room temperature, and the speed of the rollers is 3±0.4 m / min. The N-type crystalline silicon 1 etched with hydrofluoric acid solution is placed in a tank cleaning machine and successively enters tank SC1 and tank SC2 for RCA cleaning to remove residual organic dirt and metal ions. The chemical solution in tank SC1 mainly includes KOH, H2O2 and H2O, and the chemical solution in tank SC2 includes HCl, H2O2 and H2O. The reaction temperature is 55±10℃ and the reaction time is 200±20s.

[0030] Furthermore, the process of creating openings in the intrinsic amorphous silicon layer 6 and the boron-doped amorphous silicon layer 7 within the negative electrode region 113, exposing the N-type doped layer 3, includes: An opening is created by laser ablation of the intrinsic amorphous silicon layer 6 and the boron-doped amorphous silicon layer 7 within the negative electrode region 113; The N-type crystalline silicon 1 with the opening made is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon 1 facing upwards and the back side of the N-type crystalline silicon 1 in contact with the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the silicon oxide layer formed on the surface of the N-type doped layer 3 due to laser ablation. The concentration of the hydrofluoric acid solution is 5±1%, the reaction temperature is room temperature, and the speed of the rollers is 4.5±1m / min.

[0031] Further, the step of depositing a transparent conductive film (ITO layer) on the back side of the N-type crystalline silicon 1, etching away the transparent conductive film located at the junction of the positive electrode region 112 and the negative electrode region 113, forming a first transparent conductive layer 8 in the negative electrode region 113, and forming a second transparent conductive layer 9 in the positive electrode region 112 includes: The thickness of the transparent conductive film is 100±20nm, the sheet resistance is 50±20Ω / sq, the reaction temperature is 160±20℃, and the reaction time is 300±40s. The transparent conductive film located at the junction of the positive electrode region 112 and the negative electrode region 113 is removed by etching with acidic etching paste. A first transparent conductive layer 8 is formed in the negative electrode region 113, and a second transparent conductive layer 9 is formed in the positive electrode region 112. The width at the junction of the positive electrode region 112 and the negative electrode region 113 is 120±20um. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s. After the N-type crystalline silicon 1 is printed with etching paste, it is placed in a tank cleaning machine and the residual acidic etching paste is cleaned with SC1 solution, which includes KOH, H2O2 and H2O. The reaction temperature is 35±10℃ and the reaction time is 150±20s.

[0032] like Figure 1 As shown, this application also provides a back-contact solar cell structure, which is manufactured using the manufacturing method for the back-contact solar cell structure described above. The back-contact solar cell structure includes: N-type crystalline silicon 1, the front side of the N-type crystalline silicon 1 has a pyramidal microstructure 111, the back side of the N-type crystalline silicon 1 is a plane, and the back side of the N-type crystalline silicon 1 is divided into a positive electrode region 112 and a negative electrode region 113. An aluminum oxide layer 4 is disposed on the front side of the N-type crystalline silicon 1; A silicon nitride layer 5 is disposed on the aluminum oxide layer 4; The tunneling oxide layer 2 is disposed within the negative electrode region 113 and located below the back surface of the N-type crystalline silicon 1; An N-type doped layer 3 is disposed within the negative electrode region 113 and located below the tunneling oxide layer 2; The intrinsic amorphous silicon layer 6 is partially located below the N-type doped layer 3 of the negative electrode region 113, and partially located below the back side of the N-type crystalline silicon 1 of the positive electrode region 112. A boron-doped amorphous silicon layer 7 is disposed below the intrinsic amorphous silicon layer 6; wherein the boron-doped amorphous silicon layer 7 and the intrinsic amorphous silicon layer 6 located in the negative electrode region 113 are provided with openings; A first transparent conductive layer 8 is disposed below the boron-doped amorphous silicon layer 7 within the negative electrode region 113 and is connected to the N-type doped layer 3 through the opening; The second transparent conductive layer 9 is disposed beneath the boron-doped amorphous silicon layer 7 within the positive electrode region 112; The negative electrode fine grid line 11 is disposed below the first transparent conductive layer 8; The positive electrode fine grid line 12 is disposed below the second transparent conductive layer 9.

[0033] In the back-contact solar cell structure of the above embodiments of this application, the intrinsic amorphous silicon layer 6 and the boron-doped amorphous silicon layer 7 in the positive electrode region 112 are disposed on a plane, which is different from the intrinsic amorphous silicon layer 6 and the boron-doped amorphous silicon layer 7 in the existing back-contact solar cell structure, which are disposed on a textured pyramid structure. This results in better passivation effect, while reducing the metal ion content in the silicon substrate of the cell, reducing cell recombination, and improving cell efficiency.

[0034] The existing back-contact solar cell structure is used as a comparative example to verify the above-mentioned technical effects by comparing it with the back-contact solar cell structure of the present application embodiment.

[0035] Please see Figure 1 The method for fabricating a back-contact solar cell structure according to an embodiment of this application includes: N-type bare silicon wafers (c-Si) are placed in a tank cleaning machine for texturing cleaning. This process removes the mechanically damaged layer of the silicon wafer while cleaning it, and forms a pyramidal microstructure 111 on both sides of the wafer. This light-trapping structure significantly reduces the reflectivity of the silicon wafer. The process parameters are: reflectivity 10±2%, weight reduction 0.4±0.1g. The reaction solution is a texturing solution, whose main components are KOH, H2O, and texturing additives. These materials are standard materials commonly used in the photovoltaic industry. The process reaction temperature is 80±20℃, and the reaction time is 600±200s.

[0036] After the previous process, the silicon wafers are placed in a phosphorus diffusion furnace, with two wafers inserted back-to-back into a quartz boat for phosphorus diffusion. This forms a heavily doped PSG layer on the silicon wafer surface. Based on the segregation coefficient characteristics of metal ions, they are more easily enriched in PSG than in the silicon substrate. During the actual diffusion process, metal ions migrate to the surface PSG layer. The main reaction sources are POCl3, O2, and N2. Process parameters: sheet resistance: 20±2Ω / sq, PSG thickness: 50±5nm. Process reaction temperature: 900±20℃, process time: 130±5min.

[0037] The phosphorus-diffused silicon wafers are placed in a chain-type HF acid cleaning machine, with the front side facing up and the back side in contact with the rollers for transmission. A layer of PSG has been deposited on the back side of the wafer in the previous process. The chain-type machine rollers, carrying liquid HF solution, etch the aforementioned PSG layer. Process parameters: no PSG residue on the back side, no over-etching on the front side. HF acid concentration: 20±5%, process temperature: room temperature, machine belt speed: 4±0.5 m / min.

[0038] After the previous process, the silicon wafer is placed in a tank cleaning machine for polishing and cleaning. The polishing solution mainly consists of KOH, H2O, and polishing additives. Since PSG does not react with KOH, only the exposed silicon substrate on the back reacts with the polishing solution, thus etching the textured pyramid structure on the back into a smooth silicon surface. Process parameters: reflectivity 40±2%, weight reduction 0.3±0.05g. Process reaction temperature 70±10℃, process time 250±50s.

[0039] After the previous process, the silicon wafers are placed in an LPCVD furnace, with two wafers side-by-side inserted into a quartz boat. A tunneling oxide layer (SiO2) is first deposited on the back of the wafer, followed by an intrinsic polycrystalline silicon layer (poly). The main reactant gases are SiH4, O2, and N2. These are standard materials. Process parameters: SiO2 thickness 1.4±0.1nm, poly thickness 120±10nm. Process reaction temperature 600±20℃, process time 120±5min.

[0040] The silicon wafer, after the previous process, is placed in a laser. Based on the cell pattern design, the PSG layer above the P-region on the back of the cell is removed using laser ablation. Process specifications: P-region width 520±30µm, no PSG residue in the reaction area, and no burrs on the laser spot. The process is performed at room temperature, and the reaction time per wafer is calculated based on the cell pattern, laser spot size, and laser rate.

[0041] The laser-treated silicon wafer is placed in a chain-type HF acid cleaning machine with the back side facing up and the front side in contact with the rollers for transmission. A layer of PSG (phosphorus silicon glass) is deposited around the perimeter of the front side of the wafer. The chain-type machine rollers carry liquid HF solution to etch the PSG layer. Process parameters: no PSG residue on the front side, no over-etching on the back side. HF acid concentration: 30±10%, machine speed: 4.5±1 m / min.

[0042] After the previous process, the silicon wafer is placed in a tank cleaning machine, first entering the polishing tank. The main components of the solution are KOH, H2O, and polishing additives. The purpose is to use the alkaline solution to etch the N-poly layer on the front side and the N-type doped layer 3 (Npoly) in the positive electrode region 112 on the back side. Process parameters: no Npoly residue, reaction temperature 70±10℃, reaction time 300±100s. After alkaline cleaning, the silicon wafer enters the acid tank. The main components of the solution are HF and H2O. The purpose is to use HF acid to etch the SiNx layer on the front side and the residual PSG layer on the back side. Process parameters: no SiNx or PSG residue, reaction temperature room temperature, reaction time 220±40s.

[0043] The silicon wafer after the previous process is placed in the ALD equipment, and an AlOx thin film is deposited simultaneously on both sides of the silicon wafer as an alumina layer 4. The main reactive gases are: TMA, H2O, O3, and N2. Process parameters: AlOx film thickness 8±2nm. Reaction temperature: 220±40℃, reaction time 45±4min.

[0044] The silicon wafer after ALD is placed in a tube-type PECVD furnace, and a layer of SiNx is deposited on the front side of the silicon wafer as a silicon nitride antireflection layer 5. The main reactive gases are: SiH4, NH3, N2O, and N2. The above-mentioned specialty gases are conventional standard materials. Process parameters: SiNx film thickness 160±20nm, refractive index 1.8±0.2%. Process reaction temperature 500±40℃, reaction time 60±4min.

[0045] The silicon wafers coated with SiNx are placed into a chain-type HF acid cleaning machine, with the front side facing up and the back side in contact with the rollers for transmission. A layer of SiNx has been deposited around the perimeter of the back side of the wafer during the previous process. The chain-type machine rollers, carrying HF solution, etch the aforementioned SiNx layer and the underlying AlOx layer. Process parameters: No SiNx or AlOx residue on the back side, no over-etching on the front side. HF acid concentration: 20±4%, reaction temperature: room temperature, machine speed: 3±0.4 m / min.

[0046] After the previous process, the silicon wafers are placed in a tank-type cleaning machine for RCA cleaning. The purpose is to clean the silicon wafers and remove any residual organic dirt and metal ions from their surface. The silicon wafers are sequentially placed in SC1 and SC2 tanks for cleaning. The main components of the SC1 cleaning solution are KOH, H2O2, and H2O, while the main components of the SC2 cleaning solution are HCl, H2O2, and H2O. Process parameters: No abnormalities in appearance. Reaction temperature: 55±10℃, reaction time: 200±20s.

[0047] The silicon wafer after the previous process is placed in a plate CVD machine. An intrinsic amorphous silicon layer 6 (i layer) is first deposited on the back side of the silicon wafer, and then a boron-doped amorphous silicon layer 7 (P layer) is deposited on the i layer. Process parameters: i layer thickness 8±2nm, P layer thickness 20±4nm. Reaction temperature: 200±20℃, reaction time 400±40s.

[0048] The CVD-processed silicon wafer is placed in a laser, and the IP layer above the N-poly region of the cell is removed by laser ablation according to the cell pattern design. Process specifications: laser aperture width 150±20µm, no IP layer residue in the reaction area, and no burrs on the laser spot. The process is carried out at room temperature, and the reaction time per wafer is calculated based on the cell pattern, spot size, and rate.

[0049] The laser-processed silicon wafer is placed in a chain-type HF acid cleaning machine with the front side facing up and the back side in contact with the rollers for transmission. After the previous laser process, a SiO2 thin film will grow on the Npoly surface. The chain-type machine rollers carry liquid HF solution to etch the SiO2 layer. Process parameters: no SiO2 residue on the back side, no over-etching on the front side. HF acid concentration: 5±1%, reaction temperature: room temperature, machine belt speed: 4.5±1 m / min.

[0050] The silicon wafer after the previous process is placed in a PVD apparatus, and a transparent conductive film (ITO layer) is deposited on the back of the silicon wafer. The process parameters are: film thickness 100±20nm, sheet resistance 50±20Ω / sq. The reaction temperature is 160±20℃, and the reaction time is 300±40s.

[0051] The silicon wafer after the previous process is placed in a screen printing machine. A screen pattern is designed based on the cell pattern, and etching paste is printed on the back of the wafer. The etching paste is acidic and will etch away the ITO layer. The area where the etching paste is printed is the boundary between the N-region and the P-region. Process parameters: linewidth (aperture width) 120±20um, no broken grids. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s.

[0052] After the etching paste is printed, the silicon wafer is placed in a tank cleaning machine. Residual etching paste is cleaned using SC1 solution. The main components of SC1 solution are KOH, H2O2, and H2O. Process parameters: no etching paste residue, no abnormal appearance. Reaction temperature: 35±10℃, reaction time: 150±20s.

[0053] The cleaned silicon wafer is placed in a screen printing machine. A screen pattern is designed based on the battery pattern. Metal paste is then printed on the back of the silicon wafer for main grid lines 10, negative electrode fine grid lines 11, and positive electrode fine grid lines 12. The process parameters are: main grid line 10 width 500±100µm, negative electrode fine grid lines 11 and positive electrode fine grid lines 12 width 80±40µm, with no grid breaks. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s.

[0054] After screen printing, the silicon wafers enter a chain drying oven to dry the metal paste, then undergo photoinjection, and finally electrical performance testing (IV testing) and sorting.

[0055] Please see Figure 2 The comparative method for fabricating a back-contact solar cell structure includes: N-type bare silicon wafers are placed in a tank-type cleaning machine for polishing and cleaning. This removes mechanical damage to the wafers, cleans them, and creates a smooth microstructure on both sides. The process parameters are: reflectivity 40±2%, weight loss 0.45±0.1g. The reaction solution is a polishing solution, whose main components are KOH, H2O, and polishing additives. These materials are standard materials commonly used in the photovoltaic industry. The process reaction temperature is 80±10℃, and the reaction time is 200±40s.

[0056] After polishing, the silicon wafers are placed in an LPCVD furnace, with two wafers inserted side-by-side into a quartz boat. A tunneling oxide layer 2 (SiO2) is first deposited on the back of the wafer, followed by an intrinsic polycrystalline silicon layer (poly). The main reactant gases are SiH4, O2, and N2. These are standard materials. Process parameters: SiO2 thickness 1.4±0.2nm, poly thickness 120±20nm. Process reaction temperature 600±40℃, reaction time 120±10min.

[0057] After the previous process, the silicon wafers are placed in a phosphorus diffusion furnace, with two wafers inserted face-to-face into a quartz boat. The phosphorus generated in the reaction diffuses into the poly layer, forming an N-type poly layer. The main reaction sources are POCl3, O2, and N2. Process parameters: sheet resistance: 360±80 Ω / sq, phosphorus silicate glass (PSG) layer thickness: 35±10 nm. Process reaction temperature: 870±40℃, reaction time: 115±10 min.

[0058] Phosphorus-diffused silicon wafers are placed in a tube-type PECVD furnace, and a SiNx thin film is deposited on the back of the wafer as a silicon nitride protective layer. The main reacting gases are SiH4, NH3, N2O, and N2. These specialty gases are standard materials. Process parameters: SiNx film thickness 40±10nm, refractive index 2.0±0.2%. Process reaction temperature 500±40℃, reaction time 35±4min.

[0059] The silicon wafer, after the previous process, is placed in a laser. Based on the cell pattern design, the silicon nitride protective layer and phosphosilicate glass layer above the P-region on the back of the cell are removed using laser ablation. Process specifications: P-region width 520±30µm, no SiNx or PSG residue in the reaction area, and no burrs on the laser spot. The process is performed at room temperature, and the reaction time per wafer is calculated based on the cell pattern, laser spot size, and laser rate.

[0060] The laser-treated silicon wafer is placed in a chain-type HF acid cleaning machine with the back side facing up and the front side in contact with the rollers for transmission. A layer of PSG and SiNx thin films has been deposited around the perimeter of the front side of the wafer during the previous process. The chain-type machine rollers, carrying HF solution, etch the aforementioned PSG and SiNx layers. Process parameters: No PSG or SiNx residue on the front side, no over-etching on the back side. HF acid concentration: 35±10%, machine speed: 4.0±1 m / min.

[0061] The silicon wafers after the previous process are placed in a tank cleaning machine for texturing cleaning, forming a pyramidal microstructure 111 at the laser openings on the front and back of the wafer. Process parameters: reflectivity 11±2%, weight reduction 0.25±0.04g. The reaction solution is a texturing solution, its main components being KOH, H2O, and texturing additives; these materials are standard materials commonly used in the photovoltaic industry. The process reaction temperature is 80±10℃, and the reaction time is 600±100s. The texturized silicon wafers are then placed in an acid bath, the main components of which are HF and H2O. The purpose is to use HF acid to etch away any remaining SiNx and PSG layers on the back side. Process parameters: no SiNx or PSG residue; reaction temperature is room temperature, and reaction time is 220±40s.

[0062] The cleaned silicon wafer is placed in an ALD (Al₂O₃) device, where an AlO₂ thin film is deposited simultaneously on both sides of the wafer as an alumina layer 4. The main reactive gases are TMA, H₂O, O₃, and N₂. Process parameters: AlO₂ film thickness 8±2 nm. Reaction temperature: 220±40℃, reaction time 45±4 min.

[0063] The silicon wafer after ALD is placed in a tube-type PECVD furnace, and a layer of SiNx is deposited on the front side of the silicon wafer as a silicon nitride antireflection layer 5. The main reactive gases are: SiH4, NH3, N2O, and N2. The above-mentioned specialty gases are conventional standard materials. Process parameters: SiNx film thickness 160±20nm, refractive index 1.8±0.2%. Process reaction temperature 500±40℃, reaction time 60±4min.

[0064] The silicon wafers coated with SiNx are placed into a chain-type HF acid cleaning machine, with the front side facing up and the back side in contact with the rollers for transmission. A layer of SiNx has been deposited around the perimeter of the back side of the wafer during the previous process. The chain-type machine rollers, carrying HF solution, etch the aforementioned SiNx layer and the underlying AlOx layer. Process parameters: No SiNx or AlOx residue on the back side, no over-etching on the front side. HF acid concentration: 20±4%, reaction temperature: room temperature, machine speed: 3±0.4 m / min.

[0065] After the previous process, the silicon wafers are placed in a tank-type cleaning machine for RCA cleaning. The purpose is to clean the silicon wafers and remove any residual organic dirt and metal ions from their surface. The silicon wafers are sequentially placed in SC1 and SC2 tanks for cleaning. The main components of the SC1 cleaning solution are KOH, H2O2, and H2O, while the main components of the SC2 cleaning solution are HCl, H2O2, and H2O. Process parameters: No abnormalities in appearance. Reaction temperature: 55±10℃, reaction time: 200±20s.

[0066] The silicon wafer after the previous process is placed in a plate CVD machine. An intrinsic amorphous silicon layer 6 (i layer) is first deposited on the back side of the silicon wafer, and then a boron-doped amorphous silicon layer 7 (P layer) is deposited on the i layer. Process parameters: i layer thickness 8±2nm, P layer thickness 20±4nm. Reaction temperature: 200±20℃, reaction time 400±40s.

[0067] The CVD-processed silicon wafer is placed in a laser, and the IP layer above the N-poly region of the cell is removed by laser ablation according to the cell pattern design. Process specifications: laser aperture width 150±20µm, no IP layer residue in the reaction area, and no burrs on the laser spot. The process is carried out at room temperature, and the reaction time per wafer is calculated based on the cell pattern, spot size, and rate.

[0068] The laser-processed silicon wafer is placed in a chain-type HF acid cleaning machine with the front side facing up and the back side in contact with the rollers for transmission. After the previous laser process, a SiO2 thin film will grow on the Npoly surface. The chain-type machine rollers carry liquid HF solution to etch the SiO2 layer. Process parameters: no SiO2 residue on the back side, no over-etching on the front side. HF acid concentration: 5±1%, reaction temperature: room temperature, machine belt speed: 4.5±1 m / min.

[0069] The silicon wafer after the previous process is placed in a PVD apparatus, and a transparent conductive film (ITO layer) is deposited on the back of the silicon wafer. The process parameters are: film thickness 100±20nm, sheet resistance 50±20Ω / sq. The reaction temperature is 160±20℃, and the reaction time is 300±40s.

[0070] The silicon wafer after the previous process is placed in a screen printing machine. A screen pattern is designed based on the cell pattern, and etching paste is printed on the back of the wafer. The etching paste is acidic and will etch away the ITO layer. The area where the etching paste is printed is the boundary between the N-region and the P-region. Process parameters: linewidth (aperture width) 120±20um, no broken grids. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s.

[0071] After the etching paste is printed, the silicon wafer is placed in a tank cleaning machine. Residual etching paste is cleaned using SC1 solution. The main components of SC1 solution are KOH, H2O2, and H2O. Process parameters: no etching paste residue, no abnormal appearance. Reaction temperature: 35±10℃, reaction time: 150±20s.

[0072] The cleaned silicon wafer is placed in a screen printing machine. A screen pattern is designed based on the battery pattern. Metal paste is then printed on the back of the silicon wafer for main grid lines 10, negative electrode fine grid lines 11, and positive electrode fine grid lines 12. The process parameters are: main grid line 10 width 500±100µm, negative electrode fine grid lines 11 and positive electrode fine grid lines 12 width 80±40µm, with no grid breaks. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s.

[0073] After screen printing, the silicon wafers enter a chain drying oven to dry the metal paste, then undergo photoinjection, and finally electrical performance testing (IV testing) and sorting.

[0074] Figure 3 This is a schematic diagram of the metallization scheme for the embodiments and comparative examples. The difference between the embodiments and the comparative examples is that in this application, the pyramidal shape of the silicon surface in the P-region of the HTBC cell in the comparative example is transformed into a polished plane. The IP layer is deposited on a flat silicon surface, resulting in better passivation. At the same time, the gettering effect of phosphorus diffusion is utilized to further reduce the metal ion content in the silicon wafer, which can further improve the open-circuit voltage of the cell, thereby improving the cell conversion efficiency and achieving higher economic value. In addition, the embodiments use PSG instead of SiNx as the mask, reducing one coating step, reducing equipment investment and floor space, and further reducing the cell manufacturing cost.

[0075] Table 1 shows the electrical performance comparison data of the batteries from the same batch of examples and comparative examples: Table 1 The table above shows that, compared with the comparative example, the battery open-circuit voltage of the embodiments of the present invention is increased by 5mV and the battery efficiency is increased by 0.22%abs, which has significant experimental effects and economic value.

[0076] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0077] The foregoing has provided a detailed description of a back-contact solar cell structure and its manufacturing method according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for manufacturing a back-contact solar cell structure, characterized in that, include: N-type crystalline silicon is provided, and a pyramid microstructure is fabricated by texturing and cleaning the front and back sides of the N-type crystalline silicon. A heavily doped phosphosilicate glass layer is fabricated on the front side of the N-type crystalline silicon, and the heavily doped phosphosilicate glass layer located on the back side of the N-type crystalline silicon is etched away. The pyramidal microstructure located on the back side of the N-type crystalline silicon is etched away, so that the back side of the N-type crystalline silicon forms a plane; A tunneling oxide layer and an intrinsic polycrystalline silicon layer are sequentially fabricated on the back side of the N-type crystalline silicon, and the intrinsic polycrystalline silicon layer is subjected to phosphorus diffusion treatment to form an N-type doped layer. The back side of the N-type crystalline silicon is divided into a positive electrode region and a negative electrode region. The tunneling oxide layer and N-type doped layer located in the positive electrode region are removed by laser ablation. Etching removes the phosphorus silica glass layer formed by phosphorus diffusion treatment; An aluminum oxide layer and a silicon nitride layer are sequentially fabricated on the front side of the N-type crystalline silicon. An intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer are sequentially fabricated on the back side of the N-type crystalline silicon. An opening is made in the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer in the negative electrode region, and the opening exposes the N-type doped layer. A transparent conductive film is deposited on the back side of the N-type crystalline silicon, and the transparent conductive film located at the junction of the positive electrode region and the negative electrode region is etched away. A first transparent conductive layer is formed in the negative electrode region, and a second transparent conductive layer is formed in the positive electrode region. Negative electrode fine grid lines and positive electrode fine grid lines are fabricated under the first transparent conductive layer and the second transparent conductive layer, respectively.

2. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The provision of N-type crystalline silicon, and the texturing and cleaning of the front and back sides of the N-type crystalline silicon to create a pyramidal microstructure, includes: The N-type crystalline silicon is placed in a tank cleaning machine and texturing cleaning is performed using a texturing solution, which includes KOH, H2O and texturing additives. The reaction temperature for texturing cleaning is 80±20℃ and the reaction time is 600±200s, forming a pyramid microstructure on the front and back sides of the N-type crystalline silicon.

3. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The process of fabricating a heavily doped phosphosilicate glass layer on the front side of the N-type crystalline silicon and etching away the heavily doped phosphosilicate glass layer on the back side of the N-type crystalline silicon includes: The texturized N-type crystalline silicon is placed in a phosphorus diffusion furnace. The back sides of two N-type crystalline silicon wafers are then attached together and inserted into a quartz boat for phosphorus diffusion treatment. The reaction source in the phosphorus diffusion furnace includes POCl3, O2, and N2, with a sheet resistance of 20±2Ω / sq. The thickness of the phosphorus silicon glass layer formed by the phosphorus diffusion treatment is 50±5nm, the reaction temperature is 900±20℃, and the reaction time is 130±5min. A heavily doped phosphorus silicon glass layer is formed on the front side of the N-type crystalline silicon. After diffusion of elemental phosphorus, N-type crystalline silicon is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards. The back side of the N-type crystalline silicon contacts the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the heavily doped phosphorus silicon glass layer located on the back side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 20±5%, the reaction temperature is room temperature, and the speed of the rollers is 4±1 m / min.

4. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The etching and removal of the pyramidal microstructure located on the back side of the N-type crystalline silicon, thereby forming a plane on the back side of the N-type crystalline silicon, includes: The N-type crystalline silicon is placed in a tank cleaning machine for polishing and cleaning. The polishing solution in the tank cleaning machine includes KOH, H2O and polishing additives. The pyramid microstructure on the back of the N-type crystalline silicon is etched away. The reaction temperature is 70±20℃ and the reaction time is 250±100s, so that the back of the N-type crystalline silicon forms a plane.

5. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The process involves sequentially fabricating a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side of the N-type crystalline silicon, and then subjecting the intrinsic polycrystalline silicon layer to phosphorus diffusion treatment to form an N-type doped layer, including: Two N-type crystalline silicon wafers are attached face-to-face and inserted into a quartz boat. The quartz boat is then placed in a phosphorus diffusion furnace for phosphorus diffusion treatment. The reaction source in the phosphorus diffusion furnace includes POCl3, O2, and N2, with a sheet resistance of 360±80Ω / sq. Due to the phosphorus diffusion treatment, the thickness of the phosphorus-silicon glass layer formed is 35±10nm, the reaction temperature is 870±40℃, and the reaction time is 115±10min, thus forming an N-type doped layer from the intrinsic polycrystalline silicon layer.

6. The method for manufacturing a back-contact solar cell structure as described in claim 5, characterized in that, The step of dividing the back side of the N-type crystalline silicon into a positive electrode region and a negative electrode region, and removing the tunneling oxide layer and N-type doped layer located in the positive electrode region by laser ablation includes: An N-type crystalline silicon with the N-type doped layer is placed in a laser, and the phosphorosilicate glass layer in the positive electrode region is removed by laser ablation. After laser ablation treatment, N-type crystalline silicon is placed in a chain hydrofluoric acid cleaning machine with the back side of the N-type crystalline silicon facing upwards. The front side of the N-type crystalline silicon contacts the rollers of the chain hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the phosphosilicate glass layer located on the front side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 30±10%, and the speed of the rollers is 4±1m / min. The N-type crystalline silicon, after being etched with hydrofluoric acid solution, is placed in a tank cleaning machine. It first enters a polishing tank where an alkaline solution is used to etch the N-type doped layer located on the front side of the N-type crystalline silicon and the positive electrode region. The alkaline solution in the polishing tank includes KOH, H2O, and polishing additives. The reaction temperature is 70±10℃ and the reaction time is 300±100s. The alkaline-washed N-type crystalline silicon is then placed in an acid tank to etch the residual phosphosilicate glass layer located on the front and back sides of the N-type crystalline silicon. The acid solution in the acid tank includes HF and H2O. The reaction temperature is room temperature and the reaction time is 220±40s.

7. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The step of sequentially fabricating an aluminum oxide layer and a silicon nitride layer on the front side of the N-type crystalline silicon includes: The N-type crystalline silicon is placed in an atomic layer deposition apparatus to form an alumina layer on the front and back sides of the N-type crystalline silicon. The reaction gases include TMA, H2O, O3, and N2. The thickness of the alumina layer is 8±2 nm, the reaction temperature is 220±40℃, and the reaction time is 45±4 min. N-type crystalline silicon with the aforementioned alumina layer was placed in a tubular plasma-enhanced chemical vapor deposition furnace. A silicon nitride layer was fabricated on the front side of the N-type crystalline silicon. The furnace was filled with a reactive gas comprising SiH4, NH3, N2O, and N2. The reaction temperature was 500±40℃, and the reaction time was 60±4 min. The thickness of the fabricated silicon nitride layer was 160±20 nm, and the refractive index was 1.8±0.2%. An N-type crystalline silicon with the alumina layer and the silicon nitride layer is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards and the back side of the N-type crystalline silicon in contact with the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the alumina layer and the silicon nitride layer located on the back side and surrounding area of ​​the N-type crystalline silicon. The concentration of the hydrofluoric acid solution is 20±4%, the reaction temperature is room temperature, and the speed of the rollers is 3±0.4 m / min. The N-type crystalline silicon etched with hydrofluoric acid solution is placed in a tank cleaning machine and then sequentially enters tank SC1 and tank SC2 for RCA cleaning to remove residual organic dirt and metal ions. The solution in tank SC1 mainly includes KOH, H2O2, and H2O, while the solution in tank SC2 includes HCl, H2O2, and H2O. The reaction temperature is 55±10℃ and the reaction time is 200±20s.

8. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The method of creating openings in the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer within the negative electrode region, the openings exposing the N-type doped layer, includes: An opening is created by laser ablation of the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer in the negative electrode region; The N-type crystalline silicon with the opening made is placed in a chain-type hydrofluoric acid cleaning machine with the front side of the N-type crystalline silicon facing upwards and the back side of the N-type crystalline silicon contacting the rollers of the chain-type hydrofluoric acid cleaning machine for transmission. The rollers drive the hydrofluoric acid solution to etch the silicon oxide layer formed on the surface of the N-type doped layer due to laser ablation. The concentration of the hydrofluoric acid solution is 5±1%, the reaction temperature is room temperature, and the speed of the rollers is 4.5±1m / min.

9. The method for manufacturing a back-contact solar cell structure as described in claim 1, characterized in that, The process involves depositing a transparent conductive film on the back side of the N-type crystalline silicon, etching away the transparent conductive film located at the boundary between the positive and negative electrode regions, forming a first transparent conductive layer in the negative electrode region, and forming a second transparent conductive layer in the positive electrode region, including: The thickness of the transparent conductive film is 100±20nm, the sheet resistance is 50±20Ω / sq, the reaction temperature is 160±20℃, and the reaction time is 300±40s. The transparent conductive film located at the junction of the positive and negative electrode regions is removed by etching with acidic etching paste. A first transparent conductive layer is formed in the negative electrode region, and a second transparent conductive layer is formed in the positive electrode region. The width at the junction of the positive and negative electrode regions is 120±20um. The reaction temperature is room temperature, and the reaction time is 0.85±0.1s. After the N-type crystalline silicon is printed with etching paste, it is placed in a tank cleaning machine and the residual acidic etching paste is cleaned with SC1 solution, which includes KOH, H2O2 and H2O. The reaction temperature is 35±10℃ and the reaction time is 150±20s.

10. A back-contact solar cell structure, characterized in that, The back-contact solar cell structure is manufactured using the manufacturing method of the back-contact solar cell structure according to any one of claims 1 to 9, wherein the back-contact solar cell structure comprises: N-type crystalline silicon, wherein the front side of the N-type crystalline silicon has a pyramidal microstructure, the back side of the N-type crystalline silicon is a plane, and the back side of the N-type crystalline silicon is divided into a positive electrode region and a negative electrode region; An aluminum oxide layer is disposed on the front side of the N-type crystalline silicon; A silicon nitride layer is disposed on the aluminum oxide layer; A tunneling oxide layer is disposed in the negative electrode region and located below the back surface of the N-type crystalline silicon; An N-type doped layer is disposed in the negative electrode region and located below the tunneling oxide layer; The intrinsic amorphous silicon layer is partially located below the N-type doped layer in the negative electrode region, and partially located below the back surface of the N-type crystalline silicon in the positive electrode region. A boron-doped amorphous silicon layer is disposed below the intrinsic amorphous silicon layer; wherein the boron-doped amorphous silicon layer and the intrinsic amorphous silicon layer located in the negative electrode region are provided with openings; A first transparent conductive layer is disposed below the boron-doped amorphous silicon layer in the negative electrode region and is connected to the N-type doped layer through the opening; A second transparent conductive layer is disposed beneath the boron-doped amorphous silicon layer within the positive electrode region; The negative electrode fine grid line is disposed below the first transparent conductive layer; The positive electrode fine gate line is disposed under the second transparent conductive layer.

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