Wafer-level packaged III-V flexible thin-film solar cells and their fabrication methods

Abstract

This invention discloses a wafer-level packaged III-V flexible thin-film solar cell and its fabrication method, comprising an epitaxial layer, a front functional layer, a back functional layer, and a front electrode; at least one first extension and a second extension are formed at the edge of the back functional layer, and an insulating dielectric layer is disposed on the first extension; the grid lines of the front electrode are disposed between the epitaxial layer and the front functional layer, and the front electrode pads are disposed on the first extension, forming a first interconnect structure composed of the first extension, the insulating dielectric layer, and the front electrode pads; a back electrode pad is disposed on the second extension, forming a second interconnect structure composed of the second extension and the back electrode pads. This invention achieves wafer-level CIC packaging and testing of large-size single-cell cells, eliminating the traditional CIC module processing steps, reducing the use of cell interconnect solder ribbons, improving the utilization rate of the effective wafer area, and effectively reducing costs while improving the manufacturing quality and reliability of solar cells.

Description

Technical Field

[0001] This invention relates to the technical field of solar photovoltaics, and in particular to a wafer-level packaged III-V group flexible thin-film solar cell and its preparation method. Background Technology

[0002] III-V group flexible thin-film solar cells, with their high conversion efficiency of over 30%, areal density of less than 120 g / m², and millimeter-level bending radius, demonstrate irreplaceable advantages in applications with stringent requirements for weight and surface fit, such as satellites, high-altitude drones, wearable devices, and automotive curved surfaces. They employ an epitaxial lift-off process to transfer micron-sized multi-junction cell layers, such as GaAs and GaInP, to flexible substrates like polyimide or metal foil. This process retains the high absorption, high carrier mobility, and radiation resistance of III-V materials while significantly reducing material costs through multiple substrate recycling. Combining lightweight, bendability, high specific power, and long-term reliability, it is currently the only photovoltaic technology that simultaneously achieves the pinnacle of efficiency, weight, and mechanical flexibility.

[0003] Conventional III-V flexible thin-film solar cells cannot be directly used for module interconnection; they require CIC (Completely In-Chips) encapsulation processes such as ribbon welding, adhesive coating, and cover glass before being used in modules. The bendability and micron-level thickness of flexible samples make them prone to damage during CIC encapsulation, leading to cell failure and performance degradation. Furthermore, the vertical stacked structure of conventional III-V flexible thin-film solar cells, with the front and back electrode pads covering the top and bottom surfaces of the epitaxial layer respectively, makes them susceptible to epitaxial layer damage during CIC encapsulation and module welding. Adopting a same-side electrode structure design often complicates wafer fabrication. In addition, the ribbon welding, cover glass, and special adhesive coating involved in CIC encapsulation significantly increase material and time costs. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a wafer-level packaged III-V flexible thin-film solar cell and its preparation method. This invention enables wafer-level CIC packaging and testing of large-size single cells, eliminates the traditional CIC module processing steps, reduces the use of cell interconnect solder ribbons, improves the utilization rate of the effective area of ​​the wafer, and effectively reduces costs while improving the manufacturing quality and reliability of solar cells.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A wafer-level packaged III-V group flexible thin-film solar cell includes an epitaxial layer, a front functional layer, a back functional layer, and a front electrode. The front functional layer and the back functional layer are respectively disposed on the front and back sides of the epitaxial layer. The front functional layer includes an anti-reflection film, a water-blocking layer, and an anti-radiation layer arranged sequentially from bottom to top. The back functional layer includes a permanent substrate, a metal contact layer, and an etching stop layer arranged sequentially from bottom to top, with the permanent substrate serving as the back electrode of the cell. At least one first extension and at least one second extension are formed at the edge of the back functional layer, and an insulating dielectric layer is disposed on the front side of the first extension. The front electrode includes grid lines and a front electrode. A front electrode pad is provided, and the gate line is disposed between the epitaxial layer and the front functional layer. The number of the front electrode pads is consistent with the number of the first extensions and corresponds one-to-one. Each front electrode pad is disposed on the front side of the corresponding first extension and insulating dielectric layer, and the front electrode pad is electrically connected to the gate line. The first extension, the insulating dielectric layer and the front electrode pad constitute a first interconnect structure for leading out the front electrode to realize battery connection. Each second extension has a back electrode pad disposed on the front side, and each back electrode pad is isolated from the gate line. The second extension and the back electrode pad constitute a second interconnect structure for leading out the back electrode to realize battery connection.

[0007] Furthermore, the permanent substrate is a flexible metal foil with a thickness of 20μm to 50μm, and the flexible metal foil is connected to the epitaxial layer by an electroplating process.

[0008] Furthermore, the metal contact layer is a combination of at least two materials selected from Pd, Zn, Ag, Au, ITO, IZO, and Ti.

[0009] Furthermore, the ratio of the area of ​​the gate line to the front area of ​​the epitaxial layer is 0.02 to 0.05; the front electrode is a combination of at least two materials selected from Pd, Ge, Ag, Au, Pt, and Ni.

[0010] Furthermore, the antireflective film is made of SiO2 or SiN. x It is one or a combination of Al2O3, with a total thickness of 150nm~250nm, covering the entire epitaxial layer.

[0011] Furthermore, the water-blocking layer is a double-layer membrane structure, or a multi-layer membrane structure formed by stacking a double-layer membrane structure at least twice in cycles, wherein the double-layer membrane structure comprises SiN layers stacked sequentially. x The epitaxial layer consists of an Al2O3 layer and an Al2O3 layer; the total thickness of the water-blocking layer is 100nm~150nm, covering the entire epitaxial layer.

[0012] Furthermore, the radiation-resistant layer is a multilayer film structure, comprising a multi-element doped SiO2 layer, an Al2O3 layer, and a MgF2 layer stacked sequentially. The doping elements of the multi-element doped SiO2 layer include cerium, boron, and phosphorus, wherein the content of cerium doping is 4%~6%, the content of boron doping is 10%~16%, and the content of phosphorus doping is 0.2%~1.6%. The thickness of the multi-element doped SiO2 layer is 2000nm~3000nm. The total thickness of the radiation-resistant layer is 2100nm~3300nm, covering the entire epitaxial layer.

[0013] Furthermore, the insulating dielectric layer is a SiO2 / ITO double-layer film structure or a SiO2 / Al2O3 / ITO multilayer film structure; one end of the insulating dielectric layer overlaps the edge of the front side of the epitaxial layer, and the other end covers the sidewall of the epitaxial layer and extends to cover the front side of the first extension.

[0014] Furthermore, the first extension and the second extension are respectively provided with rounded corner structures at the corners where they connect to the back functional layer.

[0015] A method for fabricating a wafer-level packaged III-V flexible thin-film solar cell includes the following steps:

[0016] S1. First, a etch sacrificial layer, an epitaxial layer, and an etch stop layer are sequentially grown on a GaAs substrate using a CVD deposition process. Then, a metal contact layer is deposited on the surface of the etch stop layer. After growth is completed, rapid thermal annealing is performed to form an ohmic contact between the metal contact layer and the etch stop layer. Finally, a permanent substrate is prepared on the surface of the metal contact layer using an electroplating process to serve as the back electrode of the battery, thus completing the preparation of the epitaxial layer and the back functional layer.

[0017] S2. Apply UV protective layers to the surfaces of the permanent substrate and the GaAs substrate respectively. Use the ELO process to peel off the epitaxial layer and the back functional layer from the GaAs substrate. Then remove the UV protective layer on the surface of the permanent substrate and bond the surface of the permanent substrate to the temporary bonding substrate using a temporary bonding method.

[0018] S3. The epitaxial layer portion located in the preset invalid region of the battery is etched using photolithography and chemical etching processes, and the etching terminates at the etching stop layer, thereby forming at least one first extension and a second extension. After the etching of the epitaxial layer is completed, an insulating dielectric layer is deposited using vapor deposition, and the epitaxial layer portion and the second extension located in the preset valid region of the battery are exposed using photolithography. Then, the insulating dielectric layer in the exposed region is etched using chemical etching, and finally the photoresist is removed to complete the patterned deposition of the insulating dielectric layer.

[0019] S4. A gate line is deposited on the surface of the epitaxial layer using a vapor deposition process, and front electrode pads and back electrode pads are deposited on the first extension and the second extension, respectively. The first extension, the insulating dielectric layer and the front electrode pads form the first interconnect structure, and the second extension and the back electrode pads form the second interconnect structure. Then, the anti-reflection film, the water-blocking layer and the anti-radiation layer are deposited in sequence, thereby completing the preparation of the front functional layer.

[0020] S5. The preset pattern is covered on the surface of the radiation-resistant layer by photolithography. Then, the anti-reflection film, water-blocking layer and radiation-resistant layer on the first interconnect structure and the second interconnect structure are removed by etching. Then, the battery is cut and separated. Finally, the permanent substrate and the temporary bonding substrate are separated by debonding process to complete the fabrication.

[0021] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0022] This invention achieves wafer-scale CIC packaging and testing. It replaces solder ribbon welding with the permanent substrate of the individual cell itself as the back electrode, avoiding damage to the epitaxial layer during processing of the hard-connected structure and saving solder ribbon material. By replacing the rigid cover plate of CIC processing with a special vapor-deposited film, the bending capability of the module can be significantly improved in large-size flexible cells such as 40mm×80mm. Simultaneously, the special vapor-deposited film replaces special adhesive coating to improve overall reliability. Furthermore, by extending the permanent substrate and metal contact layer in ineffective areas, interconnect structures are formed on the permanent substrate and metal contact layer through vapor deposition, photolithography, and laser cutting. This self-structure replaces the solder ribbon in the CIC processing, effectively reducing the cost from individual solar cells to solar panels and the processing loss of individual cells, improving efficiency and overall reliability. Compared to traditional CIC cells with rigid cover plates, it effectively improves the ultimate bending capability of individual cells and modules. Attached Figure Description

[0023] Figure 1 This is a planar schematic diagram of the flexible thin-film solar cell of the present invention.

[0024] Figure 2 This is a cross-sectional schematic diagram of the first interconnect structure and the epitaxial layer of the present invention.

[0025] Figure 3 This is a cross-sectional schematic diagram of the second interconnect structure and the epitaxial layer of the present invention.

[0026] Figure 4 This is a schematic diagram of the structure after step S1 in the preparation method of the present invention.

[0027] Figure 5 This is a schematic diagram of the structure after step S2 in the preparation method of the present invention.

[0028] Figure 6 (a) is a schematic diagram of the first interconnect structure after step S3 in the preparation method of the present invention.

[0029] Figure 6 (b) is a schematic diagram of the second interconnect structure after step S3 of the preparation method of the present invention.

[0030] Figure 7 (a) is a schematic diagram of the first interconnect structure after step S4 of the preparation method of the present invention.

[0031] Figure 7 (b) is a schematic diagram of the second interconnect structure after step S4 of the preparation method of the present invention.

[0032] Figure 8 (a) is a schematic diagram of the first interconnect structure after step S5 of the preparation method of the present invention.

[0033] Figure 8 (b) is a schematic diagram of the second interconnect structure after step S5 of the preparation method of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0035] like Figures 1 to 3As shown, this embodiment provides a wafer-level packaged III-V group flexible thin-film solar cell, including a back functional layer, an epitaxial layer 2, a front functional layer, and a front electrode; the epitaxial layer 2 is the main part of the photoelectric generation, used to generate photoelectrons, and the front functional layer and the back functional layer are respectively disposed on the front and back sides of the epitaxial layer 2; the front functional layer includes an anti-reflection film 401, a water-blocking layer 402, and an anti-radiation layer 403 arranged sequentially from bottom to top; the back functional layer includes a permanent substrate 101, a metal contact layer 102, and an etching stop layer 103 arranged sequentially from bottom to top, with the permanent substrate 101 serving as the back electrode of the cell; at least one first extension 1-a and at least one second extension 1-b are formed at the edge of the back functional layer. This embodiment takes three first extensions 1-a arranged side by side and two second extensions 1-b arranged in a dispersed manner as an example, and the first extensions 1-a... An insulating dielectric layer 104 is provided on the front side; the front electrode includes a gate line 301 and a front electrode pad 302. The gate line 301 is disposed between the epitaxial layer 2 and the front functional layer; the number of front electrode pads 302 is consistent with the number of the first extension 1-a and corresponds one-to-one. Each front electrode pad 302 is disposed on the front side of the corresponding first extension 1-a and the insulating dielectric layer 104, and the front electrode pad 302 is electrically connected to the gate line 301. The first extension 1-a, the insulating dielectric layer 104 and the front electrode pad 302 constitute a first interconnection structure for leading out the front electrode to realize battery connection. Each second extension 1-b has a back electrode pad 105 on its front side, and each back electrode pad 105 is isolated from the gate line 301. The second extension 1-b and the back electrode pad 105 constitute a second interconnection structure for leading out the back electrode to realize battery connection.

[0036] The permanent substrate 101 is a flexible metal foil with ductility and bending ability, such as silver or copper foil, which mainly serves to support the epitaxial layer. Its thickness is 20μm~50μm. The flexible metal foil is connected to the epitaxial layer 2 by electroplating process.

[0037] The metal contact layer 102 is a combination of at least two materials selected from Pd, Zn, Ag, Au, ITO, IZO, and Ti, such as a Pd / Zn / Pd / Ag multilayer metal structure, an Au / Zn / Au / Ag multilayer metal structure, an ITO / IZO / Ti / Ag composite structure, an ITO / IZO / Au composite structure, etc., used to connect the permanent substrate 101 with the epitaxial layer 2 and to form a good contact with the epitaxial layer 2.

[0038] The corrosion stop layer 103 is a functional layer used to stop the corrosion of the epitaxial layer 2 by the corrosion solution. Its composition is a highly phosphorus-doped compound, which is used to block the corrosion solution from corroding the underlying structure.

[0039] The ratio of the area of ​​the gate line 301 to the front area of ​​the epitaxial layer 2 is 0.02~0.05; the front electrode is a combination of at least two materials selected from Pd, Ge, Ag, Au, Pt, and Ni, such as Au / AuGeNi / Au / Pt / Au multilayer metal structure, Au / AuGeNi / Au / Ag / Au multilayer metal structure, Pd / Ge / Pd / Ag / Au multilayer metal structure, etc., and the thickness of the front electrode is 4μm~8μm.

[0040] Antireflective coating 401 is made of SiO2 and SiN x One or more of Al2O3, with a total thickness of 150nm~250nm, covering the entire epitaxial layer, mainly used to reduce the reflection of light by the epitaxial layer 2 and increase the light transmittance.

[0041] The water-blocking layer 402 is a double-layer membrane structure, or a multilayer membrane structure formed by stacking a double-layer membrane structure at least twice in cycles. The double-layer membrane structure includes SiN layers stacked sequentially. x The total thickness of the water-blocking layer 402, including the Al2O3 layer and the Al2O3 layer, is 100nm~150nm, covering the entire epitaxial layer 2. It is mainly used to block water vapor and isolate the epitaxial layer 2 from water vapor or other gases that may cause failure.

[0042] The radiation-resistant layer 403 is a multilayer film structure, which includes a multi-element doped SiO2 layer, an Al2O3 layer, and a MgF2 layer stacked sequentially. The doping elements of the multi-element doped SiO2 layer include cerium, boron, and phosphorus. The content of cerium doping is 4%~6%, the content of boron doping is 10%~16%, and the content of phosphorus doping is 0.2%~1.6%. The thickness of the multi-element doped SiO2 layer is 2000nm~3000nm. The total thickness of the radiation-resistant layer 403 is 2100nm~3300nm, covering the entire epitaxial layer. Its main functions are radiation resistance, protection of the solar cell epitaxial layer 2, and increasing light transmittance.

[0043] The insulating dielectric layer 104 is a SiO2 / ITO double-layer film structure or a SiO2 / Al2O3 / ITO multilayer film structure. One end of the insulating dielectric layer 104 overlaps the edge of the front side of the epitaxial layer 2, and the other end covers the sidewall of the epitaxial layer 2 and extends to cover the front side of the first extension 1-a.

[0044] The dimensions and shapes of the first extension 1-a and the second extension 1-b are designed according to actual welding requirements. The corners where the first extension 1-a and the second extension 1-b connect to the back functional layer are respectively provided with rounded corner structures.

[0045] This embodiment also provides a method for fabricating the above-mentioned wafer-level packaged III-V flexible thin-film solar cell, including the following steps:

[0046] S1. First, an etch sacrificial layer 502 (i.e., a GaAs / AlAs layer), an epitaxial layer 2 (including a top cell, a middle cell, and a bottom cell), and an etch stop layer 103 are sequentially grown on a GaAs substrate 501 using MOCVD deposition. Next, a metal contact layer 102 is deposited on the surface of the etch stop layer 103. After growth, rapid thermal annealing is performed to form an ohmic contact between the metal contact layer 102 and the etch stop layer 103. Then, a flexible metal foil, either copper or silver, is electroplated onto the surface of the metal contact layer 102 to prepare a permanent substrate 101 with a plating thickness of 20-50 μm, serving as the back electrode of the cell. This completes the fabrication of the epitaxial layer 2 and the back functional layer. Figure 4 As shown;

[0047] S2. Apply UV protective layers to the surfaces of the permanent substrate 101 and the GaAs substrate 501 respectively. Place the bonded wafer in an HF:IPA:H2O2 etching solution. Using the ELO process, selectively etch the GaAs / AlAs layer with HF to peel off the epitaxial layer 2 and the back functional layer from the GaAs substrate 501. Then remove the UV protective layer from the surface of the permanent substrate 101. Bond the surface of the permanent substrate 101 to the temporary bonding substrate 503 (such as a sapphire wafer) using a temporary bonding method. Figure 5 As shown;

[0048] S3. The epitaxial layer portion located in the preset invalid region of the battery is etched using photolithography and chemical etching processes, and the etching terminates at the etching stop layer 103, thereby forming at least one first extension 1-a and a second extension 1-b. Specifically, the top cell and middle cell in the epitaxial layer 2 can be etched using an HNO3 (98%):HCl:H2O=1:3:10 solution, and the bottom cell in the epitaxial layer 2 can be etched using an H3PO4:H2O2:H2O=1:1:1 solution. The epitaxial layer portion in the preset invalid region is cleaned by etching with the two solutions.

[0049] After etching the epitaxial layer 2, an insulating dielectric layer 104 is deposited using a vapor deposition process. Then, the epitaxial layer portion and the second extension 1-b located in the predetermined effective area of ​​the battery are exposed using a photolithography process. Next, the insulating dielectric layer in the exposed area is etched using a chemical etching process. Finally, the photoresist is removed, completing the patterned deposition of the insulating dielectric layer 104. Specifically, a SiO2 layer and an Al2O3 layer can be vapor-deposited on the surface first. After vapor deposition, an ITO layer is sputtered on the surface. The epitaxial layer portion and the second extension 1-b located in the predetermined effective area of ​​the battery are exposed using a photolithography process. Etching is performed using an HF:H2O = 1:10 solution. Figure 6 (a) Figure 6 As shown in (b);

[0050] S4. A gate line 301 is deposited on the surface of the epitaxial layer 2 using a vapor deposition process. Front electrode pads 302 and back electrode pads 105 are deposited on the first extension 1-a and the second extension 1-b, respectively. The first extension 1-a, the insulating dielectric layer 104, and the front electrode pads 302 form a first interconnect structure, and the second extension 1-b and the back electrode pads 105 form a second interconnect structure. Then, the antireflective film 401, the water-blocking layer 402, and the radiation-resistant layer 403 are deposited sequentially to complete the fabrication of the front functional layer. Figure 7 (a) Figure 7 As shown in (b), the deposition process of the antireflective coating 401, the water-blocking layer 402, and the radiation-resistant layer 403 is as follows:

[0051] First, an antireflective film 401 (SiO2 / Al2O3) is deposited using an optical coating machine. Then, SiN is deposited on the entire surface using a PECVD deposition process. x The water-blocking layer 402 is an Al2O3 double-layer film structure. Then, a multi-element doped SiO2 layer is deposited on the surface using PECVD deposition process. On the surface of the multi-element doped SiO2 layer, an Al2O3 layer with a thickness of 10~20nm and a MgF2 layer with a thickness of 100~120nm are deposited by IAD evaporation.

[0052] S5. A pre-defined pattern is applied to the surface of the radiation-resistant layer 403 using photolithography. Then, an HF:H2O = 1:10 solution is used to etch the anti-reflection film 401, water-blocking layer 402, and radiation-resistant layer 403 from the first and second interconnect structures for 30-120 seconds. A laser cutting protective solution is then coated onto the surface. A laser cutting machine is used to cut and separate the individual cells from the entire wafer. After cleaning, the individual cells are tested. Finally, a debonding process is used to separate the permanent substrate 101 from the temporary bonding substrate 503, thus completing the fabrication. Figure 8 (a) Figure 8 As shown in (b).

[0053] In summary, the wafer-level packaged III-V flexible thin-film solar cell provided by this invention transforms the traditional vertical structure into a same-side cell structure, enabling sample testing and cell interconnection to be completed on the same side. This achieves CIC (Completely In-Chips) packaging of individual cells on the wafer, reducing processing steps from chip to module, eliminating the CIC packaging process, improving the reliability and extreme bending capability of the packaged cells, and providing a solution for large-scale fully automated production from chip to module.

[0054] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A wafer-level packaged III-V group flexible thin-film solar cell, characterized in that: The battery comprises an epitaxial layer, a front functional layer, a back functional layer, and a front electrode. The front and back functional layers are respectively disposed on the front and back sides of the epitaxial layer. The front functional layer includes an anti-reflection film, a water-blocking layer, and an anti-radiation layer arranged sequentially from bottom to top. The back functional layer includes a permanent substrate, a metal contact layer, and an etching stop layer arranged sequentially from bottom to top, with the permanent substrate serving as the back electrode of the battery. At least one first extension and at least one second extension are formed at the edge of the back functional layer, and an insulating dielectric layer is disposed on the front side of the first extension. The front electrode includes a gate line and a front electrode pad. The first extension is positioned between the epitaxial layer and the front functional layer. The number of front electrode pads corresponds to the number of first extensions. Each front electrode pad is disposed on the front side of the corresponding first extension and insulating dielectric layer. The front electrode pad is electrically connected to the gate line. The first extension, the insulating dielectric layer, and the front electrode pad constitute a first interconnect structure for leading out the front electrode to achieve battery connection. Each second extension has a back electrode pad on its front side. Each back electrode pad is isolated from the gate line. The second extension and the back electrode pad constitute a second interconnect structure for leading out the back electrode to achieve battery connection.

2. The wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The permanent substrate is a flexible metal foil with a thickness of 20μm to 50μm. The flexible metal foil is connected to the epitaxial layer by an electroplating process.

3. The wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The metal contact layer is a combination of at least two materials selected from Pd, Zn, Ag, Au, ITO, IZO, and Ti.

4. A wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The ratio of the area of ​​the gate line to the front area of ​​the epitaxial layer is 0.02 to 0.05; the front electrode is a combination of at least two materials selected from Pd, Ge, Ag, Au, Pt, and Ni.

5. A wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The antireflective coating is made of SiO2 or SiN. x It is one or a combination of Al2O3, with a total thickness of 150nm~250nm, covering the entire epitaxial layer.

6. A wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The water-blocking layer is a double-layer membrane structure, or a multilayer membrane structure formed by stacking a double-layer membrane structure at least twice in cycles. The double-layer membrane structure includes SiN layers stacked sequentially. x The epitaxial layer consists of an Al2O3 layer and an Al2O3 layer; the total thickness of the water-blocking layer is 100nm~150nm, covering the entire epitaxial layer.

7. A wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The radiation-resistant layer is a multilayer film structure, comprising a multi-element doped SiO2 layer, an Al2O3 layer, and a MgF2 layer stacked sequentially. The doping elements of the multi-element doped SiO2 layer include cerium, boron, and phosphorus, with the cerium content being 4%~6%, the boron content being 10%~16%, and the phosphorus content being 0.2%~1.6%. The thickness of the multi-element doped SiO2 layer is 2000nm~3000nm. The total thickness of the radiation-resistant layer is 2100nm~3300nm, covering the entire epitaxial layer.

8. A wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The insulating dielectric layer is a SiO2 / ITO double-layer film structure or a SiO2 / Al2O3 / ITO multilayer film structure; one end of the insulating dielectric layer overlaps the edge of the front side of the epitaxial layer, and the other end covers the sidewall of the epitaxial layer and extends to cover the front side of the first extension.

9. A wafer-level packaged III-V flexible thin-film solar cell according to claim 1, characterized in that: The first extension and the second extension are respectively provided with rounded corner structures at the corners where they connect to the back functional layer.

10. A method for fabricating a wafer-level packaged III-V flexible thin-film solar cell according to any one of claims 1 to 9, characterized in that: Including steps, S1. First, a etch sacrificial layer, an epitaxial layer, and an etch stop layer are sequentially grown on a GaAs substrate using a CVD deposition process. Then, a metal contact layer is deposited on the surface of the etch stop layer. After growth is completed, rapid thermal annealing is performed to form an ohmic contact between the metal contact layer and the etch stop layer. Finally, a permanent substrate is prepared on the surface of the metal contact layer using an electroplating process to serve as the back electrode of the battery, thus completing the preparation of the epitaxial layer and the back functional layer. S2. Apply UV protective layers to the surfaces of the permanent substrate and the GaAs substrate respectively. Use the ELO process to peel off the epitaxial layer and the back functional layer from the GaAs substrate. Then remove the UV protective layer on the surface of the permanent substrate and bond the surface of the permanent substrate to the temporary bonding substrate using a temporary bonding method. S3. The epitaxial layer portion located in the preset invalid region of the battery is etched using photolithography and chemical etching processes, and the etching terminates at the etching stop layer, thereby forming at least one first extension and a second extension. After the etching of the epitaxial layer is completed, an insulating dielectric layer is deposited using vapor deposition, and the epitaxial layer portion and the second extension located in the preset valid region of the battery are exposed using photolithography. Then, the insulating dielectric layer in the exposed region is etched using chemical etching, and finally the photoresist is removed to complete the patterned deposition of the insulating dielectric layer. S4. A gate line is deposited on the surface of the epitaxial layer using a vapor deposition process, and front electrode pads and back electrode pads are deposited on the first extension and the second extension, respectively. The first extension, the insulating dielectric layer and the front electrode pads form the first interconnect structure, and the second extension and the back electrode pads form the second interconnect structure. Then, the anti-reflection film, the water-blocking layer and the anti-radiation layer are deposited in sequence, thereby completing the preparation of the front functional layer. S5. The preset pattern is covered on the surface of the radiation-resistant layer by photolithography. Then, the anti-reflection film, water-blocking layer and radiation-resistant layer on the first interconnect structure and the second interconnect structure are removed by etching. Then, the battery is cut and separated. Finally, the permanent substrate and the temporary bonding substrate are separated by debonding process to complete the fabrication.

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