A piezoresistive pressure chip and a preparation method thereof

Abstract

The present application relates to the field of piezoresistive pressure chip, and particularly relates to a piezoresistive pressure chip and a preparation method thereof, which comprises, from top to bottom, a silicon nitride passivation layer, a device layer, a first buried oxygen layer, a single crystal silicon layer, a second buried oxygen layer, a substrate silicon layer and glass; the device layer is arranged between the silicon nitride passivation layer and the first buried oxygen layer, and a piezoresistor assembly is arranged on the device layer; the piezoresistor assembly comprises a piezoresistor R1, a piezoresistor R2, a piezoresistor R3 and a piezoresistor R4; a pressure cavity is arranged on the substrate silicon layer; the piezoresistor R1, the piezoresistor R2, the piezoresistor R3 and the piezoresistor R4 are all located in the extension direction of the pressure cavity; the single crystal silicon layer in the middle is an N-type single crystal silicon, and is located between the first buried oxygen layer and the second buried oxygen layer, and is used for controlling the thickness of a pressure sensing film; the first buried oxygen layer is located below the piezoresistor assembly, and electrically isolates the piezoresistor strip and the single crystal silicon layer, so that the pressure chip can work stably in a wide temperature range.

Description

Technical Field

[0001] This invention relates to the field of piezoresistive pressure chips, and more specifically to a piezoresistive pressure chip and its fabrication method. Background Technology

[0002] A piezoresistive pressure sensor is a core component of a sensor that utilizes the piezoresistive effect of semiconductor materials such as single-crystal silicon to sense pressure changes and convert them into electrical signals, playing a crucial role in multiple fields. Its core principle is based on the piezoresistive effect of single-crystal silicon. When pressure is applied to a diffused silicon thin film, the lattice structure of the single-crystal silicon deforms, causing a change in the mobility of charge carriers, which in turn causes a change in resistivity, ultimately altering the resistance value. This change is linearly proportional to the applied pressure. A conventional piezoresistive pressure sensor consists of an elastic membrane and four resistors integrated on the membrane, forming a Wheatstone bridge structure. When pressure is applied to the elastic membrane, the bridge generates a voltage output signal that is linearly proportional to the applied pressure. By measuring this voltage signal, the magnitude of the pressure can be accurately determined.

[0003] Traditional piezoresistive pressure chips, with their conventional packaging structures, once held a significant position in the field of pressure measurement. They utilize the piezoresistive effect to convert pressure signals into electrical signals, providing an effective pressure monitoring method for numerous industrial and scientific research scenarios. However, in practical applications, when the chip is exposed to high temperatures, the thermal motion of impurity atoms in the PN junction intensifies, causing the originally ordered distribution of charge carriers to become disordered. This makes it easier for charge carriers to cross the potential barrier of the PN junction, leading to leakage. This leakage problem not only interferes with the chip's normal electrical signal output and reduces measurement accuracy but can also seriously damage the chip's long-term reliability and lifespan. Summary of the Invention

[0004] The purpose of this invention is to provide a piezoresistive pressure chip and its fabrication method, aiming to improve the problem that existing piezoresistive pressure chips are prone to leakage under excessive temperature conditions.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A piezoresistive pressure chip includes, from top to bottom, a silicon nitride passivation layer, a device layer, a first buried oxide layer, a single crystal silicon layer, a second buried oxide layer, a substrate silicon layer, and glass. The device layer is disposed between the silicon nitride passivation layer and the first buried oxide layer. A varistor assembly is provided on the device layer. The varistor assembly includes varistors R1, R2, R3, and R4. One end of varistor R1 and R2 is electrically connected and serves as VCC, connected to an external power supply. The other end of varistor R1 is electrically connected to one end of varistor R3 and serves as Vout+, connected to an external power supply. The other end of varistor R2 is electrically connected to one end of varistor R4 and serves as Vout-, connected to an external power supply. The other ends of varistor R3 and R4 serve as independent negative terminals (GND). A pressure cavity is provided on the substrate silicon layer, and the varistor R1, varistor R2, varistor R3 and varistor R4 are all located in the extension direction of the pressure cavity.

[0006] Furthermore, both the first and second buried oxide layers are silicon dioxide buried oxide layers.

[0007] To achieve the above objectives, the present invention also adopts the following technical solution: A method for fabricating the piezoresistive pressure chip includes the following steps: S01. Select wafers and clean them; S02. Place the cleaned wafer in an oxidation furnace, introduce oxygen, and oxidize at 1050℃ for 2 hours to generate a silicon dioxide masking layer on the surface of the top monocrystalline silicon layer; S03. The silicon dioxide masking layer is patterned using photolithography to form an injection window for the varistor region on the silicon dioxide masking layer; S04. Boron ion implantation is performed on the photolithographically defined device layer using an ion implanter, with the implantation energy set to 70 keV and the implantation dose to be 2 × 10⁻⁶. 16 ions / cm 2 During the implantation process, the wafer temperature is maintained at 25°C, and a P-type doped region is formed on the surface of the top single-crystal silicon layer. S05. Transfer the ion-implanted wafer to an annealing furnace, introduce nitrogen gas at a flow rate of 5 L / min, anneal at 1100℃, and anneal for 120 min, then cool it to room temperature in the furnace. S06. Immerse the annealed wafer in a diluted hydrofluoric acid solution and etch it at room temperature for 10 minutes to remove the silicon dioxide masking layer on the surface of the device layer. S07. Using photolithography, excess doped single-crystal silicon material is removed from the device layer, while retaining the varistor material, forming four symmetrically distributed resistor strips, and then wire material is implanted using an ion implanter; S08. Deposit a silicon nitride passivation layer on the resistor strip and the first buried oxide layer, and anneal the silicon nitride passivation layer after deposition; S09. Define the pad area on the silicon nitride passivation layer using photolithography, remove the silicon nitride in the pad area to expose the wires, deposit a metal layer in the pad area to form a pad, and connect the power supply terminal, ground terminal and signal output terminal of the Wheatstone bridge. S10. Thinning and polishing the back side of the wafer; S11. Use photolithography to define a pressure chamber region on the back side of the wafer, and etch the single-crystal silicon in the pressure chamber region until the second buried oxide layer is reached; S12. Glass bonding encapsulation; S13. Finished product inspection.

[0008] Furthermore, step S03 specifically includes the following steps: Photoresist is uniformly coated on the top surface of the silicon dioxide masking layer at a coating speed of 3000 r / min to form a photoresist layer. The varistor pattern mask is projected onto the photoresist layer using a photolithography machine. After exposure, the mask is developed for 2 minutes to remove the photoresist in the unexposed areas, exposing the silicon dioxide masking layer in the area to be injected. The exposed silicon dioxide is then removed to form the injection window of the varistor region.

[0009] Furthermore, step S01, specifically the cleaning of the wafer, includes the following steps: Acetone ultrasonic cleaning was performed at 30℃ for 15 minutes, followed by alcohol ultrasonic cleaning for 10 minutes, deionized water rinsing for 5 minutes, and then hot nitrogen blowing at 120℃.

[0010] Furthermore, in step S06, the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is 1:10.

[0011] Furthermore, in step S07, removing the doped single-crystal silicon material from the excess device layer specifically includes the following steps: Etching was performed for 5 minutes using a mixture of Cl2 and O2 gas, with a Cl2 to O2 ratio of 4:1. After etching, ultrasonic cleaning with acetone was performed for 5 minutes. Step S07, which involves implanting wire material using an ion implanter, specifically includes the following steps: The injection energy was 60 keV, and the injection dose was 1.8 × 10⁻⁶. 16 ions / cm 2 Boron ion implantation is performed to form P-type silicon wires on the surface of the device layer, which are made of the same material as the varistor component; After injection, anneal at 1080°C for 60 minutes in a nitrogen atmosphere.

[0012] Furthermore, in step S08, depositing a silicon nitride passivation layer on the resistor strip and the first buried oxide layer specifically includes the following steps: At a temperature of 700℃ and a deposition pressure of 200 mTorr, a reaction was carried out using SiH4 gas and NH3 gas for 60 min to form a 400 nm thick silicon nitride passivation layer. The volume ratio of SiH4 gas to NH3 gas is 1:3; In step S08, the silicon nitride passivation layer after deposition is annealed, specifically including the following steps. Annealing was performed at 900℃ for 30 minutes under a nitrogen atmosphere.

[0013] Furthermore, the metal layer is a multilayer metal layer, which includes a Ti layer, a W layer, a Ni layer, and an Au layer. Step S09 further includes the following steps. After the metal layer is deposited, it is ultrasonically cleaned with acetone for 10 minutes; and the pad area is then subjected to secondary photolithography and etching.

[0014] Furthermore, step S12 specifically includes the following steps: The back side of the wafer and the glass surface are plasma cleaned using Ar gas for 2 minutes. After aligning and bonding the glass with the back side of the wafer, the wafer is placed in a bonding furnace and anodic bonding is performed under a nitrogen atmosphere at a bonding temperature of 350°C and a voltage of 1000V for 30 minutes.

[0015] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: 1. The middle monocrystalline silicon layer is an N-type monocrystalline silicon layer located between the first and second buried oxide layers, used to control the thickness of the pressure-sensitive film; the first buried oxide layer is located below the varistor component, providing electrical isolation between the varistor strip and the monocrystalline silicon layer, eliminating the PN junction leakage current problem at high temperatures, and enabling the pressure chip to operate stably in a wide temperature range from -55℃ to 200℃.

[0016] 2. A silicon nitride passivation layer covers the surface of the varistor component, providing protection against moisture and impurities.

[0017] 3. During operation, VCC and dual GND provide power. Pressure causes the resistance of the varistor to change, breaking the bridge balance. A differential voltage signal proportional to the pressure is generated between Vout+ and Vout-. Dual GND can be connected in series with a compensation resistor to flexibly correct zero drift and improve measurement accuracy. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the piezoresistive pressure chip described in this invention; Figure 2 This is a schematic cross-sectional view of the piezoresistive pressure chip described in this invention. Figure 3 This is a circuit diagram of the piezoresistive component of the piezoresistive pressure chip described in this invention. Figure 4 This is a schematic diagram of the piezoresistive component of the piezoresistive pressure chip described in this invention; Figure 5 This is a flowchart of the preparation method described in this invention; Figure 6 This is a schematic diagram of the wafer selection structure in step S01 of the preparation method described in this invention; Figure 7 This is a schematic diagram of the wafer state in step S02 of the preparation method described in this invention.

[0019] Explanation of reference numerals in the attached figures: 1. First buried oxide layer; 2. Single crystal silicon layer; 3. Second buried oxide layer; 4. Substrate silicon layer; 41. Pressure chamber; 5. Glass; 6. Device layer; 61. Varistor assembly; 7. Silicon nitride passivation layer; 8. Top single crystal silicon layer; 9. Silicon dioxide masking layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0022] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0023] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0024] Please refer to Figure 1-4 As shown, this embodiment provides a piezoresistive pressure chip, which includes, from top to bottom, a silicon nitride passivation layer, a device layer, a first buried oxide layer, a single crystal silicon layer, a second buried oxide layer, a substrate silicon layer, and glass.

[0025] A device layer is disposed between a silicon nitride passivation layer and a first buried oxide layer. A varistor assembly is provided on the device layer, comprising varistors R1, R2, R3, and R4. One end of varistors R1 and R2 is electrically connected and serves as VCC, connected to an external power supply. The other end of varistor R1 is electrically connected to one end of varistor R3 and serves as Vout+, connected to an external power supply. The other end of varistor R2 is electrically connected to one end of varistor R4 and serves as Vout-, connected to an external power supply. The other ends of varistor R3 and R4 serve as independent negative terminals (GND). A pressure cavity is provided on the substrate silicon layer, and varistors R1, R2, R3, and R4 are all located along the extension direction of the pressure cavity. In this embodiment, both the first and second buried oxide layers are silicon dioxide buried oxide layers.

[0026] The middle single-crystal silicon layer is N-type single-crystal silicon, located between the first and second buried oxide layers, used to control the thickness of the pressure-sensitive film. The first buried oxide layer is located below the varistor component, providing electrical isolation between the varistor strip and the single-crystal silicon layer, eliminating the PN junction leakage current problem at high temperatures, and enabling the pressure chip to operate stably within a wide temperature range of -55℃ to 200℃. A silicon nitride passivation layer covers the surface of the varistor component, providing protection against moisture and impurities. During operation, VCC and dual GND provide power. Pressure causes a change in the varistor resistance, disrupting the bridge balance and generating a differential voltage signal proportional to the pressure between Vout+ and Vout-. The dual GND can be connected in series with a compensation resistor to flexibly correct zero-point drift and improve measurement accuracy.

[0027] Please refer to Figure 5-7 As shown, this embodiment also discloses a method for preparing the above-mentioned piezoresistive pressure chip, including the following steps: S01. Wafer selection and wafer cleaning; please refer to... Figure 6 As shown, in this embodiment, a five-layer SOI wafer is selected. From top to bottom, the five layers are a top single-crystal silicon layer, a first buried oxide layer, a single-crystal silicon layer, a second buried oxide layer, and a substrate silicon layer. The top single-crystal silicon layer forms the device layer in subsequent processing. The top single-crystal silicon layer is N-type single-crystal silicon with a thickness of 8 μm; the first and second buried oxide layers are SiO2 with a thickness of 1.5 μm; both the substrate silicon layer and the single-crystal silicon layer are high-purity single-crystal silicon. The overall wafer size is 6 inches to ensure lattice integrity and structural uniformity, laying the foundation for subsequent processes.

[0028] Please refer to Figure 7 As shown, in step S02, the cleaned wafer is placed in an oxidation furnace, oxygen is introduced, and oxidation is carried out at 1050°C for 2 hours to generate a silicon dioxide masking layer on the surface of the top single-crystal silicon layer. In this embodiment, the oxygen introduced is high-purity oxygen with a purity of 99.999%. Ordinary photoresist cannot withstand the energy of ion implantation. Without protection, the subsequently implanted boron ions will destroy the silicon lattice structure. The SiO2 buried oxide layer is set to protect the silicon, making the implantation smooth, the lattice structure stable, and the defects less doped.

[0029] S03. The silicon dioxide masking layer is patterned using photolithography to form an injection window for the varistor region on the silicon dioxide masking layer; S04. Boron ion implantation is performed on the photolithographically defined device layer using an ion implanter, with the implantation energy set to 70 keV and the implantation dose to be 2 × 10⁻⁶. 16 ions / cm 2 During the implantation process, the wafer temperature is maintained at 25°C, forming a P-type doped region on the surface of the top single-crystal silicon layer. In this embodiment, the ion beam current density uniformity is ≤±2%, ensuring the formation of a uniform P-type doped region on the surface of the top single-crystal silicon layer.

[0030] S05. Transfer the ion-implanted wafer to an annealing furnace, introduce nitrogen gas at a flow rate of 5 L / min, anneal at 1100℃, and anneal for 120 min, then cool to room temperature in the furnace. This annealing process achieves a boron ion activation rate of >95%, while repairing lattice damage generated during ion implantation and improving the electrical stability of the varistor.

[0031] S06. Immerse the annealed wafer in a diluted hydrofluoric acid solution and etch it at room temperature for 10 minutes to remove the silicon dioxide masking layer on the surface of the device layer. S07. Using photolithography, excess doped single-crystal silicon material is removed from the device layer, while retaining the varistor material, forming four symmetrically distributed resistor strips, and then wire material is implanted using an ion implanter; S08. Deposit a silicon nitride passivation layer on the resistor strip and the first buried oxide layer, and anneal the silicon nitride passivation layer after deposition; S09. Define the pad area on the silicon nitride passivation layer using photolithography, remove the silicon nitride in the pad area to expose the wires, deposit a metal layer in the pad area to form a pad, and connect the power supply terminal, ground terminal and signal output terminal of the Wheatstone bridge. S10. Thinning and polishing the back side of the wafer; S11. Use photolithography to define a pressure chamber region on the back side of the wafer, and etch the single-crystal silicon in the pressure chamber region until the second buried oxide layer is reached; S12. Glass bonding encapsulation; S13. Finished product inspection.

[0032] Specifically, step S01, cleaning the wafer, includes the following steps: Acetone ultrasonic cleaning was performed for 15 minutes at 30°C to remove organic contaminants from the wafer surface. After acetone ultrasonic cleaning, alcohol ultrasonic cleaning was performed for 10 minutes to further clean residual impurities. After alcohol ultrasonic cleaning, deionized water was rinsed for 5 minutes to avoid contaminant residue. After deionized water rinsing, hot nitrogen was blown dry at 120°C to ensure that the wafer surface was free of moisture and impurities, meeting the cleanliness requirements of subsequent processes.

[0033] Specifically, step S03 includes the following steps: Photoresist was uniformly coated on the top surface of the silicon dioxide masking layer at a coating speed of 3000 r / min to form a photoresist layer. A varistor pattern mask was then projected onto the photoresist layer using a photolithography machine at an exposure dose of 80 mJ / cm². 2 Exposure is performed, followed by development with a developer for 2 minutes to remove the photoresist in the unexposed areas, exposing the silicon dioxide masking layer in the area to be injected. Then, dry etching is performed using CF4 gas for 3 minutes to remove the exposed silicon dioxide, forming the injection window for the varistor region.

[0034] Specifically, in step S06, the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is 1:10; and after the etching is completed, the wafer surface is rinsed with a large amount of deionized water for 5 minutes to remove residual hydrofluoric acid and etching products, and then dried with hot nitrogen gas.

[0035] Specifically, in step S07, the excess area of ​​the top monocrystalline silicon layer is exposed by exposure and development using a dedicated mask; the removal of the excess doped monocrystalline silicon material from the device layer includes the following steps. Etching was performed for 5 minutes using a mixture of Cl2 and O2 gas with a ratio of 4:1; followed by ultrasonic cleaning with acetone for 5 minutes to remove residual photoresist.

[0036] Furthermore, in step S07, the implantation of the wire material using an ion implanter specifically includes the following steps: The injection energy was 60 keV, and the injection dose was 1.8 × 10⁻⁶. 16 ions / cm 2 Boron ion implantation was performed to form P-type silicon wires on the surface of the device layer, with the same material as the varistor component. After implantation, the surface was annealed at 1080°C for 60 minutes in a nitrogen atmosphere. The electrical performance of the wires and the varistor component was ensured to match, achieving precise connection of the four varistor strips to form a complete Wheatstone bridge circuit. The four varistor strips are varistors R1, R2, R3, and R4, respectively.

[0037] Specifically, in step S08, a silicon nitride passivation layer is deposited on the resistor strip and the first buried oxide layer, which includes the following steps: At 700℃ and a deposition pressure of 200 mTorr, a silicon nitride passivation layer with a thickness of 400 nm was formed by reacting SiH4 and NH3 gases for 60 min. The volume ratio of SiH4 to NH3 gases was 1:3. The silicon nitride passivation layer was used to completely cover the surface of the varistor component, the ion-implanted silicon wire, and the top monocrystalline silicon layer, thus blocking moisture and impurity corrosion.

[0038] In step S08, the silicon nitride passivation layer after deposition is annealed, specifically including the following steps: Under a nitrogen atmosphere, the annealing temperature is 900℃ and the annealing is carried out for 30 minutes to improve the interfacial bonding force between silicon nitride and the top monocrystalline silicon layer, avoid interfacial reactions under high temperature environment, and enhance the long-term stability of the passivation layer.

[0039] In this embodiment, the metal layer is a multilayer metal layer, including a Ti layer, a W layer, a Ni layer, and an Au layer. Step S09 further includes the following steps: After the metal layer is deposited, it undergoes ultrasonic cleaning with acetone for 10 minutes; then, a second photolithography and etching process is performed on the pad area. Excess photoresist and the overlying metal layer are removed, forming four metal pads, corresponding to the power supply, ground, and two signal output terminals of the Wheatstone bridge, respectively. After cleaning, a second photolithography and etching process is performed on the metal pad area to ensure that there is no residual silicon nitride on the pad surface, fully exposing the metal layer, in preparation for subsequent wire bonding processes.

[0040] Specifically, in step S10, the back side of the wafer is physically polished at a polishing speed of 1500 r / min and a polishing pressure of 50 N. After physical polishing, chemical mechanical polishing is performed to remove surface damage generated during the polishing process, ensuring that the roughness Ra of the back side of the wafer is ≤0.1 μm after polishing. Finally, the silicon dioxide layer on the back side of the wafer is removed by etching with diluted hydrofluoric acid solution for 8 min, ensuring that the wafer thickness meets the sensitivity requirements of the pressure sensor.

[0041] Specifically, in step S11, photoresist is coated on the back side of the wafer at a rotation speed of 2000 r / min and a coating thickness of 2 μm. After exposure and development, the back cavity region is exposed. Using a mixture of SF6 and O2 gas, the substrate silicon layer is etched from the back side at an etching rate of 1 μm / min until the second buried oxide layer is reached, forming a pressure cavity with a depth of 90 μm and a size corresponding to the Wheatstone bridge region. This cavity provides space for the deformation of the varistor, ensuring the response sensitivity of the pressure sensor.

[0042] In this embodiment, the glass is BF33 glass, and step S12 specifically includes the following steps. The back side of the wafer and the glass surface are subjected to plasma cleaning using Ar gas for 2 minutes to remove surface contaminants and activate the surface. After aligning and bonding the glass to the back side of the wafer, it is placed in a bonding furnace for anodic bonding under a nitrogen atmosphere at a bonding temperature of 350℃ and an applied voltage of 1000V for 30 minutes, forming a vacuum-sealed cavity with a vacuum degree ≤1×10⁻⁶. - 3 Pa. Simultaneously, it achieves insulating encapsulation of the sensor, preventing interference from the external environment on the internal structure.

[0043] Specifically, step S13 includes the following steps: The packaged chips are subjected to electrical performance tests, including the initial balance of the Wheatstone bridge (matching error <0.05% is acceptable); the varistor sensitivity ≥100mV / V·MPa is acceptable; and the measurement accuracy ±0.1%FS is acceptable. Unacceptable products are screened out.

[0044] The chip was placed in a high and low temperature test chamber and cycled 100 times within a temperature range of -55℃ to 200℃, with each cycle held at that temperature for 1 hour. The resistance drift and signal stability were tested at different temperatures. A resistance drift of ≤0.05% was considered acceptable, ensuring that the chip could work stably in a wide temperature range.

[0045] Qualified chips undergo 10,000 hours of continuous operation reliability testing at an ambient temperature of 150°C. The resistance drift and signal output consistency are recorded to ensure that the long-term operating life of the chips meets the requirements of industrial applications.

[0046] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A piezoresistive pressure chip, characterized in that, It includes, from top to bottom, a silicon nitride passivation layer, a device layer, a first buried oxide layer, a single crystal silicon layer, a second buried oxide layer, a substrate silicon layer, and glass; The device layer is disposed between the silicon nitride passivation layer and the first buried oxide layer. A varistor assembly is provided on the device layer. The varistor assembly includes varistors R1, R2, R3, and R4. One end of varistor R1 and R2 is electrically connected and serves as VCC, connected to an external power supply. The other end of varistor R1 is electrically connected to one end of varistor R3 and serves as Vout+, connected to an external power supply. The other end of varistor R2 is electrically connected to one end of varistor R4 and serves as Vout-, connected to an external power supply. The other ends of varistor R3 and R4 serve as independent negative terminals (GND). A pressure cavity is provided on the substrate silicon layer, and the varistor R1, varistor R2, varistor R3 and varistor R4 are all located in the extension direction of the pressure cavity.

2. The piezoresistive pressure chip according to claim 1, characterized in that: Both the first and second buried oxide layers are silicon dioxide buried oxide layers.

3. A method for preparing a piezoresistive pressure chip according to any one of claims 1-2, characterized in that, Includes the following steps, S01. Select wafers and clean them; S02. Place the cleaned wafer in an oxidation furnace, introduce oxygen, and oxidize at 1050℃ for 2 hours to generate a silicon dioxide masking layer on the surface of the top monocrystalline silicon layer; S03. The silicon dioxide masking layer is patterned using photolithography to form an injection window for the varistor region on the silicon dioxide masking layer; S04. Boron ion implantation is performed on the photolithographically defined device layer using an ion implanter, with the implantation energy set to 70 keV and the implantation dose to be 2 × 10⁻⁶. 16 ions / cm 2 During the implantation process, the wafer temperature is maintained at 25°C, and a P-type doped region is formed on the surface of the top single-crystal silicon layer. S05. Transfer the ion-implanted wafer to an annealing furnace, introduce nitrogen gas at a flow rate of 5 L / min, anneal at 1100℃, and anneal for 120 min, then cool it to room temperature in the furnace. S06. Immerse the annealed wafer in a diluted hydrofluoric acid solution and etch it at room temperature for 10 minutes to remove the silicon dioxide masking layer on the surface of the device layer. S07. Use photolithography to remove excess doped single-crystal silicon material from the device layer, retain the varistor component, form four symmetrically distributed resistor strips, and implant wire material through an ion implanter; S08. Deposit a silicon nitride passivation layer on the resistor strip and the first buried oxide layer, and anneal the silicon nitride passivation layer after deposition; S09. Define the pad area on the silicon nitride passivation layer using photolithography, remove the silicon nitride in the pad area to expose the wires, deposit a metal layer in the pad area to form a pad, and connect the power supply terminal, ground terminal and signal output terminal of the Wheatstone bridge. S10. Thinning and polishing the back side of the wafer; S11. Use photolithography to define a pressure chamber region on the back side of the wafer, and etch the single-crystal silicon in the pressure chamber region until the second buried oxide layer is reached; S12. Glass bonding encapsulation; S13. Finished product inspection.

4. The preparation method according to claim 3, characterized in that: Step S03 specifically includes the following steps. Photoresist is uniformly coated on the top surface of the silicon dioxide masking layer at a coating speed of 3000 r / min to form a photoresist layer. The varistor pattern mask is projected onto the photoresist layer using a photolithography machine. After exposure, the mask is developed for 2 minutes to remove the photoresist in the unexposed areas, exposing the silicon dioxide masking layer in the area to be injected. The exposed silicon dioxide is then removed to form the injection window of the varistor region.

5. The preparation method according to claim 3, characterized in that: Step S01, which involves cleaning the wafer, specifically includes the following steps: Acetone ultrasonic cleaning was performed at 30℃ for 15 minutes, followed by alcohol ultrasonic cleaning for 10 minutes, deionized water rinsing for 5 minutes, and then hot nitrogen blowing at 120℃.

6. The preparation method according to claim 3, characterized in that: In step S06, the volume ratio of hydrofluoric acid to water in the diluted hydrofluoric acid solution is 1:

10.

7. The preparation method according to claim 3, characterized in that: In step S07, removing the doped single-crystal silicon material from the excess device layers specifically includes the following steps. Etching was performed for 5 minutes using a mixture of Cl2 and O2 gas, with a Cl2 to O2 ratio of 4:

1. After etching, ultrasonic cleaning with acetone was performed for 5 minutes. Step S07, which involves implanting wire material using an ion implanter, specifically includes the following steps: The injection energy was 60 keV, and the injection dose was 1.8 × 10⁻⁶. 16 ions / cm 2 Boron ion implantation is performed to form P-type silicon wires on the surface of the device layer, which are made of the same material as the varistor component; After injection, anneal at 1080°C for 60 minutes in a nitrogen atmosphere.

8. The preparation method according to claim 3, characterized in that: In step S08, a silicon nitride passivation layer is deposited on the resistor strip and the first buried oxide layer, specifically... Includes the following steps, At a temperature of 700℃ and a deposition pressure of 200 mTorr, a reaction was carried out using SiH4 gas and NH3 gas for 60 min to form a 400 nm thick silicon nitride passivation layer. The volume ratio of SiH4 gas to NH3 gas is 1:3; In step S08, the silicon nitride passivation layer after deposition is annealed, specifically including the following steps. Annealing was performed at 900℃ for 30 minutes under a nitrogen atmosphere.

9. The preparation method according to claim 3, characterized in that: The metal layer is a multilayer metal layer, which includes a Ti layer, a W layer, a Ni layer, and an Au layer. Step S09 further includes the following steps. After the metal layer is deposited, it is ultrasonically cleaned with acetone for 10 minutes; and the pad area is then subjected to secondary photolithography and etching.

10. The preparation method according to claim 3, characterized in that: Step S12 specifically includes the following steps: The back side of the wafer and the glass surface are plasma cleaned using Ar gas for 2 minutes. After aligning and bonding the glass with the back side of the wafer, the wafer is placed in a bonding furnace and anodic bonding is performed under a nitrogen atmosphere at a bonding temperature of 350°C and a voltage of 1000V for 30 minutes.

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